Dallas DS1670E Portable system controller Datasheet

DS1670
Portable System Controller
www.dalsemi.com
FEATURES
Provides real time clock:
− Counts seconds, minutes, hours, date of
the month, month, day of the week, and
year with leap year compensation valid up
to 2100
− Power control circuitry supports system
power-on from day/time alarm
Microprocessor monitor:
− Halts microprocessor during power fail
− Automatically restarts microprocessor
after power failure
− Monitors pushbutton for external override
− Halts and resets an out of control
microprocessor
NV RAM control:
− Automatic battery backup and write
protection to external SRAM
3-channel, 8-bit analog-to-digital converter
Simple 3-wire interface
3.3V operation
PIN ASSIGNMENT
VBAT
1
20
ST
VCCO
2
19
VCC
SCLK
3
18
X1
I/O
4
17
X2
CS
5
16
AIN0
CEI
6
15
AIN1
CEOL
7
14
AIN2
CEOH
8
13
RST
INT
9
12
BLE
GND
10
11
BHE
20-Pin TSSOP (4.4mm)
20-Pin SOIC (300 mil)
Package Dimension Information can be found at:
http://www.dalsemi.com/datasheets/mechdwg.html
ORDERING INFORMATION
DS1670E
DS1670S
20-pin TSSOP
20-pin SOIC
DESCRIPTION
The Portable System Controller is a circuit, which incorporates many of the functions necessary for low
power portable products integrated into one chip. The DS1670 provides a Real Time Clock, NV RAM
controller, microprocessor monitor, and a 3-channel, 8-bit analog-to-digital converter. Communication
with the DS1670 is established through a simple 3-wire interface.
The Real Time Clock (RTC) provides seconds, minutes, hours, day, date, month, and year information
with leap year compensation. The RTC also provides an alarm interrupt. This interrupt works when the
DS1670 is powered by the system power supply or when in battery backup operation so the alarm can be
used to wake up a system that is powered down.
Automatic backup and write protection of an external SRAM is provided through the VCCO, CEOL , and
CEOH pins. The backup energy source used to power the RTC is also used to retain RAM data in the
absence of VCC through the VCCO pin. The chip-enable outputs to RAM ( CEOL and CEOH ) are
controlled during power transients to prevent data corruption.
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DS1670
The microprocessor monitor circuitry of the DS1670 provides three basic functions. First, a precision
temperature-compensated reference and comparator circuit monitors the status of VCC. When an out-oftolerance condition occurs, an internal power-fail signal is generated which forces the reset to the active
state. When VCC returns to an in-tolerance condition, the reset signals are kept in the active state for
250 ms to allow the power supply and processor to stabilize. The second microprocessor monitor
function is pushbutton reset control. The DS1670 debounces a pushbutton input and guarantees an active
reset pulse width of 250 ms. The third function is a watchdog timer. The DS1670 has an internal timer
that forces the reset signals to the active state if the strobe input is not driven low prior to watchdog
time-out.
The DS1670 also provides a 3-channel, 8-bit successive approximation analog-to-digital converter. The
converter has an internal 2.55-volt (typical) reference voltage generated by an on-board band-gap circuit.
The A/D converter is monotonic (no missing codes) and has an internal analog filter to reduce high
frequency noise.
OPERATION
The block diagram in Figure 1 shows the main elements of the DS1670. The following paragraphs
describe the function of each pin.
DS1670 BLOCK DIAGRAM Figure 1
SIGNAL DESCRIPTIONS
VCC, GND - DC power is provided to the device on these pins. VCC is the +3.3 volt input. When
3.3 volts are applied within nominal limits, the device is fully accessible and data can be written and read.
When VCC drops below 2.88 volts (typical) access to the device is prohibited. When VCC drops below the
lower of VBAT and 2.7 volts (typical), the device is switched over to the backup power supply.
VBAT (Backup Power Supply) - Battery input for standard 3-volt lithium cell or other energy source.
SCLK (Serial Clock Input) - SCLK is used to synchronize data movement on the serial interface.
I/O (Data Input/Output) - The I/O pin is the bi-directional data pin for the 3-wire interface.
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DS1670
CS (Chip Select) - The Chip Select signal must be asserted high during a read or a write for
communication over the 3-wire serial interface. CS had an internal 40k ohm pull down resistor.
VCCO (External SRAM Power Supply Output) - This pin is internally connected to VCC when VCC is
within nominal limits. However, during power fail VCCO is internally connected to the VBAT pin.
Switchover occurs when VCC drops below the lower of VBAT or 2.7 volts.
INT (Interrupt Output) - The INT pin is an active high output of the DS1670 that can be used as an
interrupt input to a microprocessor. The INT output remains high as long as the status bit causing the
interrupt is present and the corresponding interrupt-enable bit is set. The INT pin operates when the
DS1670 is powered by VCC or VBAT.
CEI
(RAM Chip Enable In) - CEI must be driven low to enable the external RAM.
(Byte Low Enable input) - This pin when driven low activates the CEOL output if CEI is also
driven low.
BLE
BHE (Byte High Enable input) - This pin when driven low activates the CEOH output if CEI is also
driven low.
CEOL
(RAM Chip Enable Out Low) - Chip enable output for low order SRAM byte.
CEOH
(RAM Chip Enable Out High) - Chip enable output for high order SRAM byte.
(Strobe Input) - The Strobe input pin is used in conjunction with the watchdog timer. If the ST pin
is not driven low within the watchdog time period, the RST pin is driven low.
ST
RST (Reset) - The RST pin functions as a microprocessor reset signal. This pin is driven low 1) when
VCC is outside of nominal limits; 2) when the watchdog timer has “timed out”; 3) during the power up
reset period; and 4) in response to a pushbutton reset. The RST pin also functions as a pushbutton reset
input. When the RST pin is driven low, the signal is debounced and timed such that a RST signal of at
least 250 ms is generated. This pin has an open drain output with an internal 47 kΩ pull-up resistor.
AIN0, AIN1, AIN2 (Analog Inputs) - These pins are the three analog inputs for the 3-channel analog-todigital converter.
X1, X2 - Connections for a standard 32.768 kHz quartz crystal. For greatest accuracy, the DS1670 must
be used with a crystal that has a specified load capacitance of 6 pF. There is no need for external
capacitors or resistors. Note: X1 and X2 are very high impedance nodes. It is recommended that they
and the crystal be guard-ringed with ground and that high frequency signals be kept away from the crystal
area. For more information on crystal selection and crystal layout considerations, please consult
Application Note 58, “Crystal Considerations with Dallas Real Time Clocks.”
The DS1670 will not function without a crystal.
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DS1670
POWER-UP/POWER-DOWN CONSIDERATIONS
The DS1670 was designed to operate with a power supply of 3.3 volts. When 3.3 volts are applied within
nominal limits, the device becomes fully accessible after tRPU (250 ms typical). Before tRPU elapses, all
inputs are disabled. When VCC drops below 2.88 volts (typical), the RST pin is driven low. When VCC
drops below the lower of 2.7 volts (typical) or the battery voltage, the device is switched over to the
backup power supply.
During power up, when VCC returns to an in-tolerance condition, the RST pin is kept in the active state
for 250 ms (typical) to allow the power supply and microprocessor to stabilize.
ADDRESS/COMMAND BYTE
The command byte for the DS1670 is shown in Figure 2. Each data transfer is initiated by a command
byte. Bits 0 through 6 specify the addresses of the registers to be accessed. The MSB (bit 7) is the
Read/Write bit. This bit specifies whether the accessed byte will be read or written. A read operation is
selected if bit 7 is a 0 and a write operation is selected if bit 7 is a 1. The address map for the DS1670 is
shown in Figure 3.
ADDRESS/COMMAND BYTE Figure 2
7
RD
WR
6
5
4
3
2
1
0
A6
A5
A4
A3
A2
A1
A0
DS1670 ADDRESS MAP Figure 3
BIT 7
00
01
0
0
02
0
03
04
05
0
0
0
06
07
08
M
M
09
M
0A
0B
0C
0D
0E
0F
7F
M
BIT 0
10 SECONDS
SECONDS
10 MINUTES
MINUTES
12
10 HR
10 HR
HOURS
24
A/P
0
0
0
0
DAY
0
10 DATE
DATE
0
0
10
MONTH
MO.
10 YEAR
YEAR
10 SEC ALARM
SECONDS ALARM
10 MIN ALARM
MINUTES ALARM
10 HR
12
10 HR
HOUR ALARM
24
A/P
0
0
0
DAY ALARM
CONTROL REGISTER
STATUS REGISTER
WATCHDOG REGISTER
ADC REGISTER
RESERVED
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DS1670
CLOCK, CALENDAR AND ALARM
The time and calendar information is accessed by reading/writing the appropriate register bytes. Note
that some bits are set to 0. These bits will always read 0 regardless of how they are written. Also note
that registers 0 Fh to 7 Fh are reserved. These registers will always read 0 regardless of how they are
written. The contents of the time, calendar, and alarm registers are in the Binary-Coded Decimal (BCD)
format.
The DS1670 can run in either 12-hour or 24-hour mode. Bit 6 of the hours register is defined as the
12- or 24-hour mode select bit. When high, the 12-hour mode is selected. In the 12-hour mode, bit 5 is
the AM/PM bit with logic 1 being PM. In the 24-hour mode, bit 5 is the second 10-hour bit (20-23
hours).
The DS1670 also contains a time of day alarm. The alarm registers are located in registers 07h to 0 Ah.
Bit 7 of each of the alarm registers are mask bits (see Table 1). When all of the mask bits are logic 0, an
alarm will occur once per week when the values stored in timekeeping registers 00h to 03h match the
values stored in the time of day alarm registers. An alarm will be generated every day when mask bit of
the day alarm register is set to 1. An alarm will be generated every hour when the day and hour alarm
mask bits are set to 1. Similarly, an alarm will be generated every minute when the day, hour, and minute
alarm mask bits are set to 1. When day, hour, minute, and seconds alarm mask bits are set to 1, an alarm
will occur every second.
TIME OF DAY ALARM BITS Table 1
ALARM REGISTER MASK BITS (BIT 7)
SECONDS MINUTES HOURS DAYS
1
1
1
1
0
1
1
1
0
0
1
1
0
0
0
1
0
0
0
0
Alarm once per second.
Alarm when seconds match.
Alarm when minutes and seconds match
Alarm when hours, minutes and seconds match.
Alarm when day, hours, minutes and seconds.
SPECIAL PURPOSE REGISTERS
The DS1670 has two additional registers (control register and status register) that control the real time
clock and interrupts.
CONTROL REGISTER
BIT 7
EOSC
BIT 6
WP
BIT 5 BIT 4
AIS1 AIS0
BIT 3
0
BIT 2
0
BIT 1
0
BIT 0
AIE
EOSC (Enable oscillator) - This bit when set to logic 0 will start the oscillator. When this bit is set to a
logic 1, the oscillator is stopped and the DS1670 is placed into a low-power standby mode with a current
drain of less than 200 nanoamps when in battery back-up mode. When the DS1670 is powered by VCC,
the oscillator is always on regardless of the status of the EOSC bit; however, the real time clock is
incremented only when EOSC is a logic 0.
WP (Write Protect) - Before any write operation to the real time clock or any other registers, this bit
must be logic 0. When high, the write-protect bit prevents a write operation to any register.
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DS1670
AIS0-AIS1 (Analog Input Select) - These 2 bits are used to determine the analog input for the analog-todigital conversion. Table 2 lists the specific analog input that is selected by these two bits.
AIE (Alarm Interrupt Enable) - When set to a logic 1, this bit permits the Interrupt Request Flag
(IRQF) bit in the status register to assert INT. When the AIE bit is set to logic 0, the IRQF bit does not
initiate the INT signal.
ANALOG INPUT SELECTION Table 2
AIS1
0
0
1
1
AIS0
0
1
0
1
ANALOG INPUT
NONE
AIN0
AIN1
AIN2
STATUS REGISTER
BIT 7
CU
BIT 6
LOBAT
BIT 5
0
BIT 4
0
BIT 3
0
BIT 2
0
BIT 1
0
BIT 0
IRQF
CU (Conversion Update In Progress) - When this bit is a 1, an update to the ADC Register (register
0Eh) will occur within 488 ms. When this bit is a 0, an update to the ADC Register will not occur for at
least 244 ms.
LOBAT (Low Battery Flag) - This bit reflects the status of the backup power source connected to the
V BAT pin. When VBAT is greater than 2.5 volts, LOBAT is set to a logic 0. When VBAT is less than 2.3
volts, LOBAT is set to a logic 1.
IRQF (Interrupt Request Flag) - A logic 1 in the Interrupt Request Flag bit indicates that the current
time has matched the time of day Alarm registers. If the AIE bit is also a logic 1, the INT pin will go
high. IRQF is cleared by reading or writing to any of the alarm registers.
POWER-UP DEFAULT STATES
These bits are set to a one upon initial power-up: EOSC , TD1 and TD0. These bits are cleared upon
initial power-up: WP, AIS1, and AIS0.
NONVOLATILE SRAM CONTROLLER
The DS1670 provides automatic backup and write protection for external SRAM. This function is
provided by gating the chip enable signals and by providing a constant power supply through the VCCO
pin. The DS1670 was specifically designed with the Intel 80186 and 386EX microprocessors in mind.
As such, the DS1670 has the capability to provide access to the external SRAM in either byte-wide or
word-wide format. This capability is provided by the chip enable scheme. Three input signals and two
output signals are used for enabling the external SRAM(s) (see Figure 4). CEI (chip enable in), BHE
(byte high enable), and BLE (byte low enable) are used for enabling either one or two external SRAMs
through the CEOL (chip enable low) and the CEOH (chip enable high) outputs. Table 3 illustrates the
function of these pins.
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DS1670
The DS1670 nonvolatilizes the external SRAM(s) by write protecting the SRAM(s) and by providing a
back-up power supply in the absence of VCC. When VCC falls below 2.88 volts (typical), access to the
external SRAM(s) are prohibited by forcing CEOL and CEOH high regardless of the level of CEI , BLE ,
and BHE . Also at this point, the SRAM power supply (VCCO) is switched from VCC to VBAT. Upon
power up, access is prohibited until the end of tRPU.
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DS1670
EXTERNAL SRAM CHIP ENABLE Table 3
CEI
BHE
BLE
CEOL
CEOH
0
0
0
0
0
1
0
1
0
0
0
1
0
0
1
0
1
1
X
1
X
1
1
1
1
FUNCTION
Word Transfer
Byte Transfer in upper half of data
bus (D15-D8)
Byte Transfer in lower half of data
bus (D7-D0)
External SRAMs disabled
External SRAMs disabled
EXTERNAL SRAM INTERFACE (WORD-WIDE) TO THE DS1670 Figure 4
MICROPROCESSOR MONITOR
The DS1670 monitors three vital conditions for a microprocessor: power supply, software execution, and
external override.
First, a precision temperature-compensated reference and comparator circuit monitors the status of VCC.
When an out-of-tolerance condition occurs, an internal power-fail signal is generated which forces the
RST pin to the active state, thus warning a processor-based system of impending power failure. The
power-fail trip point is 2.88 volts (typical). When VCC returns to an in-tolerance condition upon powerup, the reset signal is kept in the active state for 250 ms (typical) to allow the power supply and
microprocessor to stabilize. Note, however, that if the EOSC bit is set to a logic 1 (to disable the
oscillator during battery back-up mode), the reset signal will be kept in an active state for 250 ms plus the
start-up time of the oscillator.
The second monitoring function is pushbutton reset control. The DS1670 provides for a pushbutton
switch to be connected to the RST output pin. When the DS1670 is not in a reset cycle, it continuously
monitors the RST signal for a low-going edge. If an edge is detected, the DS1670 will debounce the
switch by pulling the RST line low. After the internal 250 ms timer has expired, the DS1670 will
continue to monitor the RST line. If the line is still low, the DS1670 will continue to monitor the line
looking for a rising edge. Upon detecting release, the DS1670 will force the RST line low and hold it
low for 250 ms.
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DS1670
The third microprocessor monitoring function provided by the DS1670 is a watchdog timer. The
watchdog timer function forces RST to the active state when the ST input is not stimulated within the
predetermined time period. The time period is set by the Time Delay (TD) bits in the Watchdog Register.
The time delay can be set to 250 ms, 500 ms, or 1000 ms (see Figure 5). If TD0 and TD1 are both set to
0, the watchdog timer is disabled. When enabled, the watchdog timer starts timing out from the set time
period as soon as RST is inactive. The default setting is for the watchdog timer to be enabled with
1000 ms time delay. If a high-to-low transition occurs on the ST input pin prior to time-out, the
watch-dog timer is reset and begins to time-out again. If the watchdog timer is allowed to time-out, then
the RST signal is driven to the active state for 250 ms (typical). The ST input can be derived from
microprocessor address signals, data signals, and/or control signals. To guarantee that the watchdog
timer does not time-out, a high-to-low transition must occur at or less than the minimum period.
WATCHDOG TIME-OUT CONTROL Figure 5
WATCHDOG REGISTER
BIT 7
BIT 6
BIT 5
0
0
0
BIT 4
0
BIT 3
0
BIT 2
0
BIT 1
TD1
BIT 0
TD0
WATCHDOG TIME-OUT
TD1
TD0
WATCHDOG TIME-OUT
0
0
Watchdog disabled
0
1
250 ms
1
0
500 ms
1
1
1000 ms
ANALOG-TO-DIGITAL CONVERTER
The DS1670 provides a 3-channel, 8-bit analog-to-digital converter. The A/D reference voltage (2.55V
typical) is derived from an on-chip band-gap circuit. Three multiplexed analog inputs are provided
through the AIN0, AIN1, and AIN2 pins. The A/D converter is monotonic (no missing codes) and uses a
successive approximation technique to convert the analog signal into a digital code. An A/D conversion
is the process of assigning a digital code to an analog input voltage. This code represents the input value
as a fraction of the full-scale voltage (FSV) range. Thus the FSV range is then divided by the A/D
converter into 256 codes (8 bits). The FSV range is bounded by an upper limit equal to the reference
voltage and the lower limit, which is ground. The DS1670 has a FSV of 2.55V (typical) which provides a
resolution of 10 mV. An input voltage equal to the reference voltage converts to FFh while an input
voltage equal to ground converts to 00h. The relative linearity of the A/D converter is ±0.5 LSB.
The A/D converter selects from one of three different analog inputs (AIN0 - AIN2). The input that is
selected is determined by the Analog Input Select (AIS) bits in the Control Register. Table 2 lists the
specific analog input that is selected by these 2 bits. Note also that the converter can be turned off by
these bits to reduce power. When the A/D is turned on by setting AIS0 and AIS1 to any value other than
0,0 the analog input voltage is converted and written to the ADC Register within 488 ms. An internal
analog filter at the input reduces high frequency noise. Subsequent updates occur approximately every
10 ms. If AIS0 and/or AIS1 are changed, updates will occur at the next 10 ms conversion time.
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DS1670
The Conversion Update In Progress (CU) bit in the Status Register indicates when the ADC Register can
be read. When this bit is a 1, an update to the ADC Register will occur within 488 ms maximum.
However, when this bit is 0 an update will not occur for at least 244 ms. The CU bit should be polled
before reading the ADC Register to insure that the contents are stable during a read cycle. Once a read
cycle to the ADC Register has been started, the DS1670 will not update that register until the read cycle
has been completed. It should also be mentioned that taking CS low will abort the read cycle and will
allow the ADC Register to be updated.
Figure 6 illustrates the timing of the CU bit relative to an instruction to begin conversion and the
completion of that conversion.
CU BIT TIMING Figure 6
3-WIRE SERIAL INTERFACE
Communication with the DS1670 is accomplished through a simple 3-wire interface consisting of the
Chip Select (CS), Serial Clock (SCLK) and Input/Output (I/O) pins.
All data transfers are initiated by driving the CS input high. The CS input serves two functions. First, CS
turns on the control logic, which allows access to the shift register for the address/command sequence.
Second, the CS signal provides a method of terminating either single byte or multiple byte (burst) data
transfer. A clock cycle is a sequence of a rising edge followed by a falling edge. For data input, data
must be valid during the rising edge of the clock and data bits are output on the falling edge of the clock.
If the CS input goes low, all data transfer terminates and the I/O pin goes to a high impedance state.
Address and data bytes are always shifted LSB first into the I/O pin. Any transaction requires the
address/command byte to specify a read or write to a specific register followed by one or more bytes of
data. The address byte is always the first byte entered after CS is driven high. The most significant bit
( RD /WR) of this byte determines if a read or write will take place. If this bit is 0, one or more read
cycles will occur. If this bit is 1, one or more write cycles will occur.
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DS1670
Data transfers can occur 1 byte at a time or in multiple-byte burst mode. After CS is driven high an
address is written to the DS1670. After the address, one or more data bytes can be read or written. For a
single-byte transfer 1 byte is read or written and then CS is driven low. For a multiple-byte transfer,
multiple bytes can be read or written to the DS1670 after the address has been written. Each read or write
cycle causes the register address to automatically increment. Incrementing continues until the device is
disabled. After accessing register 0Eh, the address wraps to 00h.
Data transfer for single-byte transfer and multiple-byte burst transfer is illustrated in Figures 7 and 8.
SINGLE-BYTE DATA TRANSFER Figure 7
CS
SCLK
A0
A1
A2
A3
A4
A5
A6
RD
WR
D0
D1
D2
D3
D4
D5
MULTIPLE-BYTE BURST TRANSFER Figure 8
CS
SCLK
I/O
ADDRESS
BYTE
DATA
BYTE 0
DATA
BYTE 1
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DATA
BYTE N
D6
D7
DS1670
ABSOLUTE MAXIMUM RATINGS*
Voltage on Any Pin Relative to Ground
Operating Temperature
Storage Temperature
Soldering Temperature
-0.3V to +6V
0°C to 70°C
-55°C to +125°C
See J-STD-020A Specification
* This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operation sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods of time may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS
PARAMETER
(0°C to 70°C)
SYMBOL
MIN
TYP
MAX
UNITS
NOTES
Power Supply Voltage
VCC
2.97
3.3
3.63
V
1
Input Logic 1
VIH
2.0
VCC + 0.3
V
1
Input Logic 0
VIL
-0.3
+0.8
V
1
VBAT
2.5
3.7
V
1
Battery Voltage
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DS1670
DC ELECTRICAL CHARACTERISTICS
PARAMETER
(0°C to 70°C)
SYMBOL
MIN
Input Leakage
ILI
-1
CS Leakage
ILO
Logic 1 Output (Iout=-0.4 mA)
VOH
Logic 0 Output (Iout=1.5 mA)
VOL
Active Supply Current
(CS = VCC-0.2)
ICCA
A/D Converter Current
MAX
UNITS
+1
µA
150
µA
7
V
2
0.4
V
3
1.0
mA
4
IADC
200
µA
5
Standby Current (CS=VIL)
ICCS
100
µA
6
Battery Current (Oscillator On)
IBAT1
500
nA
Battery Current (Oscillator Off)
IBAT2
200
nA
Internal RST Pull-up Resistor
TYP
2.4
0.75
300
RP
35
47
60
kΩ
VCC Trip Point
VCCTP
2.80
2.88
2.97
V
VCC Switchover
VCCSW
2.62
2.70
2.78
V
A/D Reference Voltage
VADC
2.47
2.55
2.63
V
Pushbutton Detect
PBDV
0.8
2.0
V
Pushbutton Release
PBRD
0.8
V
Output Voltage
VCCO
VCCO Output Current
(Source = VCC)
ICCO1
VCCO Output Current
(Source = VBAT)
ICCO2
0.3
VCC-0.3
Input Capacitance
12
V
11
100
mA
13
150
µA
14
CAPACITANCE
PARAMETER
NOTES
(tA = 25°C)
SYMBOL
MIN
TYP
MAX
UNITS
CI
10
pF
I/O Capacitance
CI/O
15
pF
Crystal Capacitance
CX
6
pF
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NOTES
DS1670
AC ELECTRICAL CHARACTERISTICS
PARAMETER
(0°C to 70°C; VCC = 3.3V ± 10%)
SYMBOL
MIN
TYP
MAX
UNITS
NOTES
Data to Clock Setup
tDC
100
ns
8
CLK to Data Hold
tCDH
140
ns
8
CLK to Data Delay
tCDD
ns
8, 9, 10
CLK to Low Time
tCL
500
ns
8
CLK to High Time
tCH
500
ns
8
CLK Frequency
tCLK
1.0
MHz
8
CLK Rise and Fall
tR, tF
1000
ns
CS to CLK Setup
tCC
2
µs
8
CLK to CS Hold
tCCH
120
ns
8
CS Inactive Time
tCWH
2
µs
8
CS to I/O High Z
tCDZ
140
ns
8
SCLK to I/O High Z
tCCZ
140
ns
8
400
VCC Slew Rate (2.85V to
2.3V)
tF
300
µs
VCC Slew Rate (2.3V to
2.85V)
tR
0
ns
100
ns
VCC Detect to RST
(VCC Falling)
tRPD
Reset Active Time
tRST
250
ms
15
Pushbutton Debounce
PBDB
250
ms
15
VCC Detect to RST
(VCC Rising)
tRPU
250
ms
15, 16
Pulse Width
tST
ST
Chip Enable Propagation
Delay to External SRAM
tCED
Nominal Voltage to VCC
Switchover Fall Time
tFB
20
ns
8
200
15
ns
µs
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DS1670
TIMING DIAGRAM: READ DATA Figure 9
TIMING DIAGERAM: WRITE DATA Figure 10
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DS1670
PUSHBUTTON RESET Figure 11
RST
VOH
PBDV
PBRD
PBDB
tRST
POWER-UP Figure 12
VCCTP
VCC
tRPU
VOH
RST
POWER-DOWN Figure 13
VCC
VCCTPMAX
VCCTP
VCCSWMIN
RST
VOL
tRPD
tFB
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DS1670
NOTES:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
All voltages are referenced to ground.
Logic 1 voltages are specified at VCC =3.3V, VOH =VCC for capacitive loads. Excludes RST pin.
Logic 0 voltages are specified at VCC =3.3V, VOL =GND for capacitive loads.
ICCA is specified with outputs open, CS set to a logic 1, SCLK=500 kHz, oscillator enabled, and D/A
converter enabled.
IADC is specified with CS, VCCO open and I/O, SCLK at logic zero. A/D converter is enabled.
ICCS is specified with CS, VCCO open and I/O, SCLK at logic zero. A/D converter is disabled.
CS has a 40 kΩ pull-down resistor to ground.
Measured at VIH =2.0V or VIL =0.8V and 10 ns maximum rise and fall time.
Measured at VOH =2.4V or VOL =0.4V.
Load capacitance = 50 pF.
ICCO =100 mA, VCC > VCCTP.
VCCO switchover from VCC to VBAT occurs when VCC drops below the lower of VCCSW and VBAT.
Current from VCC input pin to VCCO output pin.
Current from VBAT input pin to VCCO output pin.
Time base is generated by very accurate crystal oscillator. Accuracy of this time period is based on
the crystal that is used. A typical crystal with a specified load capacitance of 6 pF will provide an
accuracy within ±100 ppm over the 0°C to 70°C temperature range.
If the EOSC bit in the Control Register is set to a logic 1, tRPU is equal to 250 ms plus the start-up
time of the crystal oscillator.
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