MM54HC242/MM74HC242 Inverting Quad TRI-STATEÉ Transceiver MM54HC243/MM74HC243 Quad TRI-STATE Transceiver General Description These TRI-STATE bidirectional inverting and non-inverting buffers utilize advanced silicon-gate CMOS technology and are intended for two-way asynchronous communication between data buses. They have high drive current outputs which enable high speed operation when driving large bus capacitances. These circuits possess the low power dissipation and high noise immunity associated with CMOS circuits, but speeds comparable to low power Schottky TTL circuits. They can also drive 15 LS-TTL loads. The MM54HC243/MM74HC243 is a non-inverting buffer and the MM54HC242/MM74HC242 is an inverting buffer. Each device has one active high enable (GBA), and one active low enable (GAB). GBA enables the A outputs and GAB enables the B outputs. This device does not have Schmitt trigger inputs. All inputs are protected from damage due to static discharge by diodes to VCC and ground. Features Y Y Y Y Y Y Typical propagation delay: 12 ns TRI-STATE outputs Two way asynchronous communication High output current: 6 mA (74HC) Wide power supply range: 2 – 6V Low quiescent supply current: 80 mA (74HC) Connection Diagrams Dual-In-Line Package Dual-In-Line Package TL/L/5019 – 1 Top View Order Number MM54HC242 or MM74HC242 TL/L/5019 – 2 Top View Order Number MM54HC243 or MM74HC243 Truth Tables ’HC242 ’HC243 Control Inputs Data Port Status Control Inputs Data Port Status GAB GBA A B GAB GBA A B H L H L H H L L OUTPUT Isolated Isolated Input Input Isolated Isolated OUTPUT H L H L H H L L OUTPUT Isolated Isolated Input Input Isolated Isolated OUTPUT TRI-STATEÉ is a registered trademark of National Semiconductor Corp. C1995 National Semiconductor Corporation TL/L/5019 RRD-B30M115/Printed in U. S. A. MM54HC242/MM74HC242 Inverting Quad TRI-STATE Transceiver MM54HC243/MM74HC243 Quad TRI-STATE Transceiver January 1988 Absolute Maximum Ratings (Notes 1 & 2) Operating Conditions If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Supply Voltage (VCC) Supply Voltage (VCC) DC Input or Output Voltage (VIN, VOUT) Operating Temp. Range (TA) MM74HC MM54HC Input Rise or Fall Times (tr, tf) VCC e 2.0V VCC e 4.5V VCC e 6.0V b 0.5 to a 7.0V b 1.5 to VCC a 1.5V DC Input Voltage (VIN) b 0.5 to VCC a 0.5V DC Output Voltage (VOUT) g 20 mA Clamp Diode Current (IIK, IOK) g 35 mA DC Output Current, per pin (IOUT) g 70 mA DC VCC or GND Current, per pin (ICC) b 65§ C to a 150§ C Storage Temperature Range (TSTG) Power Dissipation (PD) (Note 3) 600 mW S.O. Package only 500 mW Lead Temp. (TL) (Soldering 10 seconds) 260§ C Min 2 0 Max 6 VCC Units V V b 40 b 55 a 85 a 125 §C §C 1000 500 400 ns ns ns DC Electrical Characteristics (Note 4) Symbol Parameter Conditions VCC TA e 25§ C 74HC TA eb40 to 85§ C Typ 54HC TA eb55 to 125§ C Units Guaranteed Limits VIH Minimum High Level Input Voltage 2.0V 4.5V 6.0V 1.5 3.15 4.2 1.5 3.15 4.2 1.5 3.15 4.2 V V V VIL Maximum Low Level Input Voltage** 2.0V 4.5V 6.0V 0.5 1.35 1.8 0.5 1.35 1.8 0.5 1.35 1.8 V V V VOH Minimum High Level Output Voltage VIN e VIH or VIL lIOUTl s20 mA 2.0V 4.5V 6.0V 2.0 4.5 6.0 1.9 4.4 5.9 1.9 4.4 5.9 1.9 4.4 5.9 V V V 4.5V 6.0V 4.2 5.7 3.98 5.48 3.84 5.34 3.7 5.2 V V 2.0V 4.5V 6.0V 0 0 0 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 V V V VIN e VIH or VIL lIOUTl s6.0 mA lIOUTl s7.8 mA 4.5V 6.0V 0.2 0.2 0.26 0.26 0.33 0.33 0.4 0.4 V V VIN e VIH or VIL lIOUTl s6.0 mA lIOUTl s7.8 mA VOL Maximum Low Level Output Voltage VIN e VIH or VIL lIOUTl s20 mA IIN Maximum Input Current VIN e VCC or GND 6.0V g 0.1 g 1.0 g 1.0 mA IOZ Maximum TRI-STATE Output Leakage Current VOUT e VCC or GND GAB e VIH, GBA e VIL 6.0V g 0.5 g 5.0 g 10 mA ICC Maximum Quiescent Supply Current VIN e VCC or GND IOUT e 0 mA 6.0V 8.0 80 160 mA Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur. Note 2: Unless otherwise specified all voltages are referenced to ground. Note 3: Power Dissipation temperature derating Ð plastic ‘‘N’’ package: b 12 mW/§ C from 65§ C to 85§ C; ceramic ‘‘J’’ package: b 12 mW/§ C from 100§ C to 125§ C. Note 4: For a power supply of 5V g 10% the worst case output voltages (VOH, and VOL) occur for HC at 4.5V. Thus the 4.5V values should be used when designing with this supply. Worst case VIH and VIL occur at VCC e 5.5V and 4.5V respectively. (The VIH value at 5.5V is 3.85V.) The worst case leakage current (IIN, ICC, and IOZ) occur for CMOS at the higher voltage and so the 6.0V values should be used. **VIL limits are currently tested at 20% of VCC. The above VIL specification (30% of VCC) will be implemented no later than Q1, CY’89. 2 AC Electrical Characteristics (MM54HC242/MM74HC242) VCC e 5V, TA e 25§ C, tr e tf e 6 ns Symbol Parameter Conditions Typ Guaranteed Limit tPHL, tPLH Maximum Propagation Delay CL e 45 pF 12 18 Units ns tPZH, tPZL Maximum Output Enable Time to Active Output RL e 1kX CL e 45 pF 17 28 ns tPHZ, tPHL Maximum Output Disable Time from Active Output RL e 1 kX CL e 5 pF 15 25 ns AC Electrical Characteristics (MM54HC242/MM74HC242, MM54HC243/MM74HC243) VCC e 2.0V to 6.0V, CL e 50 pF, tr e tf e 6 ns (unless otherwise specified) TA e 25§ C Symbol Parameter Conditions VCC Typ tPHL, tPLH tPZH, tPZL Maximum Propagation Delay Maximum Output Enable Time to Active Output tPHZ, tPLZ Maximum Output Disable Time from Active Output tTLH, tTHL Maximum Output Rise and Fall Time CPD Power Dissipation Capacitance (Note 5) 74HC TA eb40 to 85§ C 54HC TA eb55 to 125§ C Units Guaranteed Limits CL e 50 pF CL e 150 pF 2.0V 2.0V 55 80 100 150 126 190 149 224 ns ns CL e 50 pF CL e 150 pF 4.5V 4.5V 12 22 20 30 25 38 30 45 ns ns CL e 50 pF CL e 150 pF 6.0V 6.0V 11 18 17 26 21 32 25 38 ns ns RL e 1 kX CL e 50 pF CL e 150 pF 2.0V 2.0V 75 100 150 200 189 252 224 298 ns ns CL e 50 pF CL e 150 pF 4.5V 4.5V 15 30 30 40 38 50 45 60 ns ns CL e 50 pF CL e 150 pF 6.0V 6.0V 13 17 26 34 32 43 38 51 ns ns RL e 1 kX CL e 50 pF 2.0V 4.5V 6.0V 75 15 13 150 30 26 189 38 32 224 45 38 ns ns ns 60 12 10 75 15 13 90 18 15 ns ns ns 2.0V 4.5V 6.0V (per buffer) Outputs Disabled Outputs Enabled 12 50 pF pF CIN Maximum Input Capacitance 5 10 10 10 pF COUT Maximum Output Capacitance 10 20 20 20 pF Note 5: CPD determines the no load dynamic power consumption, PD e CPD VCC2 f a ICC VCC, and the no load dynamic current consumption, IS e CPD VCC f a ICC. 3 Logic Diagrams MM54HC242/MM74HC242 MM54HC243/MM74HC243 TL/L/5019 – 4 TL/L/5019 – 3 4 5 MM54HC242/MM74HC242 Inverting Quad TRI-STATE Transceiver MM54HC243/MM74HC243 Quad TRI-STATE Transceiver Physical Dimensions inches (millimeters) Cavity Dual-In Line Package (J) Order Number MM54HC242J, MM54HC243J, MM74HC242J or MM74HC243J NS Package Number J14A LIFE SUPPORT POLICY Molded Dual-In Line Package (N) Order Number MM74HC242N or MM74HC243N NS Package Number N14A NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. 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