LINER LTM9002CV-AA 14-bit dual-channel if/baseband receiver subsystem Datasheet

LTM9002
14-Bit Dual-Channel IF/
Baseband Receiver Subsystem
FEATURES
DESCRIPTION
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The LTM®9002 is a 14-bit dual-channel IF receiver subsystem. Utilizing an integrated system in a package (SiP)
technology, it includes a dual high-speed 14-bit A/D converter, matching network, anti-aliasing filter and two low
noise, differential amplifiers. It is designed for digitizing
wide dynamic range signals with an intermediate frequency
(IF) up to 300MHz. The amplifiers allow either AC- or DCcoupled input drive. Lowpass or bandpass filter networks
can be implemented with various bandwidths. Contact
Linear Technology regarding customization.
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Integrated Dual 14-Bit, High-Speed ADC, Passive
Filters and Fixed Gain Differential Amplifiers
Up to 300MHz IF Range
Lowpass and Bandpass Filter Versions
Integrated Low Noise, Low Distortion Amplifiers
Fixed Gain: 8dB, 14dB, 20dB or 26dB
50Ω, 200Ω or 400Ω Input Impedance
Integrated Bypass Capacitance, No External
Components Required
66dB SNR Up to 140MHz Input (LTM9002-AA)
76dB SFDR Up to 140MHz Input (LTM9002-AA)
Auxiliary 12-Bit DACs for Gain Adjustment
Clock Duty Cycle Stabilizer
Single 3V to 3.3V Supply
Low Power: 1.3W (665mW/ch.)
Shutdown and Nap Modes
15mm × 11.25mm LGA Package
APPLICATIONS
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Telecommunications
Direct Conversion Receivers
Main and Diversity Receivers
Cellular Base Stations
The LTM9002 is perfect for demanding communications
applications, with AC performance that includes 66dB SNR
and 76dB spurious free dynamic range (SFDR). Auxiliary
DACs allow gain balancing between channels.
A single 3V supply allows low power operation. A separate
output supply allows the outputs to drive 0.5V to 3.3V logic.
An optional multiplexer allows both channels to share a
digital output bus. Two single-ended CLK inputs can be
driven together or independently. An optional clock duty
cycle stabilizer allows high performance at full speed for
a wide range of clock duty cycles.
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
TYPICAL APPLICATION
Dual Channel IF Receiver
VCC = 3V
64k Point FFT, fIN = 15MHz, –1dBFS,
SENSE = VDD, Channel A (LTM9002-LA)
VDD
0
OVDD
0.5V TO 3.6V
VREF
–10
–20
MAIN
RF
SAW
INA–
14-BIT
125Msps ADC
FILTER
LO
CLKOUT
DAC
ADC CLK
SPI
MUX
OF
DIFFERENTIAL
AMPLIFIERS
DAC
SAW
INB–
–40
–50
–60
–70
–80
–90
–100
INB+
DIVERSITY
RF
AMPLITUDE (dBFS)
–30
INA+
–110
14-BIT
125Msps ADC
FILTER
–120
LO
9002 TA01
OGND
0
5
10
15
20
25
FREQUENCY (MHz)
30
9002 TA01b
GND
9002f
1
LTM9002
ABSOLUTE MAXIMUM RATINGS
PIN CONFIGURATION
(Notes 1, 2)
Supply Voltage (VCC) ................................ –0.3V to 3.6V
Supply Voltage (VDD, OVDD)......................... –0.3V to 4V
Digital Output Ground Voltage (OGND) ........ –0.3V to 1V
Input Current (IN+, IN–)........................................±10mA
DAC Digital Input Voltage
(CS/LD, SDI, SCK) ................................... –0.3V to 6V
Digital Input Voltage
(Except AMPSHDN) ................. –0.3V to (VDD + 0.3V)
Digital Input Voltage
(AMPSHDN)..............................–0.3V to (VCC + 0.3V)
Digital Output Voltage ................–0.3V to (OVDD + 0.3V)
Operating Temperature Range
LTM9002C................................................ 0°C to 70°C
LTM9002I.............................................–40°C to 85°C
Storage Temperature Range...................–65°C to 125°C
SENSEB SENSEA
ALL OTHERS = GND
J
INA+
H
INA–
G
F
VCC
E
D
INB–
C
INB+
B
A
1
2
3
4
CLKA CLKB
5
6
7
CONTROL
8
9
10
11
OVDD
OGND
VDD
OGND
OVDD
12
DATA
LGA PACKAGE
108-LEAD (15mm × 11.25mm × 2.32mm)
TJMAX = 125°C, θJA = 19°C/W, θJCTOP = 16°C/W, θJCBOT = 6°C/W
θJA DERIVED FROM 101.5mm × 114.5mm PCB WITH 4 LAYERS
WEIGHT = 0.935g
ORDER INFORMATION
LEAD FREE FINISH
TRAY
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTM9002CV-AA#PBF
LTM9002CV-AA#PBF
LTM9002VAA
108-Lead (15mm × 11.25mm × 2.3mm) LGA
0°C to 70°C
LTM9002CV-LA#PBF
LTM9002CV-LA#PBF
LTM9002VLA
108-Lead (15mm × 11.25mm × 2.3mm) LGA
0°C to 70°C
LTM9002IV-AA#PBF
LTM9002IV-AA#PBF
LTM9002VAA
108-Lead (15mm × 11.25mm × 2.3mm) LGA
–40°C to 85°C
LTM9002IV-LA#PBF
LTM9002IV-LA#PBF
LTM9002VLA
108-Lead (15mm × 11.25mm × 2.3mm) LGA
–40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
This product is only offered in trays. For more information go to: http://www.linear.com/packaging/
9002f
2
LTM9002
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. Unless otherwise noted. (Note 3)
SYMBOL
PARAMETER
CONDITIONS
GDIFF
Gain
DC, LTM9002-AA
fIN = 140MHz
Channel A, DC (LTM9002-LA)
fIN = 15MHz
Channel B, DC (LTM9002-LA)
fIN = 15MHz
GTEMP
VIN
MIN
TYP
MAX
l
25
26
25
27
dB
dB
l
19.4
20.6
l
7.5
20
19
8
7
dB
dB
dB
dB
8.5
UNITS
Gain Temperature Drift
VIN = MAX, (Note 3)
1.5
Gain Matching
External Reference
5
Input Voltage Range for –1dBFS
Both Channels, fIN = 140MHz (LTM9002-AA)
100
mVP-P
Channel A, fIN = 15MHz (LTM9002-LA)
200
mVP-P
Channel B, fIN = 15MHz (LTM9002-LA)
VINCM
Input Common Mode Voltage Range
RINDIFF
Differential Input Impedance
mdB
800
1
mVP-P
1.5
V
Both Channels (LTM9002-AA)
50
Ω
Channel A (LTM9002-LA)
Channel B (LTM9002-LA)
200
400
Ω
Ω
1
pF
CINDIFF
Differential Input Capacitance
Includes Parasitic
VOS
Offset Error (Note 5)
Including Amplifier and ADC
l
–5
Offset Matching
Offset Drift
mdB/°C
Including Amplifier and ADC
0.3
5
mV
0.3
mV
±10
μV/°C
50
dB
CMRR
Common Mode Rejection Ratio
ISENSE
SENSE Input Leakage
0V < SENSE < 1V
l
–3
3
μA
IMODE
MODE Input Leakage
0V < MODE < VDD
l
–3
3
μA
tAP
Sample and Hold Acquisition Delay Time
tJITTER
Sample-and-Hold Acquisition Delay Time Jitter
0
ns
0.2
psRMS
CONVERTER CHARACTERISTICS
The l indicates specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 3)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Resolution (No Missing Codes)
LTM9002-AA
l
14
Bits
LTM9002-LA
l
12
Bits
ADC Characteristics
INL
DNL
Integral Linearity Error (Note 4)
Differential Linearity Error
LTM9002-AA
±1.5
LSB
LTM9002-LA
±0.3
LSB
LTM9002-AA
l
–1
±0.6
1
LSB
LTM9002-LA
l
–1
±0.2
1
LSB
9002f
3
LTM9002
DYNAMIC ACCURACY
The l indicates specifications which apply over the full operating temperature range,
otherwise specifications are at TA = 25°C. Input = –1dBFS. (Note 3)
SYMBOL
PARAMETER
CONDITIONS
SNR
Signal-to-Noise Ratio
70MHz Input (Both Channels), LTM9002-AA
140MHz Input (Both Channels), LTM9002-AA
SFDR
SFDR
S/(N+D)
IMD3
Spurious Free Dynamic Range, 2nd or 3rd
Harmonic
Spurious Free Dynamic Range 4th or Higher
Signal-to-Noise Plus Distortion Ratio
Third Order Inter-Modulation Distortion;
1MHz Tone Spacing, Two Tones –7dBFS
Crosstalk
MIN
TYP
MAX
UNITS
l
61.5
66
66
dBFS
dBFS
15MHz Input (Channel A), LTM9002-LA
15MHz Input (Channel B), LTM9002-LA
l
l
67.7
68.5
69.9
71.1
dBFS
dBFS
70MHz Input (Both Channels), LTM9002-AA
140MHz Input (Both Channels), LTM9002-AA
l
67.5
82
76
dBc
dBc
15MHz Input (Channel A), LTM9002-LA
15MHz Input (Channel B), LTM9002-LA
l
l
75
72.7
86.2
85.5
dBc
dBc
70MHz Input (Both Channels), LTM9002-AA
140MHz Input (Both Channels), LTM9002-AA
l
74.2
90
90
dBc
dBc
15MHz Input (Channel A), LTM9002-LA
15MHz Input (Channel B), LTM9002-LA
l
l
78.8
79.8
88.5
90.7
dBc
dBc
70MHz Input (Both Channels), LTM9002-AA
140MHz Input (Both Channels), LTM9002-AA
l
60.7
66
66
dBFS
dBFS
15MHz Input (Channel A), LTM9002-LA
15MHz Input (Channel B), LTM9002-LA
l
l
67.1
67.9
69.7
70.8
dBFS
dBFS
70MHz Input, LTM9002-AA
140MHz Input, LTM9002-AA
77
73
dBc
dBc
15MHz Input, LTM9002-LA
77
dBc
140MHz Input, LTM9002-AA
–110
dB
15MHz Input, LTM9002-LA
–110
dB
AUXILIARY DAC CHARACTERISTICS
The l indicates specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Not applicable for LTM9002-LA) (Note 3)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Resolution
l
12
Bits
Monotonicity
l
12
Bits
Full-Scale Range
Internal Reference
1.5
V
Settling Time
±0.024% (±1LSB at 12 Bits),
No External Sense Capacitor
83.5
μs
DIGITAL INPUTS AND OUTPUTS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Logic Inputs (CLK, OE, ADCSHDN, MUX, CS/LD, SCK, SDI)
VIH
High Level Input Voltage
VDD = 3V
l
VIL
Low Level Input Voltage
VDD = 3V
l
IIN
Input Current
VIN = 0V to VDD
l
CIN
Input Capacitance
(Note 6)
2
V
–10
3
0.8
V
10
μA
pF
9002f
4
LTM9002
DIGITAL INPUTS AND OUTPUTS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Logic Inputs (AMPSHDN)
VIL
Low Level Input Voltage
l
VIH
High Level Input Voltage
l
IIL
Input Low Current
AMPSHDN = 0.8V
l
IIH
Input High Current
AMPSHDN = 2.4V
l
COZ
Hi-Z Output Capacitance
OE = 3V (Note 6)
3
pF
ISOURCE
Output Source Current
VOUT = 0V
50
mA
ISINK
Output Sink Current
VOUT = 3V
50
mA
VOH
High Level Output Voltage
IO = –10μA
IO = –200μA
l
IO = 10μA
IO = 1.6mA
l
0.8
V
2.4
V
1.4
0.5
μA
3
μA
Logic Outputs
OVDD = 3V
Low Level Output Voltage
VOL
2.7
2.995
2.99
0.005
0.09
V
V
V
V
0.4
OVDD = 2.5V
VOH
High Level Output Voltage
IO = –200μA
2.49
V
VOL
Low Level Output Voltage
IO = 1.6mA
0.09
V
VOH
High Level Output Voltage
IO = –200μA
1.79
V
VOL
Low Level Output Voltage
IO = 1.6mA
0.1
V
OVDD = 1.8V
POWER REQUIREMENTS
The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 7)
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
VCC
Amplifier and Auxiliary DAC
Operating Supply Range
l
2.85
3.0
3.4
V
VDD
ADC Analog Supply Voltage
l
2.85
3.0
3.5
V
OVDD
Output Supply Voltage
l
0.5
ICC
Amplifier
ICC(SHDN) Amplifier Shutdown Supply Current
IDD(ADC)
ADC Supply Current
3.0
3.6
V
DAC Powered Up, Both Amplifiers Enabled, LTM9002-AA
l
180
207
mA
Both Amplifiers Enabled, LTM9002-LA
l
90
120
mA
AMPSHDN = 3V, DAC Powered Down
0.7
mA
LTM9002-AA
l
263
313
LTM9002-LA
l
140
159
mA
mA
PD(SHDN) ADC Shutdown Power (Each Channel) ADCSHDN = AMPSHDN = 3V, OE = 3V, No CLK
2
mW
PD(NAP)
ADC Nap Mode Power (Each Channel) ADCSHDN = AMPSHDN = 3V, OE = 0V, No CLK
15
mW
PD(AMP)
Amplifier Power Dissipation
540
mW
PD(ADC)
ADC Power Dissipation
DAC Powered Up, LTM9002-AA
LTM9002-LA
PD(TOTAL) Total Power Dissipation
270
mW
LTM9002-AA
l
790
939
mW
LTM9002-LA
l
420
477
mW
fSAMPLE = MAX, LTM9002-AA
fSAMPLE = MAX, LTM9002-LA
1329
690
mW
mW
9002f
5
LTM9002
TIMING CHARACTERISTICS
The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 6) (Not applicable for LTM9002-LA)
SYMBOL
PARAMETER
fS
Sampling Frequency
CONDITIONS
MIN
TYP
MAX
UNITS
LTM9002-AA
l
1
125
MHz
LTM9002-LA
l
1
65
MHz
tL
CLK Low Time
Duty Cycle Stabilizer Off (Note 6), LTM9002-AA
Duty Cycle Stabilizer On (Note 6), LTM9002-AA
l
l
3.8
3
4
4
500
500
ns
ns
tH
CLK High Time
Duty Cycle Stabilizer Off (Note 6), LTM9002-AA
Duty Cycle Stabilizer On (Note 6), LTM9002-AA
l
l
3.8
3
4
4
500
500
ns
ns
tL
CLK Low Time
Duty Cycle Stabilizer Off (Note 6), LTM9002-LA
Duty Cycle Stabilizer On (Note 6), LTM9002-LA
l
l
7.3
5
7.7
7.7
500
500
ns
ns
tH
CLK High Time
Duty Cycle Stabilizer Off (Note 6), LTM9002-LA
Duty Cycle Stabilizer On (Note 6), LTM9002-LA
l
l
7.3
5
7.7
7.7
500
500
ns
ns
tAP
Absolute Aperture Delay
0
ns
tD
CLK to DATA Delay
CL = 5pF (Note 6)
l
1.4
2.7
5.4
ns
tC
CLK to CLKOUT Delay
CL = 5pF (Note 6)
l
1.4
2.7
5.4
ns
DATA to CLKOUT Skew
(tD – tC) (Note 6)
l
–0.6
0
0.6
ns
MUX to DATA Delay
CL = 5pF (Note 6)
l
1.4
2.7
5.4
ns
DATA Access Time After OE↓
CL = 5pF (Note 6)
l
4.3
10
ns
(Note 6)
l
3.3
8.5
tMD
BUS Relinquish Time
Pipeline Latency
5
ns
Cycles
SPI Interface for Aux DACs, VDD = 2.7V to 3.6V
t1
SDI Valid to SCK Setup
4
ns
t2
SDI Valid to SCK Hold
4
ns
t3
SCK High Time
9
ns
t4
SCK Low Time
9
ns
t5
CS/LD Pulse Width
10
ns
t6
LSB SCK High to CS/LD
7
ns
t7
CS/LD Low to SCK High
7
ns
t10
CS/LD High to SCK Positive Edge
7
ns
SCK Frequency 50% Duty Cycle
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All voltage values are with respect to ground with GND and OGND
wired together (unless otherwise noted).
Note 3: OVDD = VCC = VDD = 3V, fSAMPLE = MAX, input range = VIN
with differential drive, CLKA = CLKB, VINCM = 1.25V, AMPSHDN =
ADCSHDN = 0V, unless otherwise noted.
50
MHz
Note 4: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 5: Offset error is the output code resulting when the inputs are
shorted together. The output code is converted to millivolts.
Note 6: Guaranteed by design, not subject to test.
Note 7: VDD = 3V, fSAMPLE = MAX, input range = VIN with differential drive.
The supply current and power dissipation are the sum total for both
channels with both channels active.
9002f
6
LTM9002
TIMING DIAGRAMS
Dual Digital Output Bus Timing
tAP
ANALOG
INPUT
N+4
N+2
N
N+1
tH
N+3
N+5
tL
CLKA = CLKB
tD
N–4
N–5
D0-D13, OF
N–3
N–2
N–1
N
tC
CLKOUT
9002 TD01
Multiplexed Digital Output Bus Timing
tAPA
ANALOG
INPUT A
A+4
A+2
A
A+1
A+3
tAPB
ANALOG
INPUT B
B+4
B+2
B
B+1
tH
tL
A–5
B–5
B+3
CLKA = CLKB = MUX
DA0-DA13
A–4
tD
DB0-DB13
B–5
B–4
A–3
B–3
A–2
B–2
A–1
B–3
A–3
B–2
A–2
B–1
tMD
A–5
B–4
A–4
tC
CLKOUT
9002 TD02
9002f
7
LTM9002
TIMING DIAGRAMS
Auxiliary DAC Timing
t1
t2
SCK
t3
1
t6
t4
2
3
23
24
t10
SDI
C3
t5
C2
C1
D1
D0
t7
CS/LD
9002 TD03
TYPICAL PERFORMANCE CHARACTERISTICS
(LTM9002-AA)
Differential Non-Linearity (DNL)
vs Output Code
Integral Non-Linearity (INL),
Best Fit vs Output Code
1.0
4.0
0.8
3.0
71
70
0.6
2.0
0.2
0
–0.2
–0.4
69
1.0
SNR (dB)
0.4
INL ERROR (LSB)
DNL ERROR (LSB)
SNR vs Frequency
72
0
–1.0
–0.8
–3.0
–1.0
–4.0
8192
12288
OUTPUT CODE
16384
63
62
0
4096
8192
12288
OUTPUT CODE
Input Impedance vs Frequency
10
0
9
–2
8
7
40
6
35
5
30
4
25
3
20
2
PHASE
9002 G03
1
–8
–10
–12
–14
–16
0
5
–1
–18
0
–2
1000
–20
10
100
FREQUENCY (MHz)
1000
–6
10
1
10
100
IF FREQUENCY (MHz)
–4
AMPLITUDE (dBFS)
45
IMPEDANCE PHASE (DEG)
IMPEDANCE MAGNITUDE (Ω)
MAGNITUDE
15
1
IF Frequency Response
60
50
16384
9002 G02
9002 G01
55
66
64
–0.6
4096
67
65
–2.0
0
68
9002 G04
1
10
100
IF FREQUENCY (MHz)
1000
9002 G05
9002f
8
LTM9002
TYPICAL PERFORMANCE CHARACTERISTICS
(LTM9002-AA)
64k Point 2-Tone FFT,
fIN = 70MHz and fIN = 74MHz,
–7dBFS Per Tone, SENSE = VDD
0
0
–10
–10
–20
–20
–30
–30
AMPLITUDE (dBFS)
AMPLITUDE (dBFS)
64k Point FFT, fIN = 70MHz,
–1dBFS, SENSE = VDD
–40
–50
–60
–70
–80
–40
–50
–60
–70
–80
–90
–90
–100
–100
–110
–110
–120
0
10
20
30
40
50
FREQUENCY (MHz)
–120
60
0
10
20
30
40
50
FREQUENCY (MHz)
9002 G06
64k Point 2-Tone FFT,
fIN = 136MHz and fIN = 140MHz,
–7dBFS Per Tone, SENSE = VDD
0
0
–10
–10
–20
–20
–30
–30
AMPLITUDE (dBFS)
AMPLITUDE (dBFS)
64k Point FFT, fIN = 140MHz,
–1dBFS, SENSE = VDD
–40
–50
–60
–70
–80
–40
–50
–60
–70
–80
–90
–90
–100
–100
–110
–110
–120
–120
0
10
60
9002 G07
20
30
40
50
FREQUENCY (MHz)
60
0
10
20
30
40
50
FREQUENCY (MHz)
60
9002 G09
9002 G08
(LTM9002-LA)
Integral Non-Linearity (INL),
Best Fit vs Output Code
SNR vs Frequency (Channel A)
0.5
72
0.8
0.4
71
0.6
0.3
70
0.4
0.2
69
0.1
68
0.2
0
–0.2
SNR (dB)
1.0
INL ERROR (LSB)
DNL ERROR (LSB)
Differential Non-Linearity (DNL)
vs Output Code
0
–0.1
67
66
–0.2
65
–0.6
–0.3
64
–0.8
–0.4
63
–1.0
–0.5
–0.4
0
1024
2048
3072
OUTPUT CODE
4096
9002 G10
0
1024
2048
3072
OUTPUT CODE
4096
9002 G11
62
1
10
IF FREQUENCY (MHz)
100
9002 G12
9002f
9
LTM9002
TYPICAL PERFORMANCE CHARACTERISTICS
Input Impedance vs Frequency
(Channel A)
SNR vs Frequency (Channel B)
72
MAGNITUDE
175
IMPEDANCE MAGNITUDE (Ω)
69
68
67
66
65
64
7
150
6
125
5
100
4
75
3
50
2
PHASE
25
63
1
10
IF FREQUENCY (MHz)
100
0
1
1
0
1000
10
100
FREQUENCY (MHz)
9002 G13
Input Impedance vs Frequency
(Channel B)
32
20
200
16
150
12
100
8
PHASE
50
4
0
0
1000
10
100
FREQUENCY (MHz)
–20
–30
–4
AMPLITUDE (dBFS)
250
–2
AMPLITUDE (dBFS)
24
0
–10
28
MAGNITUDE
1
64k Point FFT, fIN = 15MHz,
–1dBFS, SENSE = VDD (Channel A)
0
IMPEDANCE PHASE (DEG)
IMPEDANCE MAGNITUDE (Ω)
350
300
9002 G14
IF Frequency Response
400
–6
–8
–10
–50
–60
–70
–80
–90
–12
–100
–14
0.1
1
10
IF FREQUENCY (MHz)
–120
100
64k Point 2-Tone FFT, fIN = z and fIN
= 15MHz, –7dBFS Per Tone,
SENSE = VDD (Channel A)
–20
–20
–20
–30
–30
–30
–80
AMPLITUDE (dBFS)
0
–10
AMPLITUDE (dBFS)
0
–10
–70
–40
–50
–60
–70
–80
–60
–70
–80
–90
–100
–100
–100
–100
–100
–100
–120
–120
10
15
20
25
FREQUENCY (MHz)
30
35
9002 G18
0
5
10
15
20
25
FREQUENCY (MHz)
30
35
9002 G19
35
–50
–90
5
30
–40
–90
0
10
15
20
25
FREQUENCY (MHz)
64k Point 2-Tone FFT, fIN = 14MHz
and fIN = 15MHz, –7dBFS Per Tone,
SENSE = VDD (Channel B)
0
–60
5
9002 G17
–10
–50
0
9002 G16
64k Point FFT, fIN = 15MHz,
–1dBFS, SENSE = VDD (Channel B)
AMPLITUDE (dBFS)
–40
–100
9002 G15
–40
IMPEDANCE PHASE (DEG)
70
SNR (dB)
8
200
71
62
(LTM9002-LA)
–120
0
5
10
15
20
25
FREQUENCY (MHz)
30
35
9002 G20
9002f
10
LTM9002
PIN FUNCTIONS
Supply Pins
GND (Pins A1-2, A5-7, B2-4, B6, C2-3, C6, D1-3, D5-7,
D9-10, E5-6, E9-10, F1-2, F5-7, F9-10, G2-3, G6, H2-4,
H6, J1-2, J5-7): ADC Power Ground.
OGND (Pins A12, C9, G9, J12): Output Driver Ground.
OVDD (Pins B12, H12): Positive supply for the ADC output
drivers. The specified operating range is 0.5V to 3.6V. OVDD
is internally bypassed to OGND.
VCC (Pins E3, E4): Amplifier and Auxiliary DAC Power Supply. The specified operating range is 2.85V to 3.465V. The
voltage on this pin provides power for the amplifier stage
and auxiliary DACs only and is internally bypassed to GND.
Note that LTM9002-LA does not have auxiliary DACs.
VDD (Pins E7, E8): Analog 3V Supply for ADC. The specified
operating range is 2.7V to 3.6V. VDD is internally bypassed
to GND.
Analog Inputs
CLKA (Pin A3): Channel A ADC Clock Input. The input
sample starts on the positive edge.
CLKB (Pin A4): Channel B ADC Clock Input. The input
sample starts on the positive edge.
DNC1 (Pin H5): Do Not Connect. These pins are used for
testing and should not be connected on the PCB. They
should be soldered to unconnected pads and should be
well isolated. The DNC pins connect to the signal path
prior to the ADC inputs; therefore, care should be taken
to keep other signals away from these sensitive nodes.
DNC1 connects near the channel A positive differential
analog input.
DNC2 (Pin G5): Do Not Connect. These pins are used for
testing and should not be connected on the PCB. They
should be soldered to unconnected pads and should be
well isolated. The DNC pins connect to the signal path
prior to the ADC inputs; therefore, care should be taken
to keep other signals away from these sensitive nodes.
DNC2 connects near the channel A negative differential
analog input.
DNC3 (Pin C5): Do Not Connect. These pins are used for
testing and should not be connected on the PCB. They
should be soldered to unconnected pads and should be
well isolated. The DNC pins connect to the signal path
prior to the ADC inputs; therefore, care should be taken
to keep other signals away from these sensitive nodes.
DNC3 connects near the channel B positive differential
analog input.
DNC4 (Pin B5): Do Not Connect. These pins are used for
testing and should not be connected on the PCB. They
should be soldered to unconnected pads and should be
well isolated. The DNC pins connect to the signal path
prior to the ADC inputs; therefore, care should be taken
to keep other signals away from these sensitive nodes.
DNC4 connects near the channel B negative differential
analog input.
DNC5 (Pin G4): Do Not Connect. This pin is used for testing and should not be connected on the PCB. It should
be soldered to an unconnected pad and should be well
isolated. This is a test point for the auxiliary DAC channel A
voltage output.
DNC6 (Pin C4): Do Not Connect. This pin is used for testing and should not be connected on the PCB. It should
be soldered to an unconnected pad and should be well
isolated. This is a test point for the auxiliary DAC channel B
voltage output.
INA– (Pin G1): Channel A Negative (Inverting) Amplifier
Input.
INA+ (Pin H1): Channel A Positive (Noninverting) Amplifier Input.
INB– (Pin C1): Channel B Negative (Inverting) Amplifier
Input.
INB+ (Pin B1): Channel B Positive (Noninverting) Amplifier Input.
9002f
11
LTM9002
PIN FUNCTIONS
Control Pins
ADCSHDNA (Pin G7): Channel A Shutdown Mode Selection Pin. Connecting ADCSHDNA to GND and OEA to GND
results in normal operation with the outputs enabled.
Connecting ADCSHDNA to GND and OEA to VDD results
in normal operation with the outputs at high impedance.
Connecting ADCSHDNA to VDD and OEA to GND results in
nap mode with the outputs at high impedance. Connecting
ADCSHDNA to VDD and OEA to VDD results in sleep mode
with the outputs at high impedance.
ADCSHDNB (Pin C7): Channel B Shutdown Mode Selection Pin. Connecting ADCSHDNB to GND and OEB to GND
results in normal operation with the outputs enabled.
Connecting ADCSHDNB to GND and OEB to VDD results
in normal operation with the outputs at high impedance.
Connecting ADCSHDNB to VDD and OEB to GND results in
nap mode with the outputs at high impedance. Connecting
ADCSHDNB to VDD and OEB to VDD results in sleep mode
with the outputs at high impedance.
AMPSHDNA (Pin E1): Power Shutdown Pin for Channel A
Amplifier. This pin is a logic input referenced to analog
ground. AMPSHDN = low results in normal operation.
AMPSHDN = high results in powered down amplifier with
a <1mA amplifier supply current.
MUX (Pin C8): Digital Output Multiplexer Control. If MUX
= high, channel A comes out on DAx; channel B comes
out on DBx. If MUX = low, the output busses are swapped
and channel A comes out on DBx; channel B comes out
on DAx. To multiplex both channels onto a single output
bus, connect MUX, CLKA and CLKB together.
OEA (Pin F8): Channel A Output Enable Pin. Refer to
ADCSHDNA pin function.
OEB (Pin D8): Channel B Output Enable Pin. Refer to
ADCSHDNB pin function.
SENSEA (Pin J4): Channel A Reference Programming Pin.
Connecting SENSEA to VDD selects the internal reference
and the higher input range. Connecting to 1.5V selects the
lower range. An external reference greater than 0.5V and
less than 1V applied to SENSEA selects an input range of
±VSENSEA/GAIN. See SENSE Pin Operation section.
SENSEB (Pin J3): Channel B Reference Programming Pin.
Connecting SENSEB to VDD selects the internal reference
and the higher input range. Connecting to 1.5V selects the
lower range. An external reference greater than 0.5V and
less than 1V applied to SENSEB selects an input range of
±VSENSEB/GAIN. See SENSE Pin Operation section.
Digital Inputs (Not Connected on LTM9002-LA)
AMPSHDNB (Pin E2): Power Shutdown Pin for Channel B
Amplifier. This pin is a logic input referenced to analog
ground. AMPSHDN = low results in normal operation.
AMPSHDN = high results in powered down amplifier with
a <1mA amplifier supply current.
CS/LD (Pin F3): Serial Interface Chip Select/Load Input
for Auxiliary DAC. When CS/LD is low, SCK is enabled
for shifting data on SDI into the register. When CS/LD is
taken high, SCK is disabled and the specified command
(see Table 3) is executed.
MODE (Pin G8): Output Format and Clock Duty Cycle
Stabilizer Selection Pin. Note that MODE controls both
channels. Connecting MODE to GND selects straight binary
output format and turns the clock duty cycle stabilizer off.
1/3 VDD selects straight binary output format and turns
the clock duty cycle stabilizer on. 2/3 VDD selects 2’s
complement output format and turns the clock duty cycle
stabilizer on. VDD selects 2’s complement output format
and turns the clock duty cycle stabilizer off.
SCK (Pin F4): Serial Interface Clock Input for Auxiliary
DAC. CMOS and TTL compatible.
SDI (Pin D4): Serial Interface Data Input for Auxiliary
DAC. Data is applied to SDI for transfer to the device at
the rising edge of SCK. The auxiliary DAC accepts input
word lengths of either 24 or 32 bits.
9002f
12
LTM9002
PIN FUNCTIONS
Digital Outputs
CLKOUT (Pin E12, LTM9002-AA): ADC Data Ready Clock
Output. Latch data on the falling edge of CLKOUT. CLKOUT
is derived from CLKB. Tie CLKA to CLKB for simultaneous
operation.
OFB (Pin E12, LTM9002-LA): Overflow/Underflow Output.
High when an overflow or underflow has occurred on
channel B.
DA0 – DA13 (Refer to Pin Configuration Table): Channel A
ADC Digital Outputs. DA13 is the MSB for LTM9002-AA;
DA11 is the MSB for LTM9002-LA.
DB0 – DB13 (Refer to Pin Configuration Table): Channel B
ADC Digital Outputs. DB13 is the MSB for LTM9002-AA;
DB11 is the MSB for LTM9002-LA.
OF (Pin H7, LTM9002-AA): Overflow/Underflow Output.
High when an overflow or underflow has occurred on
either channel A or channel B.
OFA (Pin H7, LTM9002-LA): Overflow/Underflow Output.
High when an overflow or underflow has occurred on
channel A.
Pin Configuration (LTM9002-AA)
1
2
3
4
5
6
7
8
9
10
11
12
J
GND
GND
SENSEB
SENSEA
GND
GND
GND
DA8
DA5
DA6
DA7
OGND
H
INA+
GND
GND
GND
DNC1
GND
OF
DA10
DA12
DA11
DA9
OVDD
G
INA–
GND
GND
DNC5
DNC2
GND
ADC
SHDNA
MODE
OGND
DA13
DA4
DA3
F
GND
GND
CS/LD
SCK
GND
GND
GND
OEA
GND
GND
DA2
DA1
E
AMP
SHDNA
AMP
SHDNB
VCC
VCC
GND
GND
VDD
VDD
GND
GND
DA0
CLKOUT
D
GND
GND
GND
SDI
GND
GND
GND
OEB
GND
GND
DB13
DB12
C
INB–
GND
GND
DNC6
DNC3
GND
ADC
SHDNB
MUX
OGND
DB1
DB11
DB10
B
INB+
GND
GND
GND
DNC4
GND
DB0
DB4
DB2
DB3
DB5
OVDD
A
GND
GND
CLKA
CLKB
GND
GND
GND
DB6
DB9
DB8
DB7
OGND
Pin Configuration (LTM9002-LA)
1
2
3
4
5
6
7
8
9
10
11
12
J
GND
GND
SENSEB
SENSEA
GND
GND
GND
DA6
DA3
DA4
DA5
OGND
H
INA+
GND
GND
GND
DNC1
GND
OFA
DA8
DA10
DA9
DA7
OVDD
G
INA–
GND
GND
DNC5
DNC2
GND
ADC
SHDNA
MODE
OGND
DA11
DA2
DA1
F
GND
GND
NC
NC
GND
GND
GND
OEA
GND
GND
DA0
NC
E
AMP
SHDNA
AMP
SHDNB
VCC
VCC
GND
GND
VDD
VDD
GND
GND
NC
OFB
D
GND
GND
GND
NC
GND
GND
GND
OEB
GND
GND
DB11
DB10
C
INB–
GND
GND
DNC6
DNC3
GND
ADC
SHDNB
MUX
OGND
NC
DB9
DB8
B
INB+
GND
GND
GND
DNC4
GND
NC
DB2
DB0
DB1
DB3
OVDD
A
GND
GND
CLKA
CLKB
GND
GND
GND
DB4
DB7
DB6
DB5
OGND
9002f
13
LTM9002
BLOCK DIAGRAM
Functional Block Diagram (Only One Channel is Shown)
VCC
VDD
VCC
VDD
OVDD
PIPELINED ADC SECTIONS
IN+
ADC
DRIVER
FILTER
INPUT
S/H
1st
2nd
3rd
4th
5th
OF*
6th
–
IN
OUTPUT
DRIVERS
CLKOUT*
SHIFT REGISTER AND ERROR CORRECTION
VOLTAGE
REFERENCE
AMPSHDN
D13 … D0
OGND
VOLTAGE
REFERENCE
REFH
REF
BUFFER
DIFF
REF
AMP
INTERNAL
REFL CLOCK SIGNALS
DIFFERENTIAL
INPUT
LOW JITTER
CLOCK DRIVER
CONTROL
LOGIC
DAC
9001 BD
SENSE
*OFA AND OFB ON LTM9002-LA
SDI SCK CS/LD
GND
CLK
MODE ADC
SHDN
OE
9002f
14
LTM9002
OPERATION
DYNAMIC PERFORMANCE DEFINITIONS
The signal-to-noise plus distortion ratio [S/(N + D)] is
the ratio between the RMS amplitude of the fundamental input frequency and the RMS amplitude of all other
frequency components at the ADC output. The output is
band limited to frequencies above DC to below half the
sampling frequency.
If two pure sine waves of frequencies fa and fb are applied to the ADC input, nonlinearities in the ADC transfer
function can create distortion products at the sum and
difference frequencies of mfa ± nfb, where m and n = 0,
1, 2, 3, etc. The 3rd order intermodulation products are
2fa + fb, 2fb + fa, 2fa – fb and 2fb – fa. The intermodulation distortion is defined as the ratio of the RMS value of
either input tone to the RMS value of the largest 3rd order
intermodulation product.
Signal-to-Noise Ratio
Spurious Free Dynamic Range (SFDR)
The signal-to-noise ratio (SNR) is the ratio between the
RMS amplitude of the fundamental input frequency and
the RMS amplitude of all other frequency components
except the first five harmonics and DC.
Spurious free dynamic range is the peak harmonic or spurious noise that is the largest spectral component excluding
the input signal and DC. This value is expressed in decibels
relative to the RMS value of a full-scale input signal.
Total Harmonic Distortion
Aperture Delay Time
Total harmonic distortion is the ratio of the RMS sum
of all harmonics of the input signal to the fundamental
itself. The out-of-band harmonics alias into the frequency
band between DC and half the sampling frequency. THD
is expressed as:
The time from when CLK reaches mid supply to the instant that the input signal is held by the sample and hold
circuit.
Signal-to-Noise Plus Distortion Ratio
THD = 20Log
( V2
2
2
2
+ V3 + V4 +KVn
2
) / V1
where V1 is the RMS amplitude of the fundamental
frequency and V2 through Vn are the amplitudes of the
second through nth harmonics. The THD calculated in this
data sheet uses all the harmonics up to the fifth.
Intermodulation Distortion
If the ADC input signal consists of more than one spectral
component, the ADC transfer function nonlinearity can
produce intermodulation distortion (IMD) in addition to
THD. IMD is the change in one sinusoidal input caused
by the presence of another sinusoidal input at a different
frequency.
Aperture Delay Jitter
The variation in the aperture delay time from conversion
to conversion. This random variation will result in noise
when sampling an AC input. The signal-to-noise ratio due
to the jitter alone will be:
SNRJITTER = –20log (2π) • fIN • tJITTER
Crosstalk
The amount of signal coupled from one channel into the
other. This is measured by applying a full-scale sinusoidal
input on channel A, shorting the inputs of channel B and
taking the ratio of the signal powers in an FFT.
9002f
15
LTM9002
OPERATION
Description
Semi-Custom Options
The LTM9002 is an integrated system in a package (SiP) that
includes two high-speed 14-bit A/D converters, matching
networks, anti-aliasing filters and two low noise, differential amplifiers with fixed gain. These amplifiers need not
be the same, so that the gains and input impedances of
the two channels are different. Also included is a pair of
auxiliary DACs to allow for digital, full-scale adjustment
of each channel. The LTM9002 is designed for digitizing
high frequency, wide dynamic range signals with input
frequencies up to 300MHz. Typical applications include
digitizing in-phase and quadrature channels or main and
diversity channels in base station applications.
The μModule construction affords a new level of flexibility
in application-specific standard products. Standard ADC
and amplifier components can be integrated regardless
of their process technology and matched with passive
components to a particular application. The LTM9002-AA,
as the first example, is configured with a dual 14-bit ADC
sampling at rates up to 125Msps. The amplifier gain is
26dB with an input impedance of 50Ω and an input range
of 100mVP-P (–16dBm). The matching network is designed
to optimize the interface between the amplifier output
and the ADC under these conditions. Additionally, there
is a 3rd order lowpass filter with a cutoff at 170MHz. The
auxiliary DACs allow adjustment of the full-scale range
with 12-bit resolution.
The following sections describe in further detail the operation of each section. The SiP technology allows the
LTM9002 to be customized and this is described in the
first section. The outline of the remaining sections follows
the basic functional elements as shown in Figure 1.
AUXILIARY
DAC
AMPLIFIER
ADC
INPUT
NETWORK
ADC
9002 F01
Figure 1. Basic Functional Elements
However, other options are possible through Linear
Technology’s semi-custom development program. Linear
Technology has in place a program to deliver other speed,
resolution, IF range, gain and filter configurations for nearly
any specified application. These semi-custom designs are
based on existing ADCs and amplifiers with an appropriately
modified matching network. The final subsystem is then
tested to the exact parameters defined for the application.
The final result is a fully integrated, accurately tested and
optimized solution in the same package. For more details
on the semi-custom receiver subsystem program, contact
Linear Technology.
Table 1. Semi-Custom Options
AMPLIFIER IF
RANGE
300MHz
140MHz
AMPLIFIER INPUT
IMPEDANCE
AMPLIFIER GAIN
50Ω
26dB
200Ω (Channel A) 20dB (Channel A)
400Ω (Channel B)
8dB (Channel B)
Select Combination of Options from Columns Below
DC-300MHz
50Ω
26dB
DC-140MHz
200Ω
20dB
DC-70MHz
200Ω
14dB
DC-35MHz
400Ω
8dB
FILTER
170MHz LPF
25MHz LPF
TBD
ADC SAMPLE
RATE
125Msps
65Msps
ADC
RESOLUTION
14-Bit
12-Bit
AUXILIARY
DAC
12-Bit, SPI
None
125Msps
105Msps
80Msps
65Msps
40Msps
25Msps
10Msps
14-Bit
12-Bit
10-Bit
12-Bit, I2C
None
PART NUMBER
LTM9002-AA
LTM9002-LA
9002f
16
LTM9002
OPERATION
Note that not all combinations in Table 1 are possible at
this time and specified performance may differ significantly
from existing values.
analog input will result in a digitized value six cycles
later (see the Timing Diagram section). The CLK inputs
are single-ended. The ADC has two phases of operation,
determined by the state of the CLK input pins.
AMPLIFIER OPERATION
Each pipelined stage shown in the Block Diagram contains
an ADC, a reconstruction DAC and an interstage residue
amplifier. In operation, the ADC quantizes the input to
the stage and the quantized value is subtracted from the
input by the DAC to produce a residue. The residue is
amplified and output by the residue amplifier. Successive
stages operate out of phase so that when the odd stages
are outputting their residue, the even stages are acquiring
that residue and visa versa.
The amplifiers used in the LTM9002 are low noise and
low distortion fully differential op amps/ADC drivers with
operation from DC to 2GHz (–3dB bandwidth). The amplifiers are composed of fully differential amplifiers with on
chip feedback and output common mode voltage control
circuitry. Differential gain and input impedance are set by
internal resistors in the feedback network.
Table 2. Amplifier Gain and Input Impedance
GAIN (dB)
GAIN (V/V)
ZIN (DIFFERENTIAL)
8
2.5
400Ω
14
5
200Ω
20
10
200Ω
26
20
50Ω
The amplifiers are very flexible in terms of I/O coupling.
They can be AC- or DC-coupled at the inputs. Due to the
internal connection between input and output, users are
advised to keep input common mode voltage between 1V
and 1.7V for proper operation. If the inputs are AC-coupled,
the input common mode voltage is automatically biased
close to the ADC input common mode voltage and thus no
external circuitry is needed for bias. The input signal can
be either single-ended or differential with some difference
in distortion performance.
ADC INPUT NETWORK
The passive network between the amplifier output stage
and the ADC input stage provides a 3rd order topology
that can be configured for bandpass or lowpass response
and different cutoff frequencies and bandwidths. LTM9002AA, for example, implements a lowpass filter designed
for 170MHz.
When CLK is low, the analog input is sampled differentially
directly onto the input sample-and-hold capacitors, inside
the “Input S/H” shown in the Block Diagram. At the instant
that CLK transitions from low to high, the sampled input is
held. While CLK is high, the held input voltage is buffered
by the S/H amplifier which drives the first pipelined ADC
stage. The first stage acquires the output of the S/H during this high phase of CLK. When CLK goes back low, the
first stage produces its residue which is acquired by the
second stage. At the same time, the input S/H goes back to
acquiring the analog input. When CLK goes back high, the
second stage produces its residue which is acquired by the
third stage. An identical process is repeated for the third,
fourth and fifth stages, resulting in a fifth stage residue
that is sent to the sixth stage ADC for final evaluation.
Each ADC stage following the first has additional range to
accommodate flash and amplifier offset errors. Results
from all of the ADC stages are digitally synchronized such
that the results can be properly combined in the correction
logic before being sent to the output buffer.
AUXILIARY DAC OPERATION
CONVERTER OPERATION
The full-scale voltage span of each ADC is controlled by an
auxiliary voltage output DAC connected to SENSE. Series
resistance in the DAC output allows an external voltage
to override the DAC.
As shown in the Block Diagram, the analog-to-digital converter (ADC) is a dual CMOS pipelined multistep converter.
The converter has six pipelined ADC stages; a sampled
The internal reference sets both auxiliary DACs to a fullscale range to 1.5V. Programming the DAC to generate
an internal voltage greater than or less than the external
9002f
17
LTM9002
OPERATION
reference adjusts the ADC span proportionately; see
Adjusting the full-scale input range. Powering down the
auxiliary DAC disables the ADC span trim control. When
the auxiliary DAC is powered down, connect SENSE to
VDD or an external reference.
converted to an analog voltage at the DAC output. The
update operation also powers up the selected DAC if it had
been in power-down mode. The data path and registers
are shown in the Block Diagram.
The auxiliary DACs clear the outputs to zero-scale when
power is first applied, making system initialization consistent and repeatable.
While the minimum input word is 24-bits, it may optionally
be extended to 32-bits to accommodate microprocessors
which have a minimum word width of 16 bits (2 bytes). To
use the 32-bit word width, 8 don’t-care bits are transferred
to the device first, followed by the 24-bit word as just
described. Figure 4 shows the 32-bit sequence.
Transfer Function
Power-Down Mode
The digital-to-analog transfer function is;
Either or both DAC channels can be put into power-down
mode by using command 0100b in combination with
the appropriate DAC address, n. The 16-bit data word is
ignored.
Power-On Reset
VOUT(IDEAL) = ( k/2N ) VREF
where k is the decimal equivalent of the binary DAC input
code, N is the resolution and VREF is 1.5V, the internal
reference voltage of the ADC.
Serial Interface
All serial interface pins (CS/LD, SCK and SDI) have TTL input
levels and are 5V tolerant. The CS/LD input is level triggered. When this input is taken low, it acts as a chip-select
signal, activating the SDI and SCK buffers and enabling the
input shift register. Data (SDI input) is transferred at the
next 24 rising SCK edges. The 4-bit command, C3-C0, is
loaded first; then the 4-bit DAC address, A3-A0; and finally
the 16-bit data word. The data word comprises the 12-bit
input code, ordered MSB-to-LSB, followed by 4 don’t-care
bits. Data can only be transferred to the device when the
CS/LD signal is low. The rising edge of CS/LD ends the
data transfer and causes the device to carry out the action
specified in the 24-bit input word. The complete sequence
is shown in Figure 3.
The command (C3-C0) and address (A3-A0) assignments
are shown in Table 3. The first four commands in the table
consist of write and update operations. A write operation
loads a 16-bit data word from the 32-bit shift register
into the input register of the selected DAC, n. An update
operation copies the data word from the input register to
the DAC register. Once copied into the DAC register, the
data word becomes the active 12-bit input code, and is
Normal operation can be resumed by executing any command which includes a DAC update, as shown in Table 3.
The selected DAC is powered up as its voltage output is
updated. If both DACs are powered down, then the main
bias generation circuit block has been automatically shut
down in addition to the individual DAC amplifiers and
reference inputs. In this case, the power-up delay time is
700μs (for VCC = 3V).
Table 3. Auxiliary DAC Commands
COMMAND*
C3
C2
C1
C0
0
0
0
0
Write to Input Register n
0
0
0
1
Update (Power-Up) DAC Register n
0
0
1
0
Write to Input Register n, Update
(Power Up) All n
0
0
1
1
Write to and Update (Power-Up) n
0
1
0
0
Power Down n
1
1
1
1
No Operation
ADDRESS (n)*
A3
A2
A1
A0
0
0
0
0
DAC A
0
0
0
1
DAC B
1
1
1
1
All DACs
*Command and address codes not shown are reserved and should not
be used.
9002f
18
SDI
SCK
CS/LD
X
1
X
2
X
3
X
4
DON’T CARE
X
5
C3
SDI
C2
2
C1
3
X
6
X
7
X
COMMAND WORD
1
SCK
CS/LD
8
C0
4
A1
7
ADDRESS WORD
A2
6
A0
8
D15
9
D14
10
D12
12
D11
13
D10
14
24-BIT INPUT WORD
D13
11
D9
15
D7
17
DATA WORD
D8
16
D6
18
D5
19
C3
C2
10
C1
11
C0
12
A3
A2
14
A1
15
ADDRESS WORD
13
A0
16
D15
17
D14
18
D13
19
D12
20
D11
21
Figure 3. Auxiliary DAC 32-Bit Load Sequence
COMMAND WORD
9
D10
22
D9
23
20
24
D4
D7
25
D3
21
DATA WORD
D8
Figure 2. Auxiliary DAC 24-Bit Load Sequence (Minimum Input Word)
A3
5
D6
26
D2
22
D5
27
D1
23
D4
28
D0
24
D3
29
30
D2
9002 F02
D1
31
D0
32
9002 F03
LTM9002
OPERATION
9002f
19
LTM9002
APPLICATIONS INFORMATION
INPUT SPAN
25Ω
The LTM9002 is configured with a given input span and
input impedance. With the amplifier gain and the ADC
input network described above for LTM9002-AA, the
full-scale input range of the driver circuit is 0.1VP-P. The
recommended ADC input span is achieved by tying the
SENSE pin to VDD. However, the ADC input span can be
changed if required for the application. The resulting input
span at the IN+/IN– pins is the ADC input span divided by
the gain.
The LTM9002 is intended to be driven through the IN+ and
IN– pins. The DNC pins are used for test purposes and are
not intended to be used in the application. These are test
points within the ADC input filter network. However, care
should be taken with these pins as they connect directly
to the internal signal path. They should be soldered to an
unconnected pad and should be well isolated.
+
–
IN+
LTM9002
ZIN/2
500Ω
ZIN/2
500Ω
VIN
RT
25Ω
IN–
9002 F04
Figure 4. Input Termination for Differential 50Ω
Input Impedance Using Shunt Resistor
LTM9002
25Ω
IN+
ZIN/2
500Ω
ZIN/2
500Ω
1:4
+
–
VIN
• •
RT
Input Impedance and Matching
The input impedance of the amplifier is 50Ω, 200Ω or
400Ω depending on the gain of the amplifier. In some
applications the differential inputs may need to be terminated to a lower value impedance, e.g. 50Ω, in order
to provide an impedance match for the source. Several
choices are available.
One approach is to use a differential shunt resistor
(Figure 4). Another approach is to employ a wide band
transformer and shunt resistor (Figure 5). Both methods
provide a wide band match. The termination resistor or
the transformer must be placed close to the input pins in
order to minimize the reflection due to input mismatch.
Alternatively, one could apply a narrowband impedance
match at the inputs for frequency selection and/or noise
reduction.
Table 4. Differential Amplifier Input Termination Values
25Ω
IN–
9002 F05
Figure 5. Input Termination for Differential 50Ω
Input Impedance Using a Balun
Referring to Figure 6, amplifier inputs can be easily configured for single-ended input without a balun. The signal
is fed to one of the inputs through a matching network
while the other input is connected to the same matching
network and a source resistor. Because the return ratios
of the two feedback paths are equal, the two outputs have
the same gain and thus symmetrical swing. In general,
the single-ended input impedance and termination resistor RT are determined by the combination of RS, RG and
RF , see Table 5.
Table 5. Single-Ended Amplifier Input Termination Values
GAIN (dB)
ZIN/2
RT FIGURE 4
RT FIGURE 5
GAIN (dB)
ZIN/2
RT FIGURE 6
8
200Ω
57Ω
400Ω
8
200Ω
59Ω
14
100Ω
66.5Ω
None
14
100Ω
68.5Ω
20
100Ω
66.5Ω
None
20
100Ω
66.5Ω
26
25Ω
None
None
26
25Ω
150Ω
9002f
20
LTM9002
APPLICATIONS INFORMATION
RS
50Ω
+
–
0.1μF
LTM9002
IN+
ZIN/2
RS/2
500Ω
IN+
LTM9002
ZIN/2
500Ω
ZIN/2
500Ω
VIN
RT
+
–
0.1μF
RS
50Ω
0.1μF
IN–
ZIN/2
500Ω
RT
VIN
RT
RS/2
IN–
9002 F07
9002 F06
Figure 6. Input Termination for Differential
50Ω Input Impedance Using Shunt Resistor
The amplifier is unconditionally stable, i.e. differential
stability factor Kf > 1 and stability measure B1 > 0. However, the overall differential gain is affected by the source
impedance in Figure 7:
AV = | VOUT/VIN | = (500/(RS + ZIN/2)
The noise performance of the amplifier also depends
upon the source impedance and termination. For example,
an input 1:4 transformer in Figure 5 improves the input
noise figure by adding 6dB gain at the inputs. A trade-off
between gain and noise is obvious when constant noise
figure circle and constant gain circle are plotted within
the input Smith Chart, based on which users can choose
the optimal source impedance for a given gain and noise
requirement.
SENSE Pin Operation
The internal voltage reference can be configured for two
pin-selectable input ranges of 0.1V (±50mV differential)
or 0.5V (±25mV differential) for LTM9002-AA. Tying the
SENSE pin to VDD selects the higher range; tying the SENSE
pin to 1.5V selects the lower range. For other versions of
LTM9002, the input span is either 2VP-P divided by the
gain or 1VP-P divided by the gain.
An external reference can be used by applying its output
directly or through a resistive divider to SENSE. It is not
recommended to drive the SENSE pin with a logic device.
The SENSE pin should be tied to the appropriate level as
close to the converter as possible. The SENSE pin is internally bypassed to ground with a 1μF ceramic capacitor.
Figure 7. Calculate Differential Gain
Input Range
The input range can be set based on the application. The
0.1V input range (LTM9002-AA) will provide the best SNR
performance while maintaining excellent SFDR. The lower
input range will have slightly better SFDR performance, but
the SNR will degrade by 5dB. See the Typical Performance
Characteristics section.
Adjusting the Full-Scale Input Range
To trim the full-scale range of one channel to match that
of the other channel, first set the desired range for both
channels by applying an external reference to SENSEA
and SENSEB as shown in Figure 8. Set the DAC codes to
approximately match the external reference voltage. Apply a full-scale voltage to the input of each channel. Read
the output of both channels and adjust the setting for the
DAC of one channel until the desired channel matching
has been achieved.
The adjustment range and step size depends on the resistor
values chosen for or the source resistance of the external
reference circuit. The external reference is connected to
the SENSE pin which has 10k (±1%) series impedance
with the internal DAC voltage. For the circuit shown in Figure 8, the step size is 76μV and the code representing 1V
is 0xAAB (0.666748 decimal). In this example, the SENSE
voltage trim range is from approximately 0.79V to 1.1V
including offset and gain errors. Therefore, the effective
input span can be trimmed from ±39.6mV to 55.2mV with
a step size of 3.8μV. However, it is not recommended to
9002f
21
LTM9002
APPLICATIONS INFORMATION
exceed ±50mV. The internal 1000pF capacitor provides a
corner frequency of 64kHz when used with the 2.5k external resistor. An additional 0.1μF bypass capacitor may
be required at the SENSE pin.
Driving the Clock Inputs
The CLK inputs can be driven directly with a CMOS or TTL
level signal. A sinusoidal clock can also be used along with a
low-jitter squaring circuit before the CLK pin (Figure 9).
The auxiliary DACs can be used without an external reference in applications that are not sensitive to close-in
phase noise such as CCD imaging or oversampling of low
amplitude signals. Without an external reference, the DAC
step size will be 366μV at the SENSE pin which results in
a 18μV step for the input span. In this case, the SENSE
pin may be bypassed with 0.1μF capacitor.
The noise performance of the ADC can depend on the clock
signal quality as much as on the analog input. Any noise
present on the CLK signal will result in additional aperture
jitter that will be RMS summed with the inherent ADC
aperture jitter. In applications where jitter is critical, such
as when digitizing high input frequencies, use as large an
amplitude as possible. Also, if the ADC is clocked with a
sinusoidal signal, filter the CLK signal to reduce wideband
noise and distortion products generated by the source.
The auxiliary DACs must be subsequently set each time
the LTM9002 is powered up.
LTM9002
RANGE
SELECT
REF
1.5V
REFERENCE
1.25V
2.5k
1V (OPEN CIRCUIT,
4k THEVENIN
RESISTANCE)
REF
BUFFER
SENSE
1000pF
10k
10k
SDI
SCK
CS/LD
DAC
9002 F08
Figure 8. Using an External Reference
FERRITE
BEAD
4.7μF
CLEAN
SUPPLY
0.1μF
SINUSOIDAL
CLOCK
INPUT
1k
0.1μF
CLK
50Ω
1k
LTM9002
NC7SVU04
9002 F09
Figure 9. Sinusoidal Single-Ended CLK Driver
9002f
22
LTM9002
APPLICATIONS INFORMATION
It is recommended that CLKA and CLKB are shorted
together and driven by the same clock source. If a small
time delay is desired between when the two channels
sample the analog inputs, CLKA and CLKB can be driven
by two different signals. If this time delay exceeds 1ns,
the performance of the part may degrade. CLKA and CLKB
should not be driven by asynchronous signals.
Figure 10 and Figure 11 show alternatives for converting
a differential clock to the single-ended CLK input. The use
of a transformer provides no incremental contribution
to phase noise. The LVDS or PECL to CMOS translators
provide little degradation below 70MHz, but at 140MHz will
degrade the SNR compared to the transformer solution.
The nature of the received signals also has a large bearing on how much SNR degradation will be experienced.
For high crest factor signals such as WCDMA or OFDM,
where the nominal power level must be at least 6dB to
8dB below full-scale, the use of these translators will have
a lesser impact.
4.7μF
FERRITE
BEAD
The transformer in the example may be terminated with
the appropriate termination for the signaling in use. The
use of a transformer with a 1:4 impedance ratio may
be desirable in cases where lower voltage differential
signals are considered. The center tap may be bypassed
to ground through a capacitor close to the ADC if the
differential signals originate on a different plane. The
use of a capacitor at the input may result in peaking, and
depending on transmission line length may require a 10Ω
to 20Ω series resistor to act as both a lowpass filter for
high frequency noise that may be induced into the clock
line by neighboring digital signals, as well as a damping
mechanism for reflections.
Maximum and Minimum Conversion Rates
The maximum conversion rate for the LTM9002-AA is
125Msps and the LTM9002-LA is 65Msps. The lower
limit of the sample rate is determined by the droop of the
sample-and-hold circuits. The pipelined architecture of
this ADC relies on storing analog signals on small valued
capacitors. Junction leakage will discharge the capacitors. The specified minimum operating frequency for the
LTM9002 is 1Msps.
CLEAN
SUPPLY
0.1μF
ETC1-1T
CLK
LTM9002
DIFFERENTIAL
CLOCK
INPUT
100Ω
CLK
LTM9002
5pF TO
30pF
9002 F11
9002 F10
IF LVDS USE FIN1002 OR FIN1018.
FOR PECL, USE AZ1000ELT21 OR SIMILAR
Figure 10. CLK Driver Using an LVDS or PECL to CMOS Converter
0.1μF
FERRITE
BEAD
VCM
Figure 11. LVDS or PECL CLK Driver Using a Transformer
9002f
23
LTM9002
APPLICATIONS INFORMATION
Clock Duty Cycle Stabilizer
Digital Output Modes
An optional clock duty cycle stabilizer circuit ensures high
performance even if the input clock has a non 50% duty
cycle. Using the clock duty cycle stabilizer is recommended
for most applications. To use the clock duty cycle stabilizer,
the MODE pin should be connected to 1/3VDD or 2/3VDD
using external resistors.
Figure 12 shows an equivalent circuit for a single output
buffer. Each buffer is powered by OVDD and OGND, isolated
from the ADC power and ground. The additional N-channel
transistor in the output driver allows operation down to
low voltages. The internal resistor in series with the output
makes the output appear as 50Ω to external circuitry and
may eliminate the need for external damping resistors.
This circuit uses the rising edge of the CLK pin to sample
the analog input. The falling edge of CLK is ignored and
the internal falling edge is generated by a phase-locked
loop. The input clock duty cycle can vary from 40% to
60% and the clock duty cycle stabilizer will maintain a
constant 50% internal duty cycle. If the clock is turned off
for a long period of time, the duty cycle stabilizer circuit
will require a hundred clock cycles for the PLL to lock
onto the input clock.
As with all high speed/high resolution converters the digital
output loading can affect the performance. The digital
outputs of the ADC should drive a minimal capacitive load
to avoid possible interaction between the digital outputs
and sensitive input circuitry. For full-speed operation, the
capacitive load should be kept under 10pF.
Lower OVDD voltages will also help reduce interference
from the digital outputs.
For applications where the sample rate needs to be changed
quickly, the clock duty cycle stabilizer can be disabled. If
the duty cycle stabilizer is disabled, care should be taken to
make the sampling clock have a 50% (±5%) duty cycle.
LTM9002
OVDD
VDD
VDD
0.1μF
DIGITAL OUTPUTS
OVDD
Table 6 shows the relationship between the analog input
voltage, the digital data bits, and the overflow bit. Note that
OF is high when an overflow or underflow has occurred
on either channel A or channel B.
DATA
FROM
LATCH
PREDRIVER
LOGIC
≥ 50mV
0.000000V
≤ –50mV
OF
D13 - D0
(OFFSET BINARY)
D13 - D0
(2’S COMPLEMENT)
1
0
0
11 1111 1111 1111
11 1111 1111 1111
11 1111 1111 1110
01 1111 1111 1111
01 1111 1111 1111
01 1111 1111 1110
0
0
0
0
10 0000 0000 0001
10 0000 0000 0000
01 1111 1111 1111
01 1111 1111 1110
00 0000 0000 0001
00 0000 0000 0000
11 1111 1111 1111
11 1111 1111 1110
0
0
1
00 0000 0000 0001
00 0000 0000 0000
00 0000 0000 0000
10 0000 0000 0001
10 0000 0000 0000
10 0000 0000 0000
43Ω
TYPICAL
DATA
OUTPUT
OE
OGND
Table 6. Output Codes vs Input Voltage, 100mV Input Span
IN+ – IN–
(SENSE = VDD)
0.5V
TO 3.6V
9002 F12
Figure 12. Digital Output Buffer
9002f
24
LTM9002
APPLICATIONS INFORMATION
Data Format
Using the MODE pin, the ADC parallel digital output can
be selected for offset binary or 2’s complement format.
Note that MODE controls both channel A and channel B.
Connecting MODE to GND or 1/3 VDD selects straight
binary output format. Connecting MODE to 2/3 VDD or
VDD selects 2’s complement output format. An external
resistive divider can be used to set the 1/3 VDD or 2/3
VDD logic values. Table 7 shows the logic states for the
MODE pin.
Table 7. MODE Pin Function
MODE PIN
OUTPUT FORMAT
CLOCK DUTY CYCLE
STABILIZER
0
Straight Binary
Off
1/3VDD
Straight Binary
On
2/3VDD
2’s Complement
On
VDD
2’s Complement
Off
Overflow Bit
For LTM9002-AA, when OF outputs a logic high the converter is either overranged or underranged on channel A
or channel B. Note that both channels share a common
OF pin. OF is disabled when channel A is in sleep or nap
mode. For LTM9002-LA, OFA and OFB indicate either
condition for the respective channel.
Output Clock
The LTM9002-AA has a delayed version of the CLKB input
available as a digital output, CLKOUT. The falling edge of
the CLKOUT pin can be used to latch the digital output
data. CLKOUT is disabled when channel B is in sleep or
nap mode.
Output Driver Power
Separate output power and ground pins allow the output
drivers to be isolated from the analog circuitry. The power
supply for the digital output buffers, OVDD, should be tied
to the same supply that powers the logic being driven.
For example, if the converter drives a DSP powered by a
1.8V supply, then OVDD should be tied to that same 1.8V
supply.
OVDD can be powered with any voltage from 500mV up to
3.6V, independent of VDD. OGND can be powered with any
voltage from GND up to 1V and must be less than OVDD.
The logic outputs will swing between OGND and OVDD.
Output Enable
The outputs may be disabled with the output enable pin,
OE. OE high disables all data outputs including OF. The
data access and bus relinquish times are too slow to allow
the outputs to be enabled and disabled during full-speed
operation. The output Hi-Z state is intended for use during
test or initialization. Channels A and B have independent
output enable pins (OEA, OEB.)
Sleep and Nap Modes
The converter may be placed in shutdown or nap modes
to conserve power. Connecting ADCSHDN to GND results
in normal operation. Connecting ADCSHDN to VDD and
OE to VDD results in sleep mode, which powers down all
circuitry including the reference and the ADC typically
dissipates 1mW. When exiting sleep mode, it will take
700μs to 1ms for the output data to become valid because
the reference capacitors have to recharge and stabilize.
Connecting ADCSHDN to VDD and OE to GND results in
nap mode and the ADC typically dissipates 30mW. In nap
mode, the on-chip reference circuit is kept on, so that
recovery from nap mode is faster than that from sleep
mode, typically taking 100 clock cycles. In both sleep
and nap modes, all digital outputs are disabled and enter
the Hi-Z state.
Channels A and B have independent ADCSHDN pins
(ADCSHDNA, ADCSHDNB.) Channel A is controlled by
ADCSHDNA and OEA, and channel B is controlled by
ADCSHDNB and OEB. The nap, sleep and output enable
modes of the two channels are completely independent,
so it is possible to have one channel operating while the
other channel is in nap or sleep mode.
Digital Output Multiplexer
The digital outputs of the ADC can be multiplexed onto a
single data bus. The MUX pin is a digital input that swaps
the two data busses. If MUX is high, channel A comes
out on DAx; channel B comes out on DBx. If MUX is low,
9002f
25
LTM9002
APPLICATIONS INFORMATION
the output busses are swapped and channel A comes
out on DBx; channel B comes out on DAx. To multiplex
both channels onto a single output bus, connect MUX,
CLKA and CLKB together (see the Timing Diagram for
the multiplexed mode.) The multiplexed data is available
on either data bus – the unused data bus can be disabled
with its OE pin.
Supply Sequencing
The VCC pin provides the supply to the amplifier and the
auxiliary DAC while the VDD pin provides the supply to the
ADC. The amplifier, ADC and the DAC are separate integrated
circuits within the LTM9002; however, there are no supply
sequencing considerations beyond standard practice. It is
recommended that the amplifier, ADC and DAC all use the
same low noise, 3.0V supply, but VCC may be operated from
a different voltage level if desired. Both rails can operate
from the same 3.0V linear regulator but place a ferrite bead
between the VCC and VDD pins. Separate linear regulators
can be used without additional supply sequencing circuitry
if they have common input supplies.
Grounding and Bypassing
The LTM9002 requires a printed circuit board with a
clean unbroken ground plane; a multilayer board with an
internal ground plane is recommended. The pinout of the
LTM9002 has been optimized for a flow-through layout
so that the interaction between inputs and digital outputs
is minimized. A continuous row of ground pads facilitate
a layout that ensures that digital and analog signal lines
are separated as much as possible.
The LTM9002 is internally bypassed with the ADC, (VDD) and
amplifier and DAC (VCC) supplies returning to a common
ground (GND). The digital output supply (OVDD) is returned
to OGND. Additional bypass capacitance is optional and
may be required if power supply noise is significant.
The differential inputs should run parallel and close to each
other. The input traces should be as short as possible to
minimize capacitance and to minimize noise pickup.
Heat Transfer
Most of the heat generated by the LTM9002 is transferred
through the bottom-side ground pads. For good electrical
and thermal performance, it is critical that all ground pins
are connected to a ground plane of sufficient area with as
many vias as possible.
Recommended Layout
The high integration of the LTM9002 makes the PC board
layout very simple and easy. However, to optimize its electrical and thermal performance, some layout considerations
are still necessary.
• Use large PCB copper areas for ground. This helps
to dissipate heat in the package through the board
and also helps to shield sensitive on-board analog
signals. Common ground (GND) and output ground
(OGND) are electrically isolated on the LTM9002, but
can be connected on the PCB underneath the part to
provide a common return path.
• Use multiple ground vias. Using as many vias as
possible helps to improve the thermal performance
of the board and creates necessary barriers separating analog and digital traces on the board at high
frequencies.
• Separate analog and digital traces as much as possible, using vias to create high-frequency barriers.
This will reduce digital feedback that can reduce the
signal-to-noise ratio (SNR) and dynamic range of the
LTM9002.
The quality of the paste print is an important factor in
producing high yield assemblies. It is recommended to
use a type 3 or 4 printing no-clean solder paste. The solder
stencil design should follow the guidelines outlined in
Application Note 100.
The LTM9002 employs gold-finished pads for use with
Pb-based or tin-based solder paste. It is inherently Pb-free
and complies with the JEDEC (e4) standard. The materials declaration is available online at http://www.linear.
com/leadfree/mat_dec.jsp.
9002f
26
LTM9002
PACKAGE DESCRIPTION
LGA Package
108-Lead (15mm × 11.25mm × 2.32mm)
(Reference LTC DWG # 05-08-1757 Rev Ø)
DETAIL A
aaa Z
15
BSC
X
13.97
BSC
2.22 – 2.42
Y
0.22 × 45°
CHAMFER
J
H
G
MOLD
CAP
SUBSTRATE
F
11.25
BSC
10.16
BSC
E
0.27 – 0.37
PAD 1
CORNER
D
1.27
BSC
Z
// bbb Z
1.95 – 2.05
C
B
DETAIL B
4
A
aaa Z
PADS
SEE NOTES
PACKAGE TOP VIEW
12
11
10
9
8
7
6
5
4
3
2
1
DIA (0.635)
PAD 1
PACKAGE BOTTOM VIEW
3
6.985
5.715
4.445
3.175
1.905
0.635
0.000
0.635
1.905
3.175
4.445
5.715
6.985
DETAIL B
0.630 ±0.025 SQ. 108x
eee S X Y
5.080
3.810
2.540
1.270
DETAIL A
0.000
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994
1.270
LTMXXXXXX
μModule
2. ALL DIMENSIONS ARE IN MILLIMETERS
2.540
3
LAND DESIGNATION PER JESD MO-222, SPP-010
4
DETAILS OF PAD #1 IDENTIFIER ARE OPTIONAL,
BUT MUST BE LOCATED WITHIN THE ZONE INDICATED.
THE PAD #1 IDENTIFIER MAY BE EITHER A MOLD OR
MARKED FEATURE
3.810
5.080
SUGGESTED PCB LAYOUT
TOP VIEW
COMPONENT
PIN “A1”
TRAY PIN 1
BEVEL
5. PRIMARY DATUM -Z- IS SEATING PLANE
6. THE TOTAL NUMBER OF PADS: 108
PACKAGE IN TRAY LOADING ORIENTATION
LGA 108 0707 REV Ø
SYMBOL TOLERANCE
0.15
aaa
0.10
bbb
0.05
eee
9002f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
27
LTM9002
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LT1994
Low Noise, Low Distortion Fully Differential Input/
Output Amplifier/Driver
Low Distortion: –94dBc at 1MHz
LTC2205
16-Bit, 65Msps ADC
530mW, 79dB SNR, 100dB SFDR
LTC2206
16-Bit, 80Msps ADC
725mW, 77.9dB SNR, 100dB SFDR
LTC2207
16-Bit, 105Msps ADC
900mW, 77.9dB SNR, 100dB SFDR
LTC2208
16-Bit, 130Msps ADC
1250mW, 77.7dB SNR, 100dB SFDR
LTC2240-12
12-Bit, 170Msps, 2.5V ADC, LVDS Outputs
445mW, 65.6dB SNR, 80dB SFDR, 64-Pin QFN
LTC2241-12
12-Bit, 210Msps, 2.5V ADC, LVDS Outputs
585mW, 65.6dB SNR, 80dB SFDR, 64-Pin QFN
LTC2242-12
12-Bit, 250Msps, 2.5V ADC, LVDS Outputs
745mW, 65.6dB SNR, 80dB SFDR, 64-Pin QFN
LTC2248
14-Bit, 65Msps ADC
210mW, 74dB SNR, 5mm × 5mm QFN
LTC2249
14-Bit, 80Msps ADC
230mW, 73dB SNR, 5mm × 5mm QFN
LTC2254
14-Bit, 105Msps ADC
320mW, 72.5dB SNR, 88dB SFDR, 5mm × 5mm QFN
LTC2255
14-Bit, 125Msps ADC
395mW, 72.4dB SNR, 88dB SFDR, 5mm × 5mm QFN
LTC2282
Dual 12-Bit, 105Msps ADC
540mW, 70.1dB SNR, 88dB SFDR, 64-Pin QFN
LTC2283
Dual 12-Bit, 125Msps ADC
790mW, 70.2dB SNR, 88dB SFDR, 64-Pin QFN
LTC2284
Dual 14-Bit, 105Msps ADC
540mW, 72.4dB SNR, 88dB SFDR, 64-Pin QFN
LTC2285
Dual 14-Bit, 125Msps ADC
790mW, 72.4dB SNR, 88dB SFDR, 64-Pin QFN
LTC2293
Dual 12-Bit, 65Msps ADC
410mW, 71dB SNR, 9mm × 9mm QFN
LTC2294
Dual 12-Bit, 80Msps ADC
445mW, 70.6dB SNR, 9mm × 9mm QFN
LTC2295
Dual 14-Bit, 10Msps ADC
120mW, 74.4dB SNR, 9mm × 9mm QFN
LTC2296
Dual 14-Bit, 25Msps ADC
150mW, 74dB SNR, 9mm × 9mm QFN
LTC2297
Dual 14-Bit, 40Msps ADC
240mW, 74dB SNR, 9mm × 9mm QFN
LTC2298
Dual 14-Bit, 65Msps ADC
410mW, 74dB SNR, 9mm × 9mm QFN
LTC2299
Dual 14-Bit, 80Msps ADC
445mW, 73dB SNR, 9mm × 9mm QFN
LT5557
400MHz to 3.8GHz 3.3V High Linearity
Downconverting RF Mixer
24.7dBm IIP3 at 1.9GHz, NF = 11.7dB, Single-Ended RF and LO Ports,
3.3V Supply
LT5575
800MHz to 2.7GHz High Linearity Direct Conversion
Quadrature Demodulator
60dBm IIP2 at 1.9GHz, NF = 12.7dB, Low DC Offsets
LTC6400-8/LTC6400-14/
LTC6400-20/LTC6400-26
Low Noise, Low Distortion Differential Amplifier for
300MHz IF, Fixed Gain of 8dB, 14dB, 20dB or 26dB
3V, 90mA, 39.5dBm OIP3 at 300MHz, 6dB NF
LTC6401-8/LTC6401-14/
LTC6401-20/LTC6401-26
Low Noise, Low Distortion Differential Amplifier for
140MHz IF, Fixed Gain of 8dB, 14dB, 20dB or 26dB
3V, 45mA, 45.5dBm OIP3 at 140MHz, 6dB NF
9002f
28 Linear Technology Corporation
LT 0509 • PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900
●
FAX: (408) 434-0507 ● www.linear.com
© LINEAR TECHNOLOGY CORPORATION 2009
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