PD -96175
IRFP4568PbF
HEXFET® Power MOSFET
Applications
l High Efficiency Synchronous Rectification in SMPS
l Uninterruptible Power Supply
l High Speed Power Switching
l Hard Switched and High Frequency Circuits
D
G
S
VDSS
RDS(on) typ.
max.
ID (Silicon Limited)
Benefits
l Improved Gate, Avalanche and Dynamic dV/dt
Ruggedness
l Fully Characterized Capacitance and Avalanche
SOA
l Enhanced body diode dV/dt and dI/dt Capability
l Lead-Free
150V
4.8m
5.9m
171
:
:
D
G
D
S
TO-247AC
IRFP4568PbF
G
D
S
Gate
Drain
Source
Absolute Maximum Ratings
Symbol
ID @ TC = 25°C
ID @ TC = 100°C
IDM
PD @TC = 25°C
VGS
Parameter
Max.
Continuous Drain Current, VGS @ 10V (Silicon Limited)
Continuous Drain Current, VGS @ 10V (Silicon Limited)
c
Pulsed Drain Current
Maximum Power Dissipation
Linear Derating Factor
Gate-to-Source Voltage
Peak Diode Recovery
Operating Junction and
Storage Temperature Range
Soldering Temperature, for 10 seconds
(1.6mm from case)
Mounting torque, 6-32 or M3 screw
e
dv/dt
TJ
TSTG
Avalanche Characteristics
EAS (Thermally limited)
IAR
EAR
Single Pulse Avalanche Energy
Avalanche Current
Repetitive Avalanche Energy
c
d
f
Units
171
121
684
517
3.45
± 30
18.5
-55 to + 175
A
W
W/°C
V
V/ns
°C
300
x
x
10lb in (1.1N m)
763
See Fig. 14, 15, 22a, 22b,
mJ
A
mJ
Thermal Resistance
Symbol
RθJC
RθCS
RθJA
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Parameter
j
Junction-to-Case
Case-to-Sink, Flat Greased Surface
Junction-to-Ambient
ij
Typ.
Max.
Units
–––
0.24
–––
0.29
–––
40
°C/W
1
09/08/08
IRFP4568PbF
Static @ TJ = 25°C (unless otherwise specified)
Symbol
Parameter
V(BR)DSS
∆V(BR)DSS/∆TJ
RDS(on)
VGS(th)
IDSS
Drain-to-Source Breakdown Voltage
Breakdown Voltage Temp. Coefficient
Static Drain-to-Source On-Resistance
Gate Threshold Voltage
Drain-to-Source Leakage Current
IGSS
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
Internal Gate Resistance
RG
Min. Typ. Max. Units
150
–––
–––
3.0
–––
–––
–––
–––
–––
–––
0.17
4.8
–––
–––
–––
–––
–––
1.0
Conditions
–––
V VGS = 0V, ID = 250µA
––– V/°C Reference to 25°C, ID = 5mA
5.9
mΩ VGS = 10V, ID = 103A
5.0
V VDS = VGS, ID = 250µA
VDS =150V, VGS = 0V
20
µA
250
VDS = 150V, VGS = 0V, TJ = 125°C
100
VGS = 20V
nA
VGS = -20V
-100
–––
Ω
c
f
Dynamic @ TJ = 25°C (unless otherwise specified)
Symbol
gfs
Qg
Qgs
Qgd
Qsync
td(on)
tr
td(off)
tf
Ciss
Coss
Crss
Coss eff. (ER)
Coss eff. (TR)
Parameter
Min. Typ. Max. Units
Forward Transconductance
Total Gate Charge
Gate-to-Source Charge
Gate-to-Drain ("Miller") Charge
Total Gate Charge Sync. (Qg - Qgd)
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Effective Output Capacitance (Energy Related)
Effective Output Capacitance (Time Related)
g
h
162 ––– –––
––– 151 227
–––
52
–––
–––
55
–––
–––
96
–––
–––
27
–––
––– 119 –––
–––
47
–––
–––
84
–––
––– 10470 –––
––– 977 –––
––– 203 –––
––– 897 –––
––– 1272 –––
Conditions
S
VDS = 50V, ID = 103A
ID = 103A
VDS = 75V
nC
VGS = 10V
ID = 103A, VDS =0V, VGS = 10V
VDD = 98V
ID =103A
ns
RG =1.0Ω
VGS = 10V
VGS = 0V
VDS = 50V
pF ƒ = 1.0MHz, (See Fig 5)
VGS = 0V, VDS = 0V to 120V (SeeFig.11)
VGS = 0V, VDS = 0V to 120V
f
f
f
h
g
Diode Characteristics
Symbol
IS
Parameter
Continuous Source Current
VSD
trr
(Body Diode)
Pulsed Source Current
(Body Diode)
Diode Forward Voltage
Reverse Recovery Time
Qrr
Reverse Recovery Charge
IRRM
ton
Reverse Recovery Current
Forward Turn-On Time
ISM
c
Notes:
Repetitive rating; pulse width limited by max. junction
temperature.
Limited by TJmax, starting TJ = 25°C, L = 0.144mH
RG = 25Ω, IAS = 103A, VGS =10V. Part not recommended for use
above this value.
ISD ≤ 103A, di/dt ≤ 360A/µs, VDD ≤ V(BR)DSS, TJ ≤ 175°C.
2
Min. Typ. Max. Units
–––
–––
171
A
–––
–––
684
A
Conditions
MOSFET symbol
showing the
integral reverse
D
G
p-n junction diode.
TJ = 25°C, IS = 103A, VGS = 0V
TJ = 25°C
VR = 100V,
TJ = 125°C
IF = 103A
di/dt = 100A/µs
TJ = 25°C
f
S
––– ––– 1.3
V
––– 110 –––
ns
––– 133 –––
––– 515 –––
nC
TJ = 125°C
––– 758 –––
––– 8.8 –––
A TJ = 25°C
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
f
Pulse width ≤ 400µs; duty cycle ≤ 2%.
Coss eff. (TR) is a fixed capacitance that gives the same charging time
as Coss while VDS is rising from 0 to 80% VDSS.
Coss eff. (ER) is a fixed capacitance that gives the same energy as
Coss while VDS is rising from 0 to 80% VDSS.
When mounted on 1" square PCB (FR-4 or G-10 Material). For recom
mended footprint and soldering techniques refer to application note #AN-994.
Rθ is measured at TJ approximately 90°C.
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IRFP4568PbF
1000
1000
ID, Drain-to-Source Current (A)
100
BOTTOM
10
TOP
ID, Drain-to-Source Current (A)
TOP
VGS
15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
4.5V
1
≤60µs PULSE WIDTH
Tj = 25°C
0.1
100
BOTTOM
VGS
15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
4.5V
10
4.5V
≤60µs PULSE WIDTH
Tj = 175°C
4.5V
1
0.01
0.1
1
10
0.1
100
Fig 1. Typical Output Characteristics
100
Fig 2. Typical Output Characteristics
1000
3.0
RDS(on) , Drain-to-Source On Resistance
(Normalized)
ID, Drain-to-Source Current (A)
10
V DS, Drain-to-Source Voltage (V)
V DS, Drain-to-Source Voltage (V)
T J = 175°C
100
T J = 25°C
10
1
VDS = 50V
≤60µs PULSE WIDTH
0.1
ID = 103A
VGS = 10V
2.5
2.0
1.5
1.0
0.5
3
4
5
6
7
8
9
-60 -40 -20 0 20 40 60 80 100120140160180
T J , Junction Temperature (°C)
VGS, Gate-to-Source Voltage (V)
Fig 4. Normalized On-Resistance vs. Temperature
Fig 3. Typical Transfer Characteristics
VGS = 0V,
f = 1 MHZ
C iss = C gs + C gd, C ds SHORTED
C rss = C gd
100000
C oss = C ds + C gd
Ciss
10000
Coss
1000
Crss
100
14.0
VGS, Gate-to-Source Voltage (V)
1000000
C, Capacitance (pF)
1
ID= 103A
12.0
VDS= 120V
VDS= 75V
10.0
VDS= 30V
8.0
6.0
4.0
2.0
0.0
10
1
10
100
1000
VDS, Drain-to-Source Voltage (V)
Fig 5. Typical Capacitance vs. Drain-to-Source Voltage
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0
50
100
150
200
QG, Total Gate Charge (nC)
Fig 6. Typical Gate Charge vs. Gate-to-Source Voltage
3
IRFP4568PbF
10000
T J = 175°C
ID, Drain-to-Source Current (A)
ISD, Reverse Drain Current (A)
1000
T J = 25°C
100
10
OPERATION IN THIS AREA
LIMITED BY R DS(on)
1000
100µsec
100
1msec
DC
10
10msec
1
Tc = 25°C
Tj = 175°C
Single Pulse
VGS = 0V
0.1
1.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
0.1
1.8
160
ID, Drain Current (A)
140
120
100
80
60
40
20
0
100
125
150
175
V(BR)DSS , Drain-to-Source Breakdown Voltage (V)
180
75
Id = 5mA
185
180
175
170
165
160
155
150
145
140
-60 -40 -20 0 20 40 60 80 100120140160180
T J , Temperature ( °C )
Fig 9. Maximum Drain Current vs.
Case Temperature
Fig 10. Drain-to-Source Breakdown Voltage
3500
EAS , Single Pulse Avalanche Energy (mJ)
12.0
ID
TOP
21.5A
29.3A
BOTTOM 103A
3000
10.0
2500
8.0
Energy (µJ)
1000
190
T C , Case Temperature (°C)
2000
6.0
1500
4.0
1000
2.0
500
0
0.0
0
20
40
60
80
100 120 140 160
VDS, Drain-to-Source Voltage (V)
Fig 11. Typical COSS Stored Energy
4
100
Fig 8. Maximum Safe Operating Area
Fig 7. Typical Source-Drain Diode
Forward Voltage
50
10
VDS, Drain-to-Source Voltage (V)
VSD, Source-to-Drain Voltage (V)
25
1
25
50
75
100
125
150
175
Starting T J , Junction Temperature (°C)
Fig 12. Maximum Avalanche Energy vs. DrainCurrent
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IRFP4568PbF
Thermal Response ( Z thJC ) °C/W
1
D = 0.50
0.1
0.20
0.10
0.05
0.01
0.02
0.01
τJ
0.001
1E-005
τJ
τ1
R2
R2
τ2
τ1
R3
R3
τ2
Ci= τi/Ri
Ci i/Ri
SINGLE PULSE
( THERMAL RESPONSE )
0.0001
1E-006
R1
R1
0.0001
τ3
τ3
τC 0.06336
τ
0.11088
τi (sec)
0.000278
0.005836
0.11484
0.053606
Ri (°C/W)
Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthjc + Tc
0.001
0.01
0.1
t1 , Rectangular Pulse Duration (sec)
Fig 13. Maximum Effective Transient Thermal Impedance, Junction-to-Case
1000
Avalanche Current (A)
Duty Cycle = Single Pulse
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming ∆Tj = 150°C and
Tstart =25°C (Single Pulse)
100
0.01
0.05
10
0.10
1
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming ∆Τ j = 25°C and
Tstart = 150°C.
0.1
1.0E-06
1.0E-05
1.0E-04
1.0E-03
1.0E-02
1.0E-01
tav (sec)
Fig 14. Typical Avalanche Current vs.Pulsewidth
900
800
EAR , Avalanche Energy (mJ)
Notes on Repetitive Avalanche Curves , Figures 14, 15:
(For further info, see AN-1005 at www.irf.com)
1. Avalanche failures assumption:
Purely a thermal phenomenon and failure occurs at a temperature far in
excess of Tjmax. This is validated for every part type.
2. Safe operation in Avalanche is allowed as long asTjmax is not exceeded.
3. Equation below based on circuit and waveforms shown in Figures 16a, 16b.
4. PD (ave) = Average power dissipation per single avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase
during avalanche).
6. Iav = Allowable avalanche current.
7. ∆T = Allowable rise in junction temperature, not to exceed Tjmax (assumed as
25°C in Figure 14, 15).
tav = Average time in avalanche.
D = Duty cycle in avalanche = tav ·f
ZthJC(D, tav) = Transient thermal resistance, see Figures 13)
TOP
Single Pulse
BOTTOM 1.0% Duty Cycle
ID = 103A
700
600
500
400
300
200
100
0
25
50
75
100
125
150
175
Starting T J , Junction Temperature (°C)
PD (ave) = 1/2 ( 1.3·BV·Iav) = DT/ ZthJC
Iav = 2DT/ [1.3·BV·Zth]
EAS (AR) = PD (ave)·tav
Fig 15. Maximum Avalanche Energy vs. Temperature
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5
IRFP4568PbF
60
5.0
4.5
4.0
3.5
3.0
ID = 250µA
40
TJ = 25°C
TJ = 125°C
2.0
30
20
ID = 1.0mA
ID = 1.0A
2.5
10
1.5
1.0
0
-75 -50 -25
0
25 50 75 100 125 150 175
0
200
400
600
800
1000
T J , Temperature ( °C )
diF /dt (A/µs)
Fig 16. Threshold Voltage vs. Temperature
Fig. 17 - Typical Recovery Current vs. dif/dt
70
3600
IF = 103A
V R = 100V
60
IF = 68A
V R = 100V
3200
TJ = 25°C
TJ = 125°C
50
TJ = 25°C
TJ = 125°C
2800
2400
40
QRR (A)
IRR (A)
50
IF = 68A
V R = 100V
5.5
IRR (A)
VGS(th), Gate threshold Voltage (V)
6.0
2000
30
1600
20
1200
10
800
0
400
0
200
400
600
800
1000
0
200
diF /dt (A/µs)
400
600
800
1000
diF /dt (A/µs)
Fig. 19 - Typical Stored Charge vs. dif/dt
Fig. 18 - Typical Recovery Current vs. dif/dt
4000
IF = 103A
V R = 100V
3600
3200
TJ = 25°C
TJ = 125°C
QRR (A)
2800
2400
2000
1600
1200
800
400
0
200
400
600
800
1000
diF /dt (A/µs)
6
Fig. 20 - Typical Stored Charge vs. dif/dt
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IRFP4568PbF
Driver Gate Drive
D.U.T
-
-
-
*
D.U.T. ISD Waveform
Reverse
Recovery
Current
+
RG
•
•
•
•
dv/dt controlled by RG
Driver same type as D.U.T.
I SD controlled by Duty Factor "D"
D.U.T. - Device Under Test
VDD
P.W.
Period
VGS=10V
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
+
D=
Period
P.W.
+
+
-
Body Diode Forward
Current
di/dt
D.U.T. VDS Waveform
Diode Recovery
dv/dt
Re-Applied
Voltage
Body Diode
VDD
Forward Drop
Inductor
Current
Inductor Curent
ISD
Ripple ≤ 5%
* VGS = 5V for Logic Level Devices
Fig 21. Peak Diode Recovery dv/dt Test Circuit for N-Channel
HEXFET® Power MOSFETs
V(BR)DSS
15V
DRIVER
L
VDS
tp
D.U.T
RG
VGS
20V
+
V
- DD
IAS
A
0.01Ω
tp
I AS
Fig 22a. Unclamped Inductive Test Circuit
RD
VDS
Fig 22b. Unclamped Inductive Waveforms
VDS
90%
VGS
D.U.T.
RG
+
- VDD
V10V
GS
10%
VGS
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
td(on)
Fig 23a. Switching Time Test Circuit
tr
t d(off)
Fig 23b. Switching Time Waveforms
Id
Current Regulator
Same Type as D.U.T.
Vds
Vgs
50KΩ
12V
tf
.2µF
.3µF
D.U.T.
+
V
- DS
Vgs(th)
VGS
3mA
IG
ID
Current Sampling Resistors
Fig 24a. Gate Charge Test Circuit
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Qgs1 Qgs2
Qgd
Qgodr
Fig 24b. Gate Charge Waveform
7
IRFP4568PbF
TO-247AC Package Outline
Dimensions are shown in millimeters (inches)
TO-247AC Part Marking Information
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TO-247AC package is not recommended for Surface Mount Application.
Note: For the most current drawing please refer to IR website at http://www.irf.com/package/
Data and specifications subject to change without notice.
This product has been designed and qualified for the Industrial market.
Qualification Standards can be found on IR’s Web site.
8
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information. 09/2008
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