IDT ICS9DB401CGLFT Four output differential buffer for pci express Datasheet

DATASHEET
ICS9DB401C
Four Output Differential Buffer for PCI Express
Description
Features/Benefits
The 9DB401C is a DB400 Version 2.0 Yellow Cover part with
PCI Express support. It can be used in PC or embedded
systems to provide outputs that have low cycle-to-cycle jitter
(50ps), low output-to-output skew (100ps), and are PCI Express
gen 1 compliant. The 9DB401C supports a 1 to 4 output
configuration, taking a spread or non spread differential HCSL
input from a CK410(B) main clock such as 954101 and
932S401, or any other differential HCSL pair. 9DB401C can
generate HCSL or LVDS outputs from 50 to 200MHz in PLL
mode or 0 to 400Mhz in bypass mode. There are two de-jittering
modes available selectable through the HIGH_BW# input pin,
high bandwidth mode provides de-jittering for spread inputs and
low bandwidth mode provides extra de-jittering for non-spread
inputs. The SRC_STOP#, PD#, and OE real-time input pins
provide completely programmable power management control.
•
Spread spectrum modulation tolerant, 0 to -0.5% down
spread and +/- 0.25% center spread
•
Supports undriven differential outputs in PD# and
SRC_STOP# modes for power management.
Key Specifications
•
•
•
Outputs cycle-cycle jitter: < 50ps
Outputs skew: < 50ps
Extended frequency range in bypass mode:
Revision B: up to 333.33MHz
Revision C: up to 400MHz
Real-time PLL lock detect output pin
28-pin SSOP/TSSOP package
Available in RoHS compliant packaging
•
•
•
Output Features
•
•
•
4 - 0.7V HCSL or LVDS differential output pairs
Supports zero delay buffer mode and fanout mode
Bandwidth programming available
Funtional Block Diagram
4
OE(3:0)
SPREAD
COMPATIBLE
PLL
SRC_IN
SRC_IN#
M
U
X
PD
BYPASS#/PLL
SDATA
SCLK
4
STOP
LOGIC
DIF(3:0))
CONTROL
LOGIC
IREF
Note: Polarities shown for OE_INV = 0.
IDTTM/ICSTM Four Output Differential Buffer for PCI Express
ICS9DB401C
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ICS9DB401C
Four Output Differential Buffer for PCI Express
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
ICS9DB401
(same as ICS9DB104)
VDD
SRC_IN
SRC_IN#
GND
VDD
DIF_1
DIF_1#
OE_1
DIF_2
DIF_2#
VDD
BYPASS#/PLL
SCLK
SDATA
VDD
SRC_IN
SRC_IN#
GND
VDD
DIF_1
DIF_1#
OE1#
DIF_2
DIF_2#
VDD
BYPASS#/PLL
SCLK
SDATA
VDDA
GNDA
IREF
OE_INV
VDD
DIF_6
DIF_6#
OE_6
DIF_5
DIF_5#
VDD
HIGH_BW#
SRC_STOP#
PD#
1
2
3
4
5
6
7
8
9
10
11
12
13
14
ICS9DB401
Pin Configuration
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VDDA
GNDA
IREF
OE_INV
VDD
DIF_6
DIF_6#
OE6#
DIF_5
DIF_5#
VDD
HIGH_BW#
SRC_STOP
PD
OE_INV = 1
OE_INV = 0
28-pin SSOP & TSSOP
Polarity Inversion Pin List Table
Power Groups
Pin Number
VDD
GND
1
4
5,11,18, 24
4
N/A
27
28
27
OE_INV
Pins
0
1
8
OE_1
OE1#
15
PD#
PD
16
DIF_STOP#
DIF_STOP
21
OE_6
OE6#
IDTTM/ICSTM Four Output Differential Buffer for PCI Express
Description
SRC_IN/SRC_IN#
DIF(1,2,5,6)
IREF
Analog VDD & GND for PLL core
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ICS9DB401C
Four Output Differential Buffer for PCI Express
Pin Description for OE_INV = 0
PIN #
1
2
3
4
5
6
7
PIN NAME
VDD
SRC_IN
SRC_IN#
GND
VDD
DIF_1
DIF_1#
PIN TYPE
PWR
IN
IN
PWR
PWR
OUT
OUT
8
OE_1
9
10
11
DIF_2
DIF_2#
VDD
12
BYPASS#/PLL
IN
13
14
SCLK
SDATA
IN
I/O
15
PD#
IN
16
SRC_STOP#
IN
17
HIGH_BW#
IN
18
19
20
VDD
DIF_5#
DIF_5
21
OE_6
22
23
24
DIF_6#
DIF_6
VDD
OUT
OUT
PWR
25
OE_INV
IN
26
IREF
OUT
27
28
GNDA
VDDA
PWR
PWR
IN
OUT
OUT
PWR
PWR
OUT
OUT
IN
DESCRIPTION
Power supply, nominal 3.3V
0.7 V Differential SRC TRUE input
0.7 V Differential SRC COMPLEMENTARY input
Ground pin.
Power supply, nominal 3.3V
0.7V differential true clock output
0.7V differential complement clock output
Active high input for enabling output 1.
0 = tri-state outputs, 1= enable outputs
0.7V differential true clock output
0.7V differential complement clock output
Power supply, nominal 3.3V
Input to select Bypass(fan-out) or PLL (ZDB) mode
0 = Bypass mode, 1= PLL mode
Clock pin of SMBus circuitry, 5V tolerant.
Data pin for SMBus circuitry, 5V tolerant.
Asynchronous active low input pin used to power down the device.
The internal clocks are disabled and the VCO and the crystal are
stopped.
Active low input to stop SRC outputs.
3.3V input for selecting PLL Band Width
0 = High, 1= Low
Power supply, nominal 3.3V
0.7V differential complement clock output
0.7V differential true clock output
Active high input for enabling output 6.
0 = tri-state outputs, 1= enable outputs
0.7V differential complement clock output
0.7V differential true clock output
Power supply, nominal 3.3V
This latched input selects the polarity of the OE pins.
0 = OE pins active high, 1 = OE pins active low (OE#)
This pin establishes the reference current for the differential currentmode output pairs. This pin requires a fixed precision resistor tied
to ground in order to establish the appropriate current. 475 ohms is
the standard value.
Ground pin for the PLL core.
3.3V power for the PLL core.
IDTTM/ICSTM Four Output Differential Buffer for PCI Express
ICS9DB401C
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ICS9DB401C
Four Output Differential Buffer for PCI Express
Pin Description for OE_INV = 1
PIN #
1
2
3
4
5
6
7
8
PIN NAME
VDD
SRC_IN
SRC_IN#
GND
VDD
DIF_1
DIF_1#
OE1#
PIN TYPE
PWR
IN
IN
PWR
PWR
OUT
OUT
IN
9
10
11
DIF_2
DIF_2#
VDD
OUT
OUT
PWR
12
BYPASS#/PLL
IN
13
14
SCLK
SDATA
IN
I/O
15
PD
IN
16
SRC_STOP
IN
17
HIGH_BW#
IN
18
19
20
VDD
DIF_5#
DIF_5
21
OE6#
22
23
24
DIF_6#
DIF_6
VDD
OUT
OUT
PWR
25
OE_INV
IN
26
IREF
OUT
27
28
GNDA
VDDA
PWR
PWR
PWR
OUT
OUT
IN
DESCRIPTION
Power supply, nominal 3.3V
0.7 V Differential SRC TRUE input
0.7 V Differential SRC COMPLEMENTARY input
Ground pin.
Power supply, nominal 3.3V
0.7V differential true clock output
0.7V differential complement clock output
Active low input for enabling DIF pair 1.
1 = tri-state outputs, 0 = enable outputs
0.7V differential true clock output
0.7V differential complement clock output
Power supply, nominal 3.3V
Input to select Bypass(fan-out) or PLL (ZDB) mode
0 = Bypass mode, 1= PLL mode
Clock pin of SMBus circuitry, 5V tolerant.
Data pin for SMBus circuitry, 5V tolerant.
Asynchronous active high input pin used to power down the
device. The internal clocks are disabled and the VCO is stopped.
Active high input to stop SRC outputs.
3.3V input for selecting PLL Band Width
0 = High, 1= Low
Power supply, nominal 3.3V
0.7V differential complement clock output
0.7V differential true clock output
Active low input for enabling DIF pair 6.
1 = tri-state outputs, 0 = enable outputs
0.7V differential complement clock output
0.7V differential true clock output
Power supply, nominal 3.3V
This latched input selects the polarity of the OE pins.
0 = OE pins active high, 1 = OE pins active low (OE#)
This pin establishes the reference current for the differential
current-mode output pairs. This pin requires a fixed precision
resistor tied to ground in order to establish the appropriate
current. 475 ohms is the standard value.
Ground pin for the PLL core.
3.3V power for the PLL core.
IDTTM/ICSTM Four Output Differential Buffer for PCI Express
ICS9DB401C
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Four Output Differential Buffer for PCI Express
Absolute Max
Symbol
VDD_A
VDD_In
VIL
VIH
Parameter
3.3V Core Supply Voltage
3.3V Logic Supply Voltage
Input Low Voltage
Input High Voltage
Ts
Tambient
Tcase
Storage Temperature
Ambient Operating Temp
Case Temperature
Input ESD protection
human body model
ESD prot
Min
Max
4.6
4.6
GND-0.5
VDD+0.5V
-65
0
Units
V
V
V
V
°
150
70
115
C
°C
°C
2000
V
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70°C; Supply Voltage V DD = 3.3 V +/-5%
PARAMETER
SYMBOL
Input High Voltage
Input Low Voltage
Input High Current
V IH
VIL
I IH
I IL1
Input Low Current
CONDITIONS
VIN = 0 V; Inputs with pull-up
resistors
Operating Supply Current
I DD3.3PLL
I DD3.3ByPass
Full Active, CL = Full load;
Powerdown Current
I DD3.3PD
Input Frequency
FiPLL
Input Frequency
FiBypass
Input Frequency
FiBypass
Pin Inductance1
Lpin
CIN
COUT
PLL Bandwidth
BW
Clk Stabilization1,2
TSTAB
Modulation Frequency
fMOD
Tdrive_SRC_STOP#
Tdrive_PD#
Tfall
Trise
TYP
3.3 V +/-5%
2
3.3 V +/-5%
GND - 0.3
V IN = VDD
-5
V IN = 0 V; Inputs with no pull-5
up resistors
I IL2
Input Capacitance1
MIN
MAX
VDD + 0.3
0.8
5
uA
175
160
Logic Inputs
Output pin capacitance
PLL Bandwidth when
PLL_BW=0
PLL Bandwidth when
PLL_BW=1
50
200
175
40
4
200
mA
mA
mA
mA
MHz
0
333.33
MHz
0
400
MHz
1.5
7
4
4
nH
pF
pF
1
1
1
2.4
3
3.4
MHz
1
0.7
1
1.4
MHz
1
0.5
1
ms
1,2
33
kHz
1
15
ns
1,3
300
us
1,3
5
ns
1
5
ns
2
From VDD Power-Up and after
input clock stabilization or deassertion of PD# to 1st clock
Triangular Modulation
DIF output enable after
SRC_Stop# de-assertion
DIF output enable after
PD# de-assertion
Fall time of PD# and
SRC_STOP#
Rise time of PD# and
SRC_STOP#
V
V
uA
uA
-200
all diff pairs driven
all differential pairs tri-stated
PLL Mode
Bypass Mode (Revision
B/REV ID = 1H)
Bypass Mode (Revision
C/REV ID = 2H)
UNITS NOTES
30
10
1
Guaranteed by design and characterization, not 100% tested in production.
See timing diagrams for timing requirements.
3
Time from deassertion until outputs are >200 mV
2
IDTTM/ICSTM Four Output Differential Buffer for PCI Express
ICS9DB401C
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ICS9DB401C
Four Output Differential Buffer for PCI Express
Electrical Characteristics - Clock Input Parameters
TA = 0 - 70°C; Supply Voltage V DD = 3.3 V +/-5%
PARAMETER
SYMBOL
Differential Input High Voltage
VIHDIF
Differential Input Low Voltage
VILDIF
Input Slew Rate - DIF_IN
dv/dt
Input Leakage Current
IIN
Input Duty Cycle
Input SRC Jitter - Cycle to
Cycle
CONDITIONS
MIN
MAX
UNITS
NOTES
600
1150
mV
1
VSS - 300
300
mV
1
0.4
8
V/ns
2
VIN = VDD , VIN = GND
-5
5
uA
1
dtin
Measurement from differential
wavefrom
45
55
%
1
SRCJ C2CIn
Differential Measurement
125
ps
1
Differential inputs
(single-ended measurement)
Differential inputs
(single-ended measurement)
Measured differentially
1
Guaranteed by design and characterization, not 100% tested in production.
Slew rate measured through Vswing centered around differential zero
2
Electrical Characteristics - DIF 0.7V Current Mode Differential Pair
TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL =2pF, RS=33.2Ω, RP=49.9Ω, ΙREF = 475Ω
PARAMETER
Current Source Output
Impedance
SYMBOL
Voltage High
VHigh
Zo
CONDITIONS
MIN
VO = Vx
3000
Statistical measurement on single
ended signal using oscilloscope
math function.
Measurement on single ended
signal using absolute value.
660
1
Voltage Low
VLow
Max Voltage
Min Voltage
Crossing Voltage (abs)
Vovs
Vuds
Vcross(abs)
Crossing Voltage (var)
d-Vcross
Long Accuracy
Rise Time
Fall Time
Rise Time Variation
Fall Time Variation
ppm
tr
tf
d-tr
d-tf
Variation of crossing over all
edges
see Tperiod min-max values
VOL = 0.175V, VOH = 0.525V
VOH = 0.525V VOL = 0.175V
TYP
MAX
UNITS
NOTES
Ω
1
850
1,3
mV
-150
150
1150
-300
250
175
175
1,3
550
mV
1
1
1
140
mV
1
0
700
700
125
125
ppm
ps
ps
ps
ps
1,2
1
1
1
1
mV
Measurement from differential
45
55
%
wavefrom
VT = 50%
tsk3
50
ps
Skew
PLL mode,
50
ps
Measurement from differential
tjcyc-cyc
Jitter, Cycle to cycle
wavefrom
BYPASS mode as additive jitter
50
ps
1
Guaranteed by design and characterization, not 100% tested in production.
2
All Long Term Accuracy and Clock Period specifications are guaranteed with the assumption that the input clock
complies with CK409/CK410 accuracy requirements
3
IREF = VDD/(3xRR). For RR = 475Ω (1%), IREF = 2.32mA. IOH = 6 x IREF and VOH = 0.7V @ ZO=50Ω.
Duty Cycle
dt3
IDTTM/ICSTM Four Output Differential Buffer for PCI Express
ICS9DB401C
6
1
1
1
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ICS9DB401C
Four Output Differential Buffer for PCI Express
SRC Reference Clock
Common Recommendations for Differential Routing
Dimension or Value
L1 length, Route as non-coupled 50 ohm trace.
0.5 max
L2 length, Route as non-coupled 50 ohm trace.
0.2 max
L3 length, Route as non-coupled 50 ohm trace.
0.2 max
Rs
33
Rt
49.9
Unit
inch
inch
inch
ohm
ohm
Figure
1
1
1
1
1
Down Device Differential Routing
L4 length, Route as coupled microstrip 100 ohm differential trace.
L4 length, Route as coupled stripline 100 ohm differential trace.
Dimension or Value
2 min to 16 max
1.8 min to 14.4 max
Unit
inch
inch
Figure
1
1
Differential Routing to PCI Express Connector
L4 length, Route as coupled microstrip 100 ohm differential trace.
L4 length, Route as coupled stripline 100 ohm differential trace.
Dimension or Value
0.25 to 14 max
0.225 min to 12.6 max
Unit
inch
inch
Figure
2
2
Figure 1 Down device routing.
L1
L2
L4
Rs
L1’
L4’
L2’
Rs
Rt
HSCL Output
Buffer
L3’
Rt
PCI Ex Board
Down Device
REF_CLK Input
L3
Figure 1
Figure 2 PCI Express Connector Routing.
L1
L2
L4
Rs
L1’
L4’
L2’
Rs
HSCL Output
Buffer
Rt
L3’
Rt
L3
PCI Ex
Add In Board
REF_CLK Input
Figure 2
IDTTM/ICSTM Four Output Differential Buffer for PCI Express
ICS9DB401C
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Four Output Differential Buffer for PCI Express
Alternative termination for LVDS and other common differential signals. Figure 3.
Vdiff
Vp-p
0.45 v
0.22v
0.58
0.28
0.80
0.40
0.60
0.3
R1a = R1b = R1
Vcm
1.08
0.6
0.6
1.2
R1
33
33
33
33
R2
150
78.7
78.7
174
R3
100
137
none
140
R4
100
100
100
100
Note
ICS874003i-02 input compatible
Standard LVDS
Figure_3.
L1
L2
R3
L4
R1a
L1’
L4’
L2’
R1b
R2a
HSCL Output
Buffer
R4
R2b
Down Device
REF_CLK Input
L3
L3’
R2a = R2b = R2
Cable connected AC coupled application, figure 4
Component
R5a,R5b
R6a,R6b
Cc
Vcm
Value
8.2K 5%
1K 5%
0.1 uF
0.350 volts
Note
3.3 Volts
R5a
R5b
L4
L4’
Cc
Cc
R6a
R6b
PCIe Device
REF_CLK Input
Figure_4.
IDTTM/ICSTM Four Output Differential Buffer for PCI Express
ICS9DB401C
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Four Output Differential Buffer for PCI Express
General SMBus serial interface information for the ICS9DB401C
How to Write:
How to Read:
Controller (host) sends a start bit.
Controller (host) sends the write address DC (h)
ICS clock will acknowledge
Controller (host) sends the begining byte location = N
ICS clock will acknowledge
Controller (host) sends the data byte count = X
ICS clock will acknowledge
Controller (host) starts sending Byte N through
Byte N + X -1
• ICS clock will acknowledge each byte one at a time
• Controller (host) sends a Stop bit
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Index Block Read Operation
Index Block Write Operation
Controller (Host)
starT bit
T
Slave Address DC(h)
WRite
WR
Controller (host) will send start bit.
Controller (host) sends the write address DC (h)
ICS clock will acknowledge
Controller (host) sends the begining byte
location = N
ICS clock will acknowledge
Controller (host) will send a separate start bit.
Controller (host) sends the read address DD (h)
ICS clock will acknowledge
ICS clock will send the data byte count = X
ICS clock sends Byte N + X -1
ICS clock sends Byte 0 through byte X (if X(h)
was written to byte 8).
Controller (host) will need to acknowledge each byte
Controllor (host) will send a not acknowledge bit
Controller (host) will send a stop bit
Controller (Host)
T
starT bit
Slave Address DC(h)
WR
WRite
ICS (Slave/Receiver)
ICS (Slave/Receiver)
ACK
ACK
Beginning Byte = N
Beginning Byte = N
ACK
ACK
RT
Repeat starT
Slave Address DD(h)
RD
ReaD
Data Byte Count = X
ACK
Beginning Byte N
ACK
X Byte
ACK
Data Byte Count = X
ACK
Beginning Byte N
Byte N + X - 1
ACK
P
X Byte
ACK
stoP bit
Byte N + X - 1
N
P
IDTTM/ICSTM Four Output Differential Buffer for PCI Express
Not acknowledge
stoP bit
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Four Output Differential Buffer for PCI Express
SMBus Table: Frequency Select Register, READ/WRITE ADDRESS
Pin #
Name
Control Function
Byte 0
PD_Mode
PD# drive mode
Bit 7
STOP_Mode
SRC_Stop# drive mode
Bit 6
Power Down
PD_SRC_INV
Bit 5
and SRC Invert
Reserved
Reserved
Bit 4
Reserved
Reserved
Bit 3
PLL_BW#
Select PLL BW
Bit 2
BYPASS#
BYPASS#/PLL
Bit 1
SRC_DIV#
SRC
Divide by 2 Select
Bit 0
(DC/DD)
0
Type
RW
driven
RW
driven
RW
RW
RW
RW
RW
RW
SMBus Table: Output Control Register
Byte 1
Pin #
Name
Reserved
Bit 7
22,23
DIF_6
Bit 6
19,20
DIF_5
Bit 5
Reserved
Bit 4
Reserved
Bit 3
9,10
DIF_2
Bit 2
6,7
DIF_1
Bit 1
Reserved
Bit 0
Control Function
Reserved
Output Control
Output Control
Reserved
Reserved
Output Control
Output Control
Reserved
Type
RW
RW
RW
RW
RW
RW
RW
RW
SMBus Table: Output Control Register
Pin #
Name
Byte 2
Reserved
Bit 7
22,23
DIF_6
Bit 6
DIF_5
19,20
Bit 5
Reserved
Bit 4
Reserved
Bit 3
9,10
DIF_2
Bit 2
6,7
DIF_1
Bit 1
Reserved
Bit 0
Control Function
Reserved
Output Control
Output Control
Reserved
Reserved
Output Control
Output Control
Reserved
Type
RW
RW
RW
RW
RW
RW
RW
RW
SMBus Table: Output Control Register
Byte 3
Pin #
Name
Control Function
Reserved
Bit 7
Reserved
Bit 6
Reserved
Bit 5
Reserved
Bit 4
Reserved
Bit 3
Reserved
Bit 2
Reserved
Bit 1
Reserved
Bit 0
Type
RW
RW
RW
RW
RW
RW
RW
RW
IDTTM/ICSTM Four Output Differential Buffer for PCI Express
Normal
1
Hi-Z
Hi-Z
PWD
0
0
Invert
0
X
X
1
1
1
Reserved
Reserved
High BW
Low BW
fan-out
ZDB
x/2
1x
0
1
Reserved
Disable
Enable
Disable
Enable
Reserved
Reserved
Disable
Enable
Disable
Enable
Reserved
0
1
Reserved
Free-run Stoppable
Free-run Stoppable
Reserved
Reserved
Free-run Stoppable
Free-run Stoppable
Reserved
0
1
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
PWD
X
1
1
X
X
1
1
X
PWD
X
0
0
X
X
0
0
X
PWD
X
X
X
X
X
X
X
X
ICS9DB401C
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ICS9DB401C
Four Output Differential Buffer for PCI Express
SMBus Table: Vendor & Revision ID Register
Byte 4
Pin #
Name
Control Function
RID3
Bit 7
RID2
Bit 6
REVISION ID
RID1
Bit 5
RID0
Bit 4
VID3
Bit 3
VID2
Bit 2
VENDOR ID
VID1
Bit 1
VID0
Bit 0
Type
R
R
R
R
R
R
R
R
0
-
SMBus Table: DEVICE ID
Byte 5
Pin #
Name
Control Function
Device ID 7 (MSB)
Bit 7
Device ID 6
Bit 6
Device ID 5
Bit 5
Device ID 4
Bit 4
Device ID 3
Bit 3
Device ID 2
Bit 2
Device ID 1
Bit 1
Device ID 0
Bit 0
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
Control
Function
Type
Writing to this register
configures how many bytes
will be read back.
RW
RW
RW
RW
RW
RW
RW
RW
1
-
PWD
X
X
X
X
0
0
0
1
1
PWD
0
1
0
0
0
0
0
1
0
1
PWD
-
-
0
0
0
0
0
1
1
1
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
SMBus Table: Byte Count Register
Byte 6
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin #
-
Name
BC7
BC6
BC5
BC4
BC3
BC2
BC1
BC0
IDTTM/ICSTM Four Output Differential Buffer for PCI Express
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Four Output Differential Buffer for PCI Express
PD#
The PD# pin cleanly shuts off all clocks and places the device into a power saving mode. PD# must be asserted before shutting
off the input clock or power to insure an orderly shutdown. PD is asynchronous active-low input for both powering down the
device and powering up the device. When PD# is asserted, all clocks will be driven high, or tri-stated (depending on the PD#
drive mode and Output control bits) before the PLL is shut down.
PD# Assertion
When PD# is sampled low by two consecutive rising edges of DIF#, all DIF outputs must be held High, or tri-stated (depending
on the PD# drive mode and Output control bits) on the next High-Low transition of the DIF# outputs. When the PD# drive mode
bit is set to ‘0’, all clock outputs will be held with DIF driven High with 2 x IREF and DIF# tri-stated. If the PD# drive mode bit is
set to ‘1’, both DIF and DIF# are tri-stated.
PWRDWN#
DIF
DIF#
PD# De-assertion
Power-up latency is less than 1 ms. This is the time from de-assertion of the PD# pin, or VDD reaching 3.3V, or the time from
valid SRC_IN clocks until the time that stable clocks are output from the device (PLL Locked). If the PD# drive mode bit is set
to ‘1’, all the DIF outputs must driven to a voltage of >200 mV within 300 ms of PD# de-assertion.
Tstable
<1mS
PWRDWN#
DIF
DIF#
Tdrive_PwrDwn#
<300uS, >200mV
IDTTM/ICSTM Four Output Differential Buffer for PCI Express
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Four Output Differential Buffer for PCI Express
Note: Polarities in timing diagrams are shown OE_INV = 0. They are similar to OE_INV = 1.
SRC_STOP#
The SRC_STOP# signal is an active-low asynchronous input that cleanly stops and starts the DIF outputs. A valid clock must
be present on SRC_IN for this input to work properly. The SRC_STOP# signal is de-bounced and must remain stable for two
consecutive rising edges of DIF# to be recognized as a valid assertion or de-assertion.
SRC_STOP# - Assertion (transition from '1' to '0')
Asserting SRC_STOP# causes all DIF outputs to stop after their next transition (if the control register settings allow the output
to stop). When the SRC_STOP# drive bit is ‘0’, the final state of all stopped DIF outputs is DIF = High and DIF# = Low. There
is no change in output drive current. DIF is driven with 6xIREF. DIF# is not driven, but pulled low by the termination. When the
SRC_STOP# drive bit is ‘1’, the final state of all DIF output pins is Low. Both DIF and DIF# are not driven.
All stopped differential outputs resume normal operation in a glitch-free manner. The de-assertion latency to active outputs is
2-6 DIF clock periods, with all DIF outputs resuming simultaneously. If the SRC_STOP# drive control bit is ‘1’ (tri-state), all
stopped DIF outputs must be driven High (>200 mV) within 10 ns of de-assertion.
SRC_STOP_1 (SRC_Stop = Driven, PD = Driven)
1mS
SRC_Stop#
PWRDWN#
DIF (Free Running)
DIF# (Free Running)
DIF (Stoppable)
DIF# (Stoppable)
SRC_STOP_2 (SRC_Stop =Tristate, PD = Driven)
1mS
SRC_Stop#
PWRDWN#
DIF (Free Running)
DIF# (Free Running)
DIF (Stoppable)
DIF# (Stoppable)
13
ICS9DB401C
Four Output Differential Buffer for PCI Express
SRC_STOP_3 (SRC_Stop = Driven, PD = Tristate)
1mS
SRC_Stop#
PWRDWN#
DIF (Free Running)
DIF# (Free Running)
DIF (Stoppable)
DIF# (Stoppable)
SRC_STOP_4 (SRC_Stop = Tristate, PD = Tristate)
1mS
SRC_Stop#
PWRDWN#
DIF (Free Running)
DIF# (Free Running)
DIF (Stoppable)
DIF# (Stoppable)
IDTTM/ICSTM Four Output Differential Buffer for PCI Express
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Four Output Differential Buffer for PCI Express
209 mil SSOP
In Millimeters
In Inches
SYMBOL COMMON DIMENSIONS COMMON DIMENSIONS
MIN
MAX
MIN
MAX
A
-2.00
-.079
A1
0.05
-.002
-A2
1.65
1.85
.065
.073
b
0.22
0.38
.009
.015
c
0.09
0.25
.0035
.010
SEE VARIATIONS
SEE VARIATIONS
D
E
7.40
8.20
.291
.323
E1
5.00
5.60
.197
.220
0.65 BASIC
0.0256 BASIC
e
L
0.55
0.95
.022
.037
SEE VARIATIONS
SEE VARIATIONS
N
α
0°
8°
0°
8°
c
N
L
E1
INDEX
AREA
E
1 2
α
D
A
A2
A1
VARIATIONS
-Ce
N
SEATING
PLANE
b
28
.10 (.004) C
D mm.
MIN
9.90
D (inch)
MAX
10.50
MIN
.390
MAX
.413
Reference Doc.: JEDEC Publication 95, MO-150
10-0033
Ordering Information
ICS9DB401CFLFT
Example:
ICS XXXX C F LF T
Designation for tape and reel packaging
RoHS Compliant (Optional)
Package Type
F = SSOP
Revision Designator
Device Type (consists of 3 to 7 digit numbers)
Prefix
ICS = Standard Device
IDTTM/ICSTM Four Output Differential Buffer for PCI Express
ICS9DB401C
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ICS9DB401C
Four Output Differential Buffer for PCI Express
4.40 mm. Body, 0.65 mm. Pitch TSSOP
c
N
(173 mil)
L
E1
INDEX
AREA
SYMBOL
A
A1
A2
b
c
D
E
E1
e
L
N
a
aaa
E
1 2
α
D
A
A2
(25.6 mil)
In Millimeters
COMMON DIMENSIONS
MIN
MAX
-1.20
0.05
0.15
0.80
1.05
0.19
0.30
0.09
0.20
SEE VARIATIONS
6.40 BASIC
4.30
4.50
0.65 BASIC
0.45
0.75
SEE VARIATIONS
0°
8°
-0.10
In Inches
COMMON DIMENSIONS
MIN
MAX
-.047
.002
.006
.032
.041
.007
.012
.0035
.008
SEE VARIATIONS
0.252 BASIC
.169
.177
0.0256 BASIC
.018
.030
SEE VARIATIONS
0°
8°
-.004
VARIATIONS
A1
N
-Ce
28
SEATING
PLANE
b
D mm.
MIN
9.60
D (inch)
MAX
9.80
MIN
.378
MAX
.386
Reference Doc.: JEDEC Publication 95, MO-153
aaa C
10-0035
Ordering Information
ICS9DB401CGLFT
Example:
ICS XXXX C G LF T
Designation for tape and reel packaging
RoHS Compliant (Optional)
Package Type
G = TSSOP
Revision Designator
Device Type (consists of 3 to 7 digit numbers)
Prefix
ICS = Standard Device
IDTTM/ICSTM Four Output Differential Buffer for PCI Express
ICS9DB401C
16
REV E 03/18/08
ICS9DB401C
Four Output Differential Buffer for PCI Express
Revision History
Rev.
0.1
A
B
C
D
E
Issue Date Description
4/21/2005 Changed Ordering Information from"LN" to "LF".
1. Updated LF Ordering Information to RoHS Compliant.
8/15/2005 2. Release to web.
9/7/2006 Updated Electrical Characteristics.
5/22/2007 Updated Polarity Inversion Table.
2/28/2008 Added Input Clock Specs
3/18/2008 Fixed typo in clock Input Parameters
Page #
14,15
14-15
Various
2
6
6
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© 2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated
Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks
or registered trademarks used to identify products or services of their respective owners.
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