Data Sheet No. PD60304 IRMCF341 Sensorless Motor Control IC for Appliances Features Product Summary Maximum crystal frequency MCETM (Motion Control Engine) - Hardware based computation engine for high efficiency sinusoidal sensorless control of permanent magnet AC motor Supports both interior and surface permanent magnet motors Built-in hardware peripheral for single shunt current feedback reconstruction No external current or voltage sensing operational amplifier required Three/two-phase Space Vector PWM Three-channel analog output (PWM) Embedded 8-bit high speed microcontroller (8051) for flexible I/O and man-machine control JTAG programming port for emulation/debugger Serial communication interface (UART) I2C/SPI serial interface Watchdog timer with independent analog clock Three general purpose timers/counters Two special timers: periodic timer, capture timer External EEPROM and internal RAM facilitate debugging and code development 60 MHz Maximum internal clock (SYSCLK) frequency Sensorless control computation time TM MCE computation data range 128 MHz 11 μsec typ 16 bit signed Program RAM loaded from external EEPROM 48K bytes Data RAM 8K bytes GateKill latency (digital filtered) 2 μsec PWM carrier frequency counter 16 bits/ SYSCLK A/D input channels 8 A/D converter resolution 12 bits A/D converter conversion speed 2 μsec 8051 instruction execution speed Analog output (PWM) resolution UART baud rate (typ) Number of I/O (max) Package (lead-free) 2 SYSCLK 8 bits 57.6K bps 24 QFP64 Pin compatible with IRMCK341, OTP-ROM version 1.8V/3.3V CMOS Description IRMCF341 is a high performance RAM based motion control IC designed primarily for appliance applications. IRMCF341 is designed to achieve low cost and high performance control solutions for advanced inverterized appliance motor control. IRMCF341 contains two computation engines. One is Motion Control Engine (MCETM) for sensorless control of permanent magnet motors; the other is an 8-bit high-speed microcontroller (8051). Both computation engines are integrated into one monolithic chip. The MCETM contains a collection of control elements such as Proportional plus Integral, Vector rotator, Angle estimator, Multiply/Divide, Low loss SVPWM, Single Shunt IFB. The user can program a motion control algorithm by connecting these control elements using a graphic compiler. Key components of the sensorless control algorithms, such as the Angle Estimator, are provided as complete pre-defined control blocks implemented in hardware. A unique analog/digital circuit and algorithm to fully support single shunt current reconstruction is also provided. The 8051 microcontroller performs 2-cycle instruction execution (60MIPS at 120MHz). The MCE and 8051 microcontroller are connected via dual port RAM to process signal monitoring and command input. An advanced graphic compiler for the MCETM is seamlessly integrated into the MATLAB/Simulink environment, while third party JTAG based emulator tools are supported for 8051 developments. IRMCF341 comes with a small QFP64 pin lead-free package. Rev 1.1 IRMCF341 TABLE OF CONTENTS 1 2 3 4 Overview ....................................................................................................................................4 IRMCF341 Block Diagram and Main Functions.........................................................................5 Pinout.........................................................................................................................................7 Input/Output of IRMCF341.........................................................................................................8 4.1 8051 Peripheral Interface Group .........................................................................................8 4.2 Motion Peripheral Interface Group ....................................................................................10 4.3 Analog Interface Group .....................................................................................................10 4.4 Power Interface Group ......................................................................................................11 4.5 Test Interface Group .........................................................................................................11 5 Application Connections ..........................................................................................................12 6 DC Characteristics ...................................................................................................................13 6.1 Absolute Maximum Ratings...............................................................................................13 6.2 System Clock Frequency and Power Consumption ..........................................................13 6.3 Digital I/O DC Characteristics............................................................................................14 6.4 PLL and Oscillator DC characteristics...............................................................................15 6.5 Analog I/O DC Characteristics ..........................................................................................15 6.6 Under Voltage Lockout DC characteristics........................................................................16 6.7 CMEXT and AREF Characteristics ...................................................................................16 7 AC Characteristics ...................................................................................................................17 7.1 PLL AC Characteristics .....................................................................................................17 7.2 Analog to Digital Converter AC Characteristics.................................................................18 7.3 Op amp AC Characteristics...............................................................................................19 7.4 SYNC to SVPWM and A/D Conversion AC Timing ...........................................................20 7.5 GATEKILL to SVPWM AC Timing .....................................................................................21 7.6 Interrupt AC Timing ...........................................................................................................21 7.7 I2C AC Timing....................................................................................................................22 7.8 SPI AC Timing...................................................................................................................23 7.8.1 SPI Write AC timing ....................................................................................................23 7.8.2 SPI Read AC Timing...................................................................................................24 7.9 UART AC Timing...............................................................................................................25 7.10 CAPTURE Input AC Timing ...........................................................................................26 7.11 JTAG AC Timing ............................................................................................................27 8 Pin List .....................................................................................................................................28 9 Package Dimensions ...............................................................................................................31 10 Part Marking Information ......................................................................................................32 2 IRMCF341 TABLE OF FIGURES Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Typical Application Block Diagram Using IRMCF341.....................................................4 IRMCF341 Internal Block Diagram .................................................................................5 IRMCF341 Pin Configuration..........................................................................................7 Input/Output of IRMCF341..............................................................................................8 Application Connection of IRMCF341 ..........................................................................12 Clock Frequency vs. Power Consumption....................................................................13 TABLE OF TABLES Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Absolute Maximum Ratings ...........................................................................................13 System Clock Frequency ...............................................................................................13 Digital I/O DC Characteristics ........................................................................................14 PLL DC Characteristics .................................................................................................15 Analog I/O DC Characteristics .......................................................................................15 UVcc DC Characteristics ...............................................................................................16 CMEXT and AREF DC Characteristics..........................................................................16 PLL AC Characteristics..................................................................................................17 A/D Converter AC Characteristics .................................................................................18 Current Sensing OP Amp AC Characteristics..............................................................19 SYNC AC Characteristics ............................................................................................20 GATEKILL to SVPWM AC Timing ...............................................................................21 Interrupt AC Timing......................................................................................................21 I2C AC Timing ..............................................................................................................22 SPI Write AC Timing ....................................................................................................23 SPI Read AC Timing....................................................................................................24 UART AC Timing .........................................................................................................25 CAPTURE AC Timing ..................................................................................................26 JTAG AC Timing ..........................................................................................................27 Pin List .........................................................................................................................30 3 IRMCF341 1 Overview IRMCF341 is a new International Rectifier integrated circuit device primarily designed as a onechip solution for complete inverter controlled appliance motor control applications. Unlike a traditional microcontroller or DSP, the IRMCF341 provides a built-in closed loop sensorless control algorithm using the unique Motion Control Engine (MCETM) for permanent magnet motors. The MCETM consists of a collection of control elements, motion peripherals, a dedicated motion control sequencer and dual port RAM to map internal signal nodes. IRMCF341 also employs a unique single shunt current reconstruction circuit to eliminate additional analog/digital circuitry and enables a direct shunt resistor interface to the IC. Motion control programming is achieved using a dedicated graphical compiler integrated into the MATLAB/SimulinkTM development environment. Sequencing, user interface, host communication, and upper layer control tasks can be implemented in the 8051 high-speed 8-bit microcontroller. The 8051 microcontroller is equipped with a JTAG port to facilitate emulation and debugging tools. Figure 1 shows a typical application schematic using the IRMCF341. IRMCF341 is intended for development purpose and contains 48K bytes of RAM, which can be loaded from external EEPROM for 8051 program execution. For high volume production, IRMCK341 contains OTP ROM in place of program RAM to reduce the cost. Both IRMCF341 and IRMCK341 come in the same 64-pin QFP package with identical pin configuration to facilitate PC board layout and transition to mass production Appliance Inverter Passive EMI Filter HVIC Gate Drive & Protection Circuit Multiple Output Power Supply 1.8 V Motor (PMSM) IRMCF341 3.3 V 7 Analog Input Upto 24 Digital Input/Output I2C Interface to EEPROM UART interface to Front Panel Figure 1. Typical Application Block Diagram Using IRMCF341 4 IRMCF341 2 IRMCF341 Block Diagram and Main Functions Figure 2. Motion Control Bus 8bit uP Address/Data bus IRMCF341 block diagram is shown in Figure 2. IRMCF341 Internal Block Diagram IRMCF341 contains the following functions for sensorless AC motor control applications: • Motion Control Engine (MCETM) o Proportional plus Integral block o Low pass filter o Differentiator and lag (high pass filter) o Ramp o Limit o Angle estimate (sensorless control) o Inverse Clark transformation o Vector rotator o Bit latch o Peak detect 5 IRMCF341 o o o o o o o o o o o o o o o • Transition Multiply-divide (signed and unsigned) Divide (signed and unsigned) Adder Subtractor Comparator Counter Accumulator Switch Shift ATAN (arc tangent) Function block (any curve fitting, nonlinear function) 16-bit wide Logic operations (AND, OR, XOR, NOT, NEGATE) MCETM program and data memory (6K byte). Note 1 MCETM control sequencer 8051 microcontroller o Three 16-bit timer/counters o 16-bit periodic timer o 16-bit analog watchdog timer o 16-bit capture timer o Up to 24 discrete I/Os o Eight-channel 12-bit A/D One buffered channel for current sensing (0 – 1.2V input) Seven unbuffered channels (0 – 1.2V input) o JTAG port (4 pins) o Up to three channels of analog output (8-bit PWM) o UART o I2C/SPI port o 48K byte program RAM loaded from external EEPROM o 2K byte data RAM. Note 1 Note 1: Total size of RAM is 8K byte including MCE program, MCE data, and 8051 data. Different sizes can be allocated depending on applications. 6 IRMCF341 3 Pinout Figure 3. IRMCF341 Pin Configuration 7 IRMCF341 4 Input/Output of IRMCF341 All I/O signals of IRMCF341 are shown in Figure 4. All I/O pins are 3.3V logic interface except A/D interface pins. Crystal XTAL0 XTAL1 UART Interface P1.2/TXD P1.1/RXD I2C Interface SDA/CS0 SCL/SO-SI Discrete I/O System Reset PWMVH PWMVL PWMWH PWMWL GATEKILL P1.0/T2 P1.3/SYNC/SCK P1.4/CAP P1.5 P1.6 P1.7 P2.0/NMI P2.1 P2.2 P2.3 P2.4 P2.5 P3.0/INT2/CS1 P3.2/INT0 P3.3/INT1 P3.5/T1 AVDD (1.8V) AVSS TCK P5.3/TDI P5.1/TMS P5.2/TDO D/A Interface (PWM output) P2.6/AOPWM0 P2.7/AOPWM1 P3.1/AOPWM2 Analog power/ ground AREF IFB+ IFBIFBO AIN0 A/D Interface AIN1 AIN2 AIN3 AIN4 AIN5 AIN6 TSTMOD Figure 4. 4.1 PWM gate signal Interface CMEXT RESET JTAG port Test Mode (must be tied to VSS) PWMUH PWMUL VDD1 (3.3V) VDD2 (1.8V) VSS Digital power/ ground PLLVDD (1.8V) PLLVSS PLL power/ ground Input/Output of IRMCF341 8051 Peripheral Interface Group UART Interface TXD RXD Output, Transmit data from IRMCF341 Input, Receive data to IRMCF341 Discrete I/O Interface P1.0/T2 Input/output port 1.0, can be configured as Timer/Counter 2 input P1.1/RXD Input/output port 1.1, can be configured as RXD input P1.2/TXD Input/output port 1.2, can be configured as TXD output 8 IRMCF341 P1.3/SYNC/SCK Input/output port 1.3, can be configured as SYNC output or SPI clock output, needs to be pulled up to VDD1 in order to boot from I2C EEPROM P1.4/CAP Input/output port 1.4, can be configured as Capture Timer input P1.5 Input/output port 1.5 P1.6 Input/output port 1.6 P1.7 Input/output port 1.7 P2.0/NMI Input/output port 2.0, can be configured as non-maskable interrupt input P2.1 Input/output port 2.1 P2.2 Input/output port 2.2 P2.3 Input/output port 2.3 P2.4 Input/output port 2.4 P2.5 Input/output port 2.5 P2.6/AOPWM0 Input/output port 2.6, can be configured as AOPWM0 output P2.7/AOPWM1 Input/output port 2.7, can be configured as AOPWM1 output P3.0/INT2/CS1 Input/output port 3.0, can be configured as INT2 input or SPI chip select 1 P3.1/AOPWM2 Input/output port 3.1, can be configured as AOPWM2 output P3.2/NINT0 Input/output port 3.2, can be configured as INT0 input P3.3/NINT1 Input/output port 3.3, can be configured as INT1 input P3.5/T1 Input/output port 3.5, can be configured as Timer/Counter 1 input P5.1/TSM Input/output port 5.1, configured as JTAG port by default P5.2/TDO Input/output port 5.2, configured as JTAG port by default P5.3/TDI Input/output port 5.3, configured as JTAG port by default Analog Output Interface P2.6/AOPWM0 Input/output, can be configured as 8-bit PWM output 0 with programmable carrier frequency P2.7/AOPWM1 Input/output, can be configured as 8-bit PWM output 1 with programmable carrier frequency P3.1/AOPWM2 Input/output, can be configured as 8-bit PWM output 2 with programmable carrier frequency Crystal Interface XTAL0 XTAL1 Reset Interface RESET Input, connected to crystal Output, connected to crystal Inout, system reset, needs to be pulled up to VDD1 but doesn’t require external RC time constant I2C Interface SCL/SO-SI SDA/CS0 Output, I2C clock output, or SPI data Input/output, I2C Data line or SPI chip select 0 I2C/SPI Interface SCL/SO-SI SDA/CS0 Output, I2C clock output, or SPI data Input/output, I2C data line or SPI chip select 0 9 IRMCF341 P1.3/SYNC/SCK Input/output port 1.3, can be configured as SYNC output or SPI clock output, needs to be pulled up to VDD1 in order to boot from I2C EEPROM P3.0/INT2/CS1 Input/output port 3.0, can be configured as INT2 input or SPI chip select 1 4.2 Motion Peripheral Interface Group PWM PWMUH PWMUL PWMVH PWMVL PWMWH PWMWL Fault GATEKILL 4.3 Output, PWM phase U high side gate signal Output, PWM phase U low side gate signal Output, PWM phase V high side gate signal Output, PWM phase V low side gate signal Output, PWM phase W high side gate signal Output, PWM phase W low side gate signal Input, upon assertion, this negates all six PWM signals, programmable logic sense Analog Interface Group AVDD AVSS AREF CMEXT IFB+ IFBIFBO AIN0 AIN1 AIN2 AIN3 AIN4 AIN5 AIN6 Analog power (1.8V) Analog power return 0.6V buffered output Unbuffered 0.6V, input to the AREF buffer, capacitor needs to be connected. Input, Operational amplifier positive input for shunt resistor current sensing Input, Operational amplifier negative input for shunt resistor current sensing Output, Operational amplifier output for shunt resistor current sensing Input, Analog input channel 0 (0 – 1.2V), typically configured for DC bus voltage input Input, Analog input channel 1 (0 – 1.2V), needs to be pulled down to AVSS if unused Input, Analog input channel 2 (0 – 1.2V), needs to be pulled down to AVSS if unused Input, Analog input channel 3 (0 – 1.2V), needs to be pulled down to AVSS if unused Input, Analog input channel 4 (0 – 1.2V), needs to be pulled down to AVSS if unused Input, Analog input channel 5 (0 – 1.2V), needs to be pulled down to AVSS if unused Input, Analog input channel 6 (0 – 1.2V), needs to be pulled down to AVSS if unused 10 IRMCF341 4.4 Power Interface Group VDD1 VDD2 VSS PLLVDD PLLVSS 4.5 Digital power for I/O (3.3V) Digital power for core logic (1.8V) Digital common PLL power (1.8V) PLL ground return Test Interface Group TSTMOD P5.1/TSM P5.2/TDO P5.3/TDI TCK Must be tied to VSS, used only for factory testing. Input/output port 5.1, configured as JTAG port by default Input/output port 5.2, configured as JTAG port by default Input/output port 5.3, configured as JTAG port by default Input, JTAG test clock 11 IRMCF341 5 Application Connections Typical application connection is shown in Figure 5. All components necessary to implement a complete sensorless drive control algorithm are shown connected to IRMCF341. Figure 5. Application Connection of IRMCF341 12 IRMCF341 6 DC Characteristics 6.1 Absolute Maximum Ratings Symbol VDD1 VDD2 VIA VID TA TS Parameter Supply Voltage Supply Voltage Analog Input Voltage Digital Input Voltage Ambient Temperature Storage Temperature Table 1. Min Typ Max -0.3 V 3.6 V -0.3 V 1.98 V -0.3 V 1.98 V -0.3 V 3.65 V -40 ˚C 85 ˚C -65 ˚C 150 ˚C Absolute Maximum Ratings Condition Respect to VSS Respect to VSS Respect to AVSS Respect to VSS Caution: Stresses beyond those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only and function of the device at these or any other conditions beyond those indicated in the operational sections of the specifications are not implied. System Clock Frequency and Power Consumption Symbol SYSCLK Parameter System Clock Table 2. Min Typ Max 32 128 System Clock Frequency Unit MHz 240 200 160 Power (mW) 6.2 120 80 VDD2 (1.8V) 40 VDD1 (3.3V) Total 0 0 Figure 6. 50 100 150 Clock Frequency (MHz) Consumption Clock Frequency vs. Power 13 IRMCF341 6.3 Digital I/O DC Characteristics Symbol VDD1 VDD2 VIL VIH CIN IL IOL1(2) IOH1(2) IOL2(3) IOH2(3) Parameter Supply Voltage Supply Voltage Input Low Voltage Input High Voltage Input capacitance Input leakage current Low level output current High level output current Low level output current High level output current Table 3. Min 3.0 V 1.62 V -0.3 V 2.0 V - Typ 3.3 V 1.8 V - Condition Recommended Recommended Recommended Recommended 8.9 mA 3.6 pF ±10 nA 13.2 mA Max 3.6 V 1.98 V 0.8 V 3.6 V ±1 μA 15.2 mA 12.4 mA 24.8 mA 38 mA VOH (1) = 2.4 V 17.9 mA 26.3 mA 33.4 mA VOL (1) = 0.4 V 24.6 mA 49.5 mA 81 mA VOH (1) = 2.4 V (1) VO = 3.3 V or 0 V VOL = 0.4 V (1) Digital I/O DC Characteristics Note: (1) Data guaranteed by design. (2) Applied to SCL/SO-SI, SDA/CS0 pins. (3) Applied to P1.0/T2, P1.1/RXD, P1.2/TXD, P1.3/SYNC/SCK, P1.4/CAP, P1.5, P1.6, P1.7, P2.0/NMI, P2.1, P2.2, P2.3, P2.4, P2.5, P2.6/AOPWM0, P2.7/AOPWM1, P3.0/INT2/CS1, P3.1/AOPWM2, P3.2/INT0, P3.3/INT1, P3.5/T1, P3.6/RXD1, P3.7/TXD1, P5.1/TMS, P5.2/TDO, P5.3/TDI, GATEKILL, PWMUL, PWMUH, PWMVL, PWMVH, PWMWL, and PWMWH pins. 14 IRMCF341 6.4 PLL and Oscillator DC characteristics Symbol VPLLVDD VIL OSC VIH OSC Parameter Min Typ Max Supply Voltage 1.62 V 1.8 V 1.92 V Oscillator Input Low VPLLVSS 0.2* Voltage VPLLVDD Oscillator Input High 0.8* VPLLVDD Voltage VPLLVDD Table 4. PLL DC Characteristics Condition Recommended VPLLVDD = 1.8 V (1) VPLLVDD (1) = 1.8 V Note: (1) Data guaranteed by design. 6.5 Analog I/O DC Characteristics - OP amp for current sensing (IFB+, IFB-, IFBO) CAREF = 1nF, CMEXT= 100nF. Unless specified, Ta = 25˚C. Symbol Parameter Min Typ VAVDD Supply Voltage 1.71 V 1.8 V VOFFSET Input Offset Voltage VI Input Voltage Range 0V VOUTSW OP amp output 50 mV (1) operating range CIN Input capacitance 3.6 pF RFDBK OP amp feedback 5 kΩ resistor OP GAINCL CMRR ISRC ISNK Operating Close loop Gain Common Mode Rejection Ratio Op amp output source current Op amp output sink current Table 5. Max 1.89 V 26 mV 1.2 V 1.2 V Condition Recommended VAVDD = 1.8 V Recommended VAVDD = 1.8 V 20 kΩ (1) Requested between IFBO and IFB- 80 db - - (1) - 80 db - (1) - 1 mA - VOUT (1) = 0.6 V - 100 μA - VOUT (1) = 0.6 V Analog I/O DC Characteristics Note: (1) Data guaranteed by design. 15 IRMCF341 6.6 Under Voltage Lockout DC characteristics - Based on AVDD (1.8V) Unless specified, Ta = 25˚C. Symbol Parameter Min Typ Max UVCC+ UVcc positive going 1.53 V 1.66 V 1.71 V Threshold UVCCUVcc negative going 1.52 V 1.62 V 1.71 V Threshold UVCCH UVcc Hysteresys 40 mV Table 6. UVcc DC Characteristics 6.7 Condition VDD1 = 3.3 V VDD1 = 3.3 V CMEXT and AREF Characteristics CAREF = 1nF, CMEXT= 100nF. Unless specified, Ta = 25˚C. Symbol Parameter Min Typ Max VCM CMEXT voltage 495 mV 600 mV 700 mV VAREF Buffer Output Voltage 495 mV 600 mV 700 mV Load regulation (VDC-0.6) 1 mV ΔVo PSRR Power Supply Rejection 75 db Ratio Table 7. CMEXT and AREF DC Characteristics Condition VAVDD = 1.8 V VAVDD = 1.8 V (1) (1) 16 IRMCF341 7 AC Characteristics 7.1 PLL AC Characteristics Symbol FCLKIN FPLL FLWPW JS D TLOCK Parameter Min Typ Max Crystal input 3.2 MHz 4 MHz 60 MHz frequency Internal clock 32 MHz 50 MHz 128 MHz frequency Sleep mode output FCLKIN ÷ 256 frequency Short time jitter 200 psec Duty cycle 50 % PLL lock time 500 μsec Table 8. PLL AC Characteristics Condition (1) (see figure below) (1) (1) (1) (1) (1) Note: (1) Data guaranteed by design. R1=1M R2=10 Xtal C1=30PF C2=30PF 17 IRMCF341 7.2 Analog to Digital Converter AC Characteristics Unless specified, Ta = 25˚C. Symbol Parameter TCONV Conversion time THOLD Sample/Hold maximum hold time Min - Table 9. Typ - Max 2.05 μsec 10 μsec Condition (1) Voltage droop ≤ 15 LSB (see figure below) A/D Converter AC Characteristics Note: (1) Data guaranteed by design. Input Voltage Voltage droop S/H Voltage tSAMPLE THOLD 18 IRMCF341 7.3 Op amp AC Characteristics - OP amp for current sensing (IFB+, IFB-, IFBO) Unless specified, Ta = 25˚C. Symbol Parameter OPSR OP amp slew rate OPIMP TSET OP input impedance Settling time Table 10. Min - Typ 10 V/μsec Max - - 108 Ω 400 ns - Condition VAVDD = 1.8 V, CL = 33 pF (1) (1) VAVDD = 1.8 V, CL = 33 pF (1) Current Sensing OP Amp AC Characteristics Note: (1) Data guaranteed by design. 19 IRMCF341 7.4 SYNC to SVPWM and A/D Conversion AC Timing twSYNC SYNC tdSYNC1 IU,IV,IW tdSYNC2 AINx tdSYNC3 PWMUx,PWMVx,PWMWx Unless specified, Ta = 25˚C. Symbol Parameter twSYNC SYNC pulse width tdSYNC1 SYNC to current feedback conversion time tdSYNC2 SYNC to AIN0-6 analog input conversion time tdSYNC3 SYNC to PWM output delay time Table 11. Min - Typ 32 - Max 100 Unit SYSCLK SYSCLK - - 200 SYSCLK - - 2 SYSCLK (1) SYNC AC Characteristics Note: (1) AIN1 through AIN6 channels are converted once every 6 SYNC events 20 IRMCF341 7.5 GATEKILL to SVPWM AC Timing Unless specified, Ta = 25˚C. Symbol Parameter Min Typ Max twGK GATEKILL pulse width 32 tdGK GATEKILL to PWM 100 output delay Table 12. GATEKILL to SVPWM AC Timing 7.6 Unit SYSCLK SYSCLK Interrupt AC Timing Unless specified, Ta = 25˚C. Symbol Parameter Min Typ Max twINT INT0, INT1 Interrupt 4 Assertion Time tdINT INT0, INT1 latency 4 Table 13. Interrupt AC Timing Unit SYSCLK SYSCLK 21 IRMCF341 7.7 I2C AC Timing TI2CLK TI2CLK SCL tI2ST1 tI2WSETUP tI2ST2 tI2WHOLD tI2RSETUP tI2EN1 tI2RHOLD tI2EN2 SDA Unless specified, Ta = 25˚C. Symbol Parameter 2 TI2CLK I C clock period tI2ST1 I2C SDA start time tI2ST2 I2C SCL start time tI2WSETUP I2C write setup time tI2WHOLD I2C write hold time tI2RSETUP I2C read setup time tI2RHOLD I2C read hold time Min Typ 10 0.25 0.25 0.25 0.25 I2C filter time(1) 1 Table 14. I2C AC Timing Max 8192 - Unit SYSCLK TI2CLK TI2CLK TI2CLK TI2CLK SYSCLK SYSCLK Note: (1) I2C read setup time is determined by the programmable filter time applied to I2C communication. 22 IRMCF341 7.8 SPI AC Timing 7.8.1 SPI Write AC timing Unless specified, Ta = 25˚C. Symbol Parameter TSPICLK SPI clock period tSPICLKHT SPI clock high time tSPICLKLT SPI clock low time tCSDELAY CS to data delay time tWRDELAY CLK falling edge to data delay time tCSHIGH CS high time between two consecutive byte transfer tCSHOLD CS hold time Table 15. Min 4 - Typ 1/2 1/2 - Max 10 10 Unit SYSCLK TSPICLK TSPICLK nsec nsec 1 - - TSPICLK 1 SPI Write AC Timing TSPICLK 23 IRMCF341 7.8.2 SPI Read AC Timing Unless specified, Ta = 25˚C. Symbol Parameter TSPICLK SPI clock period tSPICLKHT SPI clock high time tSPICLKLT SPI clock low time tCSRD CS to data delay time tRDSU SPI read data setup time tRDHOLD SPI read data hold time tCSHIGH CS high time between two consecutive byte transfer tCSHOLD CS hold time Table 16. Min 4 10 10 1 Typ 1/2 1/2 - Max 10 - 1 SPI Read AC Timing Unit SYSCLK TSPICLK TSPICLK nsec nsec nsec TSPICLK TSPICLK 24 IRMCF341 7.9 UART AC Timing TBAUD TXD Start Bit Data and Parity Bit Stop Bit RXD TUARTFIL Unless specified, Ta = 25˚C. Symbol Parameter Min Typ TBAUD Baud Rate Period 57600 TUARTFIL UART sampling filter 1/16 period (1) Table 17. UART AC Timing Max - Unit bit/sec TBAUD Note: (1) Each bit including start and stop bit is sampled three times at center of a bit at an interval of 1/16 TBAUD. If three sampled values do not agree, then UART noise error is generated. 25 IRMCF341 7.10 CAPTURE Input AC Timing Unless specified, Ta = 25˚C. Symbol Parameter Min Typ Max TCAPCLK CAPTURE input period 8 tCAPHIGH CAPTURE input high 4 time tCAPLOW CAPTURE input low 4 time 4 tCRDELAY CAPTURE falling edge to capture register latch time 4 tCLDELAY CAPTURE rising edge to capture register latch time tINTDELAY CAPTURE input 4 interrupt latency time Table 18. CAPTURE AC Timing Unit SYSCLK SYSCLK SYSCLK SYSCLK SYSCLK SYSCLK 26 IRMCF341 7.11 JTAG AC Timing TJCLK TCK tJHIGH tJLOW tCO TDO tJSETUP tJHOLD TDI/TMS Unless specified, Ta = 25˚C. Symbol Parameter TJCLK TCK Period tJHIGH TCK High Period tJLOW TCK Low Period tCO TCK to TDO propagation delay time tJSETUP TDI/TMS setup time tJHOLD TDI/TMS hold time Table 19. Min 10 10 0 Typ - 4 0 JTAG AC Timing Max 50 5 Unit MHz nsec nsec nsec - nsec nsec 27 IRMCF341 8 Pin List Pin Number Pin Name Internal Pull-up /Pull-down Pin Type 1 2 3 XTAL0 XTAL1 P1.0/T2 I O I/O 4 5 P1.1/RXD P1.2/TXD I/O I/O 6 P1.3/SYNC/SCK I/O 7 8 9 10 11 12 13 14 P1.4/CAP P1.5 P1.6 P1.7 VDD2 VSS VDD1 P2.0/NMI I/O I/O I/O I/O P P P I/O 15 16 17 18 19 20 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6/AOPWM0 I/O I/O I/O I/O I/O I/O 21 P2.7/AOPWM1 I/O 22 23 24 VDD2 VSS AIN0 P P I 25 26 27 AVDD AVSS AIN1 P P I 28 CMEXT O 29 30 31 32 AREF IFBIFB+ IFBO O I I O Description Crystal input Crystal output Discrete programmable I/O or Timer/Counter 2 input Discrete programmable I/O or UART receive input Discrete programmable I/O or UART transmit output Discrete programmable I/O or SYNC output or SPI clock output, needs to be pulled up to VDD1 in order to boot from I2C EEPROM Discrete programmable I/O or Capture timer input Discrete programmable I/O Discrete programmable I/O Discrete programmable I/O 1.8V digital power Digital common 3.3V digital power Discrete programmable I/O or Non-maskable Interrupt input Discrete programmable I/O Discrete programmable I/O Discrete programmable I/O Discrete programmable I/O Discrete programmable I/O Discrete programmable I/O or PWM 0 digital output Discrete programmable I/O or PWM 1 digital output 1.8V digital power Digital common Analog input channel 0, 0-1.2V range, needs to be pulled down to AVSS if unused 1.8V analog power Analog common Analog input channel 1, 0-1.2V range, needs to be pulled down to AVSS if unused Unbuffered 0.6V output. Capacitor needs to be connected. Analog reference voltage output (0.6V) Single shunt current sensing OP amp input (-) Single shunt current sensing OP amp input (+) Single shunt current sensing OP amp output 28 IRMCF341 Pin Number Pin Name Internal Pull-up /Pull-down Pin Type 33 AIN2 I 34 AIN3 I 35 AIN4 I 36 AIN5 I 37 AIN6 I 38 39 40 41 VDD2 VSS VDD1 GATEKILL P P P I 42 PWMWL 43 PWMWH 44 PWMVL 45 PWMVH 46 PWMUL 47 PWMUH 48 P3.0/INT2/CS1 I/O 49 P3.1/AOPWM2 I/O 50 51 52 53 54 55 P3.2/INT0 P3.3/INT1 P3.5/T1 VSS VDD1 SCL/SO-SI I/O I/O I/O P P I/O 56 SDA/CS0 I/O 57 58 59 60 P5.1/TMS P5.2/TDO P5.3/TDI TCK I/O I/O I/O I 70 kΩ Pull up 70 kΩ Pull up 70 kΩ Pull up 70 kΩ Pull up 70 kΩ Pull up 70 kΩ Pull up O O O O O O Description Analog input channel 2, 0-1.2V range, needs to be pulled down to AVSS if unused Analog input channel 3, 0-1.2V range, needs to be pulled down to AVSS if unused Analog input channel 4, 0-1.2V range, needs to be pulled down to AVSS if unused Analog input channel 5, 0-1.2V range, needs to be pulled down to AVSS if unused Analog input channel 6, 0-1.2V range, needs to be pulled down to AVSS if unused 1.8V digital power Digital common 3.3V digital power PWM shutdown input, 2-μsec digital filter, configurable either high or low true. PWM gate drive for phase W low side, configurable either high or low true PWM gate drive for phase W high side, configurable either high or low true PWM gate drive for phase V low side, configurable either high or low true PWM gate drive for phase V high side, configurable either high or low true PWM gate drive for phase U low side, configurable either high or low true PWM gate drive for phase U high side, configurable either high or low true Discrete programmable I/O or external interrupt 2 input or SPI Chip Select 1 Discrete programmable I/O or PWM 2 digital output Discrete programmable I/O or Interrupt 0 input Discrete programmable I/O or Interrupt 1 input Discrete programmable I/O or Timer/Counter 1 Digital common 3.3V digital power I2C clock output (open drain, need pull up) or SPI data 2 I C data (open drain, need pull up) or SPI Chip Select 0 JTAG test mode select JTAG test data output JTAG test data input JTAG test clock 29 IRMCF341 Pin Number Pin Name 61 TSTMOD 62 63 64 RESET PLLVDD PLLVSS Internal Pull-up /Pull-down 58 kΩ pull down Pin Type Description I Test mode. Must be tied to VSS. Factory use only I/O P P Table 20. Reset, low true, Schmitt trigger input 1.8V PLL power PLL ground Pin List 30 IRMCF341 9 Package Dimensions 31 IRMCF341 10 Part Marking Information IRMCF341 Part Number IR Logo YWWP Date Code XXXXXX Production Lot Pin 1 Indentifier Order Information Lead-Free Part in 64-lead QFP Moisture sensitivity rating – MSL3 Part number IRMCF341TR IRMCF341TY Order quantities 1500 parts on tape and reel in dry pack 1600 parts on trays (160 parts per tray) in dry pack The LQFP-64 is MSL3 qualified This product has been designed and qualified for the industrial level Qualification standards can be found at www.irf.com <http://www.irf.com> IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, Tel: (310) 252-7105 Data and specifications subject to change without notice. 12/05/2006 www.irf.com 32