AD ADT7516ARQ-REEL7 Spi-/i2c-compatible, temperature sensor,4-channel adc and quad voltage output Datasheet

SPI-/I2C-Compatible, Temperature Sensor,
4-Channel ADC and Quad Voltage Output
ADT7516/ADT7517/ADT7519
FEATURES
APPLICATIONS
Portable battery-powered instruments
Personal computers
Smart battery chargers
Telecommunications systems
Electronic text equipment
Domestic appliances
Process control
PIN CONFIGURATION
VOUT-B 1
VOUT-A 2
VREF -IN 3
CS 4
16 VOUT-C
ADT7516/
ADT7517/
ADT7519
15 VOUT-D
14 AIN4
13 SCL/SCLK
TOP VIEW
12 SDA/DIN
(Not to Scale)
11 DOUT/ADD
VDD 6
D+/AIN1 7
10 INT/INT
GND 5
D–/AIN2 8
9
LDAC/AIN3
02883-006
ADT7516: four 12-bit DACs
ADT7517: four 10-bit DACs
ADT7519: four 8-bit DACs
Buffered voltage output
Guaranteed monotonic by design over all codes
10-bit temperature-to-digital converter
10-bit 4-channel ADC
DC input bandwidth
Input range: 0 V to 2.28 V
Temperature range: −40°C to +120°C
Temperature sensor accuracy: ±0.5°C typ
Supply range: 2.7 V to 5.5 V
DAC output range: 0 V to 2 VREF
Power-down current: <10 μA
Internal 2.28 VREF option
Double-buffered input logic
Buffered reference input
Power-on reset to 0 V DAC output
Simultaneous update of outputs (LDAC function)
On-chip, rail-to-rail output buffer amplifier
SPI®, I2C®, QSPI™, MICROWIRE™, and DSP compatible
4-wire serial interface
SMBus packet error checking (PEC) compatible
16-lead QSOP package
Figure 1.
GENERAL DESCRIPTION
The ADT7516/ADT7517/ADT75191 combine a 10-bit temperature-to-digital converter, a 10-bit 4-channel ADC, and a quad
12-/10-/8-bit DAC, respectively, in a 16-lead QSOP package.
The parts also include a band gap temperature sensor and a
10-bit ADC to monitor and digitize the temperature reading to
a resolution of 0.25°C.
The ADT7516/ADT7517/ADT7519 operate from a single 2.7 V
to 5.5 V supply. The input voltage range on the ADC channels is
0 V to 2.28 V, and the input bandwidth is dc. The reference for
the ADC channels is derived internally. The output voltage of
the DAC ranges from 0 V to VDD, with an output voltage settling
time of 7 μs typical.
The ADT7516/ADT7517/ADT7519 provide two serial interface
options: a 4-wire serial interface that is compatible with SPI,
QSPI, MICROWIRE, and DSP interface standards, and a 2-wire
SMBus/I2C interface. They feature a standby mode that is
controlled through the serial interface.
The reference for the four DACs is derived either internally or
from a reference pin. The outputs of all DACs can be updated
simultaneously using the software LDAC function or the
external LDAC pin. The ADT7516/ADT7517/ADT7519
incorporate a power-on reset circuit, ensuring that the DAC
output powers up to 0 V and remains there until a valid write
takes place.
The wide supply voltage range, low supply current, and SPI-/
I2C-compatible interface of the ADT7516/ADT7517/ADT7519
make them ideal for a variety of applications, including
personal computers, office equipment, and domestic appliances.
1
Protected by U.S. Patent Numbers: 6,169,442; 5,867,012; and 5,764,174. Other patents pending.
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2006 Analog Devices, Inc. All rights reserved.
ADT7516/ADT7517/ADT7519
TABLE OF CONTENTS
Features .............................................................................................. 1
Terminology .................................................................................... 17
Applications....................................................................................... 1
Theory of Operation ...................................................................... 19
Pin Configuration............................................................................. 1
Power-Up Calibration................................................................ 19
General Description ......................................................................... 1
Conversion Speed....................................................................... 19
Revision History ............................................................................... 2
Function Description—Voltage Output.................................. 20
Specifications..................................................................................... 3
Functional Description—Analog Inputs................................. 23
DAC AC Characteristics.............................................................. 6
ADC Transfer Function............................................................. 23
Timing Diagrams.......................................................................... 7
Functional Description—Measurement.................................. 25
Functional Block Diagram .............................................................. 8
ADT7516/ADT7517/ADT7519 Registers............................... 28
Absolute Maximum Ratings............................................................ 9
Serial Interface ............................................................................ 37
ESD Caution.................................................................................. 9
SMBus Alert Response .............................................................. 42
Pin Configuration and Functional Descriptions........................ 10
Outline Dimensions ....................................................................... 43
Typical Performance Characteristics ........................................... 11
Ordering Guide .......................................................................... 43
REVISION HISTORY
10/06—Rev. A to Rev. B
8/04—Rev. 0 to Rev. A
Updated Format..................................................................Universal
Changes to Features..........................................................................1
Changes to General Description.....................................................1
Changes to Specifications.................................................................3
Changes to Absolute Maximum Ratings........................................9
Changes to Table 10........................................................................28
Changes to ADT7516/ADT7517/ADT7519 Registers Section......28
Changes to Serial Interface Section...............................................37
Changes to Ordering Guide...........................................................44
Updated Format...................................................................... Universal
Deleted ADT7518
Added ADT7519..................................................................... Universal
Change to Internal VREF Value .............................................................5
Change to Equation.............................................................................26
7/03—Initial Version: Rev. 0
Rev. B | Page 2 of 44
ADT7516/ADT7517/ADT7519
SPECIFICATIONS
Temperature range is as follows: A version: −40°C to +120°C, VDD = 2.7 V to 5.5 V, GND = 0 V, REFIN = 2.25 V, unless otherwise noted.
Table 1.
Parameter 1
DAC DC PERFORMANCE 2, 3
ADT7519
Resolution
Relative Accuracy
Differential Nonlinearity
ADT7517
Resolution
Relative Accuracy
Differential Nonlinearity
ADT7516
Resolution
Relative Accuracy
Differential Nonlinearity
Offset Error
Gain Error
Lower Deadband
Min
Upper Deadband
Offset Error Drift 4
Gain Error Drift4
DC Power Supply Rejection Ratio4
DC Crosstalk4
ADC DC ACCURACY
Resolution
Total Unadjusted Error (TUE)
Total Unadjusted Error (TUE)
Offset Error
Gain Error
ADC BANDWIDTH
ANALOG INPUTS
Input Voltage Range
DC Leakage Current
Input Capacitance
Input Resistance
THERMAL CHARACTERISTICS
Internal Temperature Sensor
Accuracy @ VDD = 3.3 V ±10%
Accuracy @ VDD = 5 V ±5%
Resolution
Long-Term Drift
Typ
Max
Unit
Conditions/Comments
8
±0.15
±0.02
±1
±0.25
Bits
LSB
LSB
Guaranteed monotonic over all codes
10
±0.5
±0.05
±4
±0.5
Bits
LSB
LSB
Guaranteed monotonic over all codes
12
±2
±0.02
±0.4
±0.3
20
±16
±0.9
±2
±2
65
Bits
LSB
LSB
% of FSR
% of FSR
mV
60
100
mV
–12
–5
–60
200
2
0
0
5
10
±0.5
±2
±2
±3
0.25
ppm of FSR/°C
ppm of FSR/°C
dB
μV
10
3
2
±0.5
±2
DC
Bits
% of FSR
% of FSR
% of FSR
% of FSR
Hz
2.28
VDD
±1
20
V
V
μA
pF
MΩ
±1.5
±3
±5
±3
±5
10
°C
°C
°C
°C
°C
Bits
°C
Rev. B | Page 3 of 44
Guaranteed monotonic over all codes
Lower deadband exists only if offset error is
negative, see Figure 40
Upper deadband exists if VREF = VDD and off-set
plus gain error is positive, see Figure 41
∆VDD = ±10%
See Figure 5
Maximum VDD = 5 V
VDD = 2.7 V to 5.5 V
VDD = 3.3 V ±10%
AIN1 to AIN4, C4 = 0 in Control Configuration 3
AIN1 to AIN4, C4 = 0 in Control Configuration 3
Internal reference used, averaging on
TA = 85°C
TA = 0°C to +85°C
TA = –40°C to +120°C
TA = 0°C to +85°C
TA = –40°C to +120°C
Equivalent to 0.25°C
Drift over 10 years if part is operated at 55°C
ADT7516/ADT7517/ADT7519
Parameter 1
External Temperature Sensor
Accuracy @ VDD = 3.3 V ±10%
Min
Accuracy @ VDD = 5 V ±5%
10-Bit DAC Output
Resolution
Scale Factor
Max
Unit
±1.5
±3
±5
±3
±5
10
180
11
°C
°C
°C
°C
°C
Bits
μA
μA
Conditions/Comments
External transistor = 2N3906
TA = 85°C
TA = 0°C to +85°C
TA = −40°C to +120°C
TA = 0°C to +85°C
TA = −40°C to +120°C
Equivalent to 0.25°C
High level
Low level
8.97
17.58
°C
mV/°C
mV/°C
0 V to VREF output, TA = −40°C to +120°C
0 V to 2 VREF output, TA = −40°C to +120°C
2.2
4.39
°C
mV/°C
mV/°C
11.4
712
11.4
712
24.22
1.51
ms
μs
ms
μs
ms
ms
Averaging (16 samples) on
Averaging off
Averaging (16 samples) on
Averaging off
Averaging (16 samples) on
Averaging off
712
44.5
2.14
134
14.25
890
μs
μs
ms
μs
ms
μs
Averaging (16 samples) on
Averaging off
Averaging (16 samples) on
Averaging off
Averaging (16 samples) on
Averaging off
Time to complete one measurement cycle
through all channels
79.8
4.99
94.76
9.26
ms
ms
ms
ms
AIN1 and AIN2 are selected on Pin 7 and Pin 8
AIN1 and AIN2 are selected on Pin 7 and Pin 8
D+ and D– are selected on Pin 7 and Pin 8
D+ and D– are selected on Pin 7 and Pin 8
6.41
400.84
21.77
3.07
ms
μs
ms
ms
AIN1 and AIN2 are selected on Pin 7 and Pin 8
AIN1 and AIN2 are selected on Pin 7 and Pin 8
D+ and D– are selected on Pin 7 and Pin 8
D+ and D– are selected on Pin 7 and Pin 8
V
MΩ
dB
dB
Buffered reference
Buffered reference and power-down mode
Frequency = 10 kHz
Frequency = 10 kHz
±2
±3
Resolution
Output Source Current
Thermal Voltage Output
8-Bit DAC Output
Resolution
Scale Factor
Typ
1
0.25
CONVERSION TIMES
Slow ADC
VDD/AIN
Internal Temperature
External Temperature
Fast ADC
VDD/AIN
Internal Temperature
External Temperature
ROUND ROBIN UPDATE RATE 5
Slow ADC @ 25°C
Averaging On
Averaging Off
Averaging On
Averaging Off
Fast ADC @ 25°C
Averaging On
Averaging Off
Averaging On
Averaging Off
DAC EXTERNAL REFERENCE INPUT4
VREF Input Range
VREF Input Impedance
Reference Feedthrough
Channel-to-Channel Isolation
1
VDD
>10
–90
–75
Rev. B | Page 4 of 44
0 V to VREF output, TA = −40°C to +120°C
0 V to 2 VREF output, TA = −40°C to +120°C
Single channel mode
ADT7516/ADT7517/ADT7519
Parameter 1
ON-CHIP REFERENCE
Reference Voltage4
Temperature Coefficient4
OUTPUT CHARACTERISTICS4
Output Voltage 6
Min
Typ
Max
Unit
2.2662
2.28
80
2.2938
V
ppm/°C
VDD − 0.1
V
0.001
DC Output Impedance
Short Circuit Current
0.5
25
16
2.5
5
Power-Up Time
DIGITAL INPUTS4
Input Current
VIL, Input Low Voltage
VIH, Input High Voltage
Pin Capacitance
SCL, SDA Glitch Rejection
±1
0.8
1.89
3
μA
V
V
pF
ns
ns
2.4
This is a measure of the minimum and maximum
drive capability of the output amplifier
VDD = 5 V
VDD = 3 V
Coming out of power-down mode, VDD = 5 V
Coming out of power-down mode, VDD = 3.3 V
VIN = 0 V to VDD
All digital inputs
Input filtering suppresses noise spikes of less
than 50 ns
Edge triggered input
V
V
mA
pF
V
ISOURCE = ISINK = 200 μA
IOL = 3 mA
VOH = 5 V
2.5
50
0
50
μs
ns
ns
ns
Fast mode I2C, see Figure 2
See Figure 2
See Figure 2
50
ns
See Figure 2
300
300 9
ns
ns
See Figure 2
See Figure 2
See Figure 3
See Figure 3
See Figure 3
35
ns
ns
ns
ns
20
ns
See Figure 3
0
ns
See Figure 3
40
μs
ns
See Figure 3
See Figure 3
5.5
50
3
3
V
ms
mA
mA
VDD settles to within 10% of its final voltage level
VDD = 3.3 V, VIH = VDD, and VIL = GND
VDD = 5 V, VIH = VDD, and VIL = GND
0.4
1
50
0.8
IOUT = 4 mA
7, 8
I C TIMING CHARACTERISTICS
Serial Clock Period, t1
Data In Setup Time to SCL High, t2
Data Out Stable after SCL Low, t3
SDA Low Setup Time to SCL
Low (Start Condition), t4
SDA High Hold Time after SCL
High (Stop Condition), t5
SDA and SCL Fall Time, t6
SDA and SCL Rise Time, t7
SPI TIMING CHARACTERISTICS4, 10
CS to SCLK Setup Time, t1
SCLK High Pulse Width, t2
SCLK Low Pulse Width, t3
Data Access Time after SCLK
Falling Edge, t4 11
Data Setup Time Prior to SCLK
Rising Edge, t5
Data Hold Time after SCLK
Rising Edge, t6
CS to SCLK Hold Time, t7
CS to DOUT High Impedance, t8
POWER REQUIREMENTS
VDD
VDD Settling Time
IDD (Normal Mode) 12
10
50
20
LDAC Pulse Width
DIGITAL OUTPUT
Digital High Voltage, VOH
Output Low Voltage, VOL
Output High Current, IOH
Output Capacitance, COUT
INT/INT Output Saturation Voltage
2
Ω
mA
mA
μs
μs
Conditions/Comments
0
50
50
0
2.7
2.2
Rev. B | Page 5 of 44
ADT7516/ADT7517/ADT7519
Parameter 1
IDD (Power-Down Mode)
Min
Typ
Max
10
10
10
33
Power Dissipation
Unit
μA
μA
mW
μW
Conditions/Comments
VDD = 3.3 V, VIH = VDD, and VIL = GND
VDD = 5 V, VIH = VDD, and VIL = GND
VDD = 3.3 V, normal mode
VDD = 3.3 V, shutdown mode
1
See the Terminology section.
DC specifications are tested with the outputs unloaded.
Linearity is tested using a reduced code range: ADT7516 (Code 115 to 4095); ADT7517 (Code 28 to 1023); ADT7519 (Code 8 to 255).
4
Guaranteed by design and characterization, not production tested.
5
Round robin is the continuous sequential measurement of the following channels: VDD, internal temperature, external temperature (AIN1, AIN2), AIN3, and AIN4.
6
For the amplifier output to reach its minimum voltage, the offset error must be negative. For the amplifier output to reach its maximum voltage (VREF = VDD), the offset
plus gain error must be positive.
7
The SDA and SCL timing is measured with the input filters turned on to meet the fast mode I2C specification. Switching off the input filters improves the transfer rate
but has a negative effect on the EMC behavior of the part.
8
Guaranteed by design, not production tested. All I2C timing specifications are for fast mode operation but the interface is still capable of handling the slower standard
rate specifications.
9
The interface is also capable of handling the I2C standard mode rise time specification of 1000 ns.
10
All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD), and timed from a voltage level of 1.6 V.
11
Measured with the load circuit shown in Figure 4.
12
The IDD specification is valid for all DAC codes and full-scale analog input voltages. Interface inactive. All DACs and ADCs active. Load currents excluded.
2
3
DAC AC CHARACTERISTICS
VDD = 2.7 V to 5.5 V, RL = 4.7 kΩ to GND, CL = 200 pF to GND, 4.7 kΩ to VDD, all specifications TMIN to TMAX, unless otherwise noted.
Table 2.
Parameter 1, 2
Output Voltage Settling Time
ADT7519
ADT7517
ADT7516
Slew Rate
Major-Code Change Glitch Energy
Digital Feedthrough
Digital Crosstalk
Analog Crosstalk
DAC-to-DAC Crosstalk
Multiplying Bandwidth
Total Harmonic Distortion
1
2
3
Min
Typ 3
Max
Unit
6
7
8
0.7
12
0.5
1
0.5
3
200
–70
8
9
10
μs
μs
μs
V/μs
nV-s
nV-s
nV-s
nV-s
nV-s
kHz
dB
See the Terminology section.
Guaranteed by design and characterization, not production tested.
At 25°C.
Rev. B | Page 6 of 44
Conditions/Comments
VREF = VDD = 5 V
1/4 scale to 3/4 scale change (0x40 to 0xC0)
1/4 scale to 3/4 scale change (0x100 to 0x300)
1/4 scale to 3/4 scale change (0x400 to 0xC00)
1 LSB change around major carry
VREF = 2 V ±0.1 V p-p
VREF = 2.5 V ±0.1 V p-p; frequency = 10 kHz
ADT7516/ADT7517/ADT7519
TIMING DIAGRAMS
t1
SCL
t5
t2
t4
SDA
DATA IN
t3
02883-002
SDA
DATA OUT
t6
2
Figure 2. I C Bus Timing Diagram
CS
t1
t2
t7
SCLK
DIN
t6
t5
t8
D7
D6
D5
D4
D3
D2
D1
D0
X
X
X
X
X
X
X
X
X
X
D7
D6
X
X
X
X
X
X
D5
D4
D3
D2
D1
D0
t4
Figure 3. SPI Bus Timing Diagram
200µA
1.6V
CL
50pF
200µA
02883-004
TO OUTPUT
PIN
IOL
IOH
Figure 4. Load Circuit for Access Time and Bus Relinquish Time
VDD
4.7kΩ
TO DAC
OUTPUT
4.7kΩ
200pF
02883-005
DOUT
Figure 5. Load Circuit for DAC Outputs
Rev. B | Page 7 of 44
02883-003
t3
ADT7516/ADT7517/ADT7519
FUNCTIONAL BLOCK DIAGRAM
INTERNAL
TEMPERATURE
VALUE REGISTER
AIN4 14
VDD
SENSOR
THIGH LIMIT
REGISTERS
TLOW LIMIT
REGISTERS
VCC LIMIT
REGISTERS
AINHIGH LIMIT
REGISTERS
AINLOW LIMIT
REGISTERS
VDD
VALUE REGISTER
CONTROL CONFIG. 1
AIN1
VALUE REGISTER
CONTROL CONFIG. 2
AIN2
VALUE REGISTER
CONTROL CONFIG. 3
REGISTER
REGISTER
DAC A
REGISTERS
STRING
DAC A
2
VOUT-A
DAC B
REGISTERS
STRING
DAC B
1
VOUT-B
DAC C
REGISTERS
STRING
DAC C
16 VOUT-C
DAC D
REGISTERS
STRING
DAC D
15 VOUT-D
REGISTER
AIN3
VALUE REGISTER
DAC CONFIGURATION
AIN4
VALUE REGISTER
LDAC CONFIGURATION
GAIN
SELECT
LOGIC
REGISTERS
POWERDOWN
LOGIC
REGISTERS
STATUS
REGISTERS
10 INT/INT
INTERRUPT MASK
REGISTERS
INTERNAL
REFERENCE
SPI/SMBus INTERFACE
6
5
4
13
12
11
9
3
VDD
GND
CS
SCL
SDA
ADD
LDAC/AIN3
VREF -IN
Figure 6. Functional Block Diagram for the ADT7516/ADT7517/ADT7519
Rev. B | Page 8 of 44
02883-001
LDAC/AIN3 9
A-TO-D
CONVERTER
ANALOG
MUX
LIMIT
COMPARATOR
DIGITAL MUX
EXTERNAL
TEMPERATURE
VALUE REGISTER
D+/AIN1 7
D–/AIN2 8
ADT7516/ADT7517/ADT7519
ADDRESS POINTER
REGISTER
DIGITAL MUX
ON-CHIP
TEMPERATURE
SENSOR
ADT7516/ADT7517/ADT7519
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter
VDD to GND
Analog Input Voltage to GND
Digital Input Voltage to GND
Digital Output Voltage to GND
Reference Input Voltage to GND
Operating Temperature Range
Storage Temperature Range
Junction Temperature
Power Dissipation1
Thermal Impedance2
θJA Junction-to-Ambient
θJC Junction-to-Case
IR Reflow Soldering
Peak Temperature
Time at Peak Temperature
Ramp-Up Rate
Ramp-Down Rate
Time 25°C to Peak Temperature
IR Reflow Soldering (Pb-Free Package)
Peak Temperature
Time at Peak Temperature
Ramp-Up Rate
Ramp-Down Rate
Time 25°C to Peak Temperature
1
2
Rating
–0.3 V to +7 V
–0.3 V to VDD + 0.3 V
–0.3 V to VDD + 0.3 V
–0.3 V to VDD + 0.3 V
–0.3 V to VDD + 0.3 V
–40°C to +120°C
–65°C to +150°C
150°C
(TJ max – TA)/θJA
105.44°C/W
38.8°C/W
220°C (0°C/5°C)
10 sec to 20 sec
3°C/sec maximum
–6°C/sec maximum
6 min maximum
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Table 4. I2C Address Selection
ADD Pin
Low
Float
High
ESD CAUTION
260°C (+0°C)
20 sec to 40 sec
3°C/sec maximum
–6°C/sec maximum
8 min maximum
Values relate to the package being used on a 4-layer board.
Junction-to-case resistance is applicable to components featuring a
preferential flow direction, for example, components mounted on a heat
sink. Junction-to-ambient resistance is more useful for air cooled PCBmounted components.
Rev. B | Page 9 of 44
I2C Address
1001 000
1001 010
1001 011
ADT7516/ADT7517/ADT7519
PIN CONFIGURATION AND FUNCTIONAL DESCRIPTIONS
VOUT-B 1
VOUT-A 2
VREF -IN 3
CS 4
16 VOUT-C
ADT7516/
ADT7517/
ADT7519
15 VOUT-D
14 AIN4
13 SCL/SCLK
TOP VIEW
12 SDA/DIN
(Not to Scale)
VDD 6
11 DOUT/ADD
D+/AIN1 7
10 INT/INT
D–/AIN2 8
9
LDAC/AIN3
02883-006
GND 5
Figure 7. Pin Configuration (QSOP Package)
Table 5. Pin Function Descriptions
Pin No.
1
2
3
4
Mnemonic
VOUT-B
VOUT-A
VREF-IN
CS
5
6
7
GND
VDD
D+/AIN1
8
D–/AIN2
9
LDAC/AIN3
10
INT/INT
11
DOUT/ADD
12
SDA/DIN
13
SCL/SCLK
14
15
16
AIN4
VOUT-D
VOUT-C
Description
Buffered Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation.
Buffered Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation.
Reference Input Pin for All Four DACs. This input is buffered and has an input range from 1 V to VDD.
SPI Active Low Control Input. This is the frame synchronization signal for the input data. When CS goes low, it enables
the input register, and data is transferred in on the rising edges and out on the falling edges of the subsequent serial
clocks. It is recommended that this pin be tied high to VDD when operating the serial interface in I2C mode.
Ground Reference Point. Ground reference point for all circuitry on the part. Analog and digital ground.
Positive Supply Voltage, 2.7 V to 5.5 V. The supply should be decoupled to ground.
D+: Positive Connection to External Temperature Sensor.
AIN1: Analog Input. Single-ended analog input channel. Input range is 0 V to 2.28 V or 0 V to VDD.
D–: Negative Connection to External Temperature Sensor.
AIN2: Analog Input. Single-ended analog input channel. Input range is 0 V to 2.28 V or 0 V to VDD.
LDAC: Active Low Control Input. Transfers the contents of the input registers to their respective DAC registers. A
falling edge on this pin forces any or all DAC registers to be updated if the input registers have new data. A minimum
pulse width of 20 ns must be applied to the LDAC pin to ensure proper loading of a DAC register. This allows
simultaneous update of all DAC outputs. Bit C3 of the Control Configuration 3 register enables the LDAC pin. Default is
with the LDAC pin controlling the loading of the DAC registers.
AIN3: Analog Input. Single-ended analog input channel. Input range is 0 V to 2.28 V or 0 V to VDD.
Over Limit Interrupt. The output polarity of this pin can be set to give an active low or active high interrupt when
temperature, VDD, or AIN limits are exceeded. The default is active low. Open-drain output, needs a pull-up resistor.
DOUT: SPI Serial Data Output. Logic output. Data is clocked out of any register at this pin. Data is clocked out on the
falling edge of SCLK. Open-drain output, needs a pull-up resistor.
ADD: I2C Serial Bus Address Selection Pin. Logic input. A low on this pin gives the Address 1001 000; leaving it floating
gives the Address 1001 010; and setting it high gives the address 1001 011. The I2C address set up by the ADD pin is
not latched by the device until after this address has been sent twice. On the eighth SCL cycle of the second valid
communication, the serial bus address is latched in. Any subsequent change on this pin has no effect on the I2C serial
bus address.
SDA: I2C Serial Data Input/Output. I2C serial data to be loaded into the registers of the part and read from these
registers is provided on this pin. Open-drain configuration, needs a pull-up resistor.
DIN: SPI Serial Data Input. Serial data to be loaded into the part’s registers is provided on this pin. Data is clocked into
a register on the rising edge of SCLK. Open-drain configuration, needs a pull-up resistor.
Serial Clock Input. This is the clock input for the serial port. The serial clock is used to clock data out of any register of
the ADT7516/ADT7517/ADT7519, and also to clock data into any register that can be written to. Open-drain
configuration, needs a pull-up resistor.
Analog Input. Single-ended analog input channel. Input range is 0 V to 2.28 V or 0 V to VDD.
Buffered Analog Output Voltage from DAC D. The output amplifier has rail-to-rail operation.
Buffered Analog Output Voltage from DAC C. The output amplifier has rail-to-rail operation.
Rev. B | Page 10 of 44
ADT7516/ADT7517/ADT7519
TYPICAL PERFORMANCE CHARACTERISTICS
0.10
0.20
0.08
0.15
0.06
DNL ERROR (LSB)
INL ERROR (LSB)
0.10
0.05
0
–0.05
0.04
0.02
0
–0.02
–0.04
–0.10
–0.20
50
100
150
200
–0.08
–0.10
250
0
0.2
0.2
0.1
250
–0.2
400
600
800
–0.1
–0.2
02883-010
200
0
–0.3
1000
02883-013
0
–0.4
0
200
DAC CODE
400
600
800
1000
DAC CODE
Figure 9. ADT7517 Typical DAC INL Plot
Figure 12. ADT7517 Typical DAC DNL Plot
1.0
2.0
0.8
1.5
0.6
1.0
0.4
DNL ERROR (LSB)
2.5
0.5
0
–0.5
–1.0
0.2
0
–0.2
–0.4
–2.0
0
500
1000
1500
2000
2500
3000
02883-014
–0.6
–1.5
02883-011
INL ERROR (LSB)
200
Figure 11. ADT7519 Typical DAC DNL Plot
0.4
–2.5
150
Figure 8. ADT7519 Typical DAC INL Plot
0.3
0
100
DAC CODE
0.6
–0.6
50
DAC CODE
DNL ERROR (LSB)
INL ERROR (LSB)
0
02883-012
02883-009
–0.06
–0.15
–0.8
–1.0
3500 4000
0
500
1000
1500
2000
2500
3000
3500 4000
DAC CODE
DAC CODE
Figure 10. ADT7516 Typical DAC INL Plot
Figure 13. ADT7516 Typical DAC DNL Plot
Rev. B | Page 11 of 44
ADT7516/ADT7517/ADT7519
0.30
10
0.25
INL WCP
OFFSET ERROR
5
0
0.15
ERROR (LSB)
ERROR (LSB)
0.20
0.10
0.05
DNL WCP
VREF = 2.25V
–5
–10
0
02883-015
–0.10
1.0
1.5
2.0
2.5
3.0
3.5
GAIN ERROR
–15
INL WCN
4.0
4.5
02883-018
DNL WCN
–0.05
–20
2.7
5.0
3.3
3.6
4.5
4.0
5.0
5.5
VDD (V)
VREF (V)
Figure 14. ADT7519 DAC INL and DNL Error vs. VREF
Figure 17. DAC Offset Error and Gain Error vs. VDD
0.14
2.505
INL WCP
0.12
2.500
0.10
0.06
0.04
DNL WCP
0.02
0
SOURCE CURRENT
2.490
2.485
SINK CURRENT
2.480
2.475
–0.02
VDD = 5V
VREF = 5V
DAC OUTPUT
LOADED TO MIDSCALE
DNL WCN
02883-016
2.470
–0.04
–0.06
–40
–10
20
50
80
2.465
110
0
1
2
Figure 15. ADT7519 DAC INL Error and DNL Error vs. Temperature
4
5
6
Figure 18. DAC VOUT Source and Sink Current Capability
1.98
0
DAC OUTPUT UNLOADED
–0.2
1.96
OFFSET ERROR
–0.4
1.94
ICC (mA)
–0.6
–0.8
–1.0
1.92
DAC OUTPUT LOADED
1.90
–1.2
–1.4
–1.6
–20
0
20
40
60
80
100
1.86
120
02883-020
1.88
GAIN ERROR
02883-017
ERROR (LSB)
3
CURRENT (mA)
TEMPERATURE (°C)
–1.8
–40
02883-019
DAC OUTPUT (V)
ERROR (LSB)
2.495
INL WCN
0.08
0
500
1000
1500
2000
2500
3000
DAC CODE
TEMPERATURE (°C)
Figure 19. Supply Current vs. DAC Code
Figure 16. DAC Offset Error and Gain Error vs. Temperature
Rev. B | Page 12 of 44
3500
4000
ADT7516/ADT7517/ADT7519
1.8
2.00
ADC OFF
DAC OUTPUTS AT 0V
1.6
1.4
DAC OUTPUT (V)
1.90
1.85
1.2
1.0
0.8
0.6
0.4
02883-021
1.80
02883-024
ICC (mA)
1.95
0.2
0
1.75
2.7 2.9 3.1 3.3 3.5 3.7 3.9 4.1 4.3 4.5 4.7 4.9 5.1 5.3 5.5
VCC (V)
0
2
4
6
8
10
TIME (µs)
Figure 20. Supply Current vs. Supply Voltage @ 25°C
Figure 23. Exiting Power-Down to Midscale
0.4700
7
0.4695
6
0.4690
0.4685
DAC OUTPUT (V)
ICC (mA)
5
4
3
0.4680
0.4675
0.4670
0.4665
2
02883-022
0.4655
0.4650
2.7 2.9 3.1 3.3 3.5 3.7 3.9 4.1 4.3 4.5 4.7 4.9 5.1 5.3 5.5
VCC (V)
4
6
8
10
Figure 24. ADT7516 DAC Major Code Transition Glitch Energy;
011…11 to 100...00
0.4730
4.0
0.4725
3.5
0.4720
DAC OUTPUT (V)
3.0
DAC OUTPUT (V)
2
TIME (µs)
Figure 21. Power-Down Current vs. Supply Voltage @ 25°C
2.5
2.0
1.5
1.0
0.4715
0.4710
0.4705
0.4700
0.4695
02883-023
0.5
0
0
0
2
4
6
8
02883-026
0
02883-025
0.4660
1
0.4690
0.4685
10
0
2
4
6
8
10
TIME (µs)
TIME (µs)
Figure 25. ADT7516 DAC Major Code Transition Glitch Energy;
100…00 to 011…11
Figure 22. DAC Half-Scale Settling (1/4 to 3/4 Scale Code Change)
Rev. B | Page 13 of 44
ADT7516/ADT7517/ADT7519
0
0
VDD = 5V
TA = 25°C
±100mV RIPPLE ON VCC
VREF = 2.25V
VDD = 3.3V
TEMPERATURE = 25°C
–10
–20
AC PSRR (dB)
–6
–30
–8
–40
–10
–50
–12
1
2
3
4
–60
5
02883-030
–4
02883-027
1
10
FREQUENCY (kHz)
VREF (V)
Figure 26. DAC Full-Scale Error vs. VREF
Figure 29. PSRR vs. Supply Ripple Frequency
2.329
1.5
VDD = 5V
VREF = 5V
DAC OUTPUT LOADED
TO MIDSCALE
EXTERNAL TEMPERATURE @ 5V
INTERNAL TEMPERATURE @ 3.3V
1.0
TEMPERATURE ERROR (°C)
2.328
DAC OUTPUT (V)
2.327
2.326
2.325
2.324
02883-028
2.323
2.322
0
1
2
3
4
0.5
0
–0.5
EXTERNAL TEMPERATURE @ 3.3V
INTERNAL TEMPERATURE @ 5V
–1.0
–30
5
0
TIME (µs)
Figure 27. DAC-to-DAC Crosstalk
120
3
VDD = 3.3V
0.8
2
0.6
OFFSET ERROR
1
ERROR (LSB)
0.4
0.2
0
–0.2
0
–1
GAIN ERROR
–0.4
–2
–0.6
–0.8
0
200
400
600
ADC CODE
800
–4
–40
1000
02883-032
–3
02883-029
INL ERROR (LSB)
40
85
TEMPERATURE (°C)
Figure 30. Internal Temperature Error @ 3.3 V and 5 V
1.0
–1.0
100
02883-031
FULL-SCALE ERROR (mV)
–2
–20
0
20
40
60
TEMPERATURE (°C)
80
100
120
Figure 31. ADC Offset Error and Gain Error vs. Temperature
Figure 28. ADC INL with VREF = VDD (3.3 V)
Rev. B | Page 14 of 44
ADT7516/ADT7517/ADT7519
10
3
OFFSET ERROR
TEMPERATURE ERROR (°C)
2
ERROR (LSB)
VDD = 3.3V
COMMON-MODE
VOLTAGE = 100mV
8
1
0
–1
6
4
2
0
–2
–2
3.1
3.5
3.9
4.3
4.7
5.1
–6
5.5
02883-036
–3
2.7
–4
02883-033
GAIN ERROR
1
100
200
VDD (V)
Figure 32. ADC Offset Error and Gain Error vs. VDD
15
TEMPERATURE ERROR (°C)
VDD = 3.3V
DIFFERENTIAL-MODE
VOLTAGE = 100mV
D+ TO GND
0
D+ TO VCC
–10
–15
0
10
20
30
40
50
60
70
80
90
40
30
20
10
0
02883-034
–20
50
–10
100
02883-037
TEMPERATURE ERROR (°C)
5
–25
1
100
200
300
400
NOISE FREQUENCY (MHz)
PCB LEAKAGE RESISTANCE (MΩ)
Figure 33. External Temperature Error vs. PCB Leakage Resistance
0.6
600
VDD = 3.3V
VDD = 3.3V
0.4
TEMPERATURE ERROR (°C)
–10
–20
–30
–40
0.2
0
–0.2
±250mV
–0.4
02883-035
–50
0
5
10
15
20
25
30
35
40
45
–0.6
50
CAPACITANCE (nF)
Figure 34. External Temperature Error vs. Capacitance Between D+ and D–
02883-038
TEMPERATURE ERROR (°C)
500
Figure 36. External Temperature Error vs. DifferentialMode Noise Frequency
0
–60
600
70
60
–5
500
Figure 35. External Temperature Error vs. Common-Mode Noise Frequency
VDD = 3.3V
TEMPERATURE = 25°C
10
300
400
NOISE FREQUENCY (Hz)
1
100
200
300
400
NOISE FREQUENCY (Hz)
500
600
Figure 37. Internal Temperature Error vs. Power Supply Noise Frequency
Rev. B | Page 15 of 44
ADT7516/ADT7517/ADT7519
0
140
EXTERNAL TEMPERATURE
120
ATTENUATION (dB)
100
INTERNAL TEMPERATURE
80
60
–10
–15
40
0
0
10
20
30
TIME (s)
02883-040
–20
TEMPERATURE OF
ENVIRONMENT
CHANGED HERE
20
02883-039
TEMPERATURE (°C)
–5
40
50
Figure 38. Temperature Sensor Response to Thermal Shock
–25
1
60
10
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
Figure 39. DAC Multiplying Bandwidth (Small Signal Frequency Response)
Rev. B | Page 16 of 44
ADT7516/ADT7517/ADT7519
TERMINOLOGY
Relative Accuracy
Relative accuracy or integral nonlinearity (INL) is a measure of
the maximum deviation, in LSBs, from a straight line passing
through the endpoints of the transfer function. Typical INL vs.
code plots are shown in Figure 8, Figure 9, and Figure 10.
Differential Nonlinearity (DNL)
Differential nonlinearity is the difference between the measured
change and the ideal 1 LSB change between any two adjacent
codes. A specified differential nonlinearity of ±0.9 LSB maximum
ensures monotonicity. Typical DAC DNL vs. code plots can be
seen in Figure 11, Figure 12, and Figure 13.
Total Unadjusted Error (TUE)
Total unadjusted error is a comprehensive specification that
includes the sum of the relative accuracy error, gain error, and
offset error under a specified set of conditions.
Offset Error
Offset error is a measure of the offset error of the DAC and the
output amplifier (see Figure 40 and Figure 41). It can be
negative or positive, and it is expressed in mV.
Offset Error Match
Offset error match is the difference in offset error between any
two channels.
Gain Error
Gain error is a measure of the span error of the DAC. It is the
deviation in slope of the actual DAC transfer characteristic from
the ideal expressed as a percentage of the full-scale range.
Gain Error Match
Gain error match is the difference in gain error between any
two channels.
Offset Error Drift
Offset error drift is a measure of the change in offset error
with changes in temperature. It is expressed in ppm of
full-scale range/°C.
Gain Error Drift
Gain error drift is a measure of the change in gain error
with changes in temperature. It is expressed in ppm of
full-scale range/°C.
Long-Term Temperature Drift
Long-term temperature drift is a measure of the change in
temperature error with the passage of time. It is expressed in °C.
The concept of long-term stability has been used for many years
to describe the amount an IC parameter shifts during its
lifetime. This is a concept that has typically been applied to both
voltage references and monolithic temperature sensors.
Unfortunately, integrated circuits cannot be evaluated at room
temperature (25°C) for 10 years or so to determine this shift.
Manufacturers perform accelerated lifetime testing of integrated
circuits by operating ICs at elevated temperatures (between
125°C and 150°C) over a shorter period (typically between
500 hours and 1000 hours). As a result, the lifetime of an
integrated circuit is significantly accelerated due to the increase
in rates of reaction within the semiconductor material.
DC Power Supply Rejection Ratio (PSRR)
PSRR indicates how the output of the DAC is affected by
changes in the supply voltage. PSRR is the ratio of the change in
VOUT to a change in VDD for full-scale output of the DAC. It is
measured in dB. VREF is held at 2 V and VDD is varied ±10%.
DC Crosstalk
DC crosstalk is the dc change in the output level of one DAC in
response to a change in the output of another DAC. It is
measured with a full-scale output change on one DAC while
monitoring another DAC. It is expressed in μV.
Reference Feedthrough
Reference feedthrough is the ratio of the amplitude of the signal
at the DAC output to the reference input when the DAC output
is not being updated (that is, LDAC is high). It is expressed in dB.
Channel-to-Channel Isolation
Channel-to-channel isolation is the ratio of the amplitude of the
signal at the output of one DAC to a sine wave on the reference
input of another DAC. It is measured in dB.
Major Code Transition Glitch Energy
Major code transition glitch energy is the energy of the impulse
injected into the analog output when the code in the DAC
register changes state. It is normally specified as the area of the
glitch in nV-s and is measured when the digital code is changed
by 1 LSB at the major carry transition (011 . . . 11 to 100 . . . 00
or 100 . . . 00 to 011 . . . 11).
Digital Feedthrough
Digital feedthrough is a measure of the impulse injected into
the analog output of a DAC from the digital input pins of the
device. However, it is measured when the DAC is not being
written to. It is specified in nV-s and is measured with a fullscale change on the digital input pins, that is, from all 0s to all
1s or vice versa.
Digital Crosstalk
Digital crosstalk is the glitch impulse transferred to the output
of one DAC at midscale in response to a full-scale code change
(all 0s to all 1s and vice versa) in the input register of another
DAC. It is measured in standalone mode and is expressed in nV-s.
Rev. B | Page 17 of 44
ADT7516/ADT7517/ADT7519
DAC-to-DAC Crosstalk
DAC-to-DAC crosstalk is the glitch impulse transferred to the
output of one DAC due to a digital code change and subsequent
output change of another DAC. This includes both digital and
analog crosstalk. It is measured by loading one of the DACs
with a full-scale code change (all 0s to all 1s and vice versa) with
LDAC low and monitoring the output of another DAC. The
energy of the glitch is expressed in nV-s.
Multiplying Bandwidth
The multiplying bandwidth is a measure of the finite bandwidth
of the amplifiers within the DAC. A sine wave on the reference
(with full-scale code loaded to the DAC) appears on the output.
The multiplying bandwidth is the frequency at which the output
amplitude falls to 3 dB below the input.
Total Harmonic Distortion (THD)
THD is the difference between an ideal sine wave and its
attenuated version using the DAC. The sine wave is used as
the reference for the DAC, and the THD is a measure of the
harmonics present on the DAC output, expressed in dB.
GAIN ERROR
+
OFFSET ERROR
OUTPUT
VOLTAGE
NEGATIVE
OFFSET
ERROR
DAC CODE
ACTUAL
IDEAL
LOWER
DEADBAND
CODES
AMPLIFIER
FOOTROOM
NEGATIVE
OFFSET
ERROR
02883-007
Analog Crosstalk
Analog crosstalk is the glitch impulse transferred to the output
of one DAC due to a change in the output of another DAC. It is
measured by loading one of the input registers with a full-scale
code change (all 0s to all 1s and vice versa) while keeping
LDAC high. Then pulse LDAC low and monitor the output of
the DAC whose digital code was not changed. The area of the
glitch is expressed in nV-s.
Figure 40. DAC Transfer Function with Negative Offset
GAIN ERROR
+
OFFSET ERROR
UPPER
DEADBAND
CODES
OUTPUT
VOLTAGE
DAC Output Settling Time
DAC output settling time is the time required, following a
prescribed data change, for the output of a DAC to reach and
remain within ±0.5 LSB of the final value. A typical prescribed
change is from 1/4 scale to 3/4 scale.
Rev. B | Page 18 of 44
ACTUAL
IDEAL
POSITIVE
OFFSET
ERROR
DAC CODE
FULL-SCALE
02883-008
Round Robin
The term round robin is used to describe the ADT7516/ADT7517/
ADT7519 cycling through the available measurement channels
in sequence, taking a measurement on each channel.
Figure 41. DAC Transfer Function with Positive Offset (VREF = VDD)
ADT7516/ADT7517/ADT7519
THEORY OF OPERATION
Directly after the power-up calibration routine, the ADT7516/
ADT7517/ADT7519 go into idle mode. In this mode, the
devices are not performing any measurements and are fully
powered up. All four DAC outputs are at 0 V.
To begin monitoring, write to the Control Configuration 1
register (Address 0x18) and set Bit C0 = 1. The ADT7516/
ADT7517/ADT7519 go into the power-up default measurement
mode (round robin). The devices proceed to take measurements
on the VDD channel, internal temperature sensor channel,
external temperature sensor channel (AIN1 and AIN2), AIN3,
and finally AIN4. After they finish taking measurements on the
AIN4 channel, the devices immediately loop back to start
taking measurements on the VDD channel and repeat the same
cycle as before. This loop continues until the monitoring is
stopped by resetting Bit C0 of the Control Configuration 1
register to 0.
It is also possible to continue monitoring as well as switching to
single-channel mode by writing to the Control Configuration 2
register (Address 0x19) and setting Bit C4 = 1. Further explanation of the single-channel and round robin measurement modes
is given in later sections. All measurement channels have
averaging enabled on them at power-up. Averaging forces the
devices to take an average of 16 readings before giving a final
measured result. To disable averaging and consequently
decrease the conversion time by a factor of 16, set Bit C5 = 1 in
the Control Configuration 2 register.
There are four single-ended analog input channels on the
ADT7516/ADT7517/ADT7519, AIN1 to AIN4. AIN1 and
AIN2 are multiplexed with the external temperature sensor
terminals (D+ and D−). Bit C1 and Bit C2 of the Control
Configuration 1 register (Address 0x18) are used to select
between AIN1/AIN2 and the external temperature sensor.
The input range on the analog input channels is dependent on
whether the ADC reference used is the internal VREF or VDD. To
meet linearity specifications, it is recommended that the maximum
VDD value is 5 V. Bit C4 of the Control Configuration 3 register
be used to select between the internal reference and VDD as the
ADC reference of the analog inputs.
Controlling the DAC outputs can be done by writing to the MSB
and LSB registers of the DAC (Address 0x10 to Address 0x17).
The power-up default setting is to have a low going pulse on the
LDAC pin (Pin 9) controlling the updating of the DAC outputs
from the DAC registers. Alternatively, one can configure the
updating of the DAC outputs to be controlled by means other
than the LDAC pin by setting Bit C3 = 1 of the Control
Configuration 3 register (Address 0x1A). The DAC configuration register (Address 0x1B) and the LDAC configuration
register (Address 0x1C) can now be used to control the DAC
updating. These two registers also control the output range of
the DACs and select between the internal or external reference.
DAC A and DAC B outputs can be configured to give a voltage
output proportional to the temperature of the internal and
external temperature sensors, respectively.
The dual serial interface defaults to the I2C protocol on powerup. To select and lock in the SPI protocol, follow the selection
process as described in the Serial Interface Selection section.
The I2C protocol cannot be locked in, though the SPI protocol
is automatically locked in on selection. The interface can be
switched back to be I2C on selection when the device is powered
off and on. When using I2C, the CS pin should be tied to either
VDD or GND.
There are a number of different operating modes on the
ADT7516/ADT7517/ADT7519 devices and all of them can be
controlled by the configuration registers. These features consist
of enabling and disabling interrupts, polarity of the INT/INT
pin, enabling and disabling the averaging on the measurement
channels SMBus timeout, and software reset.
POWER-UP CALIBRATION
It is recommended that no communication to the part be
initiated until approximately 5 ms after VDD has settled to
within 10% of its final value. It is generally accepted that most
systems take a maximum of 50 ms to power up. Power-up time
is directly related to the amount of decoupling on the voltage
supply line.
During the 5 ms after VDD has settled, the part is performing a
calibration routine. Any communication to the device during
calibration interrupts this routine, and can cause erroneous
temperature measurements. If it is not possible to have VDD at its
nominal value by the time 50 ms has elapsed or if communication
to the device has started prior to VDD settling, it is recommended
that a measurement be taken on the VDD channel before a
temperature measurement is taken. The VDD measurement is
used to calibrate out any temperature measurement error due to
different supply voltage values.
CONVERSION SPEED
The internal oscillator circuit used by the ADC has the capability
to output two different clock frequencies. This means that the
ADC is capable of running at two different speeds when doing a
conversion on a measurement channel. Thus, the time taken to
perform a conversion on a channel can be reduced by setting
Bit C0 of the Control Configuration 3 register (Address 0x1A).
This increases the ADC clock speed from 1.4 kHz to 22 kHz. At
the higher clock speed, the analog filters on the D+ and D–
input pins (external temperature sensors) are switched off. This
is why the power-up default setting is to have the ADC working
at the slow speed. The typical times for fast and slow ADC
speeds are given in the Specifications section.
Rev. B | Page 19 of 44
ADT7516/ADT7517/ADT7519
Digital-to-Analog Converters
The ADT7516/ADT7517/ADT7519 have four resistor string
DACs fabricated on a CMOS process with resolutions of 12, 10,
and 8 bits, respectively. They contain four output buffer amplifiers
and are written to via I2C serial interface or SPI serial interface.
See the Serial Interface section for more information.
N = DAC resolution.
Resistor String
The resistor string section is shown in Figure 43. It is simply a
string of resistors, each of approximately 603 Ω. The digital
code loaded to the DAC register determines at which node on
the string the voltage is tapped off to be fed into the output
amplifier. The voltage is tapped off by closing one of the
switches connecting the string to the amplifier. Because it is a
string of resistors, it is guaranteed monotonic.
The ADT7516/ADT7517/ADT7519 operate from a single
supply of 2.7 V to 5.5 V, and the output buffer amplifiers
provide rail-to-rail output swing with a slew rate of 0.7 V/μs. All
four DACs share a common reference input, VREF-IN. The
reference input is buffered to draw virtually no current from the
reference source because it offers the source a high impedance
input. The devices have a power-down mode to completely turn
off all DACs with a high impedance output.
Each DAC output is not updated until it receives the LDAC
command. Therefore, though the DAC registers would have
been written to with a new value, this value is not represented
by a voltage output until the DACs receive the LDAC command.
Reading back from any DAC register prior to issuing an LDAC
command results in the digital value that corresponds to the
DAC output voltage. Thus, the digital value written to the DAC
register cannot be read back until after the LDAC command has
been initiated. This LDAC command can be given by either
pulling the LDAC pin low (falling edge loads DACs), setting up
Bit D4 and Bit D5 of the DAC configuration register
(Address 0x1B), or using the LDAC register (Address 0x1C).
When using the LDAC pin to control the DAC register loading,
the low going pulse width should be 20 ns minimum. The
LDAC pin has to go high and low again before the DAC
registers can be reloaded.
VREF -IN
REFERENCE
BUFFER
INT VREF
INPUT
REGISTER
DAC
REGISTER
GAIN MODE
(GAIN = 1 OR 2)
VOUT-A
RESISTOR
STRING
OUTPUT BUFFER
AMPLIFIER
Figure 42. Single DAC Channel Architecture
R
R
TO OUTPUT
AMPLIFIER
R
R
R
Figure 43. Resistor String
Digital-to-Analog Section
VREF -IN
where:
D = decimal equivalent of the binary code that is loaded to the
DAC register
Rev. B | Page 20 of 44
2.28V
INTERNAL VREF
STRING
DAC A
STRING
DAC B
STRING
DAC C
STRING
DAC D
02883-043
The architecture of one DAC channel consists of a resistor string
DAC followed by an output buffer amplifier. The voltage at the
VREF-IN pin or the on-chip reference of 2.28 V provides the
reference voltage for the corresponding DAC. Figure 42 shows a
block diagram of the DAC architecture. Because the input
coding to the DAC is straight binary, the ideal output voltage is
given by
VREF × D
VOUT =
2N
Figure 44. DAC Reference Buffer Circuit
02883-041
FUNCTION DESCRIPTION—VOLTAGE OUTPUT
0 to 255 for ADT7519 (8 bits)
0 to 1023 for ADT7517 (10 bits)
0 to 4095 for ADT7516 (12 bits)
02883-042
The ADT7516/ADT7517/ADT7519 power up with averaging
on. This means every channel is measured 16 times and internally averaged to reduce noise. The conversion time can also be
sped up by turning off the averaging. This is done by setting
Bit C5 of the Control Configuration 2 register (Address 0x19) to 1.
ADT7516/ADT7517/ADT7519
DAC Reference Inputs
corresponding to 1 LSB change. The default output resolution
for the ADT7516 and ADT7517 is 8 bits. To increase this to
10 bits, set C1 = 1 in the Control Configuration 3 register. The
default output range is 0 V to VREF and this can be increased to
0 V to 2 VREF. Increasing the output voltage span to 2 VREF can
be done by setting D0 = 1 for DAC A (internal temperature
sensor) and D1 = 1 for DAC B (external temperature sensor) in
the DAC configuration register (Address 0x1B).
There is an input reference pin for the DACs. This reference
input is buffered (see Figure 44).
The advantage of the buffered input is the high impedance it
presents to the voltage source driving it. The user can have an
external reference voltage as low as 1 V and as high as VDD. The
restriction of 1 V is due to the footroom of the reference buffer.
The LDAC configuration register controls the option to select
between internal and external voltage references. The default
selection is external reference.
The output voltage is capable of tracking a maximum temperature range of −128°C to +127°C, but the default setting is
−40°C to +127°C. If the output voltage range is 0 V to VREF-IN
(VREF-IN = 2.25 V), then this corresponds to 0 V representing
−40°C, and 1.48 V representing +127°C. This, of course, gives
an upper deadband between 1.48 V and VREF.
Output Amplifier
The output buffer amplifier can generate output voltages to
within 1 mV of either rail. Its actual range depends on the value
of VREF, gain, and offset error.
The internal and external analog temperature offset registers
can be used to vary this upper deadband and, consequently, the
temperature that 0 V corresponds to. Table 6 and Table 7 give
examples of how this is done using a DAC output voltage span
of VREF and 2 VREF, respectively. Simply write in the temperature
value, in twos complement format, at which 0 V is to start. For
example, if using the DAC A output and 0 V to start at −40°C,
program 0xD8 into the internal analog temperature offset
register (Address 0x21). This is an 8-bit register and has a
temperature offset resolution of only 1°C for all device models.
Use Equation 1 to Equation 4 to determine the value to
program into the offset registers.
If a gain of 1 is selected (Bit 0 to Bit 3 of the DAC configuration
register = 0), the output range is 0.001 V to VREF.
If a gain of 2 is selected (Bit 0 to Bit 3 of the DAC configuration
register = 1), the output range is 0.001 V to 2 VREF. Because
of clamping, however, the maximum output is limited to
VDD − 0.001 V.
The output amplifier can drive a load of 4.7 kΩ to GND or VDD,
in parallel with 200 pF to GND or VDD (see Figure 5). The
source and sink capabilities of the output amplifier can be seen
in the plot of Figure 18.
The slew rate is 0.7 V/μs with a half-scale settling time to
±0.5 LSB (at 8 bits) of 6 μs.
Table 6. Thermal Voltage Output (0 V to VREF)
O/P Voltage (V)
0
0.5
1
1.12
1.47
1.5
2
2.25
Thermal Voltage Output
The ADT7516/ADT7517/ADT7519 can output voltages that are
proportional to temperature. DAC A output can be configured
to represent the temperature of the internal sensor and the DAC B
output can be configured to represent the external temperature
sensor. Bit C5 and Bit C6 of the Control Configuration 3 register
select the temperature proportional output voltage. Each time a
temperature measurement is taken, the DAC output is updated.
The output resolution for the ADT7519 is 8 bits with 1°C change
corresponding to 1 LSB change. The output resolution for the
ADT7516 and ADT7517 is capable of 10 bits with 0.25°C change
1
Default °C
−40
+17
+73
+87
+127
UDB 1
UDB1
UDB1
Max °C
−128
−71
−15
−1
+39
+42
+99
+127
Upper deadband has been reached. DAC output is not capable of increasing.
See Figure 41.
VDD
I
N×I
IBIAS
OPTIONAL CAPACITOR, UP TO
3nF MAX. CAN BE ADDED TO
IMPROVE HIGH FREQUENCY
NOISE REJECTION IN NOISY
ENVIRONMENTS
VOUT+
D+
TO ADC
C1
D–
LOW-PASS
FILTER
fC = 65kHz
BIAS
DIODE
Figure 45. Signal Conditioning for External Diode Temperature Sensor
Rev. B | Page 21 of 44
VOUT–
02883-044
REMOTE
SENSING
TRANSISTOR
(2N3906)
Sample °C
0
+56
+113
+127
UDB1
UDB1
UDB1
UDB1
ADT7516/ADT7517/ADT7519
VDD
I
N×I
IBIAS
VOUT+
TO ADC
BIAS
DIODE
VOUT–
02883-045
INTERNAL
SENSE
TRANSISTOR
Figure 46. Top Level Structure of Internal Temperature Sensor
For example,
Table 7. Thermal Voltage Output (0 V to 2 VREF)
O/P Voltage (V)
0
0.25
0.5
0.75
1
1.12
1.47
1.5
2
2.25
2.5
2.75
3
3.25
3.5
3.75
4
4.25
4.5
Default °C
–40
–26
+12
+3
+17
+23
+43
+45
+73
+88
+102
+116
UDB1
UDB1
UDB1
UDB1
UDB1
UDB1
UDB1
Max °C
–128
–114
–100
–85
–71
–65
–45
–43
–15
0
+14
+28
+42
+56
+70
+85
+99
+113
+127
Sample °C
0
+14
+28
+43
+57
+63
+83
+85
+113
+127
UDB1
UDB1
UDB1
UDB1
UDB1
UDB1
UDB1
UDB1
UDB1
Offset Register Code (d) = 10d = 0x0A
The following equation is used to work out the various
temperatures for the corresponding 8-bit DAC output:
8-Bit Temp = (DAC O/P)/1 LSB + (0 V Temp)
(3)
For example, if the output is 1.5 V, VREF-IN = 2.25 V, 8-bit DAC
has an LSB size = 2.25 V/256 = 8.79 × 10–3, and 0 V temp is at
−128°C, then the resultant temperature is
1.5/(8.79 × 10−3) + (−128) = +43°C
The following equation is used to work out the various
temperatures for the corresponding 10-bit DAC output:
10-Bit Temp = [(DAC O/P)/1 LSB] × 0.25 + (0 V Temp)
(4)
For example, if the output is 0.4991 V, VREF-IN = 2.25 V, 10-bit
DAC has an LSB size = 2.25 V/1024 = 2.197 × 10–3, and 0 V
temperature is at −40°C, then the resulting temperature is
[0.4991/(2.197 × 10–3)] × 0.25 + (–40) = +16.75°C
Figure 47 shows a graph of the DAC output vs. temperature for
a VREF-IN = 2.25 V.
2.25
Upper deadband has been reached. DAC output is not capable of increasing.
See Figure 41.
2.10
1.95
1.65
(1)
where D7 of Offset Register Code is set to 1 for negative
temperatures.
For example,
1.50
1.35
0V = –40°C
1.20
1.05
0.90
0.75
0.60
Offset Register Code (d) = −40 + 128 = 88d = 0x58
0V = 0°C
0.45
Since a negative temperature has been inserted into the
equation, DB7 (MSB) of the offset register code is set to 1.
Therefore, 0x58 becomes 0xD8.
0.30
0.15
0
–128 –110 –90 –70 –50 –30 –10 10
30
50
70
90 110 127
TEMPERATURE (°C)
0x58 + DB7(1) = 0xD8
Figure 47. DAC Output vs. Temperature VREF-IN = 2.25 V
For positive temperatures,
Offset Register Code (d) = 0 V Temp
DAC OUTPUT (V)
Offset Register Code (d) = (0 V Temp) + 128
0V = –128°C
1.80
For negative temperatures,
02883-046
1
(2)
Rev. B | Page 22 of 44
ADT7516/ADT7517/ADT7519
FUNCTIONAL DESCRIPTION—ANALOG INPUTS
Single-Ended Inputs
The ADT7516/ADT7517/ADT7519 offer four single-ended
analog input channels. The analog input range is from 0 V to
2.28 V, or 0 V to VDD. To maintain the linearity specification, it
is recommended that the maximum VDD value be set at 5 V.
Selection between the two input ranges is done by Bit C4 of the
Control Configuration 3 register (Address 0x1A). Setting this
bit to 0 sets up the analog input ADC reference to be sourced
from the internal voltage reference of 2.28 V. Setting the bit to 1
sets up the ADC reference to be sourced from VDD.
The ADC resolution is 10 bits and is mostly suitable for dc
input signals. Bits[C1:C2] of the Control Configuration 1
register (Address 0x18) are used to set up Pin 7 and Pin 8 as
AIN1 and AIN2. Figure 48 shows the overall view of the
4-channel analog input path.
AIN4
111...111
111...110
TO ADC
VALUE
REGISTER
10-BIT
ADC
111...000
011...111
1LSB = INT VREF /1024
1LSB = VDD/1024
000...010
000...001
000...000
Figure 48. Quad Analog Input Path
ANALOG INPUT
The analog input channels use a successive approximation ADC
based on a capacitor DAC. Figure 49 and Figure 50 show simplified schematics of the ADC. Figure 49 shows the ADC during
acquisition phase. SW2 is closed and SW1 is in Position A.
The comparator is held in a balanced condition and the
sampling capacitor acquires the signal on AIN.
INT VREF
AIN
SW1
AIN voltage = 512 × 2.226 × 10−3 = 1.14 V
CONTROL
LOGIC
COMPARATOR
Analog Input ESD Protection
Figure 52 shows the input structure on any of the analog input
pins that provide ESD protection. The diode provides the main
ESD protection for the analog inputs. Care must be taken that
the analog input signal never drops below the GND rail by
more than 200 mV. If this happens, the diode becomes forwardbiased and starts conducting current into the substrate. The
4 pF capacitor is the typical pin capacitance and the resistor is a
lumped component made up of the on resistance of the
multiplexer switch.
Figure 49. ADC Acquisition Phase
INT VREF
SW1
VDD
REF
SAMPLING
CAPACITOR
CAP DAC
B
SW2
CONVERSION
PHASE
CONTROL
LOGIC
REF/2
COMPARATOR
02883-049
A
AIN
Convert value read back from AIN value register into decimal.
For example, if internal reference is used, VREF = 2.28 V.
AIN value = 512d
1 LSB size = 2.28 V/1024 = 2.226 × 10−3
ACQUISITION
PHASE
REF/2
1 LSB = reference (V)/1024
where d = decimal.
CAP DAC
SW2
To work out the voltage on any analog input channel, the
following method can be used:
AIN voltage = AIN value (d) × LSB size
REF
SAMPLING
CAPACITOR
B
Figure 51. Single-Ended Transfer Function
VDD
02883-048
A
+VREF – 1LSB
0V 1/2LSB
Converter Operation
02883-050
AIN3
The output coding of the ADT7516/ADT7517/ADT7519 analog
inputs is straight binary. The designed code transitions occur
midway between successive integer LSB values (that is, 1/2 LSB,
3/2 LSB). The LSB is VDD/1024 or internal VREF/1024, internal
VREF = 2.28 V. The ideal transfer characteristic is shown in
Figure 51.
02883-047
AIN2
ADC TRANSFER FUNCTION
ADC CODE
M
U
L
T
I
P
L
E
X
E
R
AIN1
the comparator to become unbalanced. The control logic and
the DAC are used to add and subtract fixed amounts of charge
from the sampling capacitor to bring the comparator back into
a balanced condition. When the comparator is rebalanced, the
conversion is complete. The control logic generates the ADC
output code. Figure 51 shows the ADC transfer function for the
analog inputs.
Figure 50. ADC Conversion Phase
When the ADC eventually goes into conversion phase (see
Figure 50), SW2 opens and SW1 moves to Position B, causing
Rev. B | Page 23 of 44
ADT7516/ADT7517/ADT7519
100Ω
AIN
02883-051
4pF
Figure 52. Equivalent Analog Input ESD Circuit
AIN Interrupts
The measured results from the AIN inputs are compared with
the AIN VHIGH (greater than comparison) and VLOW (less than or
equal to comparison) limits. An interrupt occurs if the AIN
inputs exceed or equal the limit registers. These voltage limits
are stored in on-chip registers. Note that the limit registers are
8 bits long and the AIN conversion result is 10 bits long. If the
voltage limits are not masked out, then any out-of-limit comparisons generate flags that are stored in the Interrupt Status 1
register (Address = 0x00) and one or more out-of-limit results
cause the INT/INT output to pull either high or low depending
on the output polarity setting. It is good design practice to mask
out interrupts for channels that are of no concern to the
application. Figure 53 shows the interrupt structure for the
ADT7516/ ADT7517/ADT7519. It gives a block diagram
representation of how the various measurement channels affect
the INT/INT pin.
S/W RESET
INTERNAL
TEMP
INTERRUPT
STATUS
REGISTER
(TEMP AND
AIN1 TO AIN4)
STATUS BITS
EXTERNAL
TEMP
VDD
INTERRUPT
MASK
REGISTERS
INTERRUPT
STATUS
REGISTER 2
(VDD)
AIN1 TO AIN4
STATUS BIT
READ RESET
INT/INT
(LATCHED OUTPUT)
DIODE
FAULT
CONTROL
CONFIGURATION
REGISTER 1
INT/INT
ENABLE BIT
02883-052
WATCHDOG
LIMIT
COMPARISONS
Figure 53. ADT7516/ADT7517/ADT7519 Interrupt Structure
Rev. B | Page 24 of 44
ADT7516/ADT7517/ADT7519
FUNCTIONAL DESCRIPTION—MEASUREMENT
Temperature Sensor
The ADT7516/ADT7517/ADT7519 contain an ADC with
special input signal conditioning to enable operation with
external and on-chip diode temperature sensors. When the
ADT7516/ADT7517/ADT7519 operate in single-channel mode,
the ADC continually processes the measurement taken on one
channel only. This channel is preselected by Bits[C0:C2] in the
Control Configuration 2 register (Address 0x19). When in
round robin mode, the analog input multiplexer sequentially
selects the VDD input channel, the on-chip temperature sensor
to measure its internal temperature, either the external temperature sensor or AIN1 and AIN2, AIN3, and then AIN4. These
signals are digitized by the ADC and the results are stored in
the various value registers.
The measured results from the temperature sensors are compared with the internal and external THIGH and TLOW limits.
These temperature limits are stored in on-chip registers. If the
temperature limits are not masked, any out-of-limit comparisons
generate flags that are stored in the Interrupt Status 1 register.
One or more out-of-limit results cause the INT/INT output to
pull either high or low depending on the output polarity setting.
Theoretically, the temperature measuring circuit can measure
temperatures from −128°C to +127°C with a resolution of
0.25°C. However, temperatures outside TA are outside the
guaranteed operating temperature range of the device.
Temperature measurement from −128°C to +127°C is possible
using an external sensor.
Temperature measurement is initiated by three methods. The
first method is applicable when the part is in single-channel
measurement mode. The temperature is measured 16 times and
internally averaged to reduce noise. In single-channel mode, the
part is continuously monitoring the selected channel, that is, as
soon as one measurement is taken another one is started on the
same channel. The total time to measure a temperature channel
with the ADC operating at slow speed is typically 11.4 ms
(712 μs × 16) for the internal temperature sensor and 24.22 ms
(1.51 ms × 16) for the external temperature sensor. The new
temperature value is stored in two 8-bit registers and is ready
for reading by the I2C or SPI interface. The user has the option
of disabling the averaging by setting Bit 5 in the Control
Configuration 2 register (Address 0x19). The ADT7516/
ADT7517/ADT7519 default on power-up is with averaging
enabled.
Temperature measurement is also initiated after every read or
write to the part when the part is in either single-channel
measurement mode or round robin measurement mode.
Once serial communication has started, any conversion in
progress stops and the ADC resets. Conversion restarts
immediately after the serial communication has finished. The
temperature measurement proceeds normally as described above.
VDD Monitoring
The ADT7516/ADT7517/ADT7519 also have the ability to
monitor their own power supply. The part measures the voltage
on its VDD pin to a resolution of 10 bits. The resulting value is
stored in two 8-bit registers; the two LSBs are stored in register
Address 0x03 and the eight MSBs are stored in register
Address 0x06. This allows the option of doing just a 1-byte read
if 10-bit resolution is not important. The measured result is
compared with the VHIGH and VLOW limits. If the VDD interrupt is
not masked, any out-of-limit comparison generates a flag in the
Interrupt Status 2 register and one or more out-of-limit results
cause the INT/INT output to pull either high or low, depending
on the output polarity setting.
Measuring the voltage on the VDD pin is regarded as monitoring
a channel along with the internal, external, and AIN channels.
The user can select the VDD channel for single-channel
measurement by setting Bit C4 = 1 and setting Bits[C0:C2] to all
0s in the Control Configuration 2 register.
When measuring the VDD value, the reference for the ADC is
sourced from the internal reference. Table 8 shows the data
format. As the maximum measurable VDD voltage is 7 V,
internal scaling is performed on the VDD voltage to match the
2.28 V internal reference value. Following is an example of how
the transfer function works:
VDD = 5 V
The second method is applicable when the part is in round
robin measurement mode. The part measures both the internal
and external temperature sensors as it cycles through all
possible measurement channels. The two temperature channels
are measured each time the part runs a round robin sequence.
In round robin mode, the part is continuously measuring all
channels.
Rev. B | Page 25 of 44
ADC Reference = 2.28 V
1 LSB = ADC Reference/210
= 2.28/1024
= 2.226 mV
Scale Factor = Full-Scale VCC/ADC Reference
= 7/2.28
= 3.07
Conversion Result = VDD/(Scale Factor × LSB size)
= 5/(3.07 × 2.226 mV)
= 0x2DC
ADT7516/ADT7517/ADT7519
writing to Bits[C0:C2] in the Control Configuration 2 register.
For example, to select the VDD channel for monitoring, write to
the Control Configuration 2 register and set C4 to 1 (if not done
so already), then write all 0s to Bits[C0:C2]. All subsequent
conversions are done on the VDD channel only. To change the
channel selection to the internal temperature channel, write to
the Control Configuration 2 register and set C0 = 1. When
measuring in single channel mode, conversions on the channel
selected occur directly after each other. Any communication to
the ADT7516/ADT7517/ADT7519 stops the conversions, but
they are restarted once the read or write operation is completed.
Table 8. VDD Data Format (VREF = 2.28 V)
VDD Value (V)
2.7
3
3.5
4
4.5
5
5.5
6
6.5
7
Digital Output
Binary
Hex
01 1000 1011
18B
01 1011 0111
1B7
10 0000 0000
200
10 0100 1001
249
10 1001 0010
292
10 1101 1100
2DC
11 0010 0101
325
11 0110 1110
36E
11 1011 0111
3B7
11 1111 1111
3FF
Temperature Measurement Method
On-Chip Reference
The ADT7516/ADT7517/ADT7519 have an on-chip 1.2 V band
gap reference that is gained up by a switched capacitor amplifier
to give an output of 2.28 V. The amplifier is powered up for the
duration of the device monitoring phase and is powered down
once monitoring is disabled. This saves on current consumption.
The internal reference is used as the reference for the ADC. The
ADC is used for measuring VDD, internal temperature sensor,
external temperature sensor, and AIN inputs. The internal
reference is always used when measuring VDD, and the internal
and external temperature sensors. The external reference is the
default power-up reference for the DACs.
Round Robin Measurement
On power-up, the ADT7516/ADT7517/ADT7519 go into round
robin mode, but monitoring is disabled. Setting Bit C0 of the
Control Configuration 1 register to 1 enables conversions. It
sequences through all the available channels, taking a
measurement from each in the following order: VDD, internal
temperature sensor, external temperature sensor (AIN1 and
AIN2), AIN3, and AIN4. Pin 7 and Pin 8 can be configured to
be either external temperature sensor pins or standalone analog
input pins. Once conversion is completed on the AIN4 channel,
the device loops around for another measurement cycle. This
method of taking a measurement on all the channels in one
cycle is called round robin. Setting Bit C4 of Control
Configuration 2 (Address 0x19) disables the round robin mode
and in turn sets up the single-channel mode. In single-channel
mode, only one channel (for example, the internal temperature
sensor) is measured in each conversion cycle.
The time taken to monitor all channels is normally not of
interest, because the most recently measured value can be read
at any time. For applications where the round robin time is
important, typical times at 25°C are given in the Specifications
section.
Single Channel Measurement
Setting C4 of the Control Configuration 2 register enables the
single channel mode and allows the ADT7516/ADT7517/
ADT7519 to focus on one channel only. A channel is selected by
Internal Temperature Measurement
The ADT7516/ADT7517/ADT7519 contain an on-chip band
gap temperature sensor whose output is digitized by the on-chip
ADC. The temperature data is stored in the internal temperature
value register. Because both positive and negative temperatures
can be measured, the temperature data is stored in twos complement format, as shown in Table 9. The thermal characteristics
of the measurement sensor can change and, therefore, an offset
is added to the measured value to enable the transfer function
to match the thermal characteristics. This offset is added before
the temperature data is stored. The offset value used is stored in
the internal temperature offset register.
External Temperature Measurement
The ADT7516/ADT7517/ADT7519 can measure the temperature
of one external diode sensor or diode-connected transistor.
The forward voltage of a diode or diode connected transistor,
operated at a constant current, exhibits a negative temperature
coefficient of about −2 mV/°C. Unfortunately, because the
absolute value of VBE varies from device to device, and
individual calibration is required to null this out, the technique
is unsuitable for mass production.
The technique used in the ADT7516/ADT7517/ADT7519 is to
measure the change in VBE when the device is operated at two
different currents. This is given by
ΔVBE = kT/q × ln(N)
where:
k is Boltzmann’s constant.
q is the charge on the carrier.
T is the absolute temperature in kelvins.
N is the ratio of the two currents.
Figure 45 shows the input signal conditioning used to measure
the output of an external temperature sensor. This figure shows
the external sensor as a substrate transistor, provided for
temperature monitoring on some microprocessors, but it can
equally well be a discrete transistor.
If a discrete transistor is used, the collector is not grounded, and
should be linked to the base. If a PNP transistor is used, the
base is connected to the D− input and the emitter to the D+
Rev. B | Page 26 of 44
ADT7516/ADT7517/ADT7519
input. If an NPN transistor is used, the emitter is connected to
the D− input and the base to the D+ input.
•
A 2N3906 is recommended as the external transistor.
To prevent ground noise from interfering with the
measurement, the more negative terminal of the sensor is not
referenced to ground, but is biased above ground by an internal
diode at the D− input. As the sensor is operating in a noisy
environment, C1 is provided as a noise filter. See the Layout
Considerations section for more information on C1.
To measure ΔVBE, the sensor is switched between operating
currents of I and N × I. The resulting waveform is passed
through a low-pass filter to remove noise, then to a chopper
stabilized amplifier that performs the functions of amplification
and rectification of the waveform to produce a dc voltage
proportional to ΔVBE. This voltage is measured by the ADC to
give a temperature output in 10-bit twos complement format.
To further reduce the effects of noise, digital filtering is
performed by averaging the results of 16 measurement cycles.
Thermocouple effects should not be a major problem
because 1°C corresponds to about 240 μV, and
thermocouple voltages are about 3 μV/°C of temperature
difference. Unless there are two thermocouples with a big
temperature differential between them, thermocouple
voltages should be much less than 200 mV.
•
Place 0.1 μF bypass and 2200 pF input filter capacitors
close to the ADT7516/ADT7517/ADT7519.
•
If the distance to the remote sensor is more than 8 inches,
the use of twisted-pair cable is recommended. This works
up to about 6 feet to 12 feet.
•
For long distances (up to 100 feet), use shielded twistedpair cable, such as Belden® #8451 microphone cable. Connect
the twisted pair to D+ and D− and the shield to GND, close
to the ADT7516/ADT7517/ADT7519. Leave the remote
end of the shield unconnected to avoid ground loops.
Layout Considerations
Digital boards can be electrically noisy environments and care
must be taken to protect the analog inputs from noise, particularly when measuring the very small voltages from a remote
diode sensor. The following precautions should be taken:
•
Place the ADT7516/ADT7517/ADT7519 as close as
possible to the remote sensing diode. Provided that the
worst noise sources such as clock generators, data/address
buses, and CRTs are avoided, this distance can be 4 inches
to 8 inches.
•
Route the D+ and D− tracks close together, in parallel,
with grounded guard tracks on each side. Provide a ground
plane under the tracks, if possible.
•
Use wide tracks to minimize inductance and reduce noise
pickup. A 10 mil track minimum width and spacing is
recommended.
10MIL
GND
10MIL
D+
10MIL
Because the measurement technique uses switched current
sources, excessive cable and/or filter capacitance can affect the
measurement. When using long cables, the filter capacitor can
be reduced or removed.
Cable resistance can also introduce errors. Series resistance of
1 Ω introduces about 0.5°C error.
Temperature Value Format
One LSB of the ADC corresponds to 0.25°C. The ADC can
theoretically measure a temperature span of 255°C. The internal
temperature sensor is guaranteed to a low value limit of −40°C.
It is possible to measure the full temperature span using the
external temperature sensor. The temperature data format is
shown in Table 9.
The result of the internal or external temperature measurements
is stored in the temperature value registers, and is compared
with limits programmed into the internal or external high and
low registers.
10MIL
D–
10MIL
10MIL
02883-053
10MIL
GND
Try to minimize the number of copper/solder joints
because they can cause thermocouple effects. Where
copper/solder joints are used, make sure that they are in
both the D+ and D− path and are at the same temperature.
Figure 54. Arrangement of Signal Tracks
Rev. B | Page 27 of 44
ADT7516/ADT7517/ADT7519
conversion results of measurements taken on the temperature,
VDD, and AIN channels. For example, the eight MSBs of the VDD
measurement are stored in Register Address 0x06 and the two
LSBs are stored in Register Address 0x03. These types of
registers are linked so that when the LSB register is read first,
the MSB registers associated with that LSB register are locked to
prevent any updates. To unlock these MSB registers, the user only
has to read any one of them; this has the effect of unlocking all
previously locked MSB registers. Therefore, for the preceding
example, if Register 0x03 is read first, MSB Register 0x06 and
Register 0x07 would be locked to prevent any updates to them.
If Register 0x06 is read, this register and Register 0x07 would be
subsequently unlocked.
Temperature
–40°C
–25°C
–10°C
–0.25°C
0°C
+0.25°C
+10°C
+25°C
+50°C
+75°C
+100°C
+105°C
+125°C
Digital Output
11 0110 0000
11 1001 1100
11 1101 1000
11 1111 1111
00 0000 0000
00 0000 0001
00 0010 1000
00 0110 0100
00 1100 1000
01 0010 1100
01 1001 0000
01 1010 0100
01 1111 0100
FIRST READ
COMMAND
LSB
REGISTER
OUTPUT
DATA
02883-054
Table 9. Temperature Data Format
(Internal and External Temperature)
LOCK ASSOCIATED
MSB REGISTERS
Temperature conversion formula:
Figure 55. Phase 1 of 10-Bit Read
Positive Temperature = ADC Code/4
Negative Temperature = (ADC Code – 512)/4
where DB9 is removed from the ADC Code in the Negative
Temperature equation.
SECOND READ
COMMAND
MSB
REGISTER
OUTPUT
DATA
The measured results from the internal temperature sensor,
external temperature sensor, VDD pin, and AIN inputs are
compared with the THIGH/VHIGH (greater than comparison) and
TLOW/VLOW (less than or equal to comparison) limits. An
interrupt occurs if the measurement exceeds or equals the limit
registers. These limits are stored in on-chip registers. Note that
the limit registers are 8 bits long and the conversion results are
10 bits long. If the limits are not masked, any out-of-limit
comparisons generate flags that are stored in the Interrupt
Status 1 register (Address 0x00) and Interrupt Status 2 register
(Address 0x01). One or more out-of-limit results cause the
INT/INT output to pull either high or low depending on the
output polarity setting. It is good design practice to mask out
interrupts for channels that are of no concern to the application.
Figure 53 shows the interrupt structure for the ADT7516/
ADT7517/ADT7519. It gives a block diagram representation of
how the various measurement channels affect the INT/INT pin.
ADT7516/ADT7517/ADT7519 REGISTERS
The ADT7516/ADT7517/ADT7519 contain registers that are
used to store the results of external and internal temperature
measurements, VDD value measurements, analog input measurements, high and low temperature limits, supply voltage and
analog input limits, set output DAC voltage levels, configure
multipurpose pins, and generally to control the device. A
description of these registers follows.
The register map is divided into registers of 8 bits. Each register
has its own individual address, but some consist of data that is
linked with other registers. These registers hold the 10-bit
02883-055
Interrupts
UNLOCK ASSOCIATED
MSB REGISTERS
Figure 56. Phase 2 of 10-Bit Read
If an MSB register is read first, its corresponding LSB register is
not locked, leaving the user with the option of just reading back
8 bits (MSB) of a 10-bit conversion result. Reading an MSB
register first does not lock other MSB registers, and likewise,
reading an LSB register first does not lock other LSB registers.
Table 10. ADT7516/ADT7517/ADT7519 Registers
R/W
Address
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C to
0x0F
0x10
0x11
0x12
0x13
Rev. B | Page 28 of 44
Name
Interrupt Status 1
Interrupt Status 2
Reserved
Internal Temp and VDD LSBs
External Temp and AIN1 to AIN4 LSBs
Reserved
VDD MSBs
Internal Temp MSBs
External Temp MSBs/AIN1 MSBs
AIN2 MSBs
AIN3 MSBs
AIN4 MSBs
Reserved
DAC A LSBs (ADT7516/ADT7517 Only)
DAC A MSBs
DAC B LSBs (ADT7516/ADT7517 Only)
DAC B MSBs
Power-On
Default
0x00
0x00
0x00
0x00
0x00
No default value
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
ADT7516/ADT7517/ADT7519
R/W
Address
0x14
0x15
0x16
0x17
0x18
0x19
0x1A
0x1B
0x1C
0x1D
0x1E
0x1F
0x20
0x21
0x22
0x23
0x24
0x25
0x26
0x27
0x28
0x29 to
0x2A
0x2B
0x2C
0x2D
0x2E
0x2F
0x30
0x31 to
0x4C
0x4D
0x4E
0x4F
0x50 to
0x7E
0x7F
0x80 to
0xFF
Power-On
Default
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0xD8
0xD8
0xC7
0x62
0x64
0xC9
0xFF
0x00
Table 11.
AIN2 VHIGH Limit
AIN2 VLOW Limit
AIN3 VHIGH Limit
AIN3 VLOW Limit
AIN4 VHIGH Limit
AIN4 VLOW Limit
Reserved
0xFF
0x 00
0xFF
0x00
0xFF
0x00
D7
Device ID
Manufacturer’s ID
Silicon Revision
Reserved
0x03/0x0B/0x07
0x41
Check register
for current
silicon revision
0x00
SPI Lock Status
Reserved
0x00
0x00
Name
DAC C LSBs (ADT7516/ADT7517 only)
DAC C MSBs
DAC D LSBs (ADT7516/ADT7517 only)
DAC D MSBs
Control Configuration 1
Control Configuration 2
Control Configuration 3
DAC Configuration
LDAC Configuration
Interrupt Mask 1
Interrupt Mask 2
Internal Temp Offset
External Temp Offset
Internal Analog Temp Offset
External Analog Temp Offset
VDD VHIGH Limit
VDD VLOW Limit
Internal THIGH Limit
Internal TLOW Limit
External THIGH/AIN1 VHIGH Limits
External TLOW/AIN1 VLOW Limits
Reserved
1
D5
01
Default settings at power-up.
D4
01
D3
01
D2
01
D1
01
D2
D3
D4
D5
D6
This 8-bit read-only register reflects the status of the VDD
interrupt that can cause the INT/INT pin to go active. This
register is reset by a read operation, provided that any out-oflimit event has been corrected. It is also reset by a software reset.
D7
N/A
1
D0
01
D6
N/A
D5
N/A
D4
01
D3
N/A
D2
N/A
D1
N/A
D0
N/A
Default settings at power-up.
Table 12.
Bit
D4
This 8-bit read-only register reflects the status of some of the
interrupts that can cause the INT/INT pin to go active. This
register is reset by a read operation, provided that any out-oflimit event has been corrected. It is also reset by a software reset.
D6
01
D1
Function
1 when the internal temperature value exceeds THIGH limit.
Any internal temperature reading greater than the set limit
causes an out-of-limit event.
1 when internal temperature value exceeds TLOW limit. Any
internal temperature reading less than or equal to the set
limit causes an out-of-limit event.
This status bit is linked to the configuration of Pin 7 and
Pin 8. If configured for external temperature sensor, this bit
is 1 when the external temperature value exceeds THIGH
limit. The default value for this limit register is –1°C, so any
external temperature reading greater than the set limit
causes an out-of-limit event. If configured for AIN1 and
AIN2, this bit is 1 when AIN1 input voltage exceeds VHIGH or
VLOW limits.
1 when external temperature value exceeds TLOW limit. The
default value for this limit register is 0°C, so any external
temperature reading less than or equal to the set limit
causes an out-of-limit event.
1 indicates a fault (open or short) for the external
temperature sensor.
1 when AIN2 voltage is greater than its corresponding VHIGH
limit. 1 when AIN2 voltage is less than or equal to its
corresponding VLOW limit.
1 when AIN3 voltage is greater than its corresponding VHIGH
limit. 1 when AIN3 voltage is less than or equal to its
corresponding VLOW limit.
1 when AIN4 voltage is greater than its corresponding VHIGH
limit. 1 when AIN4 voltage is less than or equal to its
corresponding VLOW limit.
Interrupt Status 2 Register (Read-Only) [Address = 0x01]
Interrupt Status 1 Register (Read-Only) [Address 0x00]
D7
01
Bit
D0
Function
1 when VDD value is greater than its corresponding VHIGH
limit. 1 when VDD is less than or equal to its corresponding
VLOW limit.
Internal Temperature Value/VDD Value Register LSBs
(Read-Only) [Address = 0x03]
This 8-bit read-only register stores the two LSBs of the 10-bit
temperature reading from the internal temperature sensor and
the two LSBs of the 10-bit supply voltage reading.
D7
N/A
N/A
1
D6
N/A
N/A
D5
N/A
N/A
Default settings at power-up.
Rev. B | Page 29 of 44
D4
N/A
N/A
D3
V1
01
D2
LSB
01
D1
T1
01
D0
LSB
01
ADT7516/ADT7517/ADT7519
temperature value is stored in twos complement format. The
eight MSBs of the 10-bit value are stored in this register.
Table 13.
Bit
D0
D1
D2
D3
Function
LSB of internal temperature value.
Bit 1 of internal temperature value.
LSB of VDD value.
Bit 1 of VDD value.
D7
T/A9
01
1
External Temperature Value and Analog Input 1 to
Analog Input 4 Register LSBs (Read-Only) [Address = 0x04]
This is an 8-bit, read-only register. Bits[D2:D7] store the two
LSBs of the analog inputs AIN2 to AIN4. Bits[D0:D1] store the
two LSBs of either the external temperature value or AIN1 input
value. The type of input for D0 and D1 is selected by Bits[C1:C2]
of the Control Configuration Register 1.
D7
A4
01
1
D6
A4LSB
01
D5
A3
01
D4
A3LSB
01
D3
A2
01
D2
A2LSB
01
D1
T/A
01
D0
T/ALSB
01
D6
T/A8
01
D5
T/A7
01
D4
T/A6
01
D3
T/A5
01
D2
T/A4
01
D1
T/A3
01
D0
T/A2
01
Default settings at power-up.
AIN2 Register MSBs (Read) [Address = 0x09]
This 8-bit read register contains the eight MSBs of the AIN2
analog input voltage word. The value in this register is combined
with Bits[D2:D3] of the external temperature value and Analog
Input 1 to Analog Input 4 register LSBs, Address 0x04, to give the
full 10-bit conversion result of the analog value on the AIN2 pin.
D7
MSB
01
1
D6
A8
01
D5
A7
01
D4
A6
01
D3
A5
01
D2
A4
01
D1
A3
01
D0
A2
01
Default settings at power-up.
Default settings at power-up.
AIN3 Register MSBs (Read) [Address = 0x0A]
Table 14.
Bit
D0
D1
D2
D3
D4
D5
D6
D7
This 8-bit read register contains the eight MSBs of the AIN3
analog input voltage word. The value in this register is combined
with Bits[D4:D5] of the external temperature value and Analog
Input 1 to Analog Input 4 register LSBs, Address 0x04, to give the
full 10-bit conversion result of the analog value on the AIN3 pin.
Function
LSB of external temperature value or AIN1 value.
Bit 1 of external temperature value or AIN1 value.
LSB of AIN2 value.
Bit 1 of AIN2 value.
LSB of AIN3 value.
Bit 1 of AIN3 value.
LSB of AIN4 value.
Bit 1 of AIN4 value.
D7
MSB
01
1
D6
A8
01
D5
A7
01
D4
A6
01
D3
A5
01
D2
A4
01
D1
A3
01
D0
A2
01
Default settings at power-up.
VDD Value Register MSBs (Read-Only) [Address = 0x06]
AIN4 Register MSBs (Read) [Address = 0x0B]
This 8-bit read-only register stores the supply voltage value. The
eight MSBs of the 10-bit value are stored in this register.
This 8-bit read register contains the eight MSBs of the AIN4
analog input voltage word. The value in this register is combined
with Bits[D6:D7] of the external temperature value and Analog
Input 1 to Analog Input 4 register LSBs, Address 0x04, to give the
full 10-bit conversion result of the analog value on the AIN4 pin.
D7
V9
x1
1
D6
V8
x1
D5
V7
x1
D4
V6
x1
D3
V5
x1
D2
V4
x1
D1
V3
x1
D0
V2
x1
Loaded with VDD value after power-up.
Internal Temperature Value Register MSBs (Read-Only)
[Address = 0x07]
This 8-bit read-only register stores the internal temperature value
from the internal temperature sensor in twos complement format.
The eight MSBs of the 10-bit value are stored in this register.
D7
T9
01
1
D6
T8
01
D5
T7
01
D4
T6
01
D3
T5
01
D2
T4
01
D1
T3
01
D0
T2
01
Default settings at power-up.
D7
MSB
01
1
D6
A8
01
D5
A7
01
D4
A6
01
D3
A5
01
D2
A4
01
D1
A3
01
D0
A2
01
Default settings at power-up.
DAC A Register LSBs (Read/Write) [Address = 0x10]
This 8-bit read/write register contains the 4/2 LSBs of the
ADT7516/ADT7517 DAC A word, respectively. The value in
this register is combined with the value in the DAC A register
MSBs and converted to an analog voltage on the VOUT-A pin.
On power-up, the voltage output on the VOUT-A pin is 0 V.
ADT7516
External Temperature Value or Analog Input AIN1
Register MSBs (Read-Only) [Address = 0x08]
This 8-bit read-only register stores, if selected, the external
temperature value or the analog input AIN1 value. Selection is
done in the Control Configuration 1 register. The external
D7
B3
01
1
D6
B2
01
D5
B1
01
D4
LSB
01
Default settings at power-up.
Rev. B | Page 30 of 44
D3
N/A
N/A
D2
N/A
N/A
D1
N/A
N/A
D0
N/A
N/A
ADT7516/ADT7517/ADT7519
ADT7517
D7
B1
01
1
ADT7516
D6
LSB
01
D5
N/A
N/A
D4
N/A
N/A
D3
N/A
N/A
D2
N/A
N/A
D1
N/A
N/A
D0
N/A
N/A
Default settings at power-up.
D7
B3
01
1
D6
B2
01
ADT7517
This 8-bit read/write register contains the eight MSBs of the
DAC A word. The value in this register is combined with the
value in the DAC A register LSBs and converted to an analog
voltage on the VOUT-A pin. On power-up, the voltage output on
the VOUT-A pin is 0 V.
D7
B1
01
D7
MSB
01
1
D6
B8
01
D5
B7
01
D4
B6
01
D3
B5
01
D2
B4
01
D1
B3
01
D0
B2
01
Default settings at power-up.
DAC B Register LSBs (Read/Write) [Address = 0x12]
1
D4
LSB
01
D3
N/A
N/A
D2
N/A
N/A
1
D6
LSB
01
1
D6
B8
01
D2
N/A
N/A
D1
N/A
N/A
D0
N/A
N/A
D5
B7
01
D4
B6
01
D3
B5
01
D2
B4
01
D1
B3
01
D0
B2
01
DAC D Register LSBs (Read/Write) [Address = 0x16]
D1
N/A
N/A
D0
N/A
N/A
D7
B3
01
ADT7516
D5
N/A
N/A
D4
N/A
N/A
D3
N/A
N/A
D2
N/A
N/A
1
D6
B2
01
ADT7517
D7
B1
01
D5
B7
01
D4
B6
01
D3
B5
01
D2
B4
01
D1
B3
01
D0
B2
01
Default settings at power-up.
DAC C Register LSBs (Read/Write) [Address = 0x14]
This 8-bit read/write register contains the 4/2 LSBs of the
ADT7516/ADT7517 DAC C word, respectively. The value in
this register is combined with the value in the DAC C register
MSBs and converted to an analog voltage on the VOUT-C pin.
On power-up, the voltage output on the VOUT-C pin is 0 V.
1
D5
B1
01
D4
LSB
01
D3
N/A
N/A
D2
N/A
N/A
D1
N/A
N/A
D0
N/A
N/A
Default settings at power-up.
This 8-bit read/write register contains the eight MSBs of the
DAC B word. The value in this register is combine with the
value in the DAC B register LSBs and converts to an analog
voltage on the VOUT-B pin. On power-up, the voltage output on
the VOUT-B pin is 0 V.
1
D3
N/A
N/A
Default settings at power-up.
DAC B Register MSBs (Read/Write) [Address = 0x13]
D6
B8
01
D4
N/A
N/A
This 8-bit read/write register contains the 4/2 LSBs of the
ADT7516/ADT7517 DAC D word, respectively. The value in
this register is combined with the value in the DAC D register
MSBs and converted to an analog voltage on the VOUT-D pin.
On power-up, the voltage output on the VOUT-D pin is 0 V.
Default settings at power-up.
D7
MSB
01
D5
N/A
N/A
D0
N/A
N/A
ADT7517
D6
LSB
01
D0
N/A
N/A
D1
N/A
N/A
Default settings at power-up.
D7
B1
01
D1
N/A
N/A
This 8-bit read/write register contains the eight MSBs of the
DAC C word. The value in this register is combined with the
value in the DAC C register LSBs and converted to an analog
voltage on the VOUT-C pin. On power-up, the voltage output on
the VOUT-C pin is 0 V.
ADT7516
D5
B1
01
D2
N/A
N/A
DAC C Register MSBs (Read/Write) [Address = 0x15]
D7
MSB
01
D6
B2
01
D3
N/A
N/A
Default settings at power-up.
This 8-bit read/write register contains the 4/2 LSBs of the
ADT7516/ADT7517 DAC B word, respectively. The value in
this register is combined with the value in the DAC B register
MSBs and converted to an analog voltage on the VOUT-B pin. On
power-up, the voltage output on the VOUT-B pin is 0 V.
D7
B3
01
D4
LSB
01
Default settings at power-up.
DAC A Register MSBs (Read/Write) [Address = 0x11]
1
D5
B1
01
D6
LSB
01
D5
N/A
N/A
D4
N/A
N/A
D3
N/A
N/A
D2
N/A
N/A
D1
N/A
N/A
D0
N/A
N/A
Default settings at power-up.
DAC D Register MSBs (Read/Write) [Address = 0x17]
This 8-bit read/write register contains the eight MSBs of the
DAC D word. The value in this register combines with the value
in the DAC D register LSBs and converts to an analog voltage
on the VOUT-D pin. On power-up, the voltage output on the
VOUT-D pin is 0 V.
D7
MSB
01
1
D6
B8
01
D5
B7
01
Default settings at power-up.
Rev. B | Page 31 of 44
D4
B6
01
D3
B5
01
D2
B4
01
D1
B3
01
D0
B2
01
ADT7516/ADT7517/ADT7519
Control Configuration 1 Register (Read/Write)
[Address = 0x18]
Table 17.
This configuration register is an 8-bit read/write register that is
used to set up some of the operating modes of the ADT7516/
ADT7517/ADT7519.
Bit
[C0:C2]
Table 15. Control Configuration 1
D7
PD
01
1
D6
C6
01
D5
C5
01
D4
C4
01
D3
C3
01
D2
C2
01
D1
C1
01
D0
C0
01
Default settings at power-up.
Table 16.
Bit
C0
[C1:C2]
C3
C4
C5
C6
PD
Function
This bit enables/disables conversions in round robin
and single-channel mode.
ADT7516/ADT7517/ADT7519 powers up in round
robin mode but monitoring is not initiated until this bit
is set. The default = 0.
0 = stop monitoring.
1 = start monitoring.
Selects between the two different analog inputs on
Pin 7 and Pin 8. ADT7516/ADT7517/ADT7519 powers
up with AIN1 and AIN2 selected.
00 = AIN1 and AIN2 selected.
01 = undefined.
10 = external TDM selected.
11 = undefined.
Selects between digital (LDAC) and analog inputs
(AIN3) on Pin 9. When AIN3 is selected, Bit C3 of the
Control Configuration 3 register is masked and has no
effect until LDAC is selected as the input on Pin 9.
0 = LDAC selected.
1 = AIN3 selected.
Reserved. Write 0 only.
0 = enable INT/INT output.
1 = disable INT/INT output.
Configures INT/INT output polarity.
0 = active low.
1 = active high.
Power-Down Bit. Setting this bit to 1 puts the
ADT7516/ADT7517/ADT7519 into standby mode. In
this mode, both ADC and DACs are fully powered
down, but the serial interface is still operational. To
power up the part again, just write 0 to this bit.
C3
C4
C5
C6
C7
Control Configuration 3 Register (Read/Write)
[Address = 0x1A]
This configuration register is an 8-bit read/write register that is
used to set up some of the operating modes of the ADT7516/
ADT7517/ADT7519.
D7
C7
01
1
This configuration register is an 8-bit read/write register that is
used to set up some of the operating modes of the ADT7516/
ADT7517/ADT7519.
1
D6
C6
01
D5
C5
01
D4
C4
01
D3
C3
01
D2
C2
01
D1
C1
01
D6
C6
01
D5
C5
01
Default settings at power-up.
Control Configuration 2 Register (Read/Write)
[Address = 0x19]
D7
C7
01
Function
In single-channel mode, these bits select between VDD,
the internal temperature sensor, external temperature
sensor/AIN1, AIN2, AIN3, and AIN4 for conversion. The
default is VDD.
000 = VDD.
001 = internal temperature sensor.
010 = external temperature sensor/AIN1.
(Bits[C1:C2] of the Control Configuration 1 register
affect this selection).
011 = AIN2.
100 = AIN3.
101 = AIN4.
110 to 111 = reserved.
Reserved.
Selects between single-channel and round robin
conversion cycle. The default is round robin.
0 = round robin.
1 = single channel.
Default condition is to average every measurement on
all channels 16 times. This bit disables this averaging.
Channels affected are temperature, analog inputs, and
VDD.
0 = enable averaging.
1 = disable averaging.
SMBus timeout on the serial clock puts a 25 ms limit
on the pulse width of the clock, ensuring that a fault
on the master SCL does not lock up the SDA line.
0 = disable SMBus timeout.
1 = enable SMBus timeout.
Software Reset. Setting this bit to 1 causes a software
reset. All registers and DAC outputs reset to their
default settings.
D0
C0
01
Default settings at power-up.
Rev. B | Page 32 of 44
D4
C4
01
D3
C3
01
D2
C2
01
D1
C1
01
D0
C0
01
ADT7516/ADT7517/ADT7519
Table 18.
Bit
C0
C1
C2
C3
C4
C5
C6
C7
Function
Selects between fast and slow ADC conversion speeds.
0 = ADC clock at 1.4 kHz.
1 = ADC clock at 22.5 kHz. D+ and D– analog filters are
disabled.
On the ADT7516 and ADT7517, this bit selects between
8-bit and 10-bit DAC output resolution on the thermal
voltage output feature. The default is 8 bits. This bit has no
effect on the ADT7519 output because this part has only
an 8-bit DAC. For the ADT7519, write 0 to this bit.
0 = 8-bit resolution.
1 = 10-bit resolution.
Reserved. Write 0 only.
0 = LDAC pin controls updating of DAC outputs.
1 = DAC configuration register and LDAC configuration
register control updating of DAC outputs.
Selects the ADC reference to be either internal VREF or VDD
for analog inputs.
0 = internal VREF.
1 = VDD.
Setting this bit selects DAC A voltage output to be
proportional to the internal temperature measurement.
Setting this bit selects DAC B voltage output to be
proportional to the external temperature measurement.
Reserved. Write 0 only.
DAC Configuration Register (Read/Write) [Address = 0x1B]
This configuration register is an 8-bit read/write register that is
used to control the output ranges of all four DACs and also to
control the loading of the DAC registers if the LDAC pin is
disabled (Bit C3 = 1, Control Configuration 3 register).
D7
D7
01
1
D6
D6
01
D5
D5
01
D4
D4
01
D3
D3
01
D2
D2
01
D1
D1
01
D0
D0
01
Bit
[D4:D5]
[D6:D7]
LDAC Configuration Register (Write-Only)[Address = 0x1C]
This configuration register is an 8-bit write register that is used
to control the updating of the quad DAC outputs if the LDAC
pin is disabled and Bits[D4:D5] of the DAC configuration
register are both set to 1. Also selects either the internal or the
external VREF for all four DACs. Bits[D0:D3] in this register are
self-clearing, that is, reading back from this register always gives
0s for these bits.
D7
D7
01
1
D1
D2
D3
D5
D5
01
D4
D4
01
D3
D3
01
D2
D2
01
D1
D1
01
D0
D0
01
Table 20.
Bit
D0
D1
D2
D3
D4
Table 19.
Function
Selects the output range of DAC A.
0 = 0 V to VREF.
1 = 0 V to 2 VREF.
Selects the output range of DAC B.
0 = 0 V to VREF.
1 = 0 V to 2 VREF.
Selects the output range of DAC C.
0 = 0 V to VREF.
1 = 0 V to 2 VREF.
Selects the output range of DAC D.
0 = 0 V to VREF.
1 = 0 V to 2 VREF.
D6
D6
01
Default settings at power-up.
Default settings at power-up.
Bit
D0
Function
00 = MSB write to any DAC register generates LDAC
command that updates that DAC only.
01 = MSB write to DAC B or DAC D register generates
LDAC command that updates DAC A and DAC B or
DAC C and DAC D, respectively.
10 = MSB write to DAC D register generates LDAC
command that updates all four DACs.
11 = LDAC command generated from LDAC register.
Reserved. Write 0s only.
D5
[D6:D7]
Function
Writing a 1 to this bit generates the LDAC command
to update DAC A output only.
Writing a 1 to this bit generates the LDAC command
to update DAC B output only.
Writing a 1 to this bit generates the LDAC command
to update DAC C output only.
Writing a 1 to this bit generates the LDAC command
to update DAC D output only.
Selects either internal VREF or external VREF for DAC A
and DAC B.
0 = external VREF.
1 = internal VREF.
Selects either internal VREF or external VREF for DAC C
and DAC D.
0 = external VREF.
1 = internal VREF.
Reserved. Write 0s only.
Interrupt Mask 1 Register (Read/Write) [Address = 0x1D]
This mask register is an 8-bit read/write register that can be
used to mask any interrupts that can cause the INT/INT pin to
go active.
D7
D7
01
1
D6
D6
01
D5
D5
01
Default settings at power-up.
Rev. B | Page 33 of 44
D4
D4
01
D3
D3
01
D2
D2
01
D1
D1
01
D0
D0
01
ADT7516/ADT7517/ADT7519
External Temperature Offset Register (Read/Write)
[Address = 0x20]
Table 21.
Bit
D0
D1
D2
D3
D4
D5
D6
D7
Function
0 = enable internal THIGH interrupt.
1 = disable internal THIGH interrupt.
0 = enable internal TLOW interrupt.
1 = disable internal TLOW interrupt.
0 = enable external THIGH interrupt or AIN1 interrupt.
1 = disable external THIGH interrupt or AIN1 interrupt.
0 = enable external TLOW interrupt.
1 = disable external TLOW interrupt.
0 = enable external temperature fault interrupt.
1 = disable external temperature fault interrupt.
0 = enable AIN2 interrupt.
1 = disable AIN2 interrupt.
0 = enable AIN3 interrupt.
1 = disable AIN3 interrupt.
0 = enable AIN4 interrupt.
1 = disable AIN4 interrupt.
This register contains the offset value for the external temperature
channel. A twos complement number can be written to this
register and is then added to the measured result before it is
stored or compared to limits. In this way, a one-point calibration
can be done, whereby the whole transfer function of the channel
can be moved up or down. From a software point of view, this
can be a very simple method to vary the characteristics of the
measurement channel if the thermal characteristics change.
Because it is an 8-bit register, the temperature resolution is 1°C.
D7
D7
01
1
This mask register is an 8-bit read/write register that can be
used to mask any interrupts that can cause the INT/INT pin to
go active.
1
D6
D6
01
D5
D5
01
D4
D4
01
D3
D3
01
D2
D2
01
D1
D1
01
D0
D0
01
Default settings at power-up.
Table 22.
Bit
[D0:D3]
D4
Function
Reserved. Write 0s only.
0 = enable VDD interrupts.
1 = disable VDD interrupts.
Reserved. Write 0s only.
[D5:D7]
D5
D5
01
D4
D4
01
D3
D3
01
D2
D2
01
D1
D1
01
D0
D0
01
Default settings at power-up.
Internal Analog Temperature Offset Register
(Read/Write) [Address = 0x21]
Interrupt Mask 2 Register (Read/Write) [Address = 0x1E]
D7
D7
01
D6
D6
01
This register contains the offset value for the internal thermal
voltage output. A twos complement number can be written to
this register and then added to the measured result before it is
converted by DAC A. Varying the value in this register has the
effect of varying the temperature span. For example, the output
voltage can represent a temperature span of −128°C to +127°C
or even 0°C to +127°C. In essence, this register changes the
position of 0 V on the temperature scale. Temperatures other
than −128°C to +127°C produce an upper deadband on the
DAC A output. Because it is an 8-bit register, the temperature
resolution is 1°C. The default value is −40°C.
D7
D7
11
1
D6
D6
11
D5
D5
01
D4
D4
11
D3
D3
11
D2
D2
01
D1
D1
01
D0
D0
01
Default settings at power-up.
Internal Temperature Offset Register (Read/Write)
[Address = 0x1F]
External Analog Temperature Offset Register
(Read/Write) [Address = 0x22]
This register contains the offset value for the internal temperature
channel. A twos complement number can be written to this
register and then added to the measured result before it is stored
or compared to limits. In this way, a one-point calibration can
be done, whereby the whole transfer function of the channel
can be moved up or down. From a software point of view, this
can be a very simple method to vary the characteristics of the
measurement channel if the thermal characteristics change.
Because it is an 8-bit register, the temperature resolution is 1°C.
This register contains the offset value for the external thermal
voltage output. A twos complement number can be written to
this register and then added to the measured result before it is
converted by DAC B. Varying the value in this register has the
effect of varying the temperature span. For example, the output
voltage can represent a temperature span of −128°C to +127°C
or even 0°C to +127°C. In essence, this register changes the
position of 0 V on the temperature scale. Temperatures other
than −128°C to +127°C produce an upper deadband on the
DAC B output. Because it is an 8-bit register, the temperature
resolution is 1°C. The default value is −40°C.
D7
D7
01
1
D6
D6
01
D5
D5
01
Default settings at power-up.
D4
D4
01
D3
D3
01
D2
D2
01
D1
D1
01
D0
D0
01
D7
D7
11
1
D6
D6
11
D5
D5
01
Default settings at power-up.
Rev. B | Page 34 of 44
D4
D4
11
D3
D3
11
D2
D2
01
D1
D1
01
D0
D0
01
ADT7516/ADT7517/ADT7519
VDD VHIGH Limit Register (Read/Write) [Address = 0x23]
This limit register is an 8-bit read/write register that stores the
VDD upper limit, and causes an interrupt and activates the
INT/INT output (if enabled). For this to happen, the measured
VDD value has to be greater than the value in this register. The
default value is 5.46 V.
D7
D7
11
1
D6
D6
11
D5
D5
01
D4
D4
01
D3
D3
01
D2
D2
11
D1
D1
11
D0
D0
11
External THIGH/AIN1 VHIGH Limit Register (Read/Write)
[Address = 0x27]
If Pin 7 and Pin 8 are configured for the external temperature
sensor, this limit register is an 8-bit read/write register that
stores the twos complement of the external temperature upper
limit, and causes an interrupt and activates the INT/INT output
(if enabled). For this to happen, the measured external
temperature value has to be greater than the value in this
register. Because it is an 8-bit register, the temperature
resolution is 1°C. The default value is −1°C.
Default settings at power-up.
Positive Temperature = Limit Register Code (d)
VDD VLOW Limit Register (Read/Write) [Address = 0x24]
This limit register is an 8-bit read/write register that stores the
VDD lower limit, and causes an interrupt and activates the
INT/INT output (if enabled). For this to happen, the measured
VDD value has to be less than or equal to the value in this
register. The default value is 2.7 V.
D7
D7
01
1
D6
D6
11
D5
D5
11
D4
D4
01
D3
D3
01
D2
D2
01
D1
D1
11
D0
D0
01
Default settings at power-up.
Internal THIGH Limit Register (Read/Write) [Address = 0x25]
This limit register is an 8-bit read/write register that stores the twos
complement of the internal temperature upper limit, and causes
an interrupt and activates the INT/INT output (if enabled). For this
to happen, the measured internal temperature value has to be
greater than the value in this register. Because it is an 8-bit register,
the temperature resolution is 1°C. The default value is +100°C.
Positive Temperature = Limit Register Code (d)
Negative Temperature = Limit Register Code (d) − 256
D7
D7
01
1
D6
D6
11
D5
D5
11
D4
D4
01
D3
D3
01
D2
D2
11
D1
D1
01
D0
D0
01
Default settings at power-up.
Internal TLOW Limit Register (Read/Write) [Address = 0x26]
This limit register is an 8-bit read/write register that stores the
twos complement of the internal temperature lower limit, and
causes an interrupt and activates the INT/INT output (if enabled).
For this to happen, the measured internal temperature value has
to be more negative than or equal to the value in this register.
Because it is an 8-bit register, the temperature resolution is 1°C.
The default value is −55°C.
Positive Temperature = Limit Register Code (d)
Negative Temperature = Limit Register Code (d) − 256
D7
D7
11
1
D6
D6
11
D5
D5
01
D4
D4
01
D3
D3
11
D2
D2
01
D1
D1
01
D0
D0
11
Negative Temperature = Limit Register Code (d) − 256
If Pin 7 and Pin 8 are configured for AIN1 and AIN2 inputs,
this limit register is an 8-bit read/write register that stores the
AIN1 input upper limit, and causes an interrupt and activates
the INT/INT output (if enabled). For this to happen, the
measured AIN1 value has to be greater than the value in this
register. Because it is an 8-bit register, the resolution is four
times less than the resolution of the 10-bit ADC. Because the
power-up default settings for Pin 7 and Pin 8 are AIN1 and
AIN2 inputs, the default value for this limit register is full-scale
voltage.
D7
D7
11
1
D6
D6
11
D5
D5
11
D4
D4
11
D3
D3
11
D2
D2
11
D1
D1
11
D0
D0
11
Default settings at power-up.
External TLOW/AIN1 VLOW Limit Register (Read/Write)
[Address = 0x28]
If Pin 7 and Pin 8 are configured for the external temperature
sensor, this limit register is an 8-bit read/write register that
stores the twos complement of the external temperature lower
limit, and causes an interrupt and activates the INT/INT output
(if enabled). For this to happen, the measured external
temperature value has to be more negative than or equal to the
value in this register. Because it is an 8-bit register, the
temperature resolution is 1°C. The default value is 0°C.
Positive Temperature = Limit Register Code (d)
Negative Temperature = Limit Register Code (d) − 256
If Pin 7 and Pin 8 are configured for AIN1 and AIN2 inputs,
this limit register is an 8-bit read/write register that stores the
AIN1 input lower limit, and causes an interrupt and activates
the INT/INT output (if enabled). For this to happen, the
measured AIN1 value has to be less than or equal to the value in
this register. Because it is an 8-bit register, the resolution is four
times less than the resolution of the 10-bit ADC. Because the
power-up default settings for Pin 7 and Pin 8 are AIN1 and
AIN2 inputs, the default value for this limit register is 0 V.
Default settings at power-up.
Rev. B | Page 35 of 44
ADT7516/ADT7517/ADT7519
D7
D7
01
1
D6
D6
01
D5
D5
01
D4
D4
01
D3
D3
01
D2
D2
01
D1
D1
01
D0
D0
01
D7
D7
01
1
Default settings at power-up.
D6
D6
01
D5
D5
01
D4
D4
01
D3
D3
01
D2
D2
01
D1
D1
01
D0
D0
01
Default settings at power-up.
AIN2 VHIGH Limit Register (Read/Write) [Address = 0x2B]
AIN4 VHIGH Limit Register (Read/Write) [Address = 0x2F]
This limit register is an 8-bit read/write register that stores the
AIN2 input upper limit, and causes an interrupt and activates
the INT/INT output (if enabled). For this to happen, the
measured AIN2 value has to be greater than the value in this
register. Because it is an 8-bit register, the resolution is four
times less than the resolution of the 10-bit ADC. The default
value is full-scale voltage.
This limit register is an 8-bit read/write register that stores the
AIN4 input upper limit, and causes an interrupt and activates
the INT/INT output (if enabled). For this to happen, the
measured AIN4 value has to be greater than the value in this
register. Because it is an 8-bit register, the resolution is four
times less than the resolution of the 10-bit ADC. The default
value is full-scale voltage.
D7
D7
11
D7
D7
11
1
D6
D6
11
D5
D5
11
D4
D4
11
D3
D3
11
D2
D2
11
D1
D1
11
D0
D0
11
1
Default settings at power-up.
D6
D6
11
D5
D5
11
D4
D4
11
D3
D3
11
D2
D2
11
D1
D1
11
D0
D0
11
Default settings at power-up.
AIN2 VLOW Limit Register (Read/Write) [Address = 0x2C]
AIN4 VLOW Limit Register (Read/Write) [Address = 0x30]
This limit register is an 8-bit read/write register that stores the
AIN2 input lower limit, and causes an interrupt and activates
the INT/INT output (if enabled). For this to happen, the measured AIN2 value has to be less than or equal to the value in this
register. Because it is an 8-bit register, the resolution is four times
less than the resolution of the 10-bit ADC. The default value is 0 V.
This limit register is an 8-bit read/write register that stores the
AIN4 input lower limit, and causes an interrupt and activates
the INT/INT output (if enabled). For this to happen, the measured
AIN4 value has to be less than or equal to the value in this register.
Because it is an 8-bit register, the resolution is four times less
than the resolution of the 10-bit ADC. The default value is 0 V.
D7
D7
01
D7
D7
01
1
D6
D6
01
D5
D5
01
D4
D4
01
D3
D3
01
D2
D2
01
D1
D1
01
D0
D0
01
Default settings at power-up.1 Default settings at power-up.
1
D6
D6
01
D5
D5
01
D4
D4
01
D3
D3
01
D2
D2
01
D1
D1
01
D0
D0
01
Default settings at power-up.
AIN3 VHIGH Limit Register (Read/Write) [Address = 0x2D]
Device ID Register (Read-Only) [Address = 0x4D]
This limit register is an 8-bit read/write register that stores the
AIN3 input upper limit, and causes an interrupt and activates
the INT/INT output (if enabled). For this to happen, the
measured AIN3 value has to be greater than the value in this
register. Because it is an 8-bit register, the resolution is four
times less than the resolution of the 10-bit ADC. The default
value is full-scale voltage.
This 8-bit read-only register indicates the part model of the
device: ADT7516 = 0x03, ADT7517 = 0x07, and ADT7519 = 0x0B.
D7
D7
11
This register is divided into the four LSBs representing the
stepping and the four MSBs representing the version. The
stepping contains the manufacturer’s code for minor revisions
or steppings to the silicon. The version is the ADT7516/
ADT7517/ADT7519 version number.
1
D6
D6
11
D5
D5
11
D4
D4
11
D3
D3
11
D2
D2
11
D1
D1
11
D0
D0
11
Default settings at power-up.
AIN3 VLOW Limit Register (Read/Write) [Address = 0x2E]
This limit register is an 8-bit read/write register that stores the
AIN3 input lower limit, and causes an interrupt and activates
the INT/INT output (if enabled). For this to happen, the measured AIN3 value has to be less than or equal to the value in this
register. Because it is an 8-bit register, the resolution is four times
less than the resolution of the 10-bit ADC. The default value is 0 V.
Manufacturer’s ID Register (Read-Only) [Address = 0x4E]
This register contains the manufacturer’s identification number.
ID number of Analog Devices, Inc. is 0x41.
Silicon Revision Register (Read-Only) [Address = 0x4F]
SPI Lock Status Register (Read-Only) [Address = 0x7F]
Bit D0 (LSB) of this read-only register indicates whether or not
the SPI interface is locked. Writing to this register causes the
device to malfunction. The default value is 0x00.
Rev. B | Page 36 of 44
0 = I2C interface.
1 = SPI interface selected and locked.
ADT7516/ADT7517/ADT7519
As per most SPI standards, the CS line must be low during
every SPI communication to the ADT7516/ADT7517/ADT7519
and high all other times. Typical examples of how to connect the
dual interface as I2C or SPI are shown in Figure 57 and Figure 58.
The following sections describe in detail how to use the I2C and
SPI protocols associated with the ADT7516/ADT7517/ADT7519.
SERIAL INTERFACE
There are two serial interfaces that can be used on this part, I2C
and SPI. The device powers up with the serial interface in I2C
mode, but it is not locked into this mode. To stay in I2C mode, it
is recommended that the user tie the CS line to either VCC or
GND. It is not possible to lock the I2C mode, but it is possible to
select and lock the SPI mode.
To select and lock the interface into the SPI mode, a number of
pulses must be sent down the CS line (Pin 4). The following
section describes how this is done.
ADT7516/
ADT7517/
ADT7519
02883-057
LOCK AND
SELECT SPI
CS
VDD
820Ω
820Ω
820Ω
SPI FRAMING
EDGE
DIN
02883-058
SCLK
DOUT
Figure 58. Typical SPI Interface Connection.
C
SPI LOCKED ON
THIRD RISING EDGE
SPI FRAMING
EDGE
C
CS
(START LOW)
SPI LOCKED ON
THIRD RISING EDGE
SPI FRAMING
EDGE
Figure 59. Serial Interface—Selecting and Locking SPI Protocol
Rev. B | Page 37 of 44
02883-056
B
I2C ADDRESS = 1001 000
Figure 57. Typical I2C Interface Connection
To communicate to the ADT7516/ADT7517/ADT7519 using
the SPI protocol, send three pulses down the CS line as shown
in Figure 59. On the third rising edge (marked as C in Figure 59),
the part selects and locks the SPI interface. The user is now
limited to communicating to the device using the SPI protocol.
A
10kΩ
SCL
ADD
The CS line controls the selection between I2C and SPI.
Figure 59 shows the selection process necessary to lock the SPI
interface mode.
B
10kΩ
SDA
Serial Interface Selection
A
VDD
CS
Once the SPI communication protocol has been locked in, it
cannot be unlocked while the device is still powered up. Bit D0
of the SPI lock status register (Address 0x7F) is set to 1 when a
successful SPI interface lock has been accomplished. To reset
the serial interface, the user must power down the part and
power it up again. A software reset does not reset the serial
interface.
CS
(START HIGH)
VDD
ADT7516/
ADT7517/
ADT7519
ADT7516/ADT7517/ADT7519
I2C Serial Interface
2.
Data is sent over the serial bus in sequences of nine clock
pulses: eight bits of data followed by an acknowledge bit
from the receiver of data. Transitions on the data line must
occur during the low period of the clock signal and remain
stable during the high period, because a low to high
transition when the clock is high can be interpreted as a
stop signal.
3.
When all data bytes have been read or written, stop
conditions are established. In write mode, the master pulls
the data line high during the 10th clock pulse to assert a
stop condition. In read mode, the master device pulls the
data line high during the low period before the ninth clock
pulse. This is known as no acknowledge. The master then
takes the data line low during the low period before the 10th
clock pulse, and then high during the 10th clock pulse to
assert a stop condition.
2
Like all I C-compatible devices, the ADT7516/ADT7517/
ADT7519 have a 7-bit serial address. The four MSBs of this
address for the ADT7516/ADT7517/ADT7519 are set to 1001.
The three LSBs are set by Pin 11, ADD. The ADD pin can be
configured three ways to give three different address options:
low, floating, and high. Setting the ADD pin low gives a serial bus
address of 1001 000, leaving it floating gives the Address 1001 010,
and setting it high gives the Address 1001 011. The recommended
pull-up resistor value is 10 kΩ.
There is an enable/disable bit for the SMBus timeout. When this
is enabled, the SMBus times out after 25 ms of no activity. To
enable it, set Bit 6 of the Control Configuration 2 register. The
power-on default is with the SMBus timeout disabled.
The ADT7516/ADT7517/ADT7519 support SMBus packet
error checking (PEC), but its use is optional. It is triggered by
supplying the extra clocks for the PEC byte. The PEC is
calculated using CRC-8. The frame clock sequence (FCS)
conforms to CRC-8 by the polynomial
Any number of bytes of data can be transferred over the serial
bus in one operation, but it is not possible to mix read and write
in one operation because the type of operation is determined at
the beginning and cannot subsequently be changed without
starting a new operation.
C(x) = x8 + x2 + x1 + 1
Consult the SMBus specification for more information.
The I2C address set up by the ADD pin is not latched by the
device until after this address has been sent twice. On the eighth
SCL cycle of the second valid communication, the serial bus
address is latched in. This is the SCL cycle directly after the
device has seen its own I2C serial bus address. Any subsequent
changes on this pin have no effect on the I2C serial bus address.
The serial bus protocol operates as follows:
The master initiates a data transfer by establishing a start
condition, defined as a high to low transition on the serial
data line (SDA) while the serial clock line (SCL) remains
high. This indicates that an address/data stream follows.
All slave peripherals connected to the serial bus respond to
the start condition and shift in the next eight bits,
consisting of a 7-bit address (MSB first) plus a R/W bit; this
determines the direction of the data transfer, that is,
whether data is written to or read from the slave device.
Writing to the ADT7516/ADT7517/ADT7519
Depending on the register being written to, there are two different
writes for the ADT7516/ADT7517/ADT7519. It is not possible
to do a block write to this part, that is, no I2C auto-increment.
Writing to the Address Pointer Register for a
Subsequent Read
The peripheral whose address corresponds to the
transmitted address responds by pulling the data line low
during the low period before the ninth clock pulse, known
as the acknowledge bit. All other devices on the bus now
remain idle while the selected device waits for data to be
read from or written to it. If the R/W bit is 0, the master
writes to the slave device. If the R/W bit is 1, the master
reads from the slave device.
1
To read data from a particular register, the address pointer
register must contain the address of that register. If it does not,
the correct address must be written to the address pointer
register by performing a single-byte write operation, as shown
in Figure 60. The write operation consists of the serial bus
address followed by the address pointer byte. No data is written
to any of the data registers. A read operation is then performed
to read the register.
9
1
9
SCL
SDA
1
0
0
1
A2
A1
START BY
MASTER
A0
R/W
P7
P6
ACK. BY
ADT7516/ADT7517/ADT7519
FRAME 1
SERIAL BUS ADDRESS BYTE
P5
P4
P3
P2
P1
P0
ACK. BY
ADT7516/ADT7517/ADT7519
FRAME 2
ADDRESS POINTER REGISTER BYTE
2
Figure 60. I C—Writing to the Address Pointer Register to Select a Register for a Subsequent Read Operation
Rev. B | Page 38 of 44
STOP BY
MASTER
02883-059
1.
ADT7516/ADT7517/ADT7519
1
9
1
9
SCL
SDA
1
0
0
1
A2
A1
A0
START BY
MASTER
P7
R/W
P6
P5
P4
P3
ACK. BY
ADT7516/ADT7517/ADT7519
P2
P1
P0
ACK. BY
ADT7516/ADT7517/ADT7519
FRAME 1
SERIAL BUS ADDRESS BYTE
FRAME 2
ADDRESS POINTER REGISTER BYTE
1
9
SCL (CONTINUED)
SDA (CONTINUED)
D7
D6
D5
D4
D3
D2
D1
D0
02883-060
ACK. BY STOP BY
ADT7516/ADT7517/ADT7519 MASTER
FRAME 3
DATA BYTE
Figure 61. I2C—Writing to the Address Pointer Register Followed by a Single Byte of Data to the Selected Register
1
9
1
9
SCL
1
0
0
1
A2
A1
A0
R/W
D7
D6
D5
D4
D3
D2
ACK. BY
ADT7616/ADT7517/ADT7519
START BY
MASTER
FRAME 1
SERIAL BUS ADDRESS BYTE
D1
D0
NO ACK. BY
MASTER
STOP BY
MASTER
FRAME 2
SINGLE DATA BYTE FROM ADT7516/ADT7517/ADT7519
02883-061
SDA
Figure 62. I2C—Reading a Single Byte of Data from a Selected Register
Writing Data to a Register
All registers are 8-bit registers, therefore only one byte of data
can be written to each register. Writing a single byte of data to
one of these read/write registers consists of the serial bus
address, the data register address written to the address pointer
register, followed by the data byte written to the selected data
register. This is illustrated in Figure 61. To write to a different
register, another start or repeated start is required. If more than
one byte of data is sent in one communication operation, the
addressed register is repeatedly loaded until the last data byte
has been sent.
Reading Data from the ADT7516/ADT7517/ADT7519
Reading data from the ADT7516/ADT7517/ADT7519 is done
in a one-byte operation. Reading back the contents of a register
is shown in Figure 62. The register address had previously been
set up by a single-byte write operation to the address pointer
register. To read from another register, write to the address
pointer register again to set up the relevant register address.
Thus, block reads are not possible, that is, no I2C auto-increment.
to the serial clock and data lines. The CS is also used to
distinguish between any two separate serial communications
(see Figure 67 for a graphical explanation). The SCLK is used to
clock data in and out of the part. The DIN line is used to write
to the registers, and the DOUT line is used to read data back
from the registers. The recommended pull-up resistor value is
between 500 Ω and 820 Ω. Strong pull-ups are needed when
serial clock speeds that are close to the maximum limit are used
or when the SPI interface lines are experiencing large capacitive
loading. Larger resistor values can be used for pull-up resistors
when the serial clock speed is reduced.
The part operates in slave mode and requires an externally
applied serial clock to the SCLK input. The serial interface is
designed to allow the part to be interfaced to systems that
provide a serial clock that is synchronized to the serial data.
There are two types of serial operations, read and write.
Command words are used to distinguish read operations from
write operations. These command words are given in Table 23.
Address auto-increment is possible in SPI mode.
SPI Serial Interface
Table 23. SPI Command Words
The SPI serial interface of the ADT7516/ADT7517/ADT7519
consists of four wires: CS , SCLK, DIN, and DOUT. The CS is
used to select the device when more than one device is connected
Write
0x90 (1001 0000)
Rev. B | Page 39 of 44
Read
0x91 (1001 0001)
ADT7516/ADT7517/ADT7519
CS
1
8
8
1
SCLK
DIN
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
START
WRITE COMMAND
REGISTER ADDRESS
CS (CONTINUED)
1
8
SCLK (CONTINUED)
D7
D6
D5
D4
D3
D2
D1
D0
STOP
DATA BYTE
02883-062
DIN (CONTINUED)
Figure 63. SPI—Writing to the Address Pointer Register Followed by a Single Byte of Data to the Selected Register
Write Operation
Read Operation
Figure 63 shows the timing diagram for a write operation to the
ADT7516/ADT7517/ADT7519. Data is clocked into the
registers on the rising edge of SCLK. When the CS line is high,
the DIN and DOUT lines are in three-state mode. Only when
the CS goes from a high to a low does the part accept any data
on the DIN line. In SPI mode, the address pointer register is
capable of auto-incrementing to the next register in the register
map without having to load the address pointer register each
time. In Figure 63, the register address portion gives the first
register that is written to. Subsequent data bytes are written into
sequential writable registers. Thus, after each data byte has been
written into a register, the address pointer register autoincrements its value to the next available register. The address
pointer register auto-increments from 0x00 to 0x3F and loops
back to start again at 0x00 when it reaches 0x3F.
Figure 64 to Figure 66 show the timing diagrams necessary to
accomplish correct read operations. To read back from a
register, first write to the address pointer register with the
address of the register to be read from. This operation is shown
in Figure 64. Figure 65 shows the procedure for reading back a
single byte of data. The read command is first sent to the part
during the first eight clock cycles. As the read command is
being sent, irrelevant data is output onto the DOUT line.
During the following eight clock cycles, the data contained in
the register selected by the address pointer register is output
onto the DOUT line. Data is output onto the DOUT line on the
falling edge of SCLK. Figure 66 shows the procedure when
reading data from two sequential registers. Multiple data reads
are possible in the SPI interface mode as the address pointer
register is auto-incremental. The address pointer register autoincrements from 0x00 to 0x3F and loops back to start again at
0x00 when it reaches 0x3F.
Rev. B | Page 40 of 44
ADT7516/ADT7517/ADT7519
CS
1
8
8
1
SCLK
D6
D7
D5
D3
D4
D1
D2
D7
D0
D6
D5
D2
D3
D4
D1
D0
STOP
START
WRITE COMMAND
02883-063
REGISTER ADDRESS
Figure 64. SPI—Writing to the Address Pointer Register to Select a Register for a Subsequent Read Operation
CS
1
8
8
1
DIN
D7
D6
D5
D4
D3
D2
D1
D0
X
X
X
X
X
X
X
X
DOUT
X
X
X
X
X
X
X
X
D7
D6
D5
D4
D3
D2
D1
D0
STOP
START
DATA BYTE 1
READ COMMAND
02883-064
SCLK
Figure 65. SPI—Reading a Single Byte of Data From a Selected Register
CS
1
8
8
1
SCLK
DIN
D7
D6
D5
D4
D3
D2
D1
D0
X
X
X
X
X
X
X
X
DOUT
X
X
X
X
X
X
X
X
D7
D6
D5
D4
D3
D2
D1
D0
START
READ COMMAND
DATA BYTE 1
CS (CONTINUED)
1
8
DIN (CONTINUED)
DOUT (CONTINUED)
X
D7
X
X
X
X
X
X
X
D6
D5
D4
D3
D2
D1
D0
02883-065
SCLK (CONTINUED)
STOP
DATA BYTE 2
Figure 66. SPI—Reading Two Bytes of Data from Two Sequential Registers
CS
SPI
READ OPERATION
WRITE OPERATION
Figure 67. SPI—Correct Use of CS during SPI Communication
Rev. B | Page 41 of 44
02883-066
DIN
ADT7516/ADT7517/ADT7519
The INT/INT pin has an open-drain configuration that allows the
outputs of several devices to be wire-AND’ed together when the
INT/INT pin is active low. Use C6 of the Control Configuration 1
register to set the active polarity of the INT/INT output. The
power-up default is active low. The INT/INT output can be
disabled or enabled by setting C5 of the Control Configuration 1
register to 1 or 0, respectively.
The INT/INT output becomes active when either the internal
temperature value, the external temperature value, VDD value, or
any of the AIN input values exceed the values in their
corresponding THIGH/VHIGH or TLOW/VLOW registers. The
INT/INT output goes inactive again when a conversion result
has the measured value back within the trip limits and when the
status register associated with the out-of-limit event is read. The
two interrupt status registers show the event that caused the
INT/INT pin to go active.
The INT/INT output requires an external pull-up resistor. This
can be connected to a voltage different from VDD, provided the
maximum voltage rating of the INT/INT output pin is not
exceeded. The value of the pull-up resistor depends on the
application but should be large enough to avoid excessive sink
currents at the INT/INT output because they can heat the chip
and affect the temperature reading.
One or more INT/INT outputs can be connected to a common
SMBALERT line connected to the master. When the
SMBALERT line is pulled low by one of the devices, the
following procedure occurs as shown in Figure 68:
1.
SMBALERT is pulled low.
2.
Master initiates a read operation and sends the alert
response address (ARA = 0001 100). This general call
address must not be used as a specific device address.
3.
A device whose INT/INT output is low responds to the
alert response address and the master reads its device
address. As the device address is seven bits long, an LSB of
1 is added. The address of the device is now known and it
can be interrogated in the usual way.
4.
If INT/INT output of more than one device is low, the one
with the lowest device address has priority in accordance
with normal SMBus specifications.
5.
When the ADT7516/ADT7517/ADT7519 have responded
to the alert response address, they reset their INT/INT
output, provided that the condition that caused the out-oflimit event no longer exists and that the status register
associated with the out-of-limit event is read. If the
SMBALERT line remains low, the master sends the ARA
again. It continues to do this until all devices whose
SMBALERT outputs were low have responded.
MASTER
RECEIVES
SMBALERT
RESPONSE
START ALERT
ADDRESS
SMBUS ALERT RESPONSE
The INT/INT pin behaves the same way as an SMBus alert pin
when the SMBus/I2C interface is selected. It is an open-drain
output and requires a pull-up to VDD. Several INT/INT outputs
can be wire-AND’ed together, so that the common line goes low
if one or more of the INT/INT outputs goes low. The polarity of
the INT/INT pin must be set active low for a number of outputs
to be wire-AND’ed together.
NO STOP
RD ACK DEVICE ADDRESS ACK
MASTER SENDS
ARA AND READ
COMMAND
02883-067
The ADT7516/ADT7517/ADT7519 INT/INT outputs are an
interrupt line for devices that want to trade their ability to
master for an extra pin. The ADT7516/ADT7517/ADT7519 are
slave devices and use the SMBus/SPI INT/INT to signal the host
device that it wants to talk to. The SMBus/SPI INT/INT on the
ADT7516/ADT7517/ADT7519 is used as an over/under limit
indicator.
allows them to do so. SMBALERT is used in conjunction with
the SMBus general call address.
DEVICE SENDS
ITS ADDRESS
Figure 68. INT/INT Responds to SMBALERT ARA
DEVICE ACK
MASTER
RECEIVES
SMBALERT
START
The INT/INT output can operate as an SMBALERT function.
Slave devices on the SMBus cannot normally signal to the
master that they want to talk, but the SMBALERT function
Rev. B | Page 42 of 44
ALERT RESPONSE
ADDRESS
MASTER SENDS
ARA AND READ
COMMAND
DEVICE
RD ACK ADDRESS
MASTER
ACK
ACK
MASTER
NACK
PEC
NO
ACK
DEVICE SENDS DEVICE SENDS
ITS ADDRESS ITS PEC DATA
Figure 69. INT/INT Responds to SMBALERT ARA
with Packet Error Checking (PEC)
STOP
02883-068
SMBus/SPI INT/INT
ADT7516/ADT7517/ADT7519
OUTLINE DIMENSIONS
0.197
0.193
0.189
9
16
0.158
0.154
0.150
1
8
0.244
0.236
0.228
PIN 1
0.069
0.053
0.065
0.049
0.010
0.025
0.004
BSC
COPLANARITY
0.004
0.012
0.008
SEATING
PLANE
0.010
0.006
8°
0°
0.050
0.016
COMPLIANT TO JEDEC STANDARDS MO-137-AB
Figure 70. 16-Lead Shrink Small Outline Package [QSOP]
(RQ-16)
Dimensions shown in inches
ORDERING GUIDE
Model
ADT7519ARQ
ADT7519ARQ-REEL
ADT7519ARQ-REEL7
ADT7519ARQZ 1
ADT7519ARQZ-REEL1
ADT7519ARQZ-REEL71
ADT7517ARQ
ADT7517ARQ-REEL
ADT7517ARQ-REEL7
ADT7517ARQZ1
ADT7517ARQZ-REEL1
ADT7517ARQZ-REEL71
ADT7516ARQ
ADT7516ARQ-REEL
ADT7516ARQ-REEL7
ADT7516ARQZ1
ADT7516ARQZ-REEL1
ADT7516ARQZ-REEL71
EVAL-ADT7516EB
1
Temperature Range
–40°C to +120°C
–40°C to +120°C
–40°C to +120°C
–40°C to +120°C
–40°C to +120°C
–40°C to +120°C
–40°C to +120°C
–40°C to +120°C
–40°C to +120°C
–40°C to +120°C
–40°C to +120°C
–40°C to +120°C
–40°C to +120°C
–40°C to +120°C
–40°C to +120°C
–40°C to +120°C
–40°C to +120°C
–40°C to +120°C
DAC
Resolution
8 Bits
8 Bits
8 Bits
8 Bits
8 Bits
8 Bits
10 Bits
10 Bits
10 Bits
10 Bits
10 Bits
10 Bits
12 Bits
12 Bits
12 Bits
12 Bits
12 Bits
12 Bits
Package
Description
16-Lead QSOP
16-Lead QSOP
16-Lead QSOP
16-Lead QSOP
16-Lead QSOP
16-Lead QSOP
16-Lead QSOP
16-Lead QSOP
16-Lead QSOP
16-Lead QSOP
16-Lead QSOP
16-Lead QSOP
16-Lead QSOP
16-Lead QSOP
16-Lead QSOP
16-Lead QSOP
16-Lead QSOP
16-Lead QSOP
Evaluation Board
Z = Pb-free part.
Rev. B | Page 43 of 44
Package Option
RQ-16
RQ-16
RQ-16
RQ-16
RQ-16
RQ-16
RQ-16
RQ-16
RQ-16
RQ-16
RQ-16
RQ-16
RQ-16
RQ-16
RQ-16
RQ-16
RQ-16
RQ-16
Ordering
Quantity
98
2,500
1,000
98
2,500
1,000
98
2,500
1,000
98
2,500
1,000
98
2,500
1,000
98
2,500
1,000
ADT7516/ADT7517/ADT7519
NOTES
Purchase of licensed I2C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I2C Patent.
Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.
©2006 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
C02883-0-10/06(B)
Rev. B | Page 44 of 44
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