ISL28130, ISL28230, ISL28430 Features The ISL28130, ISL28230 and ISL28430 are single, dual and quad micropower, low drift operational amplifiers that are optimized for single and dual supply operation from 1.65V to 5.5V and ±0.825V to ±2.75V. Their low supply current of 20µA and wide input range enable the ISL28130, ISL28230, ISL28430 to be an excellent general purpose op amp for a range of applications. The ISL28130, ISL28230 and ISL28430 are ideal for handheld devices that operate off 2 AA or single Li-ion batteries. • Low Input Offset Voltage . . . . . . . . . . . . 40µV, Max. The ISL28130 is available in industry standard pinouts for 5 Ld SOT-23, 5 Ld SC70 and 8 Ld SOIC packages. The ISL28230 is available in industry standard pinouts for 8 Ld MSOP and 8Ld SOIC packages. The ISL28430 is available in 14 Ld TSSOP and 14 Ld SOIC packages. All devices operate over the temperature range of 0°C to +70°C. • Low Offset Drift . . . . . . . . . . . . . . . 150nV/°C, Max • Input Bias Current . . . . . . . . . . . . . . 250 pA, Max. • Quiescent Current (Per Amplifier) . . . . . . 20µA, Typ. • Single Supply Range . . . . . . . . . . .+1.65V to +5.5V • Dual Supply Range . . . . . . . . . . ±0.825V to ±2.75V • Low Noise (0.01Hz to 10Hz) . . . . . . . . 1.1µVP-P, Typ. • Rail-to-Rail Inputs and Output • Operating Temperature Range . . . . . . 0°C to +70°C Applications*(see page 11) • Bi-Directional Current Sense • Temperature Measurement • Medical Equipment • Electronic Weigh Scales • Precision/Strain Gauge Sensor • Precision Regulation • Low Ohmic Current Sense • High Gain Analog Front Ends Typical Application IB vs Temperature V+ +1.65V TO +5.5V VREF 499k 4.99k + V+ 0.1 - VSENSE OUT V499k 4.99k GND I-SENSE- BI-DIRECTIONAL CURRENT SENSE AMPLIFIER August 17, 2010 FN7623.0 1 70 INPUT BIAS CURRENT IN- (pA) I-SENSE+ 60 VS = ±2.5V 50 40 30 20 VS = ±0.825V 10 0 0 10 20 30 40 50 60 70 TEMPERATURE (°C) CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2010. All Rights Reserved All other trademarks mentioned are the property of their respective owners. ISL28130, ISL28230, ISL28430 Single, Dual, and Quad Micropower, Low Drift, RRIO Operational Amplifiers ISL28130, ISL28230, ISL28430 Ordering Information PART NUMBER (Notes 2, 3) PART MARKING PACKAGE (Pb-Free) PKG. DWG. # Coming Soon ISL28130CBZ 28130 CBZ 8 Ld SOIC M8.15E Coming Soon ISL28130CBZ-T7 (Note 1) 28130 CBZ 8 Ld SOIC (Tape & Reel) M8.15E Coming Soon ISL28130CBZ-T7A (Note 1) 28130 CBZ 8 Ld SOIC (Tape & Reel) M8.15E ISL28130CHZ-T7 (Note 1) BDPA (Bottom Brand) 5 Ld SOT-23 (Tape & Reel) P5.064A ISL28130CHZ-T7A (Note 1) BDPA (Bottom Brand) 5 Ld SOT-23 (Tape & Reel) P5.064A ISL28130CEZ-T7 (Note 1) BLA (Bottom Brand) 5 Ld SC70 (Tape & Reel) P5.049 ISL28130CEZ-T7A (Note 1) BLA (Bottom Brand) 5 Ld SC70 (Tape & Reel) P5.049 ISL28230CUZ 8230Z 8 Ld MSOP M8.118A ISL28230CUZ-T7 (Note 1) 8230Z 8 Ld MSOP (Tape & Reel) M8.118A ISL28230CUZ-T7A (Note 1) 8230Z 8 Ld MSOP (Tape & Reel) M8.118A ISL28230CBZ 28230 CBZ 8 Ld SOIC M8.15E ISL28230CBZ-T7 (Note 1) 28230 CBZ 8 Ld SOIC (Tape & Reel) M8.15E ISL28230CBZ-T7A (Note 1) 28230 CBZ 8 Ld SOIC (Tape & Reel) M8.15E ISL28430CBZ 28430 CBZ 14 Ld SOIC MDP0027 ISL28430CBZ-T7 (Note 1) 28430 CBZ 14 Ld SOIC (Tape & Reel) MDP0027 ISL28430CBZ-T7A (Note 1) 28430 CBZ 14 Ld SOIC (Tape & Reel) MDP0027 ISL28430CVZ 28430 CVZ 14 Ld TSSOP MDP0044 ISL28430CVZ-T7A (Note 1) 28430 CVZ 14 Ld TSSOP (Tape & Reel) MDP0044 ISL28430CVZ-T13 (Note 1) 28430 CVZ 14 Ld TSSOP (Tape & Reel) MDP0044 NOTES: 1. Please refer to TB347 for details on reel specifications. 2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 3. For Moisture Sensitivity Level (MSL), please see device information page for ISL28130, ISL28230, ISL28430. For more information on MSL please see techbrief TB363. Pin Configurations ISL28130 (8 LD SOIC) TOP VIEW ISL28130 (5 LD SOT-23) TOP VIEW OUT 1 V- 2 5 V+ IN- 2 + - IN+ 3 NC 1 4 IN- IN+ 3 V- 4 2 8 NC - + 7 V+ 6 OUT 5 NC FN7623.0 August 17, 2010 ISL28130, ISL28230, ISL28430 Pin Configurations (Continued) ISL28230 (8 LD MSOP, SOIC) TOP VIEW ISL28130 (5 LD SC70) TOP VIEW IN+ 1 5 V+ OUT_A 1 + - V- 2 IN- 3 IN-_A 2 4 8 V+ IN+_A 3 OUT 7 OUT_B - + + - V- 4 6 IN-_B 5 IN+_B ISL28430 (14 LD TSSOP, SOIC) TOP VIEW OUT_A 1 IN-_A 2 14 OUT_D - + + - IN+_A 3 12 IN+_D V+ 4 11 V- IN+_B 5 10 IN+_C - + + - IN-_B 6 13 IN-_D 9 IN-_C 8 OUT_C OUT_B 7 Pin Descriptions ISL28130 (5 Ld SOT23) ISL28130 (8 Ld SOIC) ISL28130 (5 LD SC70) PIN NAME 3 3 1 IN+ FUNCTION EQUIVALENT CIRCUIT Non-inverting input V+ - IN- + IN+ VCircuit 1 2 4 2 V- Negative supply 4 2 3 IN- Inverting input 1 6 4 OUT Output (See “Circuit 1”) V+ OUT VCircuit 2 5 7 5 1, 5, 8 3 V+ Positive supply NC Not Connected – This pin is not electrically connected internally. FN7623.0 August 17, 2010 ISL28130, ISL28230, ISL28430 Pin Descriptions ISL28230 ISL28430 (8 Ld MSOP, SOIC) (14 Ld TSSOP, SOIC) PIN NAME 3 3 IN+_A 5 5 IN+_B 10 IN+_C FUNCTION EQUIVALENT CIRCUIT Non-inverting input V+ 12 - IN- + IN+_D IN+ VCircuit 1 4 11 V- 2 2 IN-_A 6 6 IN-_B 9 IN-_C 13 IN-_D 1 1 OUT_A 7 7 OUT_B 8 OUT_C 14 OUT_D Negative supply Inverting input (See Circuit 1) Output V+ OUT VCircuit 2 8 4 4 V+ Positive supply FN7623.0 August 17, 2010 ISL28130, ISL28230, ISL28430 Absolute Maximum Ratings Max Supply Voltage V+ to V- . . . . . . . Max Voltage VIN to GND . . . . . . (V- Max Input Differential Voltage . . . . . . Max Input Current . . . . . . . . . . . . . . Max Voltage VOUT to GND (10s) . . . . ESD Tolerance (ISL28130) Human Body Model . . . . . . . . . . . . Machine Model . . . . . . . . . . . . . . . Charged Device Model . . . . . . . . . . ESD Tolerance (ISL28230, ISL28430) Human Body Model . . . . . . . . . . . . Machine Model . . . . . . . . . . . . . . . Charged Device Model . . . . . . . . . . Latch-Up Passed Per JESD78B . . . . . . Thermal Information ........... 0.3V) to (V+ + ........... ........... ........... . .6.5V 0.3V)V . 6.5V . 20mA .±3.0V . . . . . . . . . . . 3000V . . . . . . . . . . . . 200V . . . . . . . . . . . 1500V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4000V . . 400V . 2000V +125°C Thermal Resistance (Typical) θJA (°C/W) θJC (°C/W) 5 Ld SOT-23 (Notes 4, 5) . . . . . . . . . 225 110 5 Ld SC70 (Notes 4, 5) . . . . . . . . . . 206 146 8 Ld SOIC (ISL28130CBZ) (Notes 4, 5) 135 95 8 Ld MSOP (Notes 4, 5) . . . . . . . . . . 180 65 8 Ld SOIC (ISL28230CBZ) (Notes 4, 5) 125 90 14 Ld TSSOP (Notes 4, 5) . . . . . . . . 110 40 14 Ld SOIC (Notes 4, 5) . . . . . . . . . 75 47 Maximum Storage Temperature Range-65°C to +150°C Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp Operating Conditions Temperature Range . . . . . . . . . . . . . . . . . . . . 0°C to +70°C CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES: 4. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. 5. For θJC, the “case temp” location is taken at the package top center. Electrical Specifications PARAMETER V+ = 5V, V- = 0V, VCM = 2.5V, TA = +25°C, RL = 10kΩ, unless otherwise specified. Boldface limits apply over the operating temperature range, 0°C to +70°C. DESCRIPTION CONDITIONS MIN (Note 6) TYP MAX (Note 6) UNIT -40 ±5 40 µV -46.8 - 46.8 µV -150 20 150 nV/°C DC SPECIFICATIONS VOS Input Offset Voltage Vs = 1.65V to 5.5V TCVOS Input Offset Voltage Temperature Coefficient IOS Input Offset Current - -60 - pA TCIOS Input Offset Current Temperature Coefficient - 0.11 - pA/°C IB Input Bias Current -250 - 250 pA Guaranteed by CMRR -0.1 - 5.1 V VCM = -0.1V to 5.1V 110 125 - dB 105 - - dB 105 138 - dB 105 - - dB Common Mode Input Voltage Range CMRR PSRR Common Mode Rejection Ratio Power Supply Rejection Ratio Vs = 2.0V to 5.5V VOH Output Voltage Swing, High 4.950 4.981 - V VOL Output Voltage Swing, Low - 18 50 mV AOL Open Loop Gain RL = 1MΩ - 150 - dB V+ Supply Voltage Guaranteed by VOS 1.65 - 5.5 V IS Supply Current, Per Amplifier RL = OPEN - 18 25 µA - - 35 µA - 15 - mA ISC+ Output Source Short Circuit Current RL = Short V- 5 FN7623.0 August 17, 2010 ISL28130, ISL28230, ISL28430 Electrical Specifications PARAMETER ISC- V+ = 5V, V- = 0V, VCM = 2.5V, TA = +25°C, RL = 10kΩ, unless otherwise specified. Boldface limits apply over the operating temperature range, 0°C to +70°C. (Continued) MIN (Note 6) TYP MAX (Note 6) UNIT RL = Short V+ - -15 - mA DESCRIPTION CONDITIONS Output Sink Short Circuit Current AC SPECIFICATIONS GBWP Gain Bandwidth Product AV = 100, RF = 100kΩ, RG = 1kΩ, RL = 10kΩ to VCM - 400 - kHz eN VP-P Peak-to-Peak Input Noise Voltage f = 0.01Hz to 10Hz - 1.1 - µVP-P eN Input Noise Voltage Density f = 1kHz - 65 - nV/√(Hz) iN Input Noise Current Density f = 1kHz - 72 - fA/√(Hz) f = 10Hz - 80 - fA/√(Hz) f = 1MHz - 1.6 - pF - 1.12 - pF - 0.2 - V/µs - 0.1 - V/µs - 1.1 - µs - 1.1 - µs AV = +1, VOUT = 2VP-P, RF = 0Ω, RL = 10kΩ, CL = 1.2pF - 20 - µs - 30 - µs Differential Input Capacitance Cin Common Mode Input Capacitance TRANSIENT RESPONSE SR Positive Slew Rate VOUT = 1V to 4V, RL = 10kΩ Negative Slew Rate tr, tf, Small Signal Rise Time, tr 10% to 90% AV = +1, VOUT = 0.1VP-P, RF = 0Ω, RL = 10kΩ, CL = 1.2pF Fall Time, tf 10% to 90% tr, tf Large Signal Rise Time, tr 10% to 90% Fall Time, tf 10% to 90% ts Settling Time to 0.1%, 2VP-P Step AV = +1, RF = 0Ω, RL = 10kΩ, CL = 1.2pF - 35 - µs trecover Output Overload Recovery Time, Recovery to 90% of output saturation AV = +2, RF = 10kΩ, RL = Open, CL = 3.7pF - 10.5 - µs NOTE: 6. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. Typical Performance Curves n V+ = 5V, V- = 0V, VCM = 2.5V, RL = Open, T = +25°C, unless otherwise specified. 70 INPUT BIAS CURRENT IN- (pA) INPUT BIAS CURRENT IN+ (pA) 65 55 VS = ±2.5V 45 35 25 15 5 VS = ±0.825V -5 -15 0 10 20 30 40 50 TEMPERATURE (°C) FIGURE 1. IB+ vs TEMPERATURE 6 60 70 60 VS = ±2.5V 50 40 30 20 VS = ±0.825V 10 0 0 10 20 30 40 50 60 70 TEMPERATURE (°C) FIGURE 2. IB- vs TEMPERATURE FN7623.0 August 17, 2010 ISL28130, ISL28230, ISL28430 V+ = 5V, V- = 0V, VCM = 2.5V, RL = Open, T = +25°C, unless otherwise specified. (Continued) 22 22 21 21 SUPPLY CURRENT (µA) SUPPLY CURRENT (µA) Typical Performance Curves 20 19 18 V+ = 1.6V VIN = 0V RL = OPEN 17 16 0 10 20 30 40 50 60 20 19 18 16 70 V+ = 5V VIN = 0V RL = OPEN 17 0 10 20 TEMPERATURE (°C) FIGURE 3. SUPPLY CURRENT vs TEMPERATURE OPEN LOOP GAIN (dB)/PHASE (°) SUPPLY CURRENT (µA) 20 19 18 VIN = 0V RL = OPEN 16 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 SUPPLY VOLTAGE (V) 150 50 -50 -4 RL = 49.9k RL = OPEN -5 -8 -9 100 RL = 10M CL = 100pF SIMULATION -100 0.1m 1m 10m 100m 1 10 100 1k 10k 100k 1M 10M FREQUENCY (Hz) VS = ±0.8V CL = 3.7pF AV = +1 VOUT = 10mVP-P 1k NORMALIZED GAIN (dB) NORMALIZED GAIN (dB) RL = 100k RL = 10k -7 GAIN 0 1 -3 -6 PHASE 100 0 RL = 1k 1M 10M FIGURE 7. GAIN vs FREQUENCY vs RL, VS = ±0.8V 7 RL = 100k 0 RL = 1k -1 -2 RL = 10k RL = OPEN -3 -4 RL = 49.9k -5 -6 -7 -8 10k 100k FREQUENCY (Hz) 70 200 1 -1 60 50 FIGURE 6. FREQUENCY RESPONSE vs OPEN LOOP GAIN, RL = 10MΩ FIGURE 5. SUPPLY CURRENT vs SUPPLY VOLTAGE -2 40 FIGURE 4. SUPPLY CURRENT vs TEMPERATURE 21 17 30 TEMPERATURE (°C) VS = ±2.5V CL = 3.7pF AV = +1 VOUT = 10mVP-P -9 100 1k 10k 100k FREQUENCY (Hz) 1M 10M FIGURE 8. GAIN vs FREQUENCY vs RL, VS = ±2.5V FN7623.0 August 17, 2010 ISL28130, ISL28230, ISL28430 Typical Performance Curves V+ = 5V, V- = 0V, VCM = 2.5V, RL = Open, T = +25°C, unless otherwise specified. (Continued) 10 1 9 Rf = Rg = 1k 7 GAIN (dB) NORMALIZED GAIN (dB) 0 8 6 Rf = Rg = 10k 5 4 Rf = Rg = 100k VS = ±2.5V RL = 100k CL = 3.7pF AV = +2 VOUT = 10mVP-P 3 2 1 0 100 1k -1 -3 -5 10k 100k FREQUENCY (Hz) 1M -7 NORMALIZED GAIN (dB) GAIN (dB) V+ = 5V CL = 3.7pF RL = 100k VOUT = 10mVP-P Rg = 10k, Rf = 100k AV = 1 100 1k 10k 100k FREQUENCY (Hz) 1M VS = ±0.8V -3 -4 VS= ±1.5V -5 -6 -7 VS = ±2.75V RL = 100k CL = 3.7pF AV = +1 VOUT = 10mVP-P 1k 10k 100k FREQUENCY (Hz) 1M 10M FIGURE 12. GAIN vs FREQUENCY vs SUPPLY VOLTAGE 5.0 CL = 824pF 4.5 CL = 474pF 4.0 CL = 224pF 3.5 SIGNAL (V) NORMALIZED GAIN (dB) 10M VS = ±0.7V -2 -9 100 10M 8 0 -2 -4 1M -1 -8 Rg = OPEN, Rf = 0 FIGURE 11. FREQUENCY RESPONSE vs CLOSED LOOP GAIN 2 10k 100k FREQUENCY (Hz) 0 Rg = 1k, Rf = 100k AV = 10 -10 10 4 1k FIGURE 10. GAIN vs FREQUENCY vs VOUT Rg = 100, Rf = 100k AV = 100 10 6 VOUT = 10mV VS = ±2.5V RL = OPEN CL = 3.7pF AV = 1 1 AV = 1000 30 0 VOUT = 100mV -9 100 10M 50 20 VOUT = 250mV -6 -8 70 40 VOUT = 500mV -4 FIGURE 9. GAIN vs FREQUENCY vs FEEDBACK RESISTOR VALUES Rf/Rg 60 VOUT = 1V -2 CL = 104pF VS = ±2.5V -6 R = 100k L -8 AV = +1 VOUT = 10mVP-P -10 100 1k CL = 51pF 100k 2.0 RL = 100k CL = 3.7pF AV = 1 VOUT = 4VP-P 1.5 0.5 1M FREQUENCY (Hz) FIGURE 13. GAIN vs FREQUENCY vs CL 8 2.5 1.0 CL = 3.7pF 10k 3.0 10M 0 0 50 100 150 200 250 TIME (µs) 300 350 400 FIGURE 14. LARGE SIGNAL STEP RESPONSE (4V) FN7623.0 August 17, 2010 ISL28130, ISL28230, ISL28430 Typical Performance Curves V+ = 5V, V- = 0V, VCM = 2.5V, RL = Open, T = +25°C, unless otherwise specified. (Continued) 1.2 0.14 1.0 0.12 0.10 0.6 SIGNAL (V) SIGNAL (V) 0.8 RL = 100k CL = 3.7pF AV = 1 VOUT = 1VP-P 0.4 0.02 0 10 20 30 40 50 60 TIME (µs) 70 80 90 0 0 100 FIGURE 15. LARGE SIGNAL STEP RESPONSE (1V) 15 20 25 TIME (µs) 30 35 40 VOL ABOVE V- RAIL (mV) 20 19 18 VS = 5V RL = 10kΩ 17 0 10 20 30 40 50 TEMPERATURE (°C) 60 21 20 19 18 16 70 VS = 5V RL = 10kΩ 17 0 -40 Vs = ±0.8V RL = OPEN CL = 3.7pF AV = 1 VOUT = 1VP-P -80 -100 40 50 60 70 -60 Vs = ±2.5V RL = OPEN CL = 3.7pF AV = 1 VOUT = 1VP-P -80 -100 -120 -140 1k 30 -20 CROSSTALK (dB) -60 20 FIGURE 18. VOL vs TEMPERATURE -20 -40 10 TEMPERATURE (°C) FIGURE 17. VOH vs TEMPERATURE CROSSTALK (dB) 10 22 21 16 5 FIGURE 16. SMALL SIGNAL STEP RESPONSE (100mV) 22 VOH BELOW V+ RAIL (mV) RL = 100k CL = 3.7pF AV = 1 VOUT = 100mVP-P 0.06 0.04 0.2 0 0.08 -120 10k 100k 1M FREQUENCY (Hz) FIGURE 19. CROSSTALK vs FREQUENCY, VS = ±0.8V 9 -140 1k 10k 100k 1M FREQUENCY (Hz) FIGURE 20. CROSSTALK vs FREQUENCY, VS = ±2.5V FN7623.0 August 17, 2010 ISL28130, ISL28230, ISL28430 Applications Information Functional Description The ISL28130, ISL28230 and ISL28430 are low offset low drift operational amplifiers with a very high open loop gain (150dB). The ISL28130, ISL28230 and ISL28430 operate on a single supply range of 1.65V to 5.5V or dual supply range of ±0.825V to ±2.75V while consuming only 20µA of supply current per channel. The ISL28130, ISL28230 and ISL28430 has a 400kHz gain-bandwidth. The high open loop gain, low offset voltage, high bandwidth and low 1/f noise make the ISL28130, ISL28230 and ISL28430 ideal for precision applications. Rail-to-rail Input and Output (RRIO) The RRIO CMOS amplifier uses parallel input PMOS and NMOS that enable the inputs to swing 100mV beyond either supply rail. The inverting and non-inverting inputs do not have back-to-back input clamp diodes and are capable of maintaining high input impedance at high differential input voltages. This is effective in eliminating output distortion caused by high slew-rate input signals. The output stage uses common source connected PMOS and NMOS devices to achieve rail-to-rail output drive capability with 15mA current limit and the capability to swing to within 50mV of either rail while driving a 10kΩ load. IN+ and IN- Protection All input terminals have internal ESD protection diodes to both positive and negative supply rails, limiting the input voltage to within one diode beyond the supply rails. For applications where either input is expected to exceed the rails by 0.5V, an external series resistor must be used to ensure the input currents never exceed 20mA (see Figure 21). Layout Guidelines for High Impedance Inputs To achieve the maximum performance of the high input impedance and low offset voltage of the ISL28130, ISL28230 and ISL28430 amplifiers, care should be taken in the circuit board layout. The PC board surface must remain clean and free of moisture to avoid leakage currents between adjacent traces. Surface coating of the circuit board will reduce surface moisture and provide a humidity barrier, reducing parasitic resistance on the board. High Gain, Precision DC-Coupled Amplifier The circuit in Figure 22 implements a single-stage DC-coupled amplifier with an input DC sensitivity of under 100nV that is only possible using a low VOS amplifier with high open loop gain. High gain DC amplifiers operating from low voltage supplies are not practical using typical low offset precision op amps. For example, a typical precision amplifier in a gain of 10kV/V with a ±100µV VOS and offset drift 0.5µV/°C of a low offset op amp would produce a DC error of >1V with an additional 5mV/°C of temperature dependent error making it difficult to resolve DC input voltage changes in the mV range. The ±40µV max VOS and 150nV/°C of temperature drift of the ISL28130, ISL28230, ISL28430 produces a temperature stable maximum DC output error of only ±400mV with a maximum output temperature drift of 1.5mV/°C. The additional benefit of a very low 1/f noise corner frequency and some feedback filtering enables DC voltages and voltage fluctuations well below 10µV to be easily detected with a simple single stage amplifier. CF 0.018µF 1MΩ, +2.5V VIN RIN RL + VOUT VIN FIGURE 21. INPUT CURRENT LIMITING 100Ω 1MΩ + RL VOUT 100Ω -2.5V ACL = 10kV/V FIGURE 22. HIGH GAIN, PRECISION DC-COUPLED AMPLIFIER 10 FN7623.0 August 17, 2010 ISL28130, ISL28230, ISL28430 Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you have the latest revision. DATE REVISION 8/17/10 FN7623.0 CHANGE Initial Release Products Intersil Corporation is a leader in the design and manufacture of high-performance analog semiconductors. The Company's products address some of the industry's fastest growing markets, such as, flat panel displays, cell phones, handheld products, and notebooks. Intersil's product families address power management and analog signal processing functions. Go to www.intersil.com/products for a complete list of Intersil product families. *For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device information page on intersil.com: ISL28130, ISL28230, ISL28430. To report errors or suggestions for this datasheet, please go to www.intersil.com/askourstaff FITs are available from our website at http://rel.intersil.com/reports/search.php For additional products, see www.intersil.com/product_tree Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted in the quality certifications found at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 11 FN7623.0 August 17, 2010 ISL28130, ISL28230, ISL28430 Small Outline Transistor Plastic Packages (SC70-5) P5.049 D VIEW C e1 5 LEAD SMALL OUTLINE TRANSISTOR PLASTIC PACKAGE INCHES 5 SYMBOL 4 E CL 1 2 CL 3 e E1 b CL 0.20 (0.008) M C C CL A A2 SEATING PLANE A1 -C- PLATING b1 0.043 0.80 1.10 - 0.004 0.00 0.10 - A2 0.031 0.039 0.80 1.00 - b 0.006 0.012 0.15 0.30 - b1 0.006 0.010 0.15 0.25 c 0.003 0.009 0.08 0.22 6 c1 0.003 0.009 0.08 0.20 6 D 0.073 0.085 1.85 2.15 3 E 0.071 0.094 1.80 2.40 - E1 0.045 0.053 1.15 1.35 3 e 0.0256 Ref 0.65 Ref - e1 0.0512 Ref 1.30 Ref - L2 c1 NOTES 0.031 0.010 0.018 0.017 Ref. 0.26 0.46 4 0.420 Ref. 0.006 BSC 0o N c MAX 0.000 α WITH MIN A L b MILLIMETERS MAX A1 L1 0.10 (0.004) C MIN - 0.15 BSC 8o 0o 5 8o - 5 5 R 0.004 - 0.10 - R1 0.004 0.010 0.15 0.25 Rev. 3 7/07 NOTES: BASE METAL 1. Dimensioning and tolerances per ASME Y14.5M-1994. 2. Package conforms to EIAJ SC70 and JEDEC MO-203AA. 4X θ1 3. Dimensions D and E1 are exclusive of mold flash, protrusions, or gate burrs. R1 4. Footlength L measured at reference to gauge plane. 5. “N” is the number of terminal positions. R GAUGE PLANE SEATING PLANE L C L1 α L2 6. These Dimensions apply to the flat section of the lead between 0.08mm and 0.15mm from the lead tip. 7. Controlling dimension: MILLIMETER. Converted inch dimensions are for reference only. 4X θ1 VIEW C 0.4mm 0.75mm 2.1mm 0.65mm TYPICAL RECOMMENDED LAND PATTERN 12 FN7623.0 August 17, 2010 ISL28130, ISL28230, ISL28430 Package Outline Drawing P5.064A 5 LEAD SMALL OUTLINE TRANSISTOR PLASTIC PACKAGE Rev 0, 2/10 1.90 0-3° D A 0.08-0.20 5 4 PIN 1 INDEX AREA 2.80 3 1.60 3 0.15 C D 2x 2 5 (0.60) 0.20 C 2x 0.95 SEE DETAIL X B 0.40 ±0.05 3 END VIEW 0.20 M C A-B D TOP VIEW 10° TYP (2 PLCS) 2.90 5 H 0.15 C A-B 2x 1.45 MAX C 1.14 ±0.15 0.10 C SIDE VIEW SEATING PLANE (0.25) GAUGE PLANE 0.45±0.1 0.05-0.15 4 DETAIL "X" (0.60) (1.20) NOTES: 1. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. 2. Dimensioning and tolerancing conform to ASME Y14.5M-1994. 3. Dimension is exclusive of mold flash, protrusions or gate burrs. (2.40) 4. Foot length is measured at reference to guage plane. 5. This dimension is measured at Datum “H”. 6. Package conforms to JEDEC MO-178AA. (0.95) (1.90) TYPICAL RECOMMENDED LAND PATTERN 13 FN7623.0 August 17, 2010 ISL28130, ISL28230, ISL28430 Package Outline Drawing M8.118A 8 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE (MSOP) Rev 0, 9/09 A 3.0±0.1 8 0.25 CAB 3.0±0.1 4.9±0.15 DETAIL "X" 1.10 Max PIN# 1 ID B SIDE VIEW 2 1 0.18 ± 0.05 2 0.65 BSC TOP VIEW 0.95 BSC 0.86±0.09 GAUGE PLANE H C 0.25 SEATING PLANE 0.33 +0.07/ -0.08 0.08 C A B 0.10 ± 0.05 3°±3° 0.10 C 0.55 ± 0.15 DETAIL "X" SIDE VIEW 1 5.80 NOTES: 4.40 3.00 1. Dimensions are in millimeters. 2. Dimensioning and tolerancing conform to JEDEC MO-187-AA and AMSE Y14.5m-1994. 3. Plastic or metal protrusions of 0.15mm max per side are not included. 4. Plastic interlead protrusions of 0.25mm max per side are not included. 5. Dimensions “D” and “E1” are measured at Datum Plane “H”. 6. This replaces existing drawing # MDP0043 MSOP 8L. 0.65 0.40 1.40 TYPICAL RECOMMENDED LAND PATTERN 14 FN7623.0 August 17, 2010 ISL28130, ISL28230, ISL28430 Thin Shrink Small Outline Package Family (TSSOP) 0.25 M C A B D MDP0044 A THIN SHRINK SMALL OUTLINE PACKAGE FAMILY (N/2)+1 N MILLIMETERS SYMBOL 14 LD 16 LD 20 LD 24 LD 28 LD TOLERANCE PIN #1 I.D. E E1 0.20 C B A 1 (N/2) B 2X N/2 LEAD TIPS TOP VIEW 0.05 e C SEATING PLANE 0.10 M C A B b 0.10 C N LEADS H A 1.20 1.20 1.20 1.20 1.20 Max A1 0.10 0.10 0.10 0.10 0.10 ±0.05 A2 0.90 0.90 0.90 0.90 0.90 ±0.05 b 0.25 0.25 0.25 0.25 0.25 +0.05/-0.06 c 0.15 0.15 0.15 0.15 0.15 +0.05/-0.06 D 5.00 5.00 6.50 7.80 9.70 ±0.10 E 6.40 6.40 6.40 6.40 6.40 Basic E1 4.40 4.40 4.40 4.40 4.40 ±0.10 e 0.65 0.65 0.65 0.65 0.65 Basic L 0.60 0.60 0.60 0.60 0.60 ±0.15 L1 1.00 1.00 1.00 1.00 1.00 Reference Rev. F 2/07 NOTES: 1. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusions or gate burrs shall not exceed 0.15mm per side. SIDE VIEW 2. Dimension “E1” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm per side. SEE DETAIL “X” 3. Dimensions “D” and “E1” are measured at dAtum Plane H. 4. Dimensioning and tolerancing per ASME Y14.5M-1994. c END VIEW L1 A A2 GAUGE PLANE 0.25 L A1 0° - 8° DETAIL X 15 FN7623.0 August 17, 2010 ISL28130, ISL28230, ISL28430 Small Outline Package Family (SO) A D h X 45° (N/2)+1 N A PIN #1 I.D. MARK E1 E c SEE DETAIL “X” 1 (N/2) B L1 0.010 M C A B e H C A2 GAUGE PLANE SEATING PLANE A1 0.004 C 0.010 M C A B L b 0.010 4° ±4° DETAIL X MDP0027 SMALL OUTLINE PACKAGE FAMILY (SO) INCHES SYMBOL SO-14 SO16 (0.300”) (SOL-16) SO20 (SOL-20) SO24 (SOL-24) SO28 (SOL-28) TOLERANCE NOTES A 0.068 0.068 0.068 0.104 0.104 0.104 0.104 MAX - A1 0.006 0.006 0.006 0.007 0.007 0.007 0.007 ±0.003 - A2 0.057 0.057 0.057 0.092 0.092 0.092 0.092 ±0.002 - b 0.017 0.017 0.017 0.017 0.017 0.017 0.017 ±0.003 - c 0.009 0.009 0.009 0.011 0.011 0.011 0.011 ±0.001 - D 0.193 0.341 0.390 0.406 0.504 0.606 0.704 ±0.004 1, 3 E 0.236 0.236 0.236 0.406 0.406 0.406 0.406 ±0.008 - E1 0.154 0.154 0.154 0.295 0.295 0.295 0.295 ±0.004 2, 3 e 0.050 0.050 0.050 0.050 0.050 0.050 0.050 Basic - L 0.025 0.025 0.025 0.030 0.030 0.030 0.030 ±0.009 - L1 0.041 0.041 0.041 0.056 0.056 0.056 0.056 Basic - h 0.013 0.013 0.013 0.020 0.020 0.020 0.020 Reference - 16 20 24 28 Reference - N SO-8 SO16 (0.150”) 8 14 16 Rev. M 2/07 NOTES: 1. Plastic or metal protrusions of 0.006” maximum per side are not included. 2. Plastic interlead protrusions of 0.010” maximum per side are not included. 3. Dimensions “D” and “E1” are measured at Datum Plane “H”. 4. Dimensioning and tolerancing per ASME Y14.5M-1994 16 FN7623.0 August 17, 2010 ISL28130, ISL28230, ISL28430 Package Outline Drawing M8.15E 8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE Rev 0, 08/09 4 4.90 ± 0.10 A DETAIL "A" 0.22 ± 0.03 B 6.0 ± 0.20 3.90 ± 0.10 4 PIN NO.1 ID MARK 5 (0.35) x 45° 4° ± 4° 0.43 ± 0.076 1.27 0.25 M C A B SIDE VIEW “B” TOP VIEW 1.75 MAX 1.45 ± 0.1 0.25 GAUGE PLANE C SEATING PLANE 0.10 C 0.175 ± 0.075 SIDE VIEW “A 0.63 ±0.23 DETAIL "A" (0.60) (1.27) NOTES: (1.50) (5.40) 1. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. 2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994. 3. Unless otherwise specified, tolerance : Decimal ± 0.05 4. Dimension does not include interlead flash or protrusions. Interlead flash or protrusions shall not exceed 0.25mm per side. 5. The pin #1 identifier may be either a mold or mark feature. 6. Reference to JEDEC MS-012. TYPICAL RECOMMENDED LAND PATTERN 17 FN7623.0 August 17, 2010