AMC1210 AM C1 21 0I www.ti.com.............................................................................................................................................................. SBAS372D – APRIL 2006 – REVISED MAY 2009 Quad Digital Filter for 2nd-Order Delta-Sigma Modulator FEATURES DESCRIPTION 1 • Four Independently-Programmable Digital Filters • Four Window Comparators • Three Parallel and One Serial Interface • Comprehensive Interrupt System • Programmable Input Configuration • Carrier Frequency Generator for Resolver Applications The AMC1210 is a four-channel digital filter designed specifically for current measurement and resolver position decoding in motor control applications. Each input can receive an independent delta-sigma (ΔΣ) modulator bit stream. The bit streams are processed by four individually-programmable digital decimation filters. The AMC1210 also offers a flexible interface and a comprehensive interrupt unit, allowing customized digital functionality and immediate digital threshold comparisons for over-current monitoring. 2 APPLICATIONS • • Current Measurement Resolver Decoding AMC1210 Resolver Control Module PWM1 Signal Generator PWM2 FILTER MODULE 1 Comparator Filter IN1 ADS1205 CLK1 Input Control Sinc Filter/ Integrator CLK RST INT ACK Interrupt Unit IN2 ADS1205 Time Measurement FILTER MODULE 2 CLK2 Current Shunt Resistor AMC1203 IN3 IN4 ADS1204 CLK4 FILTER MODULE 3 Register Map Interface Module CS ALE RD WR M0 M1 AD0 AD7 FILTER MODULE 4 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2006–2009, Texas Instruments Incorporated AMC1210 SBAS372D – APRIL 2006 – REVISED MAY 2009.............................................................................................................................................................. www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ORDERING INFORMATION (1) (1) PRODUCT PACKAGE-LEAD PACKAGE DESIGNATOR AMC1210 QFN-40 RHA SPECIFIED TEMPERATURE RANGE PACKAGE MARKING –40°C to +125°C AMC1210I ORDERING NUMBER TRANSPORT MEDIA, QUANTITY AMC1210IRHAT Tape and Reel, 250 AMC1210IRHAR Tape and Reel, 2500 For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. ABSOLUTE MAXIMUM RATINGS Over operating free-air temperature range, unless otherwise noted. (1) AMC1210 UNIT –0.3 to +6 V GND – 0.3 to BVDD + 0.3 V Supply voltage, all supplies (AVDD, BVDD, CVDD, DVDD) to GND Digital input to GND Ground voltage difference, AGND to GND ±0.3 V Input current to any pin except supply pins –10 to +10 mA Power dissipation See Dissipation Ratings Table Operating virtual junction temperature range, TJ –40 to +150 °C Operating free-air temperature range, TA –40 to +125 °C Storage temperature range, TSTG –65 to +150 °C (1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under the Electrical Characteristics is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. DISSIPATION RATINGS (1) 2 PACKAGE TA ≤ +25°C POWER RATING DERATING FACTOR ABOVE TA = +25°C TA = +70°C POWER RATING TA = +85°C POWER RATING TA = +125°C POWER RATING RHA (1) 3787mW 30.3mW/°C 2424mW 1969mW 758mW The thermal resistance (junction-to-ambient) of the RHA package is 32°C/W. Submit Documentation Feedback Copyright © 2006–2009, Texas Instruments Incorporated Product Folder Link(s): AMC1210 AMC1210 www.ti.com.............................................................................................................................................................. SBAS372D – APRIL 2006 – REVISED MAY 2009 ELECTRICAL CHARACTERISTICS At –40°C to +125°C, AVDD, CVDD, DVDD = 5V, and BVDD = 2.7V, unless otherwise noted. The following condition must be true on the supplies: CVDD ≥ DVDD ≥ BVDD. AMC1210 PARAMETER TEST CONDITIONS MIN TYP MAX UNIT DIGITAL INPUT/OUTPUT Logic levels: VOH VOL CMOS BVDD = 2.7 2.4 BVDD = 5.0 4.44 V V BVDD = 2.7 BVDD = 5.0 VIH 0.4 V 0.5 V 0.7BVDD V VIL 0.3BVDD System clock frequency V Pin 'CLK' 90 MHz Pins CLK1, CLK2, CLK3, CLK4 Mode = 0 22 MHz SPI interface clock frequency Pin WR, option 1 25 MHz SPI interface clock frequency Pin WR, option 2 40 MHz Pin CS 22 MHz Modulator clock frequency Parallel interface read/write frequency POWER-SUPPLY REQUIREMENTS Power-supply voltage, pin AVDD 4.5 5.5 Power-supply voltage, pins CVDD and DVDD CVDD ≥ DVDD ≥ BVDD 3.0 5.5 V Power-supply voltage, pin BVDD CVDD ≥ DVDD ≥ BVDD 2.4 5.5 V Total power (1) All supplies = 5V 24.5 mW Power-supply current One filter module (2) 260 µA/MHz Power-supply current Four filter modules (2) 850 µA/MHz SPI interface 78 µA/MHz 83 µA/MHz 140 µA/MHz Parallel interface (3) Signal generator SIGNAL GENERATOR OUTPUT VOH RLOAD = 50Ω, bit HPE = 1 VOL RLOAD = 50Ω, bit HPE = 1 VOH RLOAD = 500Ω, bit HPE = 0 VOL RLOAD = 500Ω, bit HPE = 0 (1) (2) (3) 4.60 4.73 0.26 4.60 V 0.4 4.73 0.26 V V 0.4 V Sinc3, 3 Power consumption with two filter modules functioning, both set to SOSR = 256. The filter module is configured with the comparator unit filter set to Sinc , COSR = 32 and the sinc unit filter set to Sinc3 structure and SOSR = 256. All three modes. Submit Documentation Feedback Copyright © 2006–2009, Texas Instruments Incorporated Product Folder Link(s): AMC1210 3 AMC1210 SBAS372D – APRIL 2006 – REVISED MAY 2009.............................................................................................................................................................. www.ti.com DEVICE INFORMATION GND DVDD TE RST M1 M0 ALE CS RD WR 40 39 38 37 36 35 34 33 32 31 RHA PACKAGE(1) QFN-40 (TOP VIEW) CVDD 1 30 BVDD IN1 2 29 GND CLK1 3 28 AD0 IN2 4 27 AD1 CLK2 5 26 AD2 AMC1210 (1) 4 20 AD7 INT 21 19 10 ACK AVDD 18 AD6 SH2 22 17 9 SH1 CLK4 CLK AD5 16 23 GND 8 15 IN4 14 AD4 DVDD 24 13 7 AGND CLK3 12 AD3 PWM2 25 11 6 PWM1 IN3 The thermal pad is internally connected to the substrate. This pad can be connected to the analog ground or left floating. Keep the thermal pad separate from the digital ground, if possible. Submit Documentation Feedback Copyright © 2006–2009, Texas Instruments Incorporated Product Folder Link(s): AMC1210 AMC1210 www.ti.com.............................................................................................................................................................. SBAS372D – APRIL 2006 – REVISED MAY 2009 Table 1. TERMINAL FUNCTIONS TERMINAL (1) (2) (3) NO. NAME 1 CVDD I/O DESCRIPTION Modulator side supply (1) 2 IN1 Input 3 CLK1 Bidirectional 4 IN2 Input 5 CLK2 Bidirectional 6 IN3 Input 7 CLK3 Bidirectional 8 IN4 Input 9 CLK4 Bidirectional Data input from Modulator 1 Clock from/to Modulator 1 Data input from Modulator 2 Clock from/to Modulator 2 Data input from Modulator 3 Clock from/to Modulator 3 Data input from Modulator 4 Clock from/to Modulator 4 10 AVDD 11 PWM1 Output Signal generator supply Signal generator output 12 PWM2 Output Signal generator output (inverted) 13 AGND Signal generator ground 14 DVDD Core supply 15 GND 16 CLK Input System clock 17 SH1 Input First asynchronous sample-and-hold 18 SH2 Input Second asynchronous sample-and-hold 19 ACK Output Acknowledge signal Interrupt signal Ground 20 INT Output 21 AD7 Bidirectional Data bus bit 7 (most significant bit) 22 AD6 Bidirectional Data bus bit 6 23 AD5 Bidirectional Data bus bit 5 24 AD4 Bidirectional Data bus bit 4 25 AD3 Bidirectional Data bus bit 3 26 AD2 Bidirectional Data bus bit 2 27 AD1 Bidirectional Data bus bit 1 28 AD0 Bidirectional Data bus bit 0 (least significant bit) (2) 29 GND Ground 30 BVDD Controller side supply (3) 31 WR Input Write signal (2) 32 RD Input Read signal (2) 33 CS Input Chip select signal (2) 34 ALE Input Address latch enable 35 M0 Input First mode pin 36 M1 Input Second mode pin 37 RST Input Active-low asynchronous reset 38 TE Input For factory test only; must be tied to ground 39 DVDD 40 GND (2) Core supply Ground The pins for the modulator side are 1 to 9. Functionality is dependent on device setup. To see a list of pin functions/names in each mode, see Table 3. The pins for the controller side are 16 to 38. Submit Documentation Feedback Copyright © 2006–2009, Texas Instruments Incorporated Product Folder Link(s): AMC1210 5 AMC1210 SBAS372D – APRIL 2006 – REVISED MAY 2009.............................................................................................................................................................. www.ti.com MODULATOR INPUT MODES TIMING CHARACTERISTICS Over recommended operating free-air temperature range at –40°C to +125°C, DVDD = +5V, CVDD = +5V, and BVDD = +2.7V, unless otherwise noted. MIN MAX tw1 Mode 0 clock period CLKx PARAMETER 45 1/64th of CLK period UNIT ns tw2 Mode 0 clock high time CLKx 10 tw1 – 10 ns tsu1 Setup time from data valid to CLKx high 5 th1 Hold time from CLKx high to data invalid 5 tw3 Mode 1 clock period CLKx 90 1/128th of CLK period ns tw4 Mode 1 clock high time CLKx 20 tw3 – 10 ns tsu2 Setup time from data valid to CLKx high or low 5 ns th2 Hold time from CLKx high or low to data invalid 5 ns tw5 Mode 2 data width INx 45 ns tw6 Mode 2 data pulse width INx 22 tw7 Mode 3 clock period CLKx 22 1/32nd of CLK period ns tw8 Mode 3 clock high time CLKx 5 tw7 – 5 ns tsu3 Setup time from data valid to any CLKx high 5 th3 Hold time from any CLKx high to data invalid 5 tw9 System clock period CLK tw10 System clock high time CLK tw11 Mode 3 generated clock period CLKx tw12 Mode 3 generated high time CLKx td1 ns ns ns ns ns 11 6 ns 10 3 tw9 – 3 ns tw9 tw9 × MD control bits ns tw10 – 2 tw10 + 2 ns Delay from system clock CLK high to generated CLKx high 0 3 ns td2 Delay from system clock CLK low to generated CLKx low 0 3 ns tsu4 Setup time from data valid to any CLKx high 5 ns th4 Hold time from any CLKx high to data invalid 5 ns Mode 0 tw2 Mode 1 tw1 CLKx tw3 tw4 CLKx tsu1 th1 tsu2 tsu2 th2 th2 INx INx Mode 2 (Manchester-encoded bit stream) tw5 Modulator internal clock tw6 Modulator internal data 1 1 0 1 0 1 0 1 1 INx Mode 3 (CLKx is driven externally) tw8 tw7 Mode 3 CLKx (CLKx is generated by AMC1210) tw9 tw10 CLK tsu3 INx th3 td11 tw11 td2 tw12 CLKx tsu4 th4 INx Figure 1. Modulator Input Mode Timing 6 Submit Documentation Feedback Copyright © 2006–2009, Texas Instruments Incorporated Product Folder Link(s): AMC1210 AMC1210 www.ti.com.............................................................................................................................................................. SBAS372D – APRIL 2006 – REVISED MAY 2009 SPI INTERFACE MODES TIMING CHARACTERISTICS (1) Over recommended operating free-air temperature range at –40°C to +125°C, DVDD = +5V, and BVDD = +2.7V, unless otherwise noted. Option 1 PARAMETER MIN Option 2 MAX MIN MAX UNIT tc1 WR period 40 25 ns tw1 WR HIGH or LOW time 10 10 ns td1 Delay time from CS falling to WR rising edge 0 0 td2 Delay time from CS falling to ADO not tristate tsu1 Data setup time 5 5 th1 Input data hold time 5 5 td3 Output data delay time td4 Enable lag time td5 ADO disable time tw2 Sequential transfer delay (1) ns 10 10 ns ns ns 24 24 10 ns 10 ns 10 10 15 ns 15 ns All input signals are specified with tR = tF = 5ns (10% to 90% of BVDD) and timed from a voltage level of (VIL + VIH)/2. CS tc1 1 WR td4 3 2 td1 8 9 10 Address Address A5 A4 Address A0 (LSB) Data IN D15 (MSB) Data IN D0 (LSB) D14 th1 tsu1 tw2 24 tw1 Address A6 (MSB) Command bit R/W RD 4 td3 Data OUT D15 (MSB) AD0 td5 Data OUT D0 (LSB) D14 td2 Figure 2. SPI Interface Option 1—SPI Normal Interface CS tc1 1 WR 8 9 Address A6 (MSB) Address A5 Address A4 Address A0 (LSB) Data IN D15 (MSB) th1 tsu1 24 10 25 tw1 Command bit R/W RD 4 3 2 td1 tw2 td4 D14 Data IN D0 (LSB) td3 Data OUT D15 (MSB) AD0 D14 td5 Data OUT D0 (LSB) td2 Figure 3. SPI Interface Option 2—SPI Fast Interface (> 25MHz) Submit Documentation Feedback Copyright © 2006–2009, Texas Instruments Incorporated Product Folder Link(s): AMC1210 7 AMC1210 SBAS372D – APRIL 2006 – REVISED MAY 2009.............................................................................................................................................................. www.ti.com PARALLEL MODE 1 TIMING CHARACTERISTICS (1) Over recommended operating free-air temperature range at –40°C to +125°C, DVDD = +5V, and BVDD = +2.7V, unless otherwise noted. PARAMETER (2) MIN MAX UNIT tw1 CS low width 40 ns tw2 CS high width 5 ns td1 Delay time from CS low to WR low 3 ns td2 Delay time from WR high to CS high 5 ns tw3 WR low width 10 ns tw4 WR high width 10 ns tsu1 Setup time from ALE high to WR low 0 ns th1 Hold time from WR high to ALE low 2 ns tsu2 Setup time from address valid to WR high 6 ns th2 Hold time from WR high to address invalid 5 ns td3 Delay time from CS low to RD low 0 ns td4 Delay time from RD high to CS high 6 ns tw5 RD low width 30 ns tw6 RD high width 13 td5 Delay time from RD low to data valid td6 Delay time from RD high to databus in tristate td7 Delay time from WR high to RD low (1) (2) ns 0 30 ns 10 ns 10 ns All input signals are specified with tR = tF = 5ns (10% to 90% of BVDD) and timed from a voltage level of (VIL + VIH)/2. tw2 is obsolete if CS stays low between the WR and RD pulses. Parallel mode 1, write access CS tw1 tw2 td1 td2 tw3 tw4 WR RD th1 tsu1 ALE tsu2 AD(7:0) th2 MSB ADDR LSB MSB ADDR Internal address ADDR+1 Parallel mode 1, read access CS WR td7 td4 td3 tw6 tw5 RD ALE td5 AD(7:0) Internal address MSB ADDR td6 MSB LSB ADDR ADDR+1 Figure 4. Parallel Mode 1 Timing 8 Submit Documentation Feedback Copyright © 2006–2009, Texas Instruments Incorporated Product Folder Link(s): AMC1210 AMC1210 www.ti.com.............................................................................................................................................................. SBAS372D – APRIL 2006 – REVISED MAY 2009 PARALLEL MODE 2 TIMING CHARACTERISTICS (1) Over recommended operating free-air temperature range at –40°C to +125°C, DVDD = +5V, and BVDD = +2.7V, unless otherwise noted. PARAMETER (2) MIN MAX UNIT tw1 CS low width 40 ns tw2 CS high width 5 ns td1 Delay time from ALE low to CS high 5 ns td2 Delay time from WR high to CS high 5 ns td3 Delay time from CS low to WR low 3 ns tw3 WR low width 10 ns tw4 WR high width 10 ns tw5 ALE high width 10 ns td4 Delay time from ALE low to WR low 10 ns tsu1 Setup time from address valid to ALE low 6 ns th1 Hold time from ALE low to address invalid 5 ns td5 Delay time from CS low to RD low 0 ns tsu2 Setup time from data valid to WR high 6 ns th2 Hold time from WR high to data invalid 5 ns td6 Delay time from RD high to CS high 6 ns tw6 RD low width 30 ns tw7 RD high width 13 td7 Delay time from RD low to data valid td8 Delay time from RD high to databus in tristate td9 Delay time from ALE low to RD low (1) (2) ns 0 30 ns 10 ns 10 ns All input signals are specified with tR = tF = 5ns (10% to 90% of BVDD) and timed from a voltage level of (VIL + VIH)/2. tw2 is obsolete if CS stays low between the WR, RD and ALE pulses. Parallel mode 2, write access CS tw1 tw2 td1 td2 td3 tw4 tw3 WR RD tw5 td4 ALE tsu1 th1 Internal address th2 MSB ADDR AD(7:0) tsu2 LSB MSB ADDR+1 ADDR Parallel mode 2, read access CS WR td9 td6 tw7 td5 tw6 RD ALE td8 td7 ADDR AD(7:0) Internal address MSB LSB ADDR MSB ADDR+1 Figure 5. Parallel Mode 2 Timing Submit Documentation Feedback Copyright © 2006–2009, Texas Instruments Incorporated Product Folder Link(s): AMC1210 9 AMC1210 SBAS372D – APRIL 2006 – REVISED MAY 2009.............................................................................................................................................................. www.ti.com PARALLEL MODE 3 TIMING CHARACTERISTICS (1) Over recommended operating free-air temperature range at –40°C to +125°C, DVDD = +5V, and BVDD = +2.7V, unless otherwise noted. PARAMETER (2) MIN MAX UNIT tw1 CS low width 40 ns tw2 CS high width 5 ns td1 Delay time from WR low to CS low 5 ns td2 Delay time from ALE high to CS high 5 ns td3 Delay time from RD high to CS high 5 ns td4 Delay time from CS low to RD low 3 ns tw3 RD low width 10 ns tw4 RD high width 30 ns tw5 ALE low width td5 Delay time from ALE high to RD low tsu1 6 ns 10 ns Setup time from address valid to ALE high 5 ns th1 Hold time from ALE high to address invalid 5 ns tsu2 Setup time from data valid to RD high 5 ns th2 Hold time from RD high to data invalid 5 td6 Delay time from RD low to data valid td7 Delay time from RD high to databus in tristate 0 td8 Delay time from WR high to CS low 5 (1) (2) ns 30 ns 10 ns ns All input signals are specified with tR = tF = 5ns (10% to 90% of BVDD) and timed from a voltage level of (VIL + VIH)/2. tw2 is obsolete if CS stays low between the RD and ALE pulses. Parallel mode 3, write access CS tw2 tw1 td1 td2 td3 tw4 td4 tw3 RD WR tw5 td5 ALE tsu1 th1 Internal address th2 MSB ADDR AD(7:0) tsu2 LSB MSB ADDR+1 ADDR Parallel mode 3, read access CS RD td8 WR ALE td6 AD(7:0) Internal address ADDR MSB td7 LSB MSB ADDR ADDR+1 Figure 6. Parallel Mode 3 Timing 10 Submit Documentation Feedback Copyright © 2006–2009, Texas Instruments Incorporated Product Folder Link(s): AMC1210 AMC1210 www.ti.com.............................................................................................................................................................. SBAS372D – APRIL 2006 – REVISED MAY 2009 TYPICAL CHARACTERISTICS At –40°C to +125°C, AVDD, CVDD, DVDD = +5V, and BVDD = +2.7V, unless otherwise noted. The following condition must be true on the supplies: CVDD ≥ DVDD ≥ BVDD. FILTER MODULE CURRENT vs TEMPERATURE INTERFACE MODULE CONTROL vs TEMPERATURE 1000 90 86 Current (mA/MHz) 800 Current (mA/MHz) Parallel mode 88 4 filters 600 400 1 filter 200 84 SPI mode 82 80 78 76 74 72 70 0 68 -40 25 85 125 25 -40 85 Temperature (°C) Temperature (°C) Figure 7. Figure 8. SIGNAL GENERATOR CURRENT vs TEMPERATURE PWM OUTPUT VOLTAGE vs TEMPERATURE 125 5.0 155 4.5 VOH 4.0 3.5 Voltage (V) Current (mA/MHz) 150 145 3.0 2.5 2.0 1.5 140 1.0 VOL 0.5 0 -40 135 -40 25 85 125 25 85 Temperature (°C) Temperature (°C) Figure 9. Figure 10. 125 TYPICAL CURRENT CONSUMPTION vs SUPPLY VOLTAGE 14 Current (mA) 12 10 8 6 4 2.7 3.0 3.3 3.7 4.0 4.3 4.5 5.0 5.5 Supply (V) Figure 11. Submit Documentation Feedback Copyright © 2006–2009, Texas Instruments Incorporated Product Folder Link(s): AMC1210 11 AMC1210 SBAS372D – APRIL 2006 – REVISED MAY 2009.............................................................................................................................................................. www.ti.com THEORY OF OPERATION Overview The AMC1210 is a flexible digital filter device specifically designed for motor control applications. It incorporates four independent digital filters into a digital processing block, allowing communication via SPI bus or 8-bit, multiplexed parallel I/O. Each datastream input can be clocked in using an external clock or a clock provided by a delta-sigma modulator. A time measurement unit allows software monitoring of the sample speed and data acquisition, and a comprehensive control and interrupt unit allows real-time monitoring of the AMC1210 status. A digital comparator unit is provided to alert programmable peak conditions on the different datastreams. When used in current measurement applications, the digital comparator unit can alert a system to over- or under-current situations. Interface Module The AMC1210 can communicate with digital signal processors (DSPs) or microcontrollers (µCs) in four different interface modes: one serial mode and three 8-bit, multiplexed parallel modes. The serial mode is a standard SPI mode, normally with a 24-bit transfer. The multiplexed parallel modes are designed to work together with a wide range of controllers. Mode pins M0 and M1 determine the mode selection. Table 2 shows the digital interface configuration. Table 2. Digital Interface Configuration INTERFACE MODES PIN M1 PIN M0 SPI 0 0 Parallel Mode 1 0 1 Parallel Mode 2 1 0 Parallel Mode 3 1 1 The digital interface pins perform different functions depending on the interface mode. Table 3 shows the pin operations in different modes. Table 3. Pin Functions in Different Communication Modes 12 PIN SPI MODE PARALLEL MODE 1 PARALLEL MODE 2 PARALLEL MODE 3 M1 0 0 1 1 M0 0 1 0 1 ALE – Address/Data Select Address Latch Enable Address Valid CS Frame sync Chip Select Chip Select Chip Select RD SPI Data In Read Read Strobe WR SPI Clock Write Write Read/Write AD0 SPI Data Out Databus 0 (LSB) Databus 0 (LSB) Databus 0 (LSB) AD1 – Databus 1 Databus 1 Databus 1 AD2 – Databus 2 Databus 2 Databus 2 AD3 – Databus 3 Databus 3 Databus 3 AD4 – Databus 4 Databus 4 Databus 4 AD5 – Databus 5 Databus 5 Databus 5 AD6 – Databus 6 Databus 6 Databus 6 AD7 – Databus 7 (MSB) Databus 7 (MSB) Databus 7 (MSB) Submit Documentation Feedback Copyright © 2006–2009, Texas Instruments Incorporated Product Folder Link(s): AMC1210 AMC1210 www.ti.com.............................................................................................................................................................. SBAS372D – APRIL 2006 – REVISED MAY 2009 Clock Setup The clock pin CLK controls the timing of several functions. Table 4 shows the units and features that use the CLK signal for timing. Table 4. CLK Pin Functions MODULE/UNIT Interface/Signal Generator FEATURE Determines output data rate Manchester Decoder in control unit Allows decoding of Manchester data CLKx signal in control unit Provides timing for CLKx pin when bit CD in the control parameter = '1' Clock dividers for CLKx in control unit Divides CLKx speed Modulator failure detection Allows AMC1210 to monitor input clock CLKx Time measurement TMU counts number of CLK cycles when TM = 0 Filter/Input Control Filter/Time Measurement CLOCK FUNCTION Signal generator If none of the features in this table are needed, the CLK pin should be connected to GND to avoid any increased current consumption. SPI Mode The SPI interface runs fully asynchronously to the rest of the system. The four signals of the SPI interface are WR, RD, AD0 and CS. The maximum speed of the SPI interface is 40MHz. When the select signal CS is high, the entire SPI interface is in reset state, except the Address and the Data Register. The SPI clock WR and the serial data input RD are disabled when CS is high. The incoming data is strobed by the SPI interface on the falling edge of the WR. Outgoing data is put on the output AD0 on the rising edge of the WR (see SPI Interface Modes). For a transmission of one 16-bit data word, 24 bits are required. The first incoming bit to the AMC1210 determines if the entire transmission is a read or a write operation. A high bit indicates a read operation, and a low bit indicates a write operation. There are seven address bits. The 16 data bits are transmitted or received after the address bits, according to the sequence shown in Table 5. Table 5. SPI Write 24-Bit Word Format A23 A22 A21 A20 A19 A18 A17 A16 R/W Address MSB A15 A14 A13 A12 A11 A10 A9 A8 A7 Data A6 A5 A4 A3 A2 A1 LSB A0 SPI Option 1 In SPI option 1, one 16-bit transfer is accomplished in the following manner: 1. On the first falling edge of WR, the read/write bit is strobed. 2. On the second falling edge of WR, the MSB of the address (bit 6) is strobed. 3. On the eighth falling edge of WR, the LSB of the address (bit 0) is strobed and the corresponding data of the register map is read. 4. On the ninth rising edge (MSB), the data read from the register map is latched into a shift register and shifted one position each rising edge of the WR. At speeds below 25MHz, it is recommended to perform a read on the next falling edge (Option 1). This data is always sent out, even when a write operation is performed. 5. On the 24th falling edge of WR (LSB), the last data bit is shifted in from RD and a write pulse is generated to write the data into the register map, if a write operation was performed. Figure 2 and Figure 3 provide detailed timing information for the SPI modes. Submit Documentation Feedback Copyright © 2006–2009, Texas Instruments Incorporated Product Folder Link(s): AMC1210 13 AMC1210 SBAS372D – APRIL 2006 – REVISED MAY 2009.............................................................................................................................................................. www.ti.com During continuous read or write, the address increments after each read or write. When the address reaches 7Fh, the address counter starts over from 0. The data is written into the register map on the 16th WR of a data word. If the CS is inactive before the 16th WR in a data word, the data is not written into the register map; the data is lost. Figure 12 shows a typical example of this functionality. CS WR 8 SPICLKs 8 SPICLKs 8 SPICLKs 8 SPICLKs 8 SPICLKs 8 SPICLKs 8 SPICLKs 8 SPICLKs 8 SPICLKs RD Address AD0 Don't care 1st Data to write 1st read Data 2nd Data to write 2nd read Data 3rd Data to write 4th Data to write 3rd read Data 4th read Data Figure 12. Typical Serial Communication Operation SPI Option 2 SPI option 2 is recommended for use when the clock speed is greater than 25MHz. The only difference between option 1 and 2 is the edge from which the output data is strobed. In option 2, the user should read the data on the rising edge after the data from the register map is latched (one half clock cycle after Option 1). In this case, an extra clock cycle is needed (25 clock cycles instead of 24). See the timing diagram in Figure 3. Parallel Mode 1 In Parallel Mode 1, the host port uses WR and RD for independent write and read access to the AMC1210. The current cycle is processed only when the CS input of the AMC1210 is low. RD indicates to the AMC1210 that the host processor has requested a data transfer. The AMC1210 then outputs data to the host. To configure the registers in the AMC1210, the host process issues a WR signal to indicate that valid data is available on the bus. The data is latched into the AMC1210 with the rising edge of the WR. The address for the AMC1210 must be valid at the first rising edge of WR. To indicate that an address is issued, the signal ALE must be set to high before the WR signal is set to low. The CS signal can stay low between two consecutive writes or reads. Figure 4 provides a detailed timing diagram of Parallel Mode 1. Parallel Mode 2 In Parallel Mode 2, the host port uses WR and RD for independent write and read access to the AMC1210. The current cycle is processed only when the CS input of the AMC1210 is low. RD indicates to the AMC1210 that the host processor has requested a data transfer. The AMC1210 then outputs data to the host. To configure the AMC1210 registers, the host process issues a WR signal to indicate that valid data is available on the bus. With the rising edge of WR, the data is latched into the AMC1210. The address is latched into AMC1210 when the signal ALE is set to low. The CS signal can stay low between two consecutive writes or reads. Figure 5 provides a detailed timing diagram of Parallel Mode 2. 14 Submit Documentation Feedback Copyright © 2006–2009, Texas Instruments Incorporated Product Folder Link(s): AMC1210 AMC1210 www.ti.com.............................................................................................................................................................. SBAS372D – APRIL 2006 – REVISED MAY 2009 Parallel Mode 3 In Parallel Mode 3, the host port uses RD and WR for write and read access to the AMC1210. The current cycle is processed only when the CS input of the AMC1210 is low. WR indicates to the AMC1210 that the host processor has initiated a read or write transfer. If WR is high, the AMC1210 outputs data to the host when RD is also low. To configure the registers in the AMC1210, the host process issues a RD signal together with WR low to indicate that valid data is available on the bus. With the rising edge of the RD signal, the data is latched into the AMC1210. The address is latched into AMC1210 when the signal ALE is set high. The CS signal can stay low between two consecutive writes or reads. Figure 6 provides a detailed timing diagram of Parallel Mode 3. In all parallel modes, each address can be accessed sequentially without writing a new address to the AMC1210. When an address is set by the user, a pointer is also set to that address. After each successive read or write operation, the address is incremented by one in the register map. FILTER MODULE The filter module consists of the control block unit, the comparator filter unit, the sinc filter unit, a time measurement unit and a demodulator/integrator unit. Each unit can be individually programmed for several different modes of operation. Figure 13 shows a block diagram of one filter module. The four filter modules are identical and are able to be configured independently. Comparator Unit HLT COMPHx and COMPLx to Interrupt Unit COMPHx COMPLx LLT Control Unit Parallel or serial data Decoding Modulator Input (INx) Filter Unit Serial data Integrator Unit DEMODULATOR Data Register X INTEGRATOR Clock Modulator Clock (CLKx) 1:1 to 1:16 Mode 3 Only Parallel data Sample-and-Hold (SHx) Time Unit Time Register X TM = 1 TM = 0 System Clock (CLK) Counter Parallel data Figure 13. AMC1210 Filter Module Submit Documentation Feedback Copyright © 2006–2009, Texas Instruments Incorporated Product Folder Link(s): AMC1210 15 AMC1210 SBAS372D – APRIL 2006 – REVISED MAY 2009.............................................................................................................................................................. www.ti.com Control Unit The control unit translates the modulator input data and the corresponding clock so that it can be used by the AMC1210. Four input options are available, depending on the mode of the modulator. These options are selected through the bits MOD1 and MOD0 in the Control Parameter Register. Table 6 describes each input mode. A detailed diagram of the timing of each of these modes can be found in the Timing Characteristics section; see Figure 1. Table 6. Interface Modes MODULATOR MODE MOD1 MOD0 DESCRIPTION 0 0 0 The modulator clock is running with the modulator data rate. The modulator data is strobed at every rising edge of the modulator clock. 1 0 1 The modulator clock is running with half of the modulator data rate. The modulator data is strobed at every edge of the modulator clock. 2 1 0 The modulator clock is off and the modulator data is Manchester-encoded. 3 1 1 The modulator clock is running with double of the modulator data rate. The modulator data is strobed at every other positive modulator clock edge. In Modulator Mode 2, the data is Manchester-encoded. An automatic calibration is continuously performed to achieve optimum decoding performance. The status of this calibration can be checked in the Control Parameter Register bits MS10–MS0 and in the Status Register bits MALx and MAFx. The clock input CLKx is ignored in this mode. Input Clocking The filter module clock is separate from the system clock (except when using Modulator Mode 3). This design permits the filter module to run asynchronously from the control module, allowing two different speeds for input data and control block timing. The clock setup is different for each input mode. See Table 7. Table 7. Clock Operation in Each Interface Mode INPUT MODE CLOCK FUNCTIONALITY 0 The clock for the filter module is fed by the CLKx input, which can be either external or driven by the modulator. The frequency is the same. 1 Each edge of CLKx generates a pulse, which clocks the filter module. 2 The clock for the filter module is generated by the Manchester decoder. 3 The clock source is the system clock, from the CLK pin. This clock can be divided down by a programmed number between 1 and 8 by bits MD2–MD0 in the Clock Divider Register. This clock can also be fed to the CLKx pin to drive the modulator clock if the bit CD in the Control Parameter Register is set to '1'. Note that as long as the input data is clocked in correctly, all of the filter module functions (sinc filter unit, comparator unit, etc.) will be clocked at the same rate. 16 Submit Documentation Feedback Copyright © 2006–2009, Texas Instruments Incorporated Product Folder Link(s): AMC1210 AMC1210 www.ti.com.............................................................................................................................................................. SBAS372D – APRIL 2006 – REVISED MAY 2009 Manchester Decoding Manchester signaling is a method of encoding a data signal in such a way that it can be retrieved without the need of a separate clock line. When configured in Mode 2, the AMC1210 can translate a Manchester-encoded signal on the INx pin into a clock signal and a data signal. An automatic calibration is continuously performed to optimize the decoding of the data. The calibration mechanism follows this sequence: 1. The modulator data is sampled at the frequency of the system clock (CLK). 2. The number of CLK cycles between transitions is counted and recorded for 1024 consecutive transitions. 3. The resulting array will have a '1' in the bit location that corresponds to the number of CLK cycles counted between transitions. For example, the sequence shown in Table 8 means that there was at least one instance where three and four, as well as seven and eight, CLK cycles occurred between two transitions. This array is stored in the bits MS10–MS0 in the Control Parameter Register. 4. An algorithm looks for a group of zeros that has ones before and after it. If this pattern is not found, the bits MALx and MAFx in the Status Register are set high. 5. If the algorithm is successful, it will use the location of the first '0' as the number of CLK cycles needed to determine the frequency and which transitions are valid in the Manchester code. 6. The algorithm starts over from Step 2 automatically. Table 8. Example Control Parameter Register VALUE BIT CLK CYCLES 0 MS10 0 MS9 0 MS8 1 MS7 1 MS6 0 MS5 0 MS4 1 MS3 1 MS2 0 MS1 0 MS0 11 10 9 8 7 6 5 4 3 2 1 The MALx bit shows the status of the previous Manchester decoder calibration cycle. If it is high, the decoder calibration has failed on the previous calibration cycle. The MAFx bit shows if any failures have occurred since the last read of the Status Register. Any MALx failure will cause MAFx to go high. MAFx is reset to low when the Status Register is read. The decoding procedure is performed continuously when the AMC1210 is configured for Modulator Mode 2. Note that the CLK frequency must be at least six times the Manchester data rate for the decoder to perform properly. Comparator Unit An independent comparator unit allows the user to monitor input conditions with a fast settling time without sacrificing input measurement resolution. The filter of the comparator unit is similar to the sinc filter unit, with OSR values ranging continuously between 1 and 32. Setting the OSR to 32, a maximum 15-bit output width of 32,768 can be achieved. The output of the filter is compared with two programmed threshold levels to detect over- and under-value conditions. These threshold levels are programmed in the high and low level Threshold Registers for each individual filter module. When an over- or under-value condition occurs, it signals the interrupt unit to set an interrupt signal and store the conditions in the Interrupt Register. The Interrupt Register can then be polled to see which condition caused the interrupt signal. It is not possible to read out the value of the comparator filter. This filter, together with the comparators, is generally used to detect over-currents. It is necessary to decide on an OSR given the desired resolution/settling time combination. This programming will be discussed in more detail in the Applications Information section. Submit Documentation Feedback Copyright © 2006–2009, Texas Instruments Incorporated Product Folder Link(s): AMC1210 17 AMC1210 SBAS372D – APRIL 2006 – REVISED MAY 2009.............................................................................................................................................................. www.ti.com The comparator filter unit and the sinc filter unit differ in the way they handle input data. The comparator filter unit translates a low input signal to a '0' and a high input signal to a '1', whereas the sinc filter unit uses '–1' and '1'. The resulting calculations give only positive values for the output of the comparator filter. The data representation is straight binary. Table 9 and Figure 14 show the different full-scale values that the comparator filter can store using different oversampling ratios. Table 9. Peak Data Values for Different OSR/Filter Combinations Sinc1 Sinc2 Sinc3 Sincfast x 0 to x 2 0 to x 0 to x3 0 to 2x2 4 0 to 4 0 to 16 0 to 64 0 to 32 8 0 to 8 0 to 64 0 to 512 0 to 128 16 0 to 16 0 to 256 0 to 4096 0 to 512 32 0 to 32 0 to 1024 0 to 32,768 0 to 2048 OSR 100000 Sinc 3 10000 Resolution Sincfast 1000 Sinc 2 100 Sinc 10 1 1 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 Oversampling Ratio Figure 14. Comparator Filter Resolution The maximum resolution yields the peak values in Table 9 (15 bits binary, 32,768 decimal). Note that in order to achieve the maximum value, the delta-sigma modulator is operated at absolute maximum positive or negative full-scale, which is outside of the recommended full-scale range of 80% of most delta-sigma modulators. Sinc Filter Unit The AMC1210 utilizes a standard integration/decimation/differentiation scheme to achieve the sinc filter. It can be configured as a Sinc1, Sinc2, Sinc3 or Sincfast filter with oversampling ratios (OSRs) continuously between 1 and 256. Figure 15 illustrates the frequency response of each type of filter. 18 Submit Documentation Feedback Copyright © 2006–2009, Texas Instruments Incorporated Product Folder Link(s): AMC1210 AMC1210 www.ti.com.............................................................................................................................................................. SBAS372D – APRIL 2006 – REVISED MAY 2009 1 (1) 2 -20 -20 -40 -60 -40 -60 -80 -80 -100 -100 -120 -120 0 312.5k 625k 937.5k 1562.5k 0 312.5k Frequency (Hz) 625k 937.5k 1562.5k Frequency (Hz) 3 (1) SINCFAST FILTER RESPONSE SINC FILTER RESPONSE 0 0 -20 -20 Gain (dB) Gain (dB) (1) SINC FILTER RESPONSE 0 Gain (dB) Gain (dB) SINC FILTER RESPONSE 0 -40 -60 -40 -60 -80 -80 -100 -100 -120 (1) -120 0 312.5k 625k 937.5k 1562.5k 0 312.5k Frequency (Hz) NOTE: (1) fDATA = 312.5kHz = 625k 937.5k 1562.5k Frequency (Hz) fCLK 10MHz = OSR 32 Figure 15. AMC1210 Frequency Responses with Various Sinc Filters These figures show the digital filter frequency response for one oversampling ratio (SOSR = 32) and a modulator rate of 10MHz. The general purpose of the digital filter is to average the input modulator data. Achieving higher resolution requires additional samples for averaging, thereby increasing the total samples necessary to accurately represent an abrupt change. It also requires additional clock cycles to complete a single sample. The ratio of clock cycles to output samples is controlled by the SOSR value (the oversampling ratio for the sinc filter unit) in the Sinc Filter Parameter Register. Table 10 and Figure 16 show the maximum resolution given different filter structures and SOSR values. Table 10. Peak Data Values for Different SOSR/Filter Combinations SOSR Sinc1 Sinc2 Sinc3 2 Sincfast 3 2x2 x x x x 4 –4 to 4 –16 to 16 –64 to 64 –32 to 32 8 –8 to 8 –64 to 64 –512 to 512 –128 to 128 16 –16 to 16 –256 to 256 –4096 to 4096 –512 to 512 32 –32 to 32 –1024 to 1024 –32,768 to 32,768 –2048 to 2048 64 –64 to 64 –4096 to 4096 –262,144 to 262,144 –8192 to 8192 128 –128 to 128 –16,384 to 16, 384 –2,097,152 to 2,097,152 –32,768 to 32,768 256 –256 to 256 –65,536 to 65,536 –16,777,216 to 16,777,216 –131,072 to 131,072 Submit Documentation Feedback Copyright © 2006–2009, Texas Instruments Incorporated Product Folder Link(s): AMC1210 19 AMC1210 SBAS372D – APRIL 2006 – REVISED MAY 2009.............................................................................................................................................................. www.ti.com 100000000 Sinc 3 10000000 Sincfast Resolution 1000000 100000 Sinc 10000 2 1000 Sinc 100 1 10 1 1 21 41 61 81 101 121 141 161 181 201 221 241 261 Oversampling Ratio Figure 16. Sinc Filter Resolution The sinc filter has a bit width of 25 bits and a signed two's complementary data representation. The maximum possible resolution gives a 26-bit word (±16,777,216). Note that this value is only reached if the delta-sigma modulator is operated at absolute maximum positive or negative full-scale, which is beyond the recommended full-scale range of 80% of most delta-sigma modulators. This value also does not represent the resolution of the signal. The signal resolution is determined by the modulator, and increasing the filter bit width will not offer any improved noise performance beyond the modulator capabilities. Figure 17 shows how a typical application would use the digital filter. When the filter is enabled, it is continuously processing data and generating output words. When an output word is ready to read, the processor is first triggered by a rising edge on the ACK pin. Then the Interrupt Register is read to check which filter module generated new data. Once all valid data registers have been read, the ACK pin goes low. The data registers can be up to 32 bits. INx CLKx ACK DATA REGISTER Previous Value DATA VALID I/O READ INTERRUPT REGISTER READ DATA REGISTER Figure 17. Typical Data Read Sequence 20 Submit Documentation Feedback Copyright © 2006–2009, Texas Instruments Incorporated Product Folder Link(s): AMC1210 AMC1210 www.ti.com.............................................................................................................................................................. SBAS372D – APRIL 2006 – REVISED MAY 2009 Integrator Unit The integrator allows digital integration (summation) of the filter output data or the direct modulator input data when the sinc filter unit is bypassed. It consists of a parameterized integrator and a data shift unit. The integrator is a simple 32-bit binary two's complement accumulator. The time of integration is determined by either the IOSR value or an external sample-and-hold signal. The bit IMOD in the Integrator Parameter Register determines which mode is used. The integrator is enabled by setting the bit IEN in the Integrator Parameter Register to high. When IEN is low, the integrator is disabled, reset, and bypassed. The input to the integrator is fed by the sinc filter unit. This can be adjusted to allow the input to feed directly into the integrator. See Bypassing the Sinc Filter Unit. Sample-and-Hold Mode (IMOD = 1) If Sample-and-Hold Mode is selected, the SHS bit in the Control Parameter Register determines which sample-and-hold signal is used to determine the total integration time. When a rising edge occurs on the selected sample-and-hold pin, the resulting integrator value is stored in the Data Register and the integrator is reset. Oversampling Mode (IMOD = 0) In Oversampling Mode, the integrator sums a preset number of samples from the sinc filter unit, determined by an oversampling ratio value (IOSR) in the Integrator Parameter Register. The integrator can be configured with oversampling ratios continuously between 1 and 128. The integrator is sampled at the data output rate of the sinc filter unit. Table 11 shows the different full-scale values that the integrator can store with different oversampling ratios, assuming that the sinc filter unit is set to SOSR = 256 at the full-scale output. Table 11. Peak Data Values for Different IOSR Values IOSR INTEGRATOR OUTPUT MAX (with a Sinc3 Structure) x –(SOSR3)(x) to (SOSR3)(x) 4 –67,108,864 to 67,108,856 8 –134,217,728 to 134,217,712 16 –268,435,456 to 268,435,424 32 –536,870,912 to 536,870,848 64 –1,073,741,824 to 1,073,741,696 128 –2,147,483,648 to 2,147,483,648 The start of an integrator cycle in Oversampling Mode is controlled by the sinc filter unit. A new integrator cycle is started when the sinc filter is enabled. The bit MFE in the Clock Divider Register can be used to synchronize the integrator unit in all four of the filter modules. Following the rising edge of the MFE bit, the integrator will begin to accumulate data in all four modules. When the same data output rate is used on all sinc filters, synchronous timing is achieved. Integrator Overflow Meeting or exceeding the maximum values will trigger an integrator overflow (IOx goes high). This overflow condition is only possible in Oversampling Mode when the sinc filter is set to a Sinc3 structure and it outputs only full-scale values. In Sample-and-Hold Mode, the integrator flag will go high if the maximum integrator value is exceeded (–2,147,483,648 or 2,147,483,648). This event will occur if the sample-and-hold signal SHx is held in the active state longer than the overflow time. Submit Documentation Feedback Copyright © 2006–2009, Texas Instruments Incorporated Product Folder Link(s): AMC1210 21 AMC1210 SBAS372D – APRIL 2006 – REVISED MAY 2009.............................................................................................................................................................. www.ti.com Equation 1 calculates the time it takes for the integrator to overflow: (INT MAX @ SOSR) t OVERFLOW + ǒFILT OUT @ f INPUTǓ (1) where: • • • • INTMAX = the maximum integrator value (–2,147,483,648 if FILTOUT< 0, 2,147,483,648 otherwise) FILTOUT = Average Sinc filter output value (from –FILTMAX to +FILTMAX; see Table 10 ) SOSR = oversampling ratio of the Sinc filter fINPUT = modulator data rate For example, if the sinc filter outputs an average code value of 100,000 at a rate of 39.06kHz (fINPUT = 10.0MHz/SOSR = 256), it will take 549.8ms for an integrator overflow flag to occur. When integrator overflow occurs, the integrator value is reset and integration continues. 16-Bit Data Shifting If 16-bit data representation is chosen (DR is low), the shift control bits SH in the Integrator Parameter Register control which 16-bit part of a 32-bit data word is sent to the register map. The shift control bits are the number of left shifts in the 32-bit data word to achieve the maximum 16-bit value range. For example, if the sinc filter runs with a Sinc3 structure and an oversampling ratio of 256, the data values will be in the range of –16,777,216 to 16,777,216. To get a maximum 16-bit range of –32,767 to 32,767, the shift control bits should be set to 9. In this case, 9 LSBs of the 25-bit word are lost. The sign bit is not affected by the shift, which means the sign is always correct, regardless of the shift control bits. Table 12 shows an example. The first column shows the original 32-bit word, the second column shows the SH bits value, and the last column shows which bits of the 32-bit word will be output in 16-bit mode. Table 12. 16-Bit Representation Example 32-BIT WORD b31–b0 SH VALUE 16-BIT REPRESENTATION 1 b16–b1 9 b24–b9 14 b29–b14 Bypassing the Sinc Filter Unit If the integrator is used without the sinc filter unit, the bit FEN has to be set high, the sinc filter structure has to be set to Sinc1, and the sinc filter OSR has to be set to '1'. In this case, the integrator will sum the direct input data from the modulator. Demodulation Obtaining the resolver position from the AM-modulated resolver input signal requires mathematical demodulation. This calculation is performed by the AMC1210 after phase calibration. Modulation is enabled by setting the DEN bit in the Integrator Parameter Register high. For more information, see the Signal Generator Unit description and the Applications Information. Time Measure Unit The time measure unit provides two modes of measuring times, depending on the TM bit in the Control Parameter Register. A counter is implemented in the time measure unit that counts clock cycles from the modulator clock input or the system clock. The maximum measured time, tMAX, is calculated with the formula shown in Equation 2. fCLK is either the modulator clock speed or the system clock speed. t MAX + 65536 f CLK (2) 22 Submit Documentation Feedback Copyright © 2006–2009, Texas Instruments Incorporated Product Folder Link(s): AMC1210 AMC1210 www.ti.com.............................................................................................................................................................. SBAS372D – APRIL 2006 – REVISED MAY 2009 Mode 1 (TM = 1) In Mode 1, the time measure unit updates the Time Register with the elapsed amount of incoming modulator clock cycles between two rising edges of the selected sample-and-hold signal (selected by the SHS bit of the Control Parameter Register). This mode can be used to measure the speed of the modulator clock or determine the number of input bits that have been clocked into the filter module. Each time a positive edge of the selected sample-and-hold is detected, the Time Register will be updated with the time counter value, and the time counter will be reset. Figure 18 shows an example of a typical functional timer sequences in Mode 1. MODE 1 (TM = 1) SH1 or SH2 CLKx TIMER 1 2 3 61 62 63 TIME REGISTER 64 65 66 67 125 126 127 128 1 2 3 61 62 Previous Value 63 64 65 66 67 68 69 70 71 128 Figure 18. Typical Functional Timer Sequence, Mode 1 (TM = 1) Mode 2 (TM = 0) In Mode 2, the time measure unit updates the Time Register with the elapsed amount of system clock cycles from the last available data to the next rising edge of the selected sample-and-hold signal. Each time data is available, that is, when the sinc filter or the integrator has new data, the timer will reset. The timer continuously counts when a rising edge of the selected sample-and-hold signal occurs. At this point, the Time Register is updated with the time counter value, and the time counter will be reset. Figure 19 shows an example of a typical functional timer sequence in Mode 2. Since the Time Register is a 16-bit register, the maximum time measured is 65,536 clock cycles. The bit TOx in the Status Register is set to high when the time counter receives an overflow (that is, when the counter changes from 0xFFFF to 0x0000). This status bit is reset when the Status Register is read. MODE 2 (TM = 0) DATA REGISTER Data Valid SH1 or SH2 ACK CLKx TIMER TIME REGISTER 1 2 3 1 2 3 ... ... ... ... 125 126 127 128 129 1 2 3 63 64 65 128 Previous Value 66 67 68 69 70 71 67 Figure 19. Typical Functional Timer Sequence, Mode 2 (TM = 0) Submit Documentation Feedback Copyright © 2006–2009, Texas Instruments Incorporated Product Folder Link(s): AMC1210 23 AMC1210 SBAS372D – APRIL 2006 – REVISED MAY 2009.............................................................................................................................................................. www.ti.com CONTROL AND INTERRUPT MODULE The control and interrupt module consists of a Signal Generator unit, a comprehensive interrupt unit and a register map. The register map contains all control parameters, output data and status bits for the AMC1210. A detailed description of each register is available in the Register Map section. Signal Generator Unit The signal generator (see Figure 20) provides a 5V Pulse Width Modulated (PWM) signal at pin PWM1 and a complementary signal at PWM2. The output of PWM1 to PWM2 is a 5V differential signal that can be externally low-pass-filtered to generate a carrier signal with a predefined clock frequency. The signal generator is a shift register with a length between 1 and 1024. The shift register is programmed through the Pattern Register (bits SP). On the first write command to the bits SP, the first 16 bits of the shift register are loaded. Each following write command causes the data in the shift register to shift 16 bits upwards, and the 16 bits from the Pattern Register are placed in the LSBs of the shift register. For example, if 874 bits of predefined pattern are to be stored in the shift register, 55 writes to the Pattern Register must be issued (with MSB first and LSB last), and the value 873 must be written into the bits PC in the Control Register. PATTERN REGISTER BIT 15 BIT 0 SHIFT REGISTER WORD 63 WORD 0 DIRECTION OF DATA OUTPUT FLOW DIRECTION OF DATA SHIFT WHEN LOADING Figure 20. AMC1210 Signal Generator Unit The output data rate of the signal generator is programmed with the Clock Divider Register (bits SD). The output data rate can be selected to be an integer division of the CLK rate. For example, if the CLK pin is operating at 40MHz with the bits SD = 4, the bit rate of the signal generator is 10MHz. The length of the pattern can be programmed with the Control Register (bits PC). A length can be chosen between 1 and 1024 bits. This signal is designed for use as the carrier frequency in resolver applications, where proper demodulation requires a completely synchronous clock to the carrier timing. 24 Submit Documentation Feedback Copyright © 2006–2009, Texas Instruments Incorporated Product Folder Link(s): AMC1210 AMC1210 www.ti.com.............................................................................................................................................................. SBAS372D – APRIL 2006 – REVISED MAY 2009 Calibrating the Signal Generator The Signal Generator unit also must be in phase with the total system for resolver demodulation. This condition requires a calibration to align the phase of the Signal Generator output to the sinc filter output. The phase calibration begins when the bit PCAL in the Clock Divider Register is set high. The AMC1210 performs the calibration by monitoring the polarity of both the output of the signal generator and the sinc filter. Once the polarities are defined, a demodulation signal is generated with the corresponding phase shift. The bit PCAL controls demodulation. Initially, it is set high. The AMC1210 then outputs a low on bit PCAL when the modulation is performed correctly. The microcontroller can monitor the calibration by reading PCAL. The first calibration attempt will try to calibrate for one period of the Signal Generator. If PCAL stays high after that period, then calibration has failed. In order to restart calibration, a low must be written to PCAL in order to reset the PCAL state. Writing a subsequent high starts the calibration over. Driving a Signal with the Signal Generator The resolver can be driven directly from the AMC1210. If the bit HBE is set to high, the pins PWM1 and PWM2 are capable of driving 100mA directly into the resolver coils. If bit HBE = 0, the drive capability is lowered. The pattern generator is enabled by the bit SGE in the Clock Divider Register. Interrupt Unit Figure 21 shows the structure of the interrupt unit. HLT1 MIE MIE COMPH1 S R Q IFH1 S R Q IEH1 IEH1 COMP1 LLT1 IP MIE MIE COMPL1 IEL1 IFL1 =1 INT Pin >1 IEL1 From the other filter units Signal when Interrupt Register is read From the watchdog timers Figure 21. AMC1210 Interrupt Unit Each comparator output is one interrupt source (COMPHx or COMPLx) creating eight total comparator outputs in the AMC1210. Each of these eight interrupt sources is stored in a flag register (IFHx or IFLx), if the master interrupt enable (MIE) and the appropriate interrupt enable (IEHx or IELx) are set to high. This flag register will be set to high if an interrupt is issued. This flag will be reset if the Interrupt Register is read and the interrupt source is no longer active. If an interrupt source is still active when the Interrupt Register is read, the appropriate flag and the INT pin will remain set. Figure 22 illustrates an example of the interrupt behavior depending on the value of the threshold registers and the corresponding read access to reset the interrupt flag. If the modulator clock is failing (when the modulator clock is slower than 1/64th of the system clock CLK), a watchdog timer will set a flag MFx, if the appropriate modulator flag interrupt enable bit (MFIEx) and the master interrupt enable (MIE) is set. If the modulator clock is still failing when the Interrupt Register is read, the appropriate flag remains set. The flag clears if the fail condition is no longer true, and the Interrupt Register is read. Any of the 12 interrupt bits will activate the interrupt pin INT, if enabled. The polarity of the INT pin can be chosen with the Interrupt polarity control bit (IP) in the Control Register. Submit Documentation Feedback Copyright © 2006–2009, Texas Instruments Incorporated Product Folder Link(s): AMC1210 25 AMC1210 SBAS372D – APRIL 2006 – REVISED MAY 2009.............................................................................................................................................................. www.ti.com HTL (threshold register) IN1 LTL (threshold register) Parallel Mode 1 INT (pin 20) CS WR RD AD[7:0] 0x00 0xnnn1 0x00 0xnnn2 IFH1 (interrupt register) IFL1 (interrupt register) Figure 22. Interrupt Behavior Acknowledge The acknowledge pin ACK indicates that new data is available from one of the filter modules. When the acknowledge pin goes high, new data is available in one or more of the Data Registers. By reading the Interrupt Register, the filter module with new data can be determined. When one Data Register is read, the appropriate acknowledge flag in the Interrupt Register will be reset; when all flags are reset, the acknowledge pin is reset to low. The acknowledge pin can be inverted if the acknowledge polarity control bit (AP) in the Control Register is set high. The acknowledge flags cannot be set if both the sinc filter and the integrator are disabled. Each acknowledge flag can be disabled if the Acknowledge Enable control bit (AE) in the appropriate Sinc Filter Parameter Register is set to low. The acknowledge flag is not set when the oversampling rates of the sinc filter and the integrator are both set to '1'. 26 Submit Documentation Feedback Copyright © 2006–2009, Texas Instruments Incorporated Product Folder Link(s): AMC1210 AMC1210 www.ti.com.............................................................................................................................................................. SBAS372D – APRIL 2006 – REVISED MAY 2009 REGISTER MAP Filter Module 1 Filter Module 2 Filter Module 3 Filter Module 4 Data/Time Output ADDRESS RESET VALUE 0x00 0x0000 Interrupt Register 0x01 0x0000 Control Parameter Register for Filter Module 1 0x02 0x0000 Sinc Filter Parameter Register for Filter Module 1 0x03 0x0000 Integrator Parameter Register for Filter Module 1 0x04 0x7FFF High-level Threshold Register for Filter Module 1 0x05 0x0000 Low-level Threshold Register for Filter Module 1 0x06 0x0000 Comparator Parameter Register for Filter Module 1 0x07 0x0000 Control Parameter Register for Filter Module 2 0x08 0x0000 Sinc Filter Parameter Register for Filter Module 2 0x09 0x0000 Integrator Parameter Register for Filter Module 2 0x0A 0x7FFF High-level Threshold Register for Filter Module 2 0x0B 0x0000 Low-level Threshold Register for Filter Module 2 0x0C 0x0000 Comparator Parameter Register for Filter Module 2 0x0D 0x0000 Control Parameter Register for Filter Module 3 0x0E 0x0000 Sinc Filter Parameter Register for Filter Module 3 0x0F 0x0000 Integrator Parameter Register for Filter Module 3 0x10 0x7FFF High-level Threshold Register for Filter Module 3 0x11 0x0000 Low-level Threshold Register for Filter Module 3 0x12 0x0000 Comparator Parameter Register for Filter Module 3 0x13 0x0000 Control Parameter Register for Filter Module 4 0x14 0x0000 Sinc Filter Parameter Register for Filter Module 4 0x15 0x0000 Integrator Parameter Register for Filter Module 4 0x16 0x7FFF High-level Threshold Register for Filter Module 4 0x17 0x0000 Low-level Threshold Register for Filter Module 4 0x18 0x0000 Comparator Parameter Register for Filter Module 4 0x19 0x0000 Control Register 0x1A 0x0000 Pattern Register 0x1B 0x0000 Clock Divider Register 0x1C 0x0000 Status Register 0x1D 0x0000/0x00000000 (1) 0x1E 0x0000 0x1F 0x0000/0x00000000 (1) 0x20 0x0000 0x21 0x0000/0x00000000 (1) 0x22 0x0000 0x23 (1) 0x0000/0x00000000 NAME Data Register for Filter Module 1 (1) Time Register for Filter Module 1 Data Register for Filter Module 2 (1) Time Register for Filter Module 2 Data Register for Filter Module 3 (1) Time Register for Filter Module 3 (1) Data Register for Filter Module 4 (1) 0x24 0x0000 Time Register for Filter Module 4 0x25 to 0x7F 0x0000 Not used. Read will return 0x0000 The Data Registers can also be represented as 32-bit. Submit Documentation Feedback Copyright © 2006–2009, Texas Instruments Incorporated Product Folder Link(s): AMC1210 27 AMC1210 SBAS372D – APRIL 2006 – REVISED MAY 2009.............................................................................................................................................................. www.ti.com All control parameters are stored in the register map. Additionally, the status of the AMC1210 is read out through the register map. The mnemonic in the succeeding register description is given in Example 1. Example 1: Register Description Mnemonic Bit 8 Bit 9 Bit 10 The bit position in the register. The name of the register bit. A '–' means Not Used and therefore a write to such a bit position will get lost. CS1 – SHS '1' '0' '0' The digit is the reset value. RW Indicates if the bit position is a read-only (R), readable and writable (RW) or write-only (W). W R REGISTER DESCRIPTIONS This section describes the functionality of each register and its corresponding bits. Interrupt Register (address 0x00) The Interrupt Register contains the 12 interrupt flags together with the acknowledge flags. If an interrupt occurs (that is, when the output of the comparator filter is above the high level threshold or below the low level threshold, or when one of the modulators is not functional), the appropriate interrupt flag is set (if enabled). An interrupt flag is reset when the Interrupt Register is read and the corresponding interrupt source is no longer active. The acknowledge bits are reset when the corresponding data register is read. Table 13 describes the Interrupt Register. Table 13. Interrupt Register Bit 15 AF4 Bit 14 AF3 Bit 13 AF2 Bit 12 AF1 Bit 11 MF4 Bit 10 MF3 Bit 9 MF2 Bit 8 MF1 Bit 7 IFL4 Bit 6 IFH4 Bit 5 IFL3 Bit 4 IFH3 Bit 3 IFL2 Bit 2 IFH2 Bit 1 IFL1 Bit 0 IFH1 '0' '0' '0' '0' '0' '0' '0' '0' '0' '0' '0' '0' '0' '0' '0' '0' R R R R R R R R R R R R R R R R BIT POSITION 28 BIT DESCRIPTION 15 AF4 Acknowledge flag for Filter 4. 0: No new data available for Filter 4 1: New data available for Filter 4 14 AF3 Acknowledge flag for Filter 3. 0: No new data available for Filter 3 1: New data available for Filter 3 13 AF2 Acknowledge flag for Filter 2. 0: No new data available for Filter 2 1: New data available for Filter 2 12 AF1 Acknowledge flag for Filter 1. 0: No new data available for Filter 1 1: New data available for Filter 1 11 MF4 Modulator failure flag for Filter 4. 0: Modulator is operating normally for Filter 4 1: Modulator failure for Filter 4 10 MF3 Modulator failure flag for Filter 3. 0: Modulator is operating normally for Filter 3 1: Modulator failure for Filter 3 9 MF2 Modulator failure flag for Filter 2. 0: Modulator is operating normally for Filter 2 1: Modulator failure for Filter 2 Submit Documentation Feedback Copyright © 2006–2009, Texas Instruments Incorporated Product Folder Link(s): AMC1210 AMC1210 www.ti.com.............................................................................................................................................................. SBAS372D – APRIL 2006 – REVISED MAY 2009 BIT POSITION BIT DESCRIPTION 8 MF1 Modulator failure flag for Filter 1. 0: Modulator is operating normally for Filter 1 1: Modulator failure for Filter 1 7 IFL4 Low-level interrupt flag for Filter 4 0: Comparator Filter 4 output is above the low limit threshold 1: Comparator Filter 4 output is equal to or below the low level threshold, if enabled 6 IFH4 High-level interrupt flag for Filter 4 0: Comparator Filter 4 output is below the high limit threshold 1: Comparator Filter 4 output is equal to or above the high level threshold, if enabled 5 IFL3 Low-level interrupt flag for Filter 3 0: Comparator Filter 3 output is above the low limit threshold 1: Comparator Filter 3 output is equal to or below the low level threshold, if enabled 4 IFH3 High-level interrupt flag for Filter 3 0: Comparator Filter 3 output is below the high limit threshold 1: Comparator Filter 3 output is equal to or above the high level threshold, if enabled 3 IFL2 Low-level interrupt flag for Filter 2 0: Comparator Filter 2 output is above the low limit threshold 1: Comparator Filter 2 output is equal to or below the low level threshold, if enabled 2 IFH2 High-level interrupt flag for Filter 2 0: Comparator Filter 2 output is below the high limit threshold 1: Comparator Filter 2 output is equal to or above the high level threshold, if enabled 1 IFL1 Low-level interrupt flag for Filter 1 0: Comparator Filter 1 output is above the low limit threshold 1: Comparator Filter 1 output is equal to or below the low level threshold, if enabled 0 IFH1 High-level interrupt flag for Filter 1 0: Comparator Filter 1 output is below the high limit threshold 1: Comparator Filter 1 output is equal to or above the high level threshold, if enabled Control Parameter Register (addresses 0x01, 0x07, 0x0D and 0x13) The Control Parameter Registers control several parameters for the data acquisition process. The Control Parameter Register functions include the Manchester decoder calibration status, clock pin direction control, delta-sigma modulator mode select, sample-and-hold select and time measure mode. Table 14 describes the Control Parameter Register. Table 14. Control Parameter Register Bit 15 MS10 Bit 14 MS9 Bit 13 MS8 Bit 12 MS7 Bit 11 MS6 Bit 10 MS5 Bit 9 MS4 Bit 8 MS3 Bit 7 MS2 Bit 6 MS1 Bit 5 MS0 '0' '0' '0' '0' '0' '0' '0' '0' '0' '0' '0' '0' '0' '0' '0' '0' R R R R R R R R R R R RW RW RW RW RW BIT POSITION BIT 15–5 MS10–MS0 4 CD 3 SHS 2 1–0 TM MOD1–MOD0 Bit 4 CD Bit 3 SHS Bit 2 TM Bit 1 MOD1 Bit 0 MOD0 DESCRIPTION Manchester status Input clock direction. 0: Pin CLKx is an input 1: Pin CLKx is an output. The outgoing clock comes from the modulator clock divider. Sample-and-hold select. 0: Signal SH1 is chosen as sample-and-hold signal 1: Signal SH2 is chosen as sample-and-hold signal Time measure mode. 0: The time is measured from the last filter update to the last rising edge of the selected sample-and-hold signal 1: The time is measured between two rising edges of the selected sample-and-hold signal Delta-Sigma Modulator mode. 00: The clock speed is equal to the data rate from the modulator 01: The clock rate is half of the data rate from the modulator 10: The data from the modulator is Manchester decoded 11: The clock rate is twice the data rate of the modulator Submit Documentation Feedback Copyright © 2006–2009, Texas Instruments Incorporated Product Folder Link(s): AMC1210 29 AMC1210 SBAS372D – APRIL 2006 – REVISED MAY 2009.............................................................................................................................................................. www.ti.com Sinc Filter Parameter Register (addresses 0x02, 0x08, 0x0E,and 0x14) The Sinc Filter Parameter Register includes the oversampling ratio (OSR), filter enable, structure and signal mode control bits. Table 15 shows the Sinc Filter Parameter Register. Table 15. Sinc Filter Parameter Register Bit 15 – Bit 14 – Bit 13 – Bit 12 – Bit 11 SST1 Bit 10 SST0 Bit 9 AE Bit 8 FEN Bit 7 SOSR 7 Bit 6 SOSR 6 Bit 5 SOSR 5 Bit 4 SOSR 4 Bit 3 SOSR 3 Bit 2 SOSR 2 Bit 1 SOSR 1 Bit 0 SOSR 0 '0' '0' '0' '0' '0' '0' '0' '0' '0' '0' '0' '0' '0' '0' '0' '0' R R R R RW RW RW RW RW RW RW RW RW RW RW RW 30 BIT POSITION BIT 15–12 – 11–10 SST1–SST0 9 AE 8 FEN 7–0 SOSR7–SOSR0 DESCRIPTION Unused. Always read '0'. Sinc filter structure. 00: Sinc filter runs with 01: Sinc filter runs with 10: Sinc filter runs with 11: Sinc filter runs with a a a a sincfast structure Sinc1 structure Sinc2 structure Sinc3 structure Acknowledge enable. 0: The acknowledge flag is disabled for the particular filter 1: The acknowledge flag is enabled for the particular filter Filter enable. 0: The filter is disabled and no data is produced 1: The filter is enabled and data are produced in the sinc filter and/or integrator Oversampling ratio. The actual rate is SOSR + 1. These bits set the oversampling ratio of the filter. 0xFF represents an oversampling ratio of 256. Submit Documentation Feedback Copyright © 2006–2009, Texas Instruments Incorporated Product Folder Link(s): AMC1210 AMC1210 www.ti.com.............................................................................................................................................................. SBAS372D – APRIL 2006 – REVISED MAY 2009 Integrator Parameter Register (addresses 0x03, 0x09, 0x0F and 0x15) The Integrator Parameter Register controls the integrator functionality. It specifies the integrator oversampling ratio, mode select, shift control, integrator and demodulation enable and data representation control bits. Table 16 shows the Integrator Parameter Register. Table 16. Integrator Parameter Register Bit 15 SH4 Bit 14 SH3 Bit 13 SH2 Bit 12 SH1 Bit 11 SH0 Bit 10 DR Bit 9 DEN Bit 8 IEN Bit 7 IMOD Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 IOSR6 IOSR5 IOSR4 IOSR3 IOSR2 IOSR1 IOSR0 '0' '0' '0' '0' '0' '0' '0' '0' '0' '0' '0' '0' '0' '0' '0' '0' RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW BIT POSITION BIT DESCRIPTION Shift control. These bits indicate by how many bits the 16-bit window is shifted up when 16-bit data representation is chosen. 15–11 SH4–SH0 10 DR 9 DEN Demodulation enable. 0: The demodulation for resolver applications is disabled 1: The demodulation for resolver applications is enabled 8 IEN Integrator enable. 0: The data from the sinc filter output is stored in the register map 1: The data from the integrator is stored in the register map 7 IMOD 6–0 IOSR6–IOSR0 Data representation. 0: The data is stored in 16-bit two's complement 1: The data is stored in 32-bit two's complement Integrator mode. 0: The oversampling mode updates the data output of the integrator 1: The selected sample-and-hold signal updates the data output of the integrator Oversampling ratio. The actual rate is IOSR + 1. These bits set the oversampling ratio of the integrator. 0x03 represents an oversampling ratio of 4. Submit Documentation Feedback Copyright © 2006–2009, Texas Instruments Incorporated Product Folder Link(s): AMC1210 31 AMC1210 SBAS372D – APRIL 2006 – REVISED MAY 2009.............................................................................................................................................................. www.ti.com High-Level Threshold Register (addresses 0x04, 0x0A, 0x10 and 0x16) The High-Level Threshold Register contains the upper level value of the interrupt threshold for the comparator filter. If the value of the comparator filter is equal to or above the high level threshold, the corresponding interrupt flag is set (if enabled). Table 17 describes the High-Level Threshold Register. Table 17. High-Level Threshold Register Bit 15 – Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 HLT14 HLT13 HLT12 HLT11 HLT10 Bit 9 HLT9 Bit 8 HLT8 Bit 7 HLT7 Bit 6 HLT6 Bit 5 HLT5 Bit 4 HLT4 Bit 3 HLT3 Bit 2 HLT2 Bit 1 HLT1 Bit 0 HLT0 '0' '1' '1' '1' '1' '1' '1' '1' '1' '1' '1' '1' '1' '1' '1' '1' R RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW BIT POSITION BIT 15 – DESCRIPTION 14–0 HTL14–HLT0 Unused. Always read '0'. Unsigned high level threshold for the comparator filter output. Low-Level Threshold Register (addresses 0x05, 0x0B, 0x11 and 0x17) The Low-Level Threshold Register contains the lower level of the interrupt threshold for the comparator filter. If the value of the comparator filter is equal to or below the low level threshold, the corresponding interrupt flag is set (if enabled). Table 18 describes the Low-Level Threshold Register. Table 18. Low-Level Threshold Register Bit 15 – Bit 14 LLT14 Bit 13 LLT13 Bit 12 LLT12 Bit 11 LLT11 Bit 10 LLT10 Bit 9 LLT9 Bit 8 LLT8 Bit 7 LLT7 Bit 6 LLT6 Bit 5 LLT5 Bit 4 LLT4 Bit 3 LLT3 Bit 2 LLT2 Bit 1 LLT1 Bit 0 LLT0 '0' '0' '0' '0' '0' '0' '0' '0' '0' '0' '0' '0' '0' '0' '0' '0' R RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW BIT POSITION 32 BIT 15 – 14–0 LTL14–LLT0 DESCRIPTION Unused. Always read '0'. Unsigned low level threshold for the comparator filter output. Submit Documentation Feedback Copyright © 2006–2009, Texas Instruments Incorporated Product Folder Link(s): AMC1210 AMC1210 www.ti.com.............................................................................................................................................................. SBAS372D – APRIL 2006 – REVISED MAY 2009 Comparator Filter Parameter Register (addresses 0x06, 0x0C, 0x12 and 0x18) The Comparator Filter Parameter Register controls several parameters for the comparator filters. It specifies the oversampling ratio, three interrupt enables and structure control bits. Table 19 shows the Comparator Filter Parameter Register. Table 19. Comparator Filter Parameter Register Bit 15 – Bit 14 – Bit 13 – Bit 12 – Bit 11 – Bit 10 – '0' '0' '0' '0' '0' '0' '0' '0' '0' '0' '0' '0' '0' '0' '0' '0' R R R R R R RW RW RW RW RW RW RW RW RW RW BIT POSITION BIT 15–10 – 9 MFIE Bit 9 MFIE Bit 8 CS1 Bit 7 CS0 Bit 6 IEL Bit 5 IEH Bit 4 COSR 4 Bit 3 COSR 3 Bit 2 COSR 2 Bit 1 COSR 1 Bit 0 COSR 0 DESCRIPTION Unused. Always read '0'. Modulator failure interrupt enable. 0: The modulator failure flag as well as the output INT is disabled for this particular flag 1: The modulator failure flag is enabled Comparator filter structure. 00: Comparator filter runs with 01: Comparator filter runs with 10: Comparator filter runs with 11: Comparator filter runs with a a a a sincfast structure Sinc1 structure Sinc2 structure Sinc3 structure 8–7 CS1–CS0 6 IEL Low-level interrupt enable. 0: The low-level interrupt flag as well as the output INT is disabled for this particular flag 1: The low-level interrupt flag is enabled 5 IEH High-level interrupt enable. 0: The high-level interrupt flag as well as the output INT is disabled for this particular flag 1: The high-level interrupt flag is enabled 4–0 COSR4–COSR0 Oversampling ratio. The actual rate is COSR + 1. These bits set the oversampling ratio of the filter. 0xFF represents an oversampling ratio of 256. Submit Documentation Feedback Copyright © 2006–2009, Texas Instruments Incorporated Product Folder Link(s): AMC1210 33 AMC1210 SBAS372D – APRIL 2006 – REVISED MAY 2009.............................................................................................................................................................. www.ti.com Control Register (address 0x19) The Control Register controls the signal pattern generator and the interrupt and acknowledge pin behavior. It specifies the interrupt and acknowledge pin polarities, the master interrupt enable and the signal pattern generator length. Table 20 shows the Control Register. Table 20. Control Register Bit 15 AP Bit 14 IP Bit 13 MIE Bit 12 – Bit 11 – Bit 10 – Bit 9 PC9 Bit 8 PC8 Bit 7 PC7 Bit 6 PC6 Bit 5 PC5 Bit 4 PC4 Bit 3 PC3 Bit 2 PC2 Bit 1 PC1 Bit 0 PC0 '0' '0' '0' '0' '0' '0' '0' '0' '0' '0' '0' '0' '0' '0' '0' '0' RW RW RW R R R RW RW RW RW RW RW RW RW RW RW BIT POSITION BIT DESCRIPTION 15 AP Acknowledge polarity for pin ACK. 0: New data is signaled with a '1' on the pin ACK 1: New data is signaled with a '0' on the pin ACK 14 IP Interrupt polarity for pin INT. 0: An interrupt is signaled with a positive transition on the pin INT 1: An interrupt is signaled with a negative transition on the pin INT 13 MIE 12–10 – 9–0 PC9–PC0 Master interrupt enable. 0: Interrupt pin and interrupt flags are blocked (interrupt pin INT always inactive). 1: Interrupt pin and interrupt flags are not blocked and can be set and reset (if individually enabled). Unused. Always read '0'. Pattern count. Defines the length of the shift register for the signal generator Pattern Register (address 0x1A) The shift register of the signal generator is written through the Pattern Register. Each time this register is written, the shift register is shifted 16 bits upwards and the written data is stored in the 16 LSBs of the shift register. The Pattern Register is a write-only register; a read always returns 0x0000. Table 21 describes the Pattern Register. Table 21. Pattern Register Bit 15 SP15 Bit 14 SP14 Bit 13 SP13 Bit 12 SP12 Bit 11 SP11 Bit 10 SP10 Bit 9 SP9 Bit 8 SP8 Bit 7 SP7 Bit 6 SP6 Bit 5 SP5 Bit 4 SP4 Bit 3 SP3 Bit 2 SP2 Bit 1 SP1 Bit 0 SP0 '0' '0' '0' '0' '0' '0' '0' '0' '0' '0' '0' '0' '0' '0' '0' '0' W W W W W W W W W W W W W W W W 34 BIT POSITION BIT 15–0 SP15–SP0 DESCRIPTION Shift register pattern. Submit Documentation Feedback Copyright © 2006–2009, Texas Instruments Incorporated Product Folder Link(s): AMC1210 AMC1210 www.ti.com.............................................................................................................................................................. SBAS372D – APRIL 2006 – REVISED MAY 2009 Clock Divider Register (address 0x1B) The Clock Divider Register sets up the signal generator, the modulator clock division and the signal generator clock. Table 22 shows the Clock Divider Register. Table 22. Clock Divider Register Bit 15 – Bit 14 – Bit 13 – Bit 12 HBE Bit 11 MFE Bit 10 SGE Bit 9 PCAL Bit 8 SCS1 Bit 7 SCS0 Bit 6 MD2 Bit 5 MD1 Bit 4 MD0 Bit 3 SD3 Bit 2 SD2 Bit 1 SD1 '0' '0' '0' '0' '0' '0' '0' '0' '0' '0' '0' '0' '0' '0' '0' '0' R R R RW RW RW RW RW RW RW RW RW RW RW RW RW BIT POSITION BIT 15–13 – 12 HBE Signal Generator High-Current Output. 0: The high current option for pins PWM1 and PWM2 is disabled 1: The PWM1 and PWM2 outputs are in High Current Mode 11 MFE Master Filter Enable. Functionally AND'ed with bit FEN in the Sinc Filter Parameter Register. 0: Sinc filter units of all filter modules are disabled. 1: Sinc filter units can be enabled if bit FEN is '1'. 10 SGE Signal Generator enable. 0: Signal generator is disabled 1: Signal generator is enabled PCAL Start of phase correction. Writing a '1' to this bit starts the phase calibration. Reading this bit shows the phase calibration status: 1: The phase calibration is performing 0: No phase calibration is performing 9 DESCRIPTION Unused. Always read '0'. Signal generator Control Select (necessary for Phase Calibration and Demodulation on the selected channel). 00: The phase calibration is performed on filter module 1 01: The phase calibration is performed on filter module 2. 10: The phase calibration is performed on filter module 3. 11: The phase calibration is performed on filter module 4. 8–7 SCS1–SCS0 6–4 MD2–MD0 Modulator clock divider. The coding is equal to the first eight codes in SD; see below. SD3–SD0 Signal generator clock divider. 0000: Clock divider is off, outgoing clock equals incoming clock 0001: Outgoing clock is divided by 2 0010: Outgoing clock is divided by 3 0011: Outgoing clock is divided by 4 0100: Outgoing clock is divided by 5 0101: Outgoing clock is divided by 6 0110: Outgoing clock is divided by 7 0111: Outgoing clock is divided by 8 1000: Outgoing clock is divided by 9 1001: Outgoing clock is divided by 10 1010: Outgoing clock is divided by 11 1011: Outgoing clock is divided by 12 1100: Outgoing clock is divided by 13 1101: Outgoing clock is divided by 14 1110: Outgoing clock is divided by 15 1111: Outgoing clock is divided by 16 3–0 Bit 0 SD0 Submit Documentation Feedback Copyright © 2006–2009, Texas Instruments Incorporated Product Folder Link(s): AMC1210 35 AMC1210 SBAS372D – APRIL 2006 – REVISED MAY 2009.............................................................................................................................................................. www.ti.com Status Register (address 0x1C) The Status Register shows the overflow conditions of the timer and the integrator, and the locked status of the Manchester Decoder. When the Status Register is read, the flags MAFx, TOx and IOx are reset. Table 23 describes the Status Register. Table 23. Status Register Bit 15 MAL4 Bit 14 MAL3 Bit 13 MAL2 Bit 12 MAL1 Bit 11 MAF4 Bit 10 MAF3 Bit 9 MAF2 Bit 8 MAF1 Bit 7 TO4 Bit 6 IO4 Bit 5 TO3 Bit 4 IO3 Bit 3 TO2 Bit 2 IO2 Bit 1 TO1 Bit 0 IO1 '0' '0' '0' '0' '0' '0' '0' '0' '0' '0' '0' '0' '0' '0' '0' '0' R R R R R R R R R R R R R R R R BIT POSITION 36 BIT DESCRIPTION 15 MAL4 Manchester locked status for filter module 4. 0: The automatic Manchester encoder calibration is working properly 1: The automatic Manchester encoder calibration has not been able to perform a successful calibration 14 MAL3 Manchester locked status for filter module 3. 0: The automatic Manchester encoder calibration is working properly 1: The automatic Manchester encoder calibration has not been able to perform a successful calibration 13 MAL2 Manchester locked status for filter module 2. 0: The automatic Manchester encoder calibration is working properly 1: The automatic Manchester encoder calibration has not been able to perform a successful calibration 12 MAL1 Manchester locked status for filter module 1. 0: The automatic Manchester encoder calibration is working properly 1: The automatic Manchester encoder calibration has not been able to perform a successful calibration 11 MAF4 Manchester failure status for filter module 4. 0: The automatic Manchester encoder calibration has worked properly since last read access 1: The automatic Manchester encoder has detected problems since last read access 10 MAF3 Manchester failure status for filter module 3. 0: The automatic Manchester encoder calibration has worked properly since last read access 1: The automatic Manchester encoder has detected problems since last read access 9 MAF2 Manchester failure status for filter module 2. 0: The automatic Manchester encoder calibration has worked properly since last read access 1: The automatic Manchester encoder has detected problems since last read access 8 MAF1 Manchester failure status for filter module 1. 0: The automatic Manchester encoder calibration has worked properly since last read access 1: The automatic Manchester encoder has detected problems since last read access 7 TO4 Time counter overflow for filter module 4. 0: No overflow has occurred 1: An overflow occurred in the time measurement unit in filter module 4 6 IO4 Integrator overflow for filter module 4. 0: No overflow has occurred 1: An overflow occurred in the integrator unit in filter module 4 5 TO3 Time counter overflow for filter module 3. 0: No overflow has occurred 1: An overflow occurred in the time measurement unit in filter module 3 4 IO3 Integrator overflow for filter module 3. 0: No overflow has occurred 1: An overflow occurred in the integrator unit in filter module 3 3 TO2 Time counter overflow for filter module 2. 0: No overflow has occurred 1: An overflow occurred in the time measurement unit in filter module 2 2 IO2 Integrator overflow for filter module 2. 0: No overflow has occurred 1: An overflow occurred in the integrator unit in filter module 2 1 TO1 Time counter overflow for filter module 1. 0: No overflow has occurred 1: An overflow occurred in the time measurement unit in filter module 1 0 IO1 Integrator overflow for filter module 1. 0: No overflow has occurred 1: An overflow occurred in the integrator unit in filter module 1 Submit Documentation Feedback Copyright © 2006–2009, Texas Instruments Incorporated Product Folder Link(s): AMC1210 AMC1210 www.ti.com.............................................................................................................................................................. SBAS372D – APRIL 2006 – REVISED MAY 2009 Data Registers (addresses 0x1D, 0x1F, 0x21 and 0x23) The Data Registers store the latest data from either the sinc filter or the integrator output for each filter module. The data is presented in two's complement 16-bit or 32-bit format. The bit DR in the Integrator Parameter Register controls the bit width of the Data Register. It takes two bytes to read the 16-bit formatted data and four bytes to read the 32-bit formatted data. The acknowledge flag for the appropriate filter module is cleared when reading the Data Register. Table 24 describes the Data Register in 16-bit formatting. Table 24. Data Register (16-Bit Format) Bit 15 D15 Bit 14 D14 Bit 13 D13 Bit 12 D12 Bit 11 D11 Bit 10 D10 Bit 9 D9 Bit 8 D8 Bit 7 D7 Bit 6 D6 Bit 5 D5 Bit 4 D4 Bit 3 D3 Bit 2 D2 Bit 1 D1 Bit 0 D0 '0' '0' '0' '0' '0' '0' '0' '0' '0' '0' '0' '0' '0' '0' '0' '0' R R R R R R R R R R R R R R R R BIT POSITION BIT DESCRIPTION 15–0 D15–D0 Data from the sinc filter or the integrator filter in 16-bit formatting. Table 25 describes the Data Register in 32-bit formatting. Table 25. Data Register (32-Bit Format) Bit 31 D31 Bit 30 D30 Bit 29 D29 Bit 28 D28 Bit 27 D27 Bit 26 D26 Bit 25 D25 Bit 24 D24 Bit 23 D23 Bit 22 D22 Bit 21 D21 Bit 20 D20 Bit 19 D19 Bit 18 D18 Bit 17 D17 Bit 16 D16 '0' '0' '0' '0' '0' '0' '0' '0' '0' '0' '0' '0' '0' '0' '0' '0' R R R R R R R R R R R R R R R R Bit 15 D15 Bit 14 D14 Bit 13 D13 Bit 12 D12 Bit 11 D11 Bit 10 D10 Bit 9 D9 Bit 8 D8 Bit 7 D7 Bit 6 D6 Bit 5 D5 Bit 4 D4 Bit 3 D3 Bit 2 D2 Bit 1 D1 Bit 0 D0 '0' '0' '0' '0' '0' '0' '0' '0' '0' '0' '0' '0' '0' '0' '0' '0' R R R R R R R R R R R R R R R R BIT POSITION BIT 31–0 D31–D0 DESCRIPTION Data from the sinc filter or the integrator filter in 32-bit formatting. Time Registers (addresses 0x1E, 0x20, 0x22 and 0x24) The Time Registers store the latest time information for each filter module. The data is presented in straight binary 16-bit format. The bit TMx in the Control Parameter Register controls the mode of the time measure unit. Table 26 describes the Time Registers. Table 26. Time Registers Bit 15 TD15 Bit 14 TD14 Bit 13 TD13 Bit 12 TD12 Bit 11 TD11 Bit 10 TD10 Bit 9 TD9 Bit 8 TD8 Bit 7 TD7 Bit 6 TD6 Bit 5 TD5 Bit 4 TD4 Bit 3 TD3 Bit 2 TD2 Bit 1 TD1 Bit 0 TD0 '0' '0' '0' '0' '0' '0' '0' '0' '0' '0' '0' '0' '0' '0' '0' '0' R R R R R R R R R R R R R R R R BIT POSITION BIT 15–0 TD15–TD0 DESCRIPTION Data from the time measure unit. Submit Documentation Feedback Copyright © 2006–2009, Texas Instruments Incorporated Product Folder Link(s): AMC1210 37 AMC1210 SBAS372D – APRIL 2006 – REVISED MAY 2009.............................................................................................................................................................. www.ti.com APPLICATION INFORMATION The AMC1210 is designed for use in motor control systems utilizing delta-sigma modulators, particularly the ADS120x family of modulators. Resolver Applications Resolvers are used in motor control to determine the angular position and speed of the motor. The resolver consists of three coils, one connected to the rotor and the other two situated orthogonally on the stator. By supplying a sine wave carrier signal to the rotor coil, a voltage is magnetically coupled onto the stator coils, of which the amplitude of the signal is directly proportional to the position of the rotor. By digitizing the stator signals, the exact position of the rotor can be mathematically calculated. Figure 23 shows a block diagram of a standard resolver application. AMC1210 Sinc 3 OSR = 128 Demodulation (including phase adjustment) Integrator Parallel Interface (including configuration registers) OSR = 8 Carrier cancellation PWM Digital, 12-bit Digital, 14-bit ADS1205 IN1P CLK IN1N DATA IN2P DATA IN2N Analog Sine Resolver Cosine Figure 23. Typical Resolver Application with AMC1210 The AMC1210, along with the ADS120x family of modulators, provides a high-resolution resolver-to-digital converter. The user can program a carrier signal that is synchronous with the data rate of the modulator. The modulators digitize the resulting sine and cosine signals from the resolver. The AMC1210 then filters the modulator data with the sinc filter. The resulting data can then be passed to the integrator, where demodulation occurs. The demodulated signal first gets multiplied by the polarity of the carrier signal. If the integrator is programmed with the correct OSR, it sums a clock cycle of the rectified signal. The resulting signal is the baseband signal of the sine or cosine wave. These values can then be processed by a microcontroller to obtain the actual digital representation of the motor position. Several factors need to be considered for a high-performance resolver design. The first item of importance is to establish the timing of the motor control loop. This timing is the rate at which the microcontroller updates the motor driving circuitry. A typical application synchronizes the frequency of the carrier signal to the motor control loop frequency. With a known motor control frequency and a system clock frequency, the user can determine how to set up the AMC1210 for optimal performance. Example 2 shows how the AMC1210 would be set up with a carrier frequency of 8kHz and a system clock frequency of 32MHz. 38 Submit Documentation Feedback Copyright © 2006–2009, Texas Instruments Incorporated Product Folder Link(s): AMC1210 AMC1210 www.ti.com.............................................................................................................................................................. SBAS372D – APRIL 2006 – REVISED MAY 2009 Example 2: AMC1210 Configuration with 8kHz Carrier Frequency and 32MHz System Clock Frequency Motor control loop frequency + f CARRIER + 8kHz (3) f CLK + 32MHz (4) The carrier frequency is generated using the signal generator, which uses the CLK signal for timing. In order to achieve optimal resolution on the carrier signal, it is recommended to use the largest number of bits possible, up to 1024, for a single cycle of the carrier signal. In this example, the length of the signal generator (PC9–PC0 in the Control Register) was chosen to be 1000. This length means the carrier frequency will be: f CLK 32MHz f CARRIER + + ǒN CDiv @ 1000Ǔ ǒNCDiv @ NPATǓ (5) Now the Clk_divider value for the signal generator (SD3–SD0 in the Clock Divider Register) can be calculated: f CLK 32MHz CLK_Divider + + +4 ǒf CARRIER @ N PATǓ (8kHz @ 1000) (6) Therefore, the user can generate a carrier frequency of 8kHz using a CLK speed of 32MHz, and programming bits PC9–PC0 to 999 (1000 – 1) and bits SD3–SD0 to 3 (4 – 1). The next matter of importance is to determine the optimal speed versus resolution tradeoff on the modulator. Figure 24 shows the tradeoff in performance for speed on the ADS1205 modulator. A higher OSR can provide increased ENOB (effective number of bits); however, it requires more data from the converter, resulting in an increased filter delay. 16 ADS1205 14 Sinc 3 12 Sinc 2 ENOB 10 8 6 Sincfast Sinc 1 4 2 0 1 100 10 1000 OSR Figure 24. Effective Number of Bits vs Oversampling Ratio (ADS1205) For maximum resolution, it is best to run the modulator as fast as possible. The speed of the modulator determines what oversampling ratio is needed on the sinc filter and the integrator. In order to synchronize to the motor control loop, the modulator must be decimated down by an integer divisor of the modulator frequency. This relationship is given in Equation 7. fMODULATOR = (fCARRIER × SOSR × ISOR)/NINT (7) Where NINT is the number of carrier signal cycles that will be integrated over. This value is usually set to 1; refer to the application note Using the AMC1210 in Resolver Motor Control Systems (SBAA144) for more detail. Submit Documentation Feedback Copyright © 2006–2009, Texas Instruments Incorporated Product Folder Link(s): AMC1210 39 AMC1210 SBAS372D – APRIL 2006 – REVISED MAY 2009.............................................................................................................................................................. www.ti.com For this example, running the ADS1205 at 16MHz works well. Equation 8 gives the total OSR. f SOSR @ ISOR + MODULATOR + 2000 f CARRIER (8) At this point, the sinc filter oversampling ratio (SOSR) and the integrator oversampling ratio (IOSR) can be defined. From Figure 15, we can see that the best value for ENOB for equivalent OSR values comes from the Sinc3 filter. Therefore, it makes the most sense to choose the Sinc3 filter with a high OSR value. To satisfy Equation 8, the product of the SOSR and ISOR must be 2000. Choosing a Sinc3 filter with an SOSR value of 125 and an ISOR value of 16 produces this result, and gives the following ENOB: ENOB + ENOB_Sincfilter ) ENOB_Integrator + 14 ) 2 + 16 (9) With these values, we can calculate the frequency of data coming out of the Sinc3 filter: f f SINC3 + MODULATOR + 128kHz SOSR (10) and the frequency of data coming out of the integrator: f 3 f INTEGRATOR + SINC + 8kHz IOSR (11) The demodulation function allows the integrator to sum a full rectified cycle of the carrier signal. When choosing IOSR = 16, the integrator will sum 16 samples of the digital filter. The demodulation causes a loss of ENOB of approximately 0.5LSB. This demodulation error gives a total system ENOB = 15.5. In order for this function to work correctly, the phase must be properly aligned between the carrier frequency and the modulator. To perform phase calibration, the carrier frequency, resolver and modulator must be running at the desired rate. Calculating the angle from two separate channels requires both channels integrating over the same period of time. To ensure that the integrators in separate channels are triggered at the same point in time, the bit MFE in the Clock Divider Register can be used. When MFE is low, all sinc filters are disabled. Conversely, when MFE goes high, all sinc filters that have bit FEN in the Sinc Filter Parameter register high are enabled. The integrator period, when in oversampling mode, is triggered by enabling the sinc filter. Therefore, when MFE goes high, all integrator periods are started simultaneously. This event only works if every other set-up procedure is done before MFE is set high. 40 Submit Documentation Feedback Copyright © 2006–2009, Texas Instruments Incorporated Product Folder Link(s): AMC1210 AMC1210 www.ti.com.............................................................................................................................................................. SBAS372D – APRIL 2006 – REVISED MAY 2009 If the drive current needed for the PWM1 or PWM2 pin is in excess of 100mA, or if filtering is desired for a cleaner signal, extra circuitry is required. Figure 25 shows a typical schematic using the AMC1210 and ADS1205 in a resolver application. 5.0V 10mF 5.0V 0.1mF RESOLVER AVDD BVDD CVDD DVDD 5.0V PWM1 M0 M1 PWM2 AMC1210 5.0V CS ALE WR RD RST INT ACK 0.1mF OPA2347 20W 5.0V AVDD BVDD CH A+ 5kW ADS1205 22pF 5kW 20W CH A- OUT A CLKOUT OUT B 20 W Microcontroller/ DSP IN1 CLK1 IN2 CLK2 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 CH B+ 5.0V 5kW 20W 22pF CH BCLKIN 5kW REFIN A REFIN B REFOUT 10mF CLK AGND GND CLKSEL 32 MHz Figure 25. Typical Schematic for Resolver Application Submit Documentation Feedback Copyright © 2006–2009, Texas Instruments Incorporated Product Folder Link(s): AMC1210 41 AMC1210 SBAS372D – APRIL 2006 – REVISED MAY 2009.............................................................................................................................................................. www.ti.com Current Measurement The AMC1210 can also serve as a stand-alone digital filter for modulator signals coming from current-shunt measurements. Performing the digital filtering in the AMC1210 frees resources in the microcontroller or DSP from having to perform the constant processing required to ensure nonstop monitoring of the motor currents. For example, a common application may require both real-time monitoring of motor over-current situations as well as constant high-resolution data to monitor motor speed. A single filter module in the AMC1210 can perform both high-resolution data filtering as well as provide a fast response, programmable over-current interrupt flag. Current Shunt Measurement Current shunt measurements require a small differential signal range (< 1V) and high voltage isolation. This configuration can be incorporated with the AMC1210 with a delta-sigma modulator on the shunt side and a digital isolation device providing common-mode voltage isolation; see Figure 26. 5.0V HV+ Floating Power Supply Gate Drive Circuit 0.1mF BVDD CVDD DVDD R1 AMC1210 R2 27W RSENSE D1 5.1V Power Supply C1 0.1mF ADS1203 M0 C2 0.1mF VDD ISO721 VCC1 VIN+ MCLK IN VIN- MDAT VCC1 M1 GND VCC2 GND2 OUT INx GND1 GND2 CLK 32 MHz Gate Drive Circuit AGND GND HV- Figure 26. Application Diagram—Isolated Current Measurement The AMC1210 offers two different ways of current measurement from a modulator. For stable currents, using the modulator along with the Sinc3 filter offers up to 18.9 effective bits of resolution at an OSR = 256 at a modulator rate of 10MHz. For unstable currents, the integrator can be used in place of (or in combination with) the digital filter to give an average filter value. When used with the time measurement unit, the integrator provides additional filtering (averaging). This averaging is achieved by using the timer in Mode 2 and the integrator in Sample-and-Hold Mode. On a rising edge of the selected Sample-and-Hold signal, both the integrator and the timer store their current values, reset and begin again. These values, once read from their respective registers, are used to calculate the average value by simply dividing the integrator value by the timer value. Figure 27 illustrates this functionality. 42 Submit Documentation Feedback Copyright © 2006–2009, Texas Instruments Incorporated Product Folder Link(s): AMC1210 AMC1210 www.ti.com.............................................................................................................................................................. SBAS372D – APRIL 2006 – REVISED MAY 2009 Period n Integrator Timer Period n+1 Accumulating Output from Digital Filter Counting Digital filter samples SH1 or SH2 CLKx Data Register Time Register Integrator Data from period n-1 Timer Data from period n-1 Integrator Data from period n Timer Data from period n Figure 27. Typical Integrator Sequence Using the integrator with a digital filter provides improved noise performance for a marginal amount of delay. For example, a Sinc2 filter with an SOSR of 16, combined with an integrator with an IOSR of 64, offers three bits of ENOB improvement at the cost of 1.6µs delay. The integrator and modulator can also be used together to calculate an average value of high bits (1) and low bits (–1) coming from the modulator in a floating point factor between –1 and 1. Through bypassing the sinc filter unit, the modulator output can be summed directly by the integrator. By setting up the timer and the integrator in the same way as discussed in the previous example (TM = 1, IMOD = 1), an external signal (SHx) triggers the integrator and timer to run simultaneously. Dividing the resulting integrator data by the time data generates a value between –1 and 1. This calculation represents a ratio of high or low bits to the total number of samples, where –1.0 is all low bits, 0.0 is an even number of high and low bits, and 1.0 is all high bits. Over-Current Measurement Configuring the AMC1210 for successful over-current measurement requires an understanding of the necessary design conditions. The first parameter to keep in mind is the settling time. Once the user has established a maximum settling time for an over-current event (the time between the over-current event and the first data sample that exceeds the comparator threshold) that the system can tolerate, a corresponding digital filter can be chosen. Figure 28 shows settling times with the ADS1203 operating at 10MHz. As the allowable settling time is increased, the amount of data that is filtered is increased, resulting in a higher ENOB. In this example, a modulator rate of 10MHz is used. However, it should be noted that the user can also run the ADS1203 at 16MHz. This speed will decrease the settling time by a factor of 1.6; however, power consumption will be increased. Submit Documentation Feedback Copyright © 2006–2009, Texas Instruments Incorporated Product Folder Link(s): AMC1210 43 AMC1210 SBAS372D – APRIL 2006 – REVISED MAY 2009.............................................................................................................................................................. www.ti.com 10 ADS1203 Sinc 9 3 8 Sincfast ENOB (bits) 7 Sinc 6 2 5 Sinc 4 1 3 2 1 0 0 2 4 6 8 10 Settling Time (ms) Figure 28. Effective Number of Bits vs Settling Time (ADS1203) The user should choose a digital filter that gives the maximum ENOB for the desired settling time. If a 3.2µs settling time is assumed, the user should select a Sinc2 filter. For any delay greater than 4µs, the user should choose a Sinc3 filter. The total delay can be represented by Equation 12: Group_Delay + Order_of_Filter @ OSR f MODULATOR (12) We can then calculate what OSR is necessary to achieve a delay time of 3.2µs by using Equation 13. Group_Delay @ f MODULATOR 3.2ms @ 10MHz OSR + + + 16 2 Order_of_Filter (13) 2 A Sinc comparator filter with an OSR of 16 satisfies the settling time requirements for this example system. A high and low comparator value can be chosen by referring to Table 9. For the present example, the comparator filter is capable of a span of 256 codes (from 0 to 256). If an over-current situation is defined at ±25% of the modulator full-scale range, the High Level Threshold level (HLT15–0) and Low Level Threshold level (LLT15–0) should be set to a maximum value of 64 from the full-scale values, or 64 to 192. It may also be necessary to lower this value to avoid an accidental over-current situation. If a 5% guardband is presumed, the threshold levels should be set to 60 and 196. Hall Sensor Measurement The AMC1210 can be used directly with the ADS120x family of modulators to interface with Hall sensors in order to provide magnetic field strength measurements. The ADS1208 is a 16-bit, second order, delta-sigma modulator with Hall element biasing circuitry. By connecting the MCLK and MDATA lines of the ADS1208 to the INx and CLKx lines, the AMC1210 needs only a system clock to provide filtered data from the modulator. 44 Submit Documentation Feedback Copyright © 2006–2009, Texas Instruments Incorporated Product Folder Link(s): AMC1210 AMC1210 www.ti.com.............................................................................................................................................................. SBAS372D – APRIL 2006 – REVISED MAY 2009 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision C (August 2007) to Revision D ................................................................................................ Page • • • Updated front page graphic to reflect AMC1203 instead of joint ADS1203 and ISO721 ...................................................... 1 Corrected Table 5 to reflect 24-bit transfer.......................................................................................................................... 13 Updated Equation 7 and added application note reference ................................................................................................ 39 Changes from Revision B (July 2007) to Revision C ..................................................................................................... Page • Added note under pin out in Device Information. .................................................................................................................. 4 Submit Documentation Feedback Copyright © 2006–2009, Texas Instruments Incorporated Product Folder Link(s): AMC1210 45 PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (°C) Top-Side Markings (3) (4) AMC1210IRHAR ACTIVE VQFN RHA 40 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 AMC 1210I AMC1210IRHARG4 ACTIVE VQFN RHA 40 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 AMC 1210I AMC1210IRHAT ACTIVE VQFN RHA 40 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 AMC 1210I AMC1210IRHATG4 ACTIVE VQFN RHA 40 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 AMC 1210I (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. 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Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 20-Mar-2014 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant AMC1210IRHAR VQFN RHA 40 2500 330.0 16.4 6.3 6.3 1.5 12.0 16.0 Q2 AMC1210IRHAT VQFN RHA 40 250 180.0 16.4 6.3 6.3 1.5 12.0 16.0 Q2 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 20-Mar-2014 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) AMC1210IRHAR VQFN RHA 40 2500 336.6 336.6 28.6 AMC1210IRHAT VQFN RHA 40 250 213.0 191.0 55.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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