NSC CLC407 Low-cost, low-power programmable gain buffer with disable Datasheet

N
Comlinear CLC407
Low-Cost, Low-Power
Programmable Gain Buffer with Disable
General Description
Features
The Comlinear CLC407 is a low-cost, high-speed (110MHz)
buffer which features user-programmable gains of +2, +1, and -1
V/V. This high-performance part has the added versatility of a
TTL-compatible disable which quickly switches the buffer off in
18ns and back on in 40ns. The CLC407’s high 60mA output
current, coupled with its ultra-low 35mW power consumption
makes it the ideal choice for demanding applications that are
sensitive to both power and cost.
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Utilizing Comlinear’s proven architectures, this current feedback
amplifier surpasses the performance of alternate solutions with a
closed-loop design that produces new standards for buffers in
gain accuracy, input impedance, and input bias currents. The
CLC407’s internal feedback network provides an excellent gain
accuracy of 0.1%. High source impedance applications will
benefit from the CLC407’s 6MΩ input impedance along with its
exceptionally low 100nA input bias current.
Applications
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With 0.1dB flatness to 30MHz and low differential gain and phase
errors, the CLC407 is very useful for professional video processing and distribution. A 110MHz -3dB bandwidth coupled with a
350V/µs slew rate also make the CLC407 a perfect choice in
cost-sensitive applications such as video monitors, fax machines,
copiers, and CATV systems. Back-terminated video applications
will especially appreciate +2 gains which require no external gain
components reducing inventory costs and board space.
Low-cost
High output current: 60mA
High input impedance: 6MΩ
Gains of +1, +2 with no external components
Low power: Icc = 3.5mA
Ultra-fast enable/disable times
Very low input bias currents: 100nA
Excellent gain accuracy: 0.1%
High speed: 110MHz -3dB BW
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Desktop video systems
Multiplexers
Video distribution
Flash A/D driver
High-speed switch/driver
High-source impedance applications
Peak detector circuits
Professional video processing
High resolution monitors
Frequency Response (AV = +2V/V)
Comlinear CLC407
Low-Cost, Low-Power, Programmable Gain Buffer with Disable
August 1996
Typical Application
2:1 Mux Cable Driver
Pinout
DIP & SOIC
NOTE: All necessary components are shown.
© 1996 National Semiconductor Corporation
Printed in the U.S.A.
http://www.national.com
CLC407 Electrical Characteristics (AV = +2, Vcc = + 5V, RL = 100Ω unless specified)
PARAMETERS
Ambient Temperature
CONDITIONS
CLC407AJ
TYP
+25˚C
MIN/MAX RATINGS
+25˚C
0 to 70˚C -40 to 85˚C
UNITS
NOTES
FREQUENCY DOMAIN RESPONSE
-3dB bandwidth
Vout < 1.0Vpp
Vout < 5.0Vpp
±0.1dB bandwidth
Vout < 1.0Vpp
gain flatness
Vout < 1.0Vpp
peaking
DC to 200MHz
rolloff
<30MHz
linear phase deviation
<20MHz
differential gain
NTSC, RL=150Ω
NTSC, RL=150Ω (Note 2)
differential phase
NTSC, RL=150Ω
NTSC, RL=150Ω (Note 2)
110
42
30
75
31
15
50
27
45
26
MHz
MHz
MHz
B
1
0
0.1
0.3
0.03
0.01
0.25
0.08
0.4
0.5
0.6
0.05
0.6
0.65
0.7
0.06
0.8
0.7
0.7
0.07
B
B
0.4
0.5
0.55
dB
dB
deg
%
%
deg
deg
TIME DOMAIN RESPONSE
rise and fall time
settling time to 0.05%
overshoot
slew rate
AV = +2
AV = -1
5
18
3
350
650
7.5
27
12
260
8.2
36
12
225
8.4
39
12
215
ns
ns
%
V/µs
V/µs
-72/-52
-70/-57
-46
-50
-45
-47
-44
-46
dBc
dBc
5
12
3
6.3
15
3.8
6.6
16
4
6.7
17
4.2
nV/√Hz
pA/√Hz
pA/√Hz
1
30
100
3
1
17
2.5
±0.1%
250
52
50
3.5
0.8
5
7
50
1600
8
6
40
17
±1.0%
8
50
2800
11
8
45
19
±1.0%
46
44
4.1
0.95
45
43
4.4
1
mV
µV/˚C
nA
nA/˚C
µA
nA/˚C
mV
V/V
Ω
dB
dB
mA
mA
2V step
2V step
2V step
2V step
1V step
DISTORTION AND NOISE RESPONSE
2nd harmonic distortion
2Vpp, 1MHz/10MHz
3rd harmonic distortion
2Vpp, 1MHz/10MHz
equivalent input noise
non-inverting voltage
>1MHz
inverting current
>1MHz
non-inverting current
>1MHz
STATIC DC PERFORMANCE
input offset voltage
average drift
input bias current
average drift
input bias current
average drift
output offset voltage
amplifier gain error
internal feedback resistor (Rf)
power supply rejection ratio
common-mode rejection ratio
supply current
disabled
DC
DC
RL= ∞
RL= ∞
SWITCHING PERFORMANCE
turn on time
turn off time
off isolation
high input voltage
low input voltage
to >50dB attn. @ 10MHz
10MHz
VIH
VIL
non-inverting
inverting
MISCELLANEOUS PERFORMANCE
input resistance
non-inverting
input capacitance
non-inverting
common mode input range
output voltage range
RL= ∞
output current
output resistance, closed loop
900
5
13
±1.0%
±20%
47
45
4.0
0.9
40
18
85
55
26
80
2
0.8
58
30
80
2
0.8
58
32
80
2
0.8
ns
ns
dB
V
V
6
1
±2.2
+4.0,-3.3
60
0.06
3
2
1.8
+3.9,-3.2
44
0.2
2.4
2
1.7
+3.8,-3.1
38
0.25
1
2
1.5
+3.7,-2.8
20
0.4
MΩ
pF
V
V
mA
Ω
2
2
B, C
B, C
A
A,3
A
B
A
A
Recommended gain range +1, +2 V/V
Min/max ratings are based on product characterization and simulation. Individual parameters are tested as noted. Outgoing quality levels are
determined from tested parameters.
Absolute Maximum Ratings
supply voltage
Iout is short circuit protected to ground
common-mode input voltage
maximum junction temperature
storage temperature range
lead temperature (soldering 10 sec)
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Notes
1) At temps < 0˚C, spec is guaranteed for RL = 500Ω.
2) An 825Ω pull-down resistor is connected between Vo and -Vcc.
3) Source impedance 1kΩ.
A) J-level: spec is 100% tested at +25˚C, sample tested at +85˚C.
LC/MC-level: spec is 100% wafer probed at +25˚C.
B) J-level: spec is sample tested at +25˚C.
C) Guaranteed at 10MHz.
±7V
±Vcc
+175˚C
-65˚C to +150˚C
+300˚C
2
CLC407 Typical Performance Characteristics (AV = +2, Rf = 250Ω: Vcc = + 5V, RL = 100Ω unless specified)
Frequency Response
Frequency Response vs. RL
Frequency Response vs. Vout (Av = +2)
AV+1
RL =1k
-45
RL =50
10
-90
RL =1k
1
100
10
Frequency (MHz)
VO =1Vpp
10
Frequency Response vs. Capacitive Load
-90
VO =0.2Vpp
-135
VO =0.2Vpp
VO =4Vpp
VO =1Vpp
-180
VO =4Vpp
-225
VO =1Vpp
-270
VO =2Vpp
-315
VO =0.2Vpp
-180
10
1
100
Magnitude (1dB/div)
VO =2Vpp
Magnitude (1dB/div)
-45
100
Frequency (MHz)
Gain
Phase
-180
CL =1kpF
Rs=10
Phase
0
-45
CL =1kpF
-90
CL =10pF
-135
CL =100pF
-360
10
CL =10pF
Rs=100
CL =100pF
Rs= 30
1
100
-180
10
Frequency (MHz)
100
Frequency (MHz)
Gain Flatness & Linear Phase Deviation
Equivalent Input Noise
100
3.0
Noise Voltage (nV/√Hz)
4.0
Phase
100
Inverting Current = 12pA/√Hz
10
10
Voltage = 5nV/√Hz
Non-Inverting Current = 3pA/√Hz
Noise Current (pA/√Hz)
5.0
Gain
LPD (0.5o/div)
Magnitude (0.1dB/div)
7.0
6.0
Phase (deg)
0
VO =4Vpp
Maximum Output Voltage vs. RL
Maximum Output Voltage (Vpp)
1
Phase (deg)
Phase
Phase (deg)
Magnitude (1dB/div)
VO =2Vpp
-135
VO =1Vpp
Gain
VO =4Vpp
-90
VO =5Vpp
-180
Frequency Response vs. Vout (Av = -1)
Frequency (MHz)
1
1
2.0
0
100
200
300
400
0
500
15
30
100
2nd Rl = 100
3rd Rl = 100
-80
2nd Rl = 1k
+
10MHz
-
5MHz
-55
+
-65
Pout
50Ω
-
Distortion (dBc)
Distortion (dBc)
-60
50Ω
1MHz
-75
-55
5MHz
-65
1MHz
-75
-10
10
0
10
-10
Output Power (dBm)
Frequency (MHz)
Output Resistance vs. Frequency
-40
Gain (dB)
30
10
-10
Differential Gain & Phase
0.20
-60
-80
Reverse
-100
-30
10
1.00
0.15
0.75
Phase
0.10
0.50
Gain
0.05
0.25
Forward
-120
-50
1
10
Frequency (MHz)
100
0
1
10
100
Frequency (MHz)
3
Differential Phase (deg)
-20
0
Output Power (dBm)
Forward & Reverse Isolation During Disable
50
500KHz
-85
Differential Gain (%)
1
10MHz
50Ω
10dBm = 2Vpp
0dBm = .63Vpp
-85
0.1
Pout
50Ω
500KHz
3rd Rl = 1k
-90
10M
-45
10dBm = 2Vpp
0dBm = .63Vpp
-50
1M
100k
3rd Harmonic Distortion vs. Pout
-45
Vo = 2Vpp
-70
10k
Frequency (Hz)
2nd Harmonic Distortion vs. Pout
2nd & 3rd Harmonic Distortion
-40
1k
Frequency (MHz)
Load (Ω)
Distortion (dBc)
VO =0.2Vpp
VO =2Vpp
VO =1Vpp
Output Resistance (20log Zout)
0
-45
VO =2Vpp
100
VO =0.2Vpp
1
VO =0.2Vpp
Phase
Frequency (MHz)
Frequency Response vs. Vout (Av = +1)
Gain
-135
RL =100
AV-1
1
0
Magnitude (1dB/div)
AV+2
RL =100
VO =5Vpp
Phase (deg)
AV+1
RL =50
Phase
VO =1Vpp
VO =2Vpp
Gain
Phase (deg)
AV+2
Phase
Magnitude (1dB/div)
Gain
Phase (45 o/div)
Magnitude (1dB/div)
Gain
AV -1
0
1
2
3
4
Number of 150Ω Loads
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CLC407 Typical Performance Characteristics (AV = +2, Rf = 250Ω: Vcc = + 5V, RL = 100Ω unless specified)
Large Signal Pulse Response
2.0
AV+2
1.0
Output Voltage
Output Voltage
AV+2
0.10
0.00
-0.10
0.0
-1.0
AV-1
-0.20
AV-1
-2.0
Time (5ns/div)
Settling Time vs. Capacitive Load
50
100
+
Rs
CLC407
-
40
CL
250Ω
1k
80
Ts
250Ω
Vo = 2V step
30
60
20
40
Rs (Ω)
Settling Time, Ts(ns) to 0.05% Error
Small Signal Pulse Response
0.20
Rs
10
20
0
Time (5ns/div)
10
0
1000
100
CL (pF)
Short Term Settling Time
4.0
60
Vout = 2Vstep
0.1
0.0
-0.1
50
Offet Voltage, VIO (mV)
PSRR/CMRR (dB)
PSRR
CMRR
40
30
20
0
40
20
60
80
100
IBN
3.0
0
IBI
2.0
-1.0
1.0
-2.0
VIO
0
-3.0
-1.0
10
-0.2
1.0
10k
100k
Time (ns)
10M
1M
100M
IBI, IBN (µA)
Vout (% Final Value)
IBI, IBN, VIO vs. Temperature
PSRR and CMRR
0.2
-4.0
-60
-20
20
60
100
140
Temperature (oC)
Frequency (Hz)
CLC407 OPERATION
Minimize this capacitive coupling during layout by removing
ground plane near pins 1, 2, and 3. This minimization
should produce a response similar to the plot labeled
“open” in Graph 1. If desired flatness is greater than plot
“open” in Graph 1, two options remain to further flatten
the frequency response. First, try shorting the inverting
input (pin 2) to the non-inverting input (pin 3). This
response is labeled “short” in Graph 1. Next, try
inserting a 300Ω resistor R between the non-inverting
input (pin 2) as shown in Figure 1. This response is
labeled “300Ω ” in Graph 1. Notice an “open” produces a
response with obvious peaking and maximum bandwidth,
a “short” minimizes peaking and bandwidth, and finally
300Ω slightly extends bandwidth with minimal peaking.
Closed Loop Gain Selection
The CLC407 is a current feedback op amp with
Rf = Rg = 250Ω on chip (in the package). Select from
three closed loop gains without using any external gain or
feedback resistors. Implement gains of +2, +1, and
-1V/V by connecting pins 2 and 3 as described in the
chart below.
Gain
Acl
Input Connections
Non-Inverting (pin3)
Inverting (pin2)
-1V/V
+1V/V
+2V/V
ground
input signal
input signal
input signal
NC (open)
ground
The gain accuracy of the CLC407 is excellent and
stable over temperature change. The internal gain
setting resistors, Rf and Rg are diffused silicon resistors
with a process variation of ± 20% and a temperature
coefficient of ˜ 2000ppm/°C. Although their absolute
values change with processing and temperature, their
ratio (Rf/Rg) remains constant. If an external resistor is
used in series with Rg, gain accuracy over temperature
will suffer .
Frequency Response vs.
Unity Gain Configuration
Magnitude (1dB/div)
Open
Non-Inverting Unity Gain Considerations (Av = +1V/V)
Achieve a gain of +1V/V by removing all resistive and
capacitive connections between pin 2 and ground plane.
Any capacitive coupling between pin 2 and ground will
cause high frequency peaking in the frequency domain
response and overshoot in the time domain response.
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300Ω
Short
1
10
Frequency (MHz)
Graph 1
4
100
1
8
2
7
Input - Bias Current, Impedances, and Source
Termination Considerations
The CLC407 has:
• a 6MΩ non-inverting input impedance.
• 100nA non-inverting input bias current.
R
SMA
Input
6
3
Rin
50Ω
4
CLC407
5
Rout
50Ω
SMA
Output
If a large source impedance application is considered,
remove all parasitic capacitance around the non-inverting input and source traces. Parasitic capacitances
near the input and source act as a low-pass filter and
reduce bandwidth.
Figure 1
Enable/Disable Operation Using +5V Supplies
The CLC407 has a TTL & CMOS logic compatible
disable function. Apply a logic low (i.e. < 0.8V) to pin
8, and the CLC407 is guaranteed disabled across its
temperature range. Apply a logic high to pin 8, (i.e. >
2.0V) and the CLC407 is guaranteed enabled. Voltage,
not current, at pin 8 determines the enable/disable
state of the CLC407.
Current feedback op amps have uncorrelated input
bias currents. These uncorrelated bias currents
prevent source impedance matching on each input
from cancelling offsets. Refer to application note
OA-07 of the data book to find specific circuits to
correct DC offsets.
Layout Considerations
Whenever questions about layout arise, USE THE
EVALUATION BOARD AS A TEMPLATE.
Disable the CLC407 and its inputs and output become
high impedances. While disabled, the CLC407’s quiescent power drops to 8mW.
Use the 730013 and 730026 evaluation boards for the
DIP and SOIC respectively. These board layouts were
optimized to produce the typical performance of the
CLC407 shown in the data sheet. To reduce parasitic
capacitances, the ground plane was removed near
pins 2, 3, and 6. To reduce series inductance, trace
lengths of components and nodes were minimized.
Use the CLC407’s disable to create analog switches or
multiplexers. Implement a single analog switch with
one CLC407 positioned between an input and output.
Create an analog multiplexer with several CLC407s.
Tie the outputs together and put a different signal on
each CLC407 input.
Operate the CLC407 without connecting pin 8. An
internal 20kΩ pull-up resistor guarantees the CLC407
is enabled when pin 8 is floating.
Parasitics on traces degrade performance. Minimize
coupling from traces to both power and ground
planes. Use low inductance resistors for leaded
components .
Enable/Disable Operation for Single or
Unbalanced Supply Operation
Supply
Mid-Point
Vcc -Vee
2
20kΩ
Bias
Circuitry
Q2
Do not use dip sockets for the CLC407 DIP amplifiers.
These sockets can peak the frequency domain
response or create overshoot in the time domain
response. Use flush-mount socket pins if socketing
cannot be avoided. The 730013 circuit board device
holes are sized for Cambion P/N 450-2598 socket pins
or their functional equivalent.
Pin 7
+Vcc
20kΩ Pull-up
Resistor
Q1
Pin 8
Disable
Insert the back matching resistor Rout shown in
Figure 3 when driving coaxial cable or a capacitive
load. Use the plot in the typical performance section
labeled “Settling Time vs. Capacitive Load” to determine
the optimum resistor value for Rout for different capacitive loads. This optimal resistance improves settling
time for pulse-type applications and increases stability.
20kΩ
I Tail
Pin 4
-Vee
CLC407
NOTE: Pins 4, 7, 8 are external
Figure 2
Figure 2 illustrates the internal enable/disable
operation of the CLC407. When pin 8 is left floating or
is tied to +Vcc, Q1 is on and pulls tail current through
the CLC407 circuitry. When pin 8 is less than 0.8V
above the supply mid-point, Q1 stops tail current from
flowing in the bias circuitry. The CLC407 is now disabled.
J1 = 0Ω
SMA
Input
1
8
2
7
6
3
Rin
50Ω
4
+5V
C1
C3 +
0.1µfd
6.8µfd
Rout
SMA
Output
50Ω
CLC407
5
-5V
Disable Limitations
The internal feedback resistor, Rf limits off isolation in
inverting gain configurations. Do not apply voltages
greater than +Vcc or less than -Vee to pin 8.
C2
0.1µfd
C4
6.8µfd
+
Figure 3
5
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Use power-supply bypassing capacitors when
operating this amplifier. Choose quality 0.1µF ceramics
for C1 and C2. Choose quality 6.8µF tantalum capacitors
for C3 and C4. Place the 0.1µF capacitors within 0.1
inches from the power pins. Place the 6.8µF capacitors
within 3/4 inches from the power pins.
J1 = 0Ω
SMA
Input
C4
C2
+5V
C1
C3 +
0.1µfd
6.8µfd
Rout
SMA
Output
50Ω
6
4
CLC407
5
Rpd
IEX
-5V
C4
6.8µfd
+
Video Cable Driver
The CLC407 was designed to produce exceptional video
performance at all three closed-loop gains. At the noninverting gain of 2V/V configuration, back terminate the
cable using Rout. A typical cable driving configuration is
shown below in Figure 6.
R4
R2
ROUT
C3
R7
R1
R3
R6
C5
+
7
Figure 5
+
C6
2
C2
0.1µfd
OUT
C1
8
3
Rin
50Ω
Special Evaluation Board
Considerations for the CLC407
To optimize off-isolation of the CLC407, cut the Rf trace on
both the 730013 and the 730027 evaluation boards. This
cut minimizes capacitive feedthrough between the input
and the output. Figure 4 shows where to cut both evaluation boards for improved off-isolation.
1
C8
R8
R5
C7
730013
REV C
-Vcc
GND
RIN
RG
RF
J1 = 0Ω
Comlinear
A National Semiconductor Company
+Vcc
SMA
Input
(303) 226-0500
IN
8
2
7
3
Rin
50Ω
Cut trace here
Cut trace here
1
4
CLC407
6
C1
0.1µfd
Rout
5
50Ω
-5V
407 Fig 3 (Right)
C2
0.1µfd
Figure 4
Video Performance vs. IEX
Improve the video performance of the CLC407 by drawing
extra current from the amplifier’s output stage. Using a
single external resistor as shown in Figure 5, you can
adjust the differential phase. Video performance vs. IEX is
illustrated below in Graph 2. This graph represents
positive video performance with negative synchronization
pulses.
C4
6.8µfd
C3
6.8µfd
+5V
+
Video
Output
Coax
50Ω
50Ω
+
Figure 6
N:1 Mux Cable Driver
The CLC407 is capable of multiplexing several signals on a
single analog output bus. The front page shows how a 2:1
multiplexer is implemented. An N:1 multiplexer is implemented in an analogous fashion by using an N:1 decoder to
enable/disable the appropriate number of CLC407’s.
Differential Gain & Phase vs. IEX
0.25
0.20
0.20
Phase
0.15
0.15
0.10
0.10
0.05
0.05
Differential Phase (deg)
Differential Gain (%)
0.25
Package Thermal Resistance
Package
Plastic (AJP)
Surface Mount (AJE)
CerDip
Gain
qjc
qjA
75˚/W
130˚/W
65˚/W
125˚/W
150˚/W
155˚/W
Ordering Information
0
0
0
2
4
6
8
10
12
14
16
Model
18
IEX in mA
405 G
CLC407AJP
-40˚C to +85˚C
CLC407AJE
-40˚C to +85˚C
CLC407AIB
-40˚C to +85˚C
CLC407ALC
-40˚C to +85˚C
CLC407A8B
-55˚C to +125˚C
CLC407AMC
-55˚C to +125˚C
Contact factory for other packages and
h1
Graph 2
The value for Rpd in Figure 5 is determined by:
Rpd =
5
IEX
at +5V supplies.
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Temperature Range
6
Description
8-pin PDIP
8-pin SOIC
8-pin CerDIP
dice
8-pin CerDIP, MIL-STD-883
dice, MIL-STD-883
DESC SMD number.
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7
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Comlinear CLC407
Low-Cost, Low-Power, Programmable Gain Buffer with Disable
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