Allegro A6B273KA 8-bit latched dmos power driver Datasheet

ADVANCE INFORMATION
8-BIT LATCHED
DMOS POWER DRIVER
(Subject to change without notice)
January 24, 2000
20
LOGIC
SUPPLY
2
19
IN 8
IN 2
3
18
IN 7
OUT 1
4
17
OUT 8
OUT 2
5
16
OUT 7
OUT 3
6
15
OUT 6
OUT 4
7
14
OUT 5
IN 3
8
13
IN 6
IN 4
9
12
IN 5
GROUND
10
11
STROBE
IN 1
VDD
LATCHES
1
LATCHES
CLEAR
Dwg. PP-015-2
Note that the A6B273KA (DIP) and the A6B273KLW
(SOIC) are electrically identical and share a common
terminal number assignment.
ABSOLUTE MAXIMUM RATINGS
at TA = 25°C
Output Voltage, VO ............................... 50 V
Output Drain Current,
Continuous, IO .......................... 150 mA*
Peak, IOM ................................... 500 mA†
Single-Pulse Avalanche Energy,
EAS ................................................. 30 mJ
Logic Supply Voltage, VDD .................. 7.0 V
Input Voltage Range,
VI ................................... -0.3 V to +7.0 V
Package Power Dissipation,
PD ........................................... See Graph
Operating Temperature Range,
TA ................................. -40°C to +125°C
Storage Temperature Range,
TS ................................. -55°C to +150°C
* Each output, all outputs on.
† Pulse duration ≤ 100 µs, duty cycle ≤ 2%.
Caution: These CMOS devices have input static
protection (Class 3) but are still susceptible to damage if
exposed to extremely high static electrical charges.
Data Sheet
26180.122
6B273
The A6B273KA and A6B273KLW combine eight (positive-edgetriggered D-type) data latches and DMOS outputs for systems requiring
relatively high load power. Driver applications include relays, solenoids, and other medium-current or high-voltage peripheral power
loads. The CMOS inputs and latches allow direct interfacing with
microprocessor-based systems. Use with TTL may require appropriate
pull-up resistors to ensure an input logic high.
The DMOS output inverts the DATA input. All of the output
drivers are disabled (the DMOS sink drivers turned OFF) with the
CLEAR input low. The A6B273KA/KLW DMOS open-drain outputs
are capable of sinking up to 500 mA. Similar devices with reduced
rDS(on) are available as the A6273KA/KLW.
The A6B273KA is furnished in a 20-pin dual in-line plastic
package. The A6B273KLW is furnished in a 20-lead wide-body,
small-outline plastic package (SOIC) with gull-wing leads for surfacemount applications. Copper lead frames, reduced supply current
requirements, and low on-state resistance allow both devices to sink
150 mA from all outputs continuously, to ambient temperatures over
85°C.
FEATURES
■ 50 V Minimum Output Clamp Voltage
■ 150 mA Output Current (all outputs simultaneously)
■ 5 Ω Typical rDS(on)
■ Low Power Consumption
■ Replacements for TPIC6B273N and TPIC6B273DW
Always order by complete part number:
Part Number
Package
A6B273KA
20-pin DIP
A6B273KLW
20-lead SOIC
RθJA
55°C/W
70°C/W
RθJC
25°C/W
17°C/W
6B273
8-BIT LATCHED
DMOS POWER DRIVER
ALLOWABLE PACKAGE POWER DISSIPATION IN WATTS
LOGIC SYMBOL
2.5
2.0
SU
FF
IX
1.5
SU
FF
IX
'A
', R
θJ
A =
'LW
', R
θJ
1.0
A
55
°C
/W
=7
0°
C/
W
0.5
0
25
50
75
100
125
AMBIENT TEMPERATURE IN °C
150
1
11
R
2
1D
4
3
1D
5
8
1D
6
9
1D
7
12
1D
14
13
1D
15
18
1D
16
19
1D
17
C1
Dwg. FP-046-1
Dwg. GS-004A
VDD
OUT
IN
Dwg. EP-010-16
Dwg. EP-063
LOGIC INPUTS
DMOS POWER DRIVER OUTPUT
FUNCTION TABLE
CLEAR
L
H
H
H
Inputs
STROBE
X
L
INX
OUTX
X
H
L
X
H
L
H
R
L = Low Logic Level
H = High Logic Level
X = Irrelevant
R = Previous State
115 Northeast Cutoff, Box 15036
Worcester,
Massachusetts 01615-0036 (508) 853-5000
W
Copyright © 2000, Allegro MicroSystems, Inc.
6B273
8-BIT LATCHED
DMOS POWER DRIVER
FUNCTIONAL BLOCK DIAGRAM
IN 1
D
OUT 1
C1
STROBE
CLR
IN2
LOGIC
SUPPLY
IN 3
D
OUT 2
C1
V DD
CLR
D
OUT 3
C1
CLR
IN 4
D
OUT 4
C1
CLR
IN5
D
OUT 5
C1
CLR
IN6
D
OUT 6
C1
CLR
IN 7
D
OUT 7
C1
CLR
IN8
D
OUT 8
C1
CLEAR
CLR
GROUND
(ACTIVE LOW)
Dwg. FP-016-2
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6B273
8-BIT LATCHED
DMOS POWER DRIVER
RECOMMENDED OPERATING CONDITIONS
over operating temperature range
Logic Supply Voltage Range, VDD ............... 4.5 V to 5.5 V
High-Level Input Voltage, VIH ............................ ≥ 0.85VDD
Low-level input voltage, VIL ................................. ≤0.15VDD
ELECTRICAL CHARACTERISTICS at TA = +25°C, VDD = 5 V, tir = tif ≤ 10 ns (unless otherwise
specified).
Limits
Characteristic
Logic Supply Voltage
Output Breakdown
Voltage
Off-State Output
Current
Static Drain-Source
On-State Resistance
Symbol
Test Conditions
Min.
Typ.
Max.
Units
VDD
Operating
4.5
5.0
5.5
V
V(BR)DSX
IO = 1 mA
50
—
—
V
VO = 40 V, VDD = 5.5 V
—
0.1
5.0
µA
VO = 40 V, VDD = 5.5 V, TA = 125°C
—
0.15
8.0
µA
IO = 100 mA, VDD = 4.5 V
—
4.2
5.7
Ω
IO = 100 mA, VDD = 4.5 V, TA = 125°C
—
6.8
9.5
Ω
IO = 350 mA, VDD = 4.5 V (see note)
—
5.5
8.0
Ω
IDSX
rDS(on)
Nominal Output
Current
ION
VDS(on) = 0.5 V, TA = 85°C
—
90
—
mA
Logic Input Current
IIH
VI = VDD = 5.5 V
—
—
1.0
µA
IIL
VI = 0, VDD = 5.5 V
—
—
-1.0
µA
tPLH
IO = 100 mA, CL = 30 pF
—
150
—
ns
tPHL
IO = 100 mA, CL = 30 pF
—
90
—
ns
Output Rise Time
tr
IO = 100 mA, CL = 30 pF
—
200
—
ns
Output Fall Time
tf
IO = 100 mA, CL = 30 pF
—
200
—
ns
IDD(OFF)
VDD = 5.5 V, Outputs off
—
20
100
µA
IDD(ON)
VDD = 5.5 V, Outputs on
—
150
300
µA
Prop. Delay Time
Supply Current
Typical Data is at VDD = 5 V and is for design information only.
NOTE — Pulse test, duration ≤100 µs, duty cycle ≤2%.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
6B273
8-BIT LATCHED
DMOS POWER DRIVER
TIMING REQUIREMENTS
INx
50%
t su(D)
STROBE
50%
t h(D)
t su(D)
t h(D)
50%
t PLH
t PHL
90%
OUTPUTx
10%
tr
tf
Dwg. WP-036-1
Input Active Time Before Strobe
(Data Set-Up Time), tsu(D) .............................................. 20 ns
Input Active Time After Strobe
(Data Hold Time), th(D) ................................................... 20 ns
Input Pulse Width, tw(D) ....................................................... 40 ns
Input Logic High, VIH ................................................ ≥ 0.85VCC
Input Logic Low, VIL ................................................. ≤ 0.15VCC
www.allegromicro.com
6B273
8-BIT LATCHED
DMOS POWER DRIVER
TEST CIRCUITS
+15 V
10.5 Ω
INPUT
200 mH
tav
IAS = 500 mA
IO
DUT
OUT
VO
V(BR)DSX
VO(ON)
Dwg. EP-066
EAS = IAS x V(BR)DSX x tAV/2
Single-Pulse Avalanche Energy Test Circuit
and Waveforms
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
6B273
8-BIT LATCHED
DMOS POWER DRIVER
TYPICAL CHARACTERISTICS
www.allegromicro.com
6B273
8-BIT LATCHED
DMOS POWER DRIVER
TYPICAL CHARACTERISTICS
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
6B273
8-BIT LATCHED
DMOS POWER DRIVER
TERMINAL DESCRIPTIONS
Terminal No.
Terminal Name
1
CLEAR
When (active) LOW, all latches are reset and all outputs go HIGH (turn OFF).
2
IN1
CMOS data input to a latch. When strobed, the output then inverts the data
input (IN1 = HIGH, OUT1 = LOW).
3
IN2
CMOS data input to a latch. When strobed, the output then inverts the data
input (IN2 = HIGH, OUT2 = LOW).
4
OUT1
Current-sinking, open-drain DMOS output.
5
OUT2
Current-sinking, open-drain DMOS output.
6
OUT3
Current-sinking, open-drain DMOS output.
7
OUT4
Current-sinking, open-drain DMOS output.
8
IN3
CMOS data input to a latch. When strobed, the output then inverts the data
input (IN3 = HIGH, OUT3 = LOW).
9
IN4
CMOS data input to a latch. When strobed, the output then inverts the data
input (IN4 = HIGH, OUT4 = LOW).
10
GROUND
Reference terminal for all voltage measurements.
11
STROBE
A CMOS dynamic input to all latches. Data on each INx terminal is loaded
into its associated latch on a low-to-high STROBE transition.
12
IN5
CMOS data input to a latch. When strobed, the output then inverts the data
input (IN5 = HIGH, OUT5 = LOW).
13
IN6
CMOS data input to a latch. When strobed, the output then inverts the data
input (IN6 = HIGH, OUT6 = LOW).
14
OUT5
Current-sinking, open-drain DMOS output.
15
OUT6
Current-sinking, open-drain DMOS output.
16
OUT7
Current-sinking, open-drain DMOS output.
17
OUT8
Current-sinking, open-drain DMOS output.
18
IN7
CMOS data input to a latch. When strobed, the output then inverts the data
input (IN7 = HIGH, OUT7 = LOW).
19
IN8
CMOS data input to a latch. When strobed, the output then inverts the data
input (IN8 = HIGH, OUT8 = LOW).
20
LOGIC SUPPLY
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Function
(VDD) The logic supply voltage (typically 5 V).
6B273
8-BIT LATCHED
DMOS POWER DRIVER
A6B273KA
Dimensions in Inches
(controlling dimensions)
0.014
0.008
11
20
0.430
MAX
0.280
0.240
0.300
BSC
1
0.070
0.045
0.100
1.060
0.980
10
0.005
BSC
MIN
0.210
MAX
0.150
0.115
0.015
MIN
0.022
0.014
Dwg. MA-001-20 in
Dimensions in Millimeters
(for reference only)
20
0.355
0.204
11
10.92
MAX
7.11
6.10
7.62
BSC
1
1.77
1.15
2.54
26.92
24.89
BSC
10
0.13
MIN
5.33
MAX
0.39
3.81
2.93
MIN
0.558
0.356
Dwg. MA-001-20 mm
NOTES: 1. Exact body and lead configuration at vendor’s option within limits shown.
2. Lead spacing tolerance is non-cumulative.
3. Lead thickness is measured at seating plane or below.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
6B273
8-BIT LATCHED
DMOS POWER DRIVER
A6B273KLW
Dimensions in Inches
(for reference only)
20
11
0.0125
0.0091
0.419
0.394
0.2992
0.2914
0.050
0.016
0.020
0.013
1
2
0.050
3
0° TO 8°
BSC
0.5118
0.4961
0.0926
0.1043
0.0040 MIN.
Dwg. MA-008-20 in
Dimensions in Millimeters
(controlling dimensions)
20
11
0.32
0.23
10.65
10.00
7.60
7.40
1.27
0.40
0.51
0.33
1
2
1.27
3
13.00
12.60
BSC
0° TO 8°
2.65
2.35
0.10 MIN.
NOTES: 1. Exact body and lead configuration at vendor’s option within limits shown.
2. Lead spacing tolerance is non-cumulative.
www.allegromicro.com
Dwg. MA-008-20 mm
6B273
8-BIT LATCHED
DMOS POWER DRIVER
The products described here are manufactured under one or more
U.S. patents or U.S. patents pending.
Allegro MicroSystems, Inc. reserves the right to make, from time to
time, such departures from the detail specifications as may be
required to permit improvements in the performance, reliability, or
manufacturability of its products. Before placing an order, the user is
cautioned to verify that the information being relied upon is current.
Allegro products are not authorized for use as critical components
in life-support devices or systems without express written approval.
The information included herein is believed to be accurate and
reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use; nor for any infringement of patents or other rights of
third parties which may result from its use.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000