PD-60330 IR3820AMPbF SupIRBuck TM HIGHLY INTEGRATED 14A WIDE-INPUT VOLTAGE, SYNCHRONOUS BUCK REGULATOR Features • • • • • • • • • • • • • • Wide Input Voltage Range 2.5V to 21V Wide Output Voltage Range 0.6V to 12V Continuous 14A Load Capability 300kHz High Frequency Operation Programmable Over-Current Protection Programmable PGood Output Hiccup Current Limit Precision Reference Voltage (0.6V) Programmable Soft-Start Pre-Bias Start-up Thermal Protection Thermally Enhanced Package Small Size 5mmx6mm QFN Pb-Free (RoHS Compliant) Applications • • • • • • • • Distributed Point-of-Loads Server and Workstations Embedded Systems Storage Systems DDR Applications Graphics Cards Game Consoles Computing Peripheral Voltage Regulators Description The IR3820A SupIRBuckTM is an easy-to-use, fully integrated and highly efficient DC/DC regulator. The onboard switching controller and MOSFETs make the IR3820A a space-efficient solution, providing accurate power delivery for low output voltage applications. The IR3820A operates from a single 4.5V to 14V input supply and generates an output voltage adjustable from 0.6V to 0.8*Vin at loads up to 14A. A versatile regulator offering programmability of startup time, power good threshold and current limit, the IR3820A’s fixed 300kHz switching frequency allows the use of small external components. The IR3820A also features important protection functions, such as Pre-Bias startup, hiccup current limit and thermal shutdown to provide the required system level security in the event of fault conditions. Fig. 1. Typical application diagram 01/08/08 1 PD-60330 IR3820AMPbF ABSOLUTE MAXIMUM RATINGS (Voltages referenced to GND) • VIN Supply Voltage -0.3V to 24V • Vcc Supply Voltage -0.3V to 16V • Vc Supply Voltage -0.3V to 30V • SW -0.3V to 30V • PGood -0.3V to 16V • Fb,COMP,SS,Vsns -0.3V to 3.5V • OCSet 10mA • AGnd to PGnd -0.3V to +0.3V • Storage Temperature Range -65°C To 150°C • Operating Junction Temperature Range -40°C To 150°C • ESD Classification JEDEC, JESD22-A114 • Moisture Sensitivity Level JEDEC Level 3 @ 260oC Caution: Stresses beyond those listed under “Absolute Maximum Rating” may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to “Absolute Maximum Rating” conditions for extended periods may affect device reliability. PACKAGE INFORMATION 5mm x 6mm POWER QFN 10 12 11 VIN SW PGnd θJA = 35 o C / W θJ -PCB = 2 o C / W HG 13 VC 14 1 Vsns 15 AGnd 2 3 4 5 6 9 PGood 8 VCC 7 FB COMP AGnd AGnd SS OCSet Fig. 2: Package outline (Top view) ORDERING INFORMATION 01/08/08 PKG DESIG PACKAGE DESCRIPTION PIN COUNT PARTS PER TUBE PARTS PER REEL M IR3820AMTRPbF 15 --------------- 4000 2 PD-60330 IR3820AMPbF Block Diagram Fig. 3. Simplified block diagram of the IR3820A. 01/08/08 3 PD-60330 IR3820AMPbF Pin Description Pin Name Description 1 Vsns PGood sense pin. Use two external resistors to program the power good threshold. 2 Fb 3 Comp Inverting input to the error amplifier. This pin is connected directly to the output of the regulator via resistor divider to set the output voltage and provide feedback to the error amplifier. Output of error amplifier. 4 AGnd Signal ground for internal reference and control circuitry. 5 AGnd Signal ground for internal reference and control circuitry. 6 SS/SD 7 OCSet Soft start / shutdown. This pin provides user programmable soft-start function. Connect an external capacitor from this pin to signal ground (AGnd) to set the start up time of the output voltage. The converter can be shutdown by pulling this pin below 0.3V. Current limit set point. A resistor from this pin to SW pin will set the current limit threshold. 8 VCC 9 PGood 10 PGnd 11 SW Switch node. This pin is connected to the output inductor 12 VIN Input voltage connection pin 13 HG 14 VC 15 AGnd This pin is connected to the high side Mosfet gate. Connect a small capacitor from this pin to switch node (SW). This pin powers the high side driver and must be connected to a voltage higher than input voltage. A minimum of 0.1uF high frequency capacitor must be connected from this pin to the power ground (PGnd). Signal ground for internal reference and control circuitry. This pin provides biasing voltage for the internal blocks of the IC. It also powers the low side driver. A minimum of 0.1uF, high frequency capacitor must be connected from this pin to power ground (PGnd). Power Good status pin. Output is open collector. Connect a pull up resistor from this pin to Vcc. Power Ground. This pin serves as a separated ground for the MOSFET drivers and should be connected to the system’s power ground plane. Pins 4, 5 and 15 need to be connected together on system board. 01/08/08 4 PD-60330 IR3820AMPbF Recommended Operating Conditions Symbol Vin Vcc Vc Vo Io Note1 Tj Definition Input Voltage Supply Voltage Supply Voltage Output Voltage Output Current Junction Temperature Min Max 2.5 4.5 Vin + 5V 0.6 0 -40 21 14 28 12 14 125 Units V A C o Electrical Specifications Unless otherwise specified, these specification apply over Vin=Vcc=Vc=12V, 0oC<Tj(Ic)<105oC. Typical values are specified at Ta = 25oC. Parameter Symbol Test Condition Min TYP MAX Units Power Loss Power Loss Ploss Vcc=Vin=12V, Vc=24V, Vo=1.8V, Io=14A, L=1.0uH, Note3 3.7 W MOSFET Rds(on) o 6.9 8.7 o 6.9 8.7 Top Switch Rds(on)_Top ID=13A, Tj(MOSFET)=25 C Bottom Switch Rds(on)_Bot ID=13A, Tj(MOSFET)=25 C mΩ Reference Voltage Feedback Voltage VFB 0.6 o Accuracy o 0 C<Tj<105 C o o -40 C<Tj<105 C, Note2 V -1.35 +1.35 % -1.5 +1.5 % Supply Current VCC Supply Current (Static) ICC(Static) SS=0V, No Switching 10 13 VC Supply Current (Static) VCC Supply Current (Dynamic) VC Supply Current (Dynamic) IC(Static) SS=0V, No Switching 4.5 7 SS=3V, Vc=24V, Vcc=Vin=12V. Vo=1.8V, Io=0A SS=3V, Vc=24V, Vcc=Vin=12V. Vo=1.8V, Io=0A 15 22 15 22 ICC(Dynamic) IC(Dynamic) mA Under Voltage Lockout VCC-Start-Threshold VCC_UVLO(R) Supply ramping up 4.0 4.4 VCC-Stop-Threshold VCC_UVLO(F) Supply ramping down 3.7 4.1 Supply ramping up and down 0.15 VCC-Hysteresis 0.25 0.3 VC-Start-Threshold VC_UVLO(R) Supply ramping up 3.1 3.5 VC-Stop-Threshold VC_UVLO(F) Supply ramping down 2.85 3.25 Supply ramping up and down 0.15 VC-Hysteresis 01/08/08 0.2 V 0.25 5 PD-60330 IR3820AMPbF Parameter SYM Test Condition Min TYP MAX Units 270 300 330 kHz Oscillator Frequency FS Ramp Amplitude Vramp Note3 1.25 V Min Pulse Width Dmin(ctrl) Note3 80 ns Max Duty Cycle Dmax Fb=0V Input Bias Current IFB1 SS=3V Input Bias Current IFB2 SS=0V Source/Sink Current Transconductance 80 % Error Amplifier -0.1 -0.5 20 35 50 I(source/Sink) 50 70 90 gm 1000 1300 1600 μmho 15 20 28 μA 0.25 V μA Soft Start/SD Soft Start Current ISS Shutdown Output Threshold SD SS=0V Power Good Vsns Low Trip Point Vsns(trip) Hysteresis PGood(Hys) PGood Output Low Voltage PG(voltage) Input Bias Current Isns Vsns Ramping Down 0.35 0.38 0.41 V 15 27.5 40 mV 0.25 0.5 V 0 0.3 1 μA 15 20 26 IPGood=4mA Over Current Protection OCSET Current IOCSET Hiccup Current IHiccup Hiccup Duty Cycle Hiccup(duty) Note3 IHiccup / ISS , Note3 3 15 μA % Thermal Shutdown Thermal Shutdown Threshold Thermal Shutdown Hysteresis 140 Note3 Note3 o 20 C Note1: Continuous output current determined by input and output voltage setting and the thermal environment. Note2: Cold temperature performance is guaranteed via correlation using statistical quality control. Not tested in production. Note3: Guaranteed by Design but not tested in production. 01/08/08 6 PD-60330 IR3820AMPbF TYPICAL OPERATING CHARACTERISTICS (-40oC - 125oC) Icc(static) Ic(static) 13.0 7.0 12.0 6.0 [mA] [mA] 11.0 10.0 9.0 4.0 3.0 8.0 7.0 -40 5.0 -20 0 20 40 60 80 100 2.0 -40 120 -20 0 20 Tem p[oC] [mA] [mA] -20 0 20 60 80 100 120 80 100 120 80 100 120 80 100 120 Ic(dynamic) Icc(dynam ic) 22.0 21.0 20.0 19.0 18.0 17.0 16.0 15.0 14.0 13.0 -40 40 Tem p[oC] 40 60 80 100 120 22.0 21.0 20.0 19.0 18.0 17.0 16.0 15.0 14.0 13.0 -40 -20 0 20 Tem p[oC] 40 60 Temp[oC] Vfb ISS 27.0 605.0 25.0 23.0 [uA] [mV] 600.0 595.0 21.0 19.0 590.0 585.0 -40 17.0 -20 0 20 40 60 80 100 15.0 -40 120 -20 0 20 Tem p[oC] [mmho] [uA] -20 0 20 40 60 Tem p[oC] 01/08/08 60 IOCSET Transconductance 1.60 1.55 1.50 1.45 1.40 1.35 1.30 1.25 1.20 1.15 1.10 1.05 1.00 -40 40 Tem p[oC] 80 100 120 26.0 25.0 24.0 23.0 22.0 21.0 20.0 19.0 18.0 17.0 16.0 15.0 -40 -20 0 20 40 60 Temp[oC] 7 PD-60330 IR3820AMPbF Circuit Description THEORY OF OPERATION The IR3820A is a voltage mode PWM synchronous regulator and operates with a fixed 300kHz switching frequency, allowing the use of small external components. The output voltage is set by feedback pin (Fb) and the internal reference voltage (0.6V). These are two inputs to error amplifier. The error signal between these two inputs is amplified and it is compared to a fixed frequency linear sawtooth ramp. A trailing edge modulation is used for generating fixed frequency pulses (PWM) which drives the internal N-channel MOSFETs. The internal oscillator circuit uses on-chip circuitry, eliminating the need for external components. The IR3820A operates with single input voltage from 4.5V to 14V allowing an extended operating input voltage range. Pre-Bias Startup The IR3820A is able to start up into pre-charged output, which prevents oscillation and disturbances of the output voltage. The output starts in asynchronous fashion and keeps the synchronous MOSFET off until the first gate signal for control MOSFET is generated. Figure 4 shows a typical Pre-Bias condition at start up. Depending on system configuration, a specific amount of output capacitors may be required to prevent discharging the output voltage. Vo V Pre-Bias Voltage The over-current protection is performed by sensing current through the RDS(on) of low side MOSFET. This method enhances the converter’s efficiency and reduces cost by eliminating a current sense resistor. The current limit is programmable by using an external resistor. Time Fig. 4: Pre-Bias start up Under-Voltage Lockout The under-voltage lockout circuit monitors the two input supplies (Vcc and Vc) and assures that the MOSFET driver outputs remain in the off state whenever the supply voltage drops below set thresholds. Lockout occurs if Vcc or Vc fall below 4.3V and 3.3V respectively. Normal operation resumes once Vcc and Vc rise above the set values. Thermal Shutdown Temperature sensing is provided inside the IR3820A. The trip threshold is typically set to 140oC. When trip threshold is exceeded, thermal shutdown turns off both MOSFETs. Thermal shutdown is not latched and automatic restart is initiated when the sensed temperature drops within the operating range. There is a 20oC hysteresis in the thermal shutdown threshold. 01/08/08 Shutdown The output can be shutdown by pulling the softstart pin below 0.3V. This can easily be done by using an external small signal transistor. During shutdown both MOSFET drivers will be turned off. Normal operation will resume by cycling soft start pin. Power Good The IR3820A provides an open collector power good signal which reports the status of the output. The output is sensed through the dedicated Vsns pin. The power good threshold can be externally programmed using two external resistors. The power good comparator is internally set to 0.38V (typical). 8 PD-60330 IR3820AMPbF Soft-Start The IR3820A has programmable soft-start to control the output voltage rise and limit the inrush current during start-up. To ensure correct start-up, the soft-start sequence initiates when Vcc and Vc rise above their threshold and generate the Power On Ready (POR) signal. The soft-start function operates by sourcing current to charge an external capacitor to about 3V. Initially, the soft-start function clamps the output of error amplifier by injecting a current (40uA) into the Fb pin and generates a voltage about 0.96V (40ux24K) across the negative input of error amplifier (see figure 5). The magnitude of the injected current is inversely proportional to the voltage at the soft-start pin. As the soft-start voltage ramps up, the injected current decreases linearly and so does the voltage at negative input of error amplifier. When the soft-start capacitor is around 1V, the voltage at the positive input of the error amplifier is approximately 0.6V. The output of error amplifier will start increasing and generating the first PWM signal. As the softstart capacitor voltage continues to rise up, the current flowing into the Fb pin will keep decreasing. The feedback voltage increases linearly as the soft start voltage ramps up. When soft-start voltage is around 2V, the output voltage reaches the steady state and the injected current is zero. Figure 6 shows the theoretical waveforms during soft-start. operating The output voltage start-up time is the time period when soft-start capacitor voltage increases from 1V to 2V. The start-up time will be dependent on the size of the external soft-start capacitor and can be estimated by: 20μA ∗ 3V 20uA SS/SD 40uA POR Comp 24K 0.6V Error Amp 24K Fb Fig. 5: Soft-Start circuit for IR3820A Output of UVLO POR 3V ≅2V ≅1V Soft-Start Voltage Current flowing into Fb pin 0V 40uA 0uA Voltage at negative input ≅0.96V of Error Amp 0.6V 0.6V Voltage at Fb pin 0V Fig. 6: Theoretical operation waveforms during soft-start Tstart = 2V −1V Css For a given start-up time, the soft-start capacitor can be estimated as: CSS ≅ 20μA * Tstart (ms) 01/08/08 --(1) 9 PD-60330 IR3820AMPbF Over-Current Protection The over-current protection is performed by sensing current through the RDS(on) of the low side MOSFET. This method enhances the converter’s efficiency and reduces cost by eliminating a current sense resistor. As shown in figure 7, an external resistor (RSET) is connected between OCSet pin and the inductor point which sets the current limit set point. The internal current source develops a voltage across RSET. When the low side MOSFET is turned on, the inductor current flows through the Q2 and results a voltage which is given by: VOCSet = (IOCSet ∗ ROCSet ) − (RDS(on) ∗ IL ) --( 2 ) Fig. 8: 3uA current source for discharging soft-start capacitor during hiccup The OCP circuit starts sampling current when the low gate drive is about 3V. The OCSet pin is internally clamped about 1.5V during on time of high side gate to prevent false trigging, figure 9 shows the OCSet pin during one switching cycle. As shown, there is about 150ns delay to mask the dead time. Since this node contains switching noises, this delay also functions as a filter. Deadtime IOCSet*ROCSet Blanking time Clamp voltage Fig. 7: Connection of over current sensing resistor The critical inductor current can be calculated by setting: VOCSet = (IOCSet ∗ ROCSet ) − (RDS(on) ∗ IL ) = 0 I SET = I L ( critical ) R ∗I = OCSet OCSet R DS ( on ) --( 3 ) An over-current is detected if the OCSet pin goes below ground. This trips the OCP comparator and cycles the soft start function in hiccup mode. The hiccup is performed by charging and discharging the soft-start capacitor in a certain slope rate. As shown in figure 8 a 3uA current source is used to discharge the soft-start capacitor. Fig. 9: OCset pin during normal condition Ch1: Inductor point, Ch3:OCSet The value of RSET should be checked in an actual circuit to ensure that the over-current protection circuit activates as expected. The IR3820A current limit is designed primarily as disaster preventing, and doesn't operate as a precision current regulator. The OCP comparator resets after every soft start cycle. The converter stays in this mode until the overload or short circuit is removed. The converter will automatically recover. 01/08/08 10 PD-60330 IR3820AMPbF Application Information Design Example: The following example is a typical application for the IR3820A. The application circuit is shown in page 17. Soft-Start Programming The soft-start timing can be programmed by selecting the soft-start capacitance value. The start-up time of the converter can be calculated by using: CSS ≅ 20μA * Tstart --(1) Where Tstart is the desired start-up time (ms) For a start-up time of 11ms, the soft-start capacitor will be 0.22uF. Vin = 12 V,( 13 .2V, max ) Vo = 1.8V Vc supply for single input voltage I o = 14 A ΔV o ≤ 30 mV Fs = 300 kHz Output Voltage Programming Output voltage is programmed by reference voltage and external voltage divider. The Fb pin is the inverting input of the error amplifier, which is internally referenced to 0.6V. The divider is ratioed to provide 0.6V at the Fb pin when the output is at its desired value. The output voltage is defined by using the following equation: ⎛ R ⎞ Vo = Vref ∗ ⎜⎜1 + 8 ⎟⎟ R9 ⎠ ⎝ VC ≅ 2 ∗Vbus − (VD1 + VD2 ) --( 4 ) When an external resistor divider is connected to the output as shown in figure 10. VOUT IR3624 IR3820A To drive the high-side switch, it is necessary to supply a gate voltage at least 4V greater than the bus voltage. This is achieved by using a charge pump configuration as shown in figure 11. This method is simple and inexpensive. The operation of the circuit is as follows: when the lower MOSFET is turned on, the capacitor (C1) is pulled down to ground and charges, up to VBUS value, through the diode (D1). The bus voltage will be added to this voltage when upper MOSFET turns on in next cycle, and providing supply voltage (Vc) through diode (D2). Vc is approximately: R8 Fb --(6 ) Capacitors in the range of 0.1uF are generally adequate for most applications. The diodes must be a fast recovery device to minimize the amount of charge fed back from the charge pump capacitor into VBUS. The diodes need to be able to block the full power rail voltage, which is seen when the high-side MOSFET is switched on. For low-voltage application, schottky diodes can be used to minimize forward drop across the diodes at start up. R9 Fig. 10: Typical application of the IR3820A for programming the output voltage Equation (4) can be rewritten as: ⎛ V R9 = R8 ∗ ⎜⎜ ref ⎝ V O−Vref ⎞ ⎟⎟ ⎠ --( 5 ) For the calculated values of R8 and R9 see feedback compensation section. 01/08/08 Fig. 11: Charge pump circuit to generate Vc voltage 11 PD-60330 IR3820AMPbF Input Capacitor Selection The input filter capacitor should be selected based on how much ripple the supply can tolerate on the DC input line. The ripple current generated during the on time of upper MOSFET should be provided by the input capacitor. The RMS value of this ripple is expressed by: IRMS = Io ∗ D ∗ (1 − D ) --(7 ) V D= o Vin Where: D is the Duty Cycle IRMS is the RMS value of the input capacitor current. Io is the output current. If Δi ≈ 40%(Io ) , then the output inductor will be: L = 1.0uH Delta MPL-104 series provides a range of inductors in different values and low profile suitable for large currents. Output Capacitor Selection The voltage ripple and transient requirements determine the output capacitors’ type and values. The criteria is normally based on the value of the Effective Series Resistance (ESR). However the actual capacitance value and the Equivalent Series Inductance (ESL) are other contributing components. These components can be described as: For Io=14A and D=0.15, the IRMS=5A. ΔVo = ΔVo(ESR) + ΔVo(ESL) + ΔVo(C ) Ceramic capacitors are recommended due to their peak current capabilities. They also feature low ESR and ESL at higher frequency which enables better efficiency. ΔVo(ESR) = ΔIL * ESR Use 3x10uF, 16V ceramic capacitors. ⎛Vin ⎞ ⎟ * ESL ⎝L⎠ ΔVo(ESL) = ⎜ Inductor Selection The inductor is selected based on output power, operating frequency and efficiency requirements. A low inductor value causes a large ripple current, resulting in the smaller size, faster response to a load transient but poor efficiency and high output noise. Generally, the selection of the inductor value can be reduced to the desired maximum ripple current in the inductor ( Δi ) . The optimum point is usually found between 20% and 50% ripple of the output current. For the buck converter, the inductor value for the desired operating ripple current can be determined using the following: Vin − Vo = L ∗ Δi 1 ; Δt = D ∗ Fs Δt Vo L = (Vin − Vo ) ∗ V ∗ Δi * Fs in Where: Vin = Maximum input voltage Vo = Output Voltage Δi = Inductor ripple current F s= Switching frequency Δt = Turn on time D = Duty cycle 01/08/08 --(8 ) - -(9) ΔVo(C ) = ΔIL 8 * Co * Fs ΔVo = Output voltage ripple ΔIL = Inductor ripple current Since the output capacitor has a major role in the overall performance of the converter and determine the result of transient response, selection of the capacitor is critical. The IR3820A can perform well with all types of capacitors. As a rule the capacitor must have low enough ESR to meet output ripple and load transient requirements, yet have high enough ESR to satisfy stability requirements. The goal for this design is to meet the voltage ripple requirement in the smallest possible capacitor size. Therefore, a ceramic capacitor is selected due to its low ESR and small size. Six of the Panasonic ECJ2FB0J226M (22uF, 6.3V, X5R and EIA 0805 case size) are a good choice. In the case of tantalum or low ESR electrolytic capacitors, the ESR dominates the output voltage ripple, equation (9) can be used to calculate the required ESR for the specific voltage ripple. 12 PD-60330 IR3820AMPbF Feedback Compensation The IR3820A is a voltage mode controller; the control loop is a single voltage feedback path including error amplifier and error comparator. To achieve fast transient response and accurate output regulation, a compensation circuit is necessary. The goal of the compensation network is to provide a closed loop transfer function with the highest 0dB crossing frequency and adequate phase margin (greater than 45o). The output LC filter introduces a double pole, – 40dB/decade gain slope above its corner resonant frequency, and a total phase lag of 180o (see figure 13). The resonant frequency of the LC filter expressed as follows: FLC = The ESR zero of the output capacitor expressed as follows: 1 FESR = - - - (12) 2 ∗ π * ESR * Co VOUT R8 Fb E/A R9 Gain VREF R3 H(s) dB Frequency Fig. 14: TypeII compensation network and its asymptotic gain plot The transfer function (Ve/Vo) is given by: H( s ) = gm * 0 0dB CPOLE Gain(dB) FZ Phase Ve C4 1 - - - (11) 2 π Lo Co Figure 13 shows gain and phase of the LC filter. Since we already have 180o phase shift from the output filter alone, the system risks being unstable. Comp R9 1 + sR3C4 * - - - (13) R9 + R8 sC4 -40dB/decade The (s) indicates that the transfer function varies as a function of frequency. This configuration introduces a gain and zero, expressed by: FLC Frequency -180 FLC Frequency [H(s)] = ⎛⎜⎜ g ⎝ Fig. 13: Gain and Phase of LC filter Fz = The IR3820A’s error amplifier is a differentialinput transconductance amplifier. The output is available for DC gain control or AC phase compensation. The error amplifier can be compensated either in type II or type III compensation. When it is used in type II compensation the transconductance properties of the error amplifier become evident and can be used to cancel one of the output filter poles. This will be accomplished with a series RC circuit from Comp pin to ground as shown in figure 14. This method requires that the output capacitor should have enough ESR to satisfy stability requirements. In general the output capacitor’s ESR generates a zero typically at 5kHz to 50kHz which is essential for an acceptable phase margin. 01/08/08 m * R9 ⎞ ⎟ * R3 - - - (14) R9 + R8 ⎟⎠ 1 2π * R3 * C4 - - - (15) The gain is determined by the voltage divider and error amplifier’s transconductance gain. First select the desired zero-crossover frequency (Fo): Fo > FESR and Fo ≤ (1/5 ~ 1/10) * Fs Use the following equation to calculate R3: R3 = Vosc * Fo * FESR * ( R8 + R9 ) Vin * FLC2 * R9 * gm - - - (16) Where: Vin = Maximum Input Voltage Vosc = Oscillator Ramp Voltage Fo = Crossover Frequency FESR = Zero Frequency of the Output Capacitor FLC = Resonant Frequency of the Output Filter R8 and R9 = Feedback Resistor Dividers gm = Error Amplifier Transconductance 13 PD-60330 IR3820AMPbF To cancel one of the LC filter poles, place the zero before the LC filter resonant frequency pole: VOUT ZIN Fz = 75%FLC C7 1 Fz = 0.75 * 2π Lo * Co - - - (17) Use equations (15) and (16) to calculate C4. One more capacitor is sometimes added in parallel with C4 and R3. This introduces one more pole which is mainly used to suppress the switching noise. The additional pole is given by: 1 FP = C *C 2π * R3 * 4 POLE C4 + CPOLE 1 1 = ≅ 1 π * R 3 * Fs π * R3 * Fs − C4 For FP << Fs 2 For a general solution for unconditional stability for any type of output capacitors, in a wide range of ESR values we should implement local feedback with a compensation network (type III). The typically used compensation network for voltage-mode controller is shown in figure 15. In such a configuration, the transfer function is given by: Ve 1 − g m Zf = Vo 1 + g m ZIN The error amplifier gain is independent of the transconductance under the following condition: g m * Zf >> 1 and g m * Zin >> 1 - - - (18) By replacing Zin and Zf according to figure 15, the transformer function can be expressed as: H (s ) = (1 + sR3C4 ) * [1 + sC7 (R8 + R10 )] 1 * sR8 (C4 + C3 ) ⎡ ⎛ C4 * C3 ⎞⎤ ⎟⎟⎥ * (1 + sR10C7 ) ⎢1 + sR3 ⎜⎜ ⎝ C4 + C3 ⎠⎦ ⎣ 01/08/08 R3 R10 C4 R8 Zf Fb R9 E/A Comp Ve VREF Gain(dB) H(s) dB FZ1 The pole sets to one half of switching frequency which results in the capacitor CPOLE: CPOLE C3 FZ2 FP2 FP3 Frequency Fig.15: Compensation network with local feedback and its asymptotic gain plot As known, the transconductance amplifier has high impedance (current source) output, therefore, consideration should be taken when loading the error amplifier output. It may exceed its source/sink output current capability, so that the amplifier will not be able to swing its output voltage over the necessary range. The compensation network has three poles and two zeros and they are expressed as follows: FP1 = 0 FP 2 = FP 3 = 1 2π * R10 * C7 1 1 ≅ ⎛ C * C3 ⎞ 2π * R3 * C3 ⎟⎟ 2π * R3 ⎜⎜ 4 ⎝ C4 + C3 ⎠ Fz1 = 1 2π * R3 * C4 Fz 2 = 1 1 ≅ 2π * C7 * (R8 + R10 ) 2π * C7 * R8 Cross over frequency is expressed as: Fo = R3 * C7 * Vin 1 * Vosc 2π * Lo * Co 14 PD-60330 IR3820AMPbF Based on the frequency of the zero generated by the output capacitor and its ESR versus crossover frequency, the compensation type can be different. The table below shows the compensation types and location of crossover frequency. Output capacitor Compensator type FESR vs. Fo Type II(PI) FLC<FESR<Fo<Fs/2 Electrolytic , Tantalum Type III (PID) Method A FLC<Fo<FESR<Fs/2 Tantalum, ceramic Type III(PID) Method B FLC<Fo<Fs/2<FESR Ceramic The DC gain will be large enough to provide high DC-regulation accuracy (typically -5dB to -12dB). The phase margin should be greater than 45o for overall stability. Desired Phase Boost: Θmax = 70 o 1 - SinΘ 1 + SinΘ FZ 2 = 10.58kHz FZ 2 = Fo * 1 + SinΘ 1 - SinΘ FP 2 = 340.28kHz FP 2 = Fo * Table1- The compensation type and location of FESR versus Fo Select : FZ1 = 0.5 * FZ 2 and FP3 = 0.5 * Fs The details of these compensation types are discussed in application note AN-1043 which can be downloaded from IR’s website at www.irf.com. Select : C7 = 180pF 2π * Fo * Lo * Co * VOSC 2 , R3=15.71KΩ, check R3 ≥ C7 * Vin gm R3 = For this design we have: Vin=12V Vo=1.8V Vosc=1.25V Vref=0.6V gm=1000umoh Lo=1.0uH Co=6x22uF, ESR=0.5mOhm Fs=300kHz Select : R3 = 15.80KΩ Calculate C4 and C3 : C4 = 1 ; C = 1.9nF, Select : C4 = 2.2nF 2π * FZ1 * R 3 4 These result to: C3 = 1 ; C = 67.15pF, Select : C3 = 39pF 2π * FP 3 * R3 3 FLC=18.76kHz FESR=4.4MHz Fs/2=300kHz Calculate R10 , R8 and R9 : Select crossover frequency: Fo < FESR and Fo ≤ (1/5 ~ 1/10) * Fs Fo=60kHz Since: FLC<Fo<Fs/2<FESR, typeIII method B is selected to place the poles and zeros. The following design rules will give a crossover frequency approximately one-tenth of the switching frequency. The higher the band width, the potentially faster the load transient response. 01/08/08 R10 = 1 1 ; R = 2.60KΩ, check R10 ≥ 2π * C7 * FP 2 10 gm Select : R10 = 2.61KΩ R8 = 1 2π * C7 * FZ 2 R9 = Vref * R8 ; R9 = 40.30KΩ, Select : R9 = 40.2KΩ Vo Vref R10 ; R8 = 80.97KΩ, Select : R8 = 80.6KΩ 15 PD-60330 IR3820AMPbF Programming the Current-Limit The Current-Limit threshold can be set by connecting a resistor (RSET) from drain of the low-side MOSFET to the OCSet pin. The resistor can be calculated by using equation (3). The RDS(on) has a positive temperature coefficient and it should be considered for the worse case operation. This resistor must be placed close to the IC, place a small ceramic capacitor from this pin to power ground (PGnd) for noise rejection purposes. ISET = IL(critical) = ROCSet ∗ IOCSet RDS(on) - -(3) RDS(on) = 6.9mΩ ∗υ = 6.9mΩ ∗1.5 = 10.35mΩ where : υ : Temperature Dependency Note : Use 9.3 mΩ for low - side MOSFET if 5V is used for Vcc ISET = (Io ∗1.5 ) + Δi 2 where : Io : Max Output Current Δi : Inductor ripple current Δi = (Vin - Vo ) ∗ Vo Vin ∗ L ∗ Fs ISET = (14A* 1.5) + 2.55A = 23.55A ROCSet = R7 = 12.1KΩ Setting the Power Good Threshold Power Good threshold can be programmed by using two external resistors (see figure 16). Layout Consideration The layout is very important when designing high frequency switching converters. Layout will affect noise pickup and can cause a good design to perform with less than expected results. Start to place the power components, making all the connection in the top layer with wide, copper filled areas. The inductor, output capacitor and the IR3820A should be as close to each other as possible. This helps to reduce the EMI radiated by the power traces due to the high switching currents through them. Place the input capacitor directly to the Vin pin of IR3820A. To reduce the ESR replace the single input capacitor with two parallel units. The feedback part of the system should be kept away from the inductor and other noise sources. The critical bypass components such as capacitors for Vcc and Vc should be close to their respective pins. It is important to place the feedback components including feedback resistors and compensation components close to Fb and Comp pins. In a multilayer PCB use one layer as a power ground plane and have a control circuit ground (analog ground), to which all signals are referenced. The goal is to localize the high current path to a separate loop that does not interfere with the more sensitive analog control function. These two grounds must be connected together on the PC board layout at a single point. The Power QFN is a thermally enhanced package. Based on thermal performance it is recommended to use at least a 4-layers PCB. To effectively remove heat from the device the exposed pad should be connected to the ground plane using vias. The following formula can be used to set the threshold: R2 = 0.38V *R 0.9*Vout - 0.38V 1 --(19 ) Where: 0.38V is reference of the internal comparator 0.9*Vout is selectable threshold for power good, for this design it is 1.62V. Select R1=10KOhm Using (18): R2=3.06KOhm Select R2=3.09K Use a pull up resistor (4.99K) from PGood pin to Vcc. 01/08/08 16 PD-60330 IR3820AMPbF Typical Application for IR3820A 12V to 1.8V @ 14A Fig.16: Typical Application circuit for 12V to 1.8V at 14A using ceramic output capacitors 01/08/08 17 PD-60330 IR3820AMPbF PCB Metal and Components Placement The lead lands (the 11 IC pins) width should be equal to the nominal part lead width. The minimum lead-to-lead spacing should be ≥ 0.2mm to minimize shorting. Lead land length should be equal to the maximum part lead length + 0.3 mm outboard extension. The outboard extension ensures a large and inspectable toe fillet. The pad lands (the 4 big pads other than the 11 IC pins) length and width should be equal to maximum part pad length and width. However, the minimum metal-to-metal spacing should be no less than 0.17mm for 2 oz. Copper; no less than 0.1mm for 1 oz. Copper and no less than 0.23mm for 3 oz. Copper. 01/08/08 18 PD-60330 IR3820AMPbF Solder Resist It is recommended that the lead lands are Non Solder Mask Defined (NSMD). The solder resist should be pulled away from the metal lead lands by a minimum of 0.025mm to ensure NSMD pads. The land pad should be Solder Mask Defined (SMD), with a minimum overlap of the solder resist onto the copper of 0.05mm to accommodate solder resist mis-alignment. Ensure that the solder resist in between the lead lands and the pad land is ≥ 0.15mm due to the high aspect ratio of the solder resist strip separating the lead lands from the pad land. 01/08/08 19 PD-60330 IR3820AMPbF Stencil Design • • 01/08/08 The Stencil apertures for the lead lands should be approximately 80% of the area of the lead lads. Reducing the amount of solder deposited will minimize the occurrences of lead shorts. If too much solder is deposited on the center pad the part will float and the lead lands will be open. The maximum length and width of the land pad stencil aperture should be equal to the solder resist opening minus an annular 0.2mm pull back to decrease the incidence of shorting the center land to the lead lands when the part is pushed into the solder paste. 20 PD-60330 IR3820AMPbF IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 This product has been designed and qualified for the Consumer market. Visit us at www.irf.com for sales contact information Data and specifications subject to change without notice. 10/07 01/08/08 21