TI1 BQ24001PWP Single-cell li-ion charge management icfor pda Datasheet

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SLUS462E − SEPTEMBER 2000 − REVISED NOVEMBER 2004
FEATURES
D Highly Integrated Solution With FET Pass
Transistor and Reverse-Blocking Schottky
and Thermal Protection
D Integrated Voltage and Current Regulation
With Programmable Charge Current
D High-Accuracy Voltage Regulation (±1%)
D Ideal for Low-Dropout Linear Charger
Designs for Single-Cell Li-Ion Packs With
Coke or Graphite Anodes
D Up to 1.2-A Continuous Charge Current
D Safety-Charge Timer During Preconditioning
and Fast Charge
D Integrated Cell Conditioning for Reviving
Deeply Discharged Cells and Minimizing Heat
Dissipation During Initial Stage of Charge
D Optional Temperature or Input-Power
Monitoring Before and During Charge
D Various Charge-Status Output Options for
Driving Single, Double, or Bicolor LEDs or
Host-Processor Interface
D Charge Termination by Minimum Current and
Time
D Low-Power Sleep Mode
D Packaging: 5 mm × 5 mm MLP or 20-Lead
TSSOP PowerPAD
APPLICATIONS
D
D
D
D
PDAs
Internet Appliances
MP3 Players
Digital Cameras
DESCRIPTION
The bq2400x series ICs are advanced Li-Ion linear
charge management devices for highly integrated and
space-limited applications. They combine highaccuracy current and voltage regulation; FET passtransistor and reverse-blocking Schottky; battery
conditioning, temperature, or input-power monitoring;
charge termination; charge-status indication; and
charge timer in a small package.
The bq2400x measures battery temperature using an
external thermistor. For safety reasons, the bq2400x
inhibits charge until the battery temperature is within the
user-defined thresholds. Alternatively, the user can
monitor the input voltage to qualify charge. The
bq2400x series then charge the battery in three phases:
preconditioning, constant current, and constant
voltage. If the battery voltage is below the internal
low-voltage threshold, the bq2400x uses low-current
precharge to condition the battery. A preconditioning
timer is provided for additional safety. Following preconditioning, the bq2400x applies a constant-charge
current to the battery. An external sense-resistor sets
the magnitude of the current. The constant-current
phase is maintained until the battery reaches the
charge-regulation voltage. The bq2400x then
transitions to the constant voltage phase. The user can
configure the device for cells with either coke or
graphite anodes. The accuracy of the voltage regulation
is better than ±1% over the operating junction
temperature and supply voltage range.
Charge is terminated by maximum time or minimum
taper current detection
The bq2400x automatically restarts the charge if the
battery voltage falls below an internal recharge
threshold.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments.
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Copyright  2002 − 2004, Texas Instruments Incorporated
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during
storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION
PACKAGE
TJ
20-LEAD HTTSOP PowerPAD
(PWP)(1)
20-LEAD 5 mm × 5 mm MLP
(RGW)(2)
CHARGE STATUS
CONFIGURATION
bq24001PWP
bq24001RGW
Single LED
bq24002PWP
bq24002RGW
2 LEDs
−40°C
−40
C to 125
125°C
C
bq24003PWP
bq24003RGW
Single bicolor LED
(1) The PWP package is available taped and reeled. Add R suffix to device type (e.g. bq24001PWPR) to order. Quantities 2500 devices per reel.
(2) The RGW package is available taped and reeled. Add R suffix to device type (e.g. bq24001RGWR) to order. Quantities 3000 devices per reel.
PACKAGE DISSIPATION RATINGS
PACKAGE
ΘJA
ΘJC
TA ≤ 25°C
POWER RATING
PWP(1)
RGW(2)
30.88°C/W
1.19°C/W
3.238 W
DERATING FACTOR
ABOVE TA = 25°C
0.0324W/°C
31.41°C/W
1.25°C/W
3.183 W
0.0318W/°C
(1) This data is based on using the JEDEC high-K board and topside traces, top and bottom thermal pad (6.5 × 3.4 mm), internal 1 oz power and
ground planes, 8 thermal via underneath the die connecting to ground plane.
(2) This data is based on using the JEDEC high-K board and topside traces, top and bottom thermal pad (3.25 × 3.25 mm), internal 1 oz power
and ground planes, 9 thermal via underneath the die connecting to ground plane.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted(1)
bq24001
bq24002
bq24003
Supply voltage (Vcc with respect to GND)
13.5 V
Input voltage (IN, ISNS, EN, APG/THERM/CR/STAT1/STAT2, VSENSE, TMR SEL, VSEL) (all with respect to GND)
13.5 V
Output current (OUT pins)
2A
Output sink/source current (STAT1 and STAT2)
10 mA
Operating free-air temperature range, TA
−40°C to 70°C
Storage temperature range, Tstg
−65°C to 150°C
Junction temperature range, TJ
−40°C to 125°C
Lead temperature (Soldering, 10 sec)
300°C
(1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
MIN
MAX
Supply voltage, VCC
4.5
10
V
Input voltage, VIN
4.5
10
V
1.2
A
−40
125
°C
Continuous output current
Operating junction temperature range, TJ
2
UNIT
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SLUS462E − SEPTEMBER 2000 − REVISED NOVEMBER 2004
ELECTRICAL CHARACTERISTICS
over recommended operating junction temperature supply and input voltages, and VI (VCC) ≥ VI (IN) ( unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC current
VCC current, standby mode
VCC > VCC_UVLO,
EN ≤ VIL(EN)
IN current, standby mode
EN ≤ VIL(EN)
MIN
TYP
EN ≤ VIH(EN)
MAX
1
VOUT = 4.3 V,
VOUT = 4.3 V,
mA
µA
1
10
Standby current (sum of currents into OUT VCC < VCC_UVLO,
and VSENSE pins)
EN <= VilEN,
UNIT
VSENSE = 4.3V
2
4
VSENSE = 4.3 V
2
4
µA
µA
VOLTAGE REGULATION, 0°C ≤ TJ ≤ 125°C
PARAMETER
Output voltage
Load regulation
Line regulation
Dropout voltage = VI(IN)-Vout
MIN
TYP
MAX
UNIT
VSEL = VSS,
TEST CONDITIONS
0 < IO ≤ 1.2 A
4.059
4.10
4.141
V
VSEL = VCC,
0 < IO ≤ 1.2 A
4.158
4.20
4.242
V
1 mA ≤ IO ≤ 1.2 A,
VI(IN)= 5 V,
VCC =5 V,
TJ = 25°C
VOUT+VDO+Vilim(MAX) < VI(VCC) < 10 V,
IO = 1.0 A,
IO = 1.2 A,
1
TJ = 25°C
4.9 V <VI(Vcc)< 10 V
mV
0.01
VOUT+VDO+VilimMAX <VI(VCC)< 10 V
%/V
0.7
V
0.8
V
CURRENT REGULATION, 0°C ≤ TJ ≤ 125°C
PARAMETER
TEST CONDITIONS
Current regulation threshold, VI(limit)
VSENSE < VO(VSEL-LOW/HIGH)
Delay time
VSENSE pulsed above VVLOWV to IO = 10% of
regulated value(1)
Rise time
IO increasing from 10% to 90% of regulated value.
RSNS≥ 0.2 Ω, (1)
MIN
TYP
MAX
UNIT
0.095
0.1
0.105
V
0.1
1
ms
1
ms
(1) Specified by design, not production tested.
CURRENT SENSE RESISTOR, 0°C ≤ TJ ≤ 125°C
PARAMETER
TEST CONDITIONS
External current sense resistor range (RSNS) 100 mA ≤ Ilim ≤ 1.2 A
MIN
TYP
0.083
MAX
1
UNIT
Ω
PRECHARGE CURRENT REGULATION, 0°C ≤ TJ ≤ 125°C
PARAMETER
Precharge current regulation
TEST CONDITIONS
VSENSE<VLOWV, 0.083 ≤ RSNS ≤ 1.0 Ω
MIN
TYP
MAX
40
60
80
UNIT
mA
VCC UVLO COMPARATOR, 0°C ≤ TJ ≤ 125°C
MIN
TYP
MAX
UNIT
Start threshold
PARAMETER
TEST CONDITIONS
4.35
4.43
4.50
V
Stop threshold
4.25
4.33
4.40
V
Hysteresis
50
mV
APG/THERM COMPARATOR, 0°C ≤ TJ ≤ 125°C
MIN
TYP
MAX
UNIT
Upper trip threshold
PARAMETER
TEST CONDITIONS
1.480
1.498
1.515
V
Lower trip threshold
0.545
0.558
0.570
Input bias current
1
V
µA
LOWV COMPARATOR, 0°C ≤ TJ ≤ 125°C
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Start threshold
2.80
2.90
3.00
V
Stop threshold
3.00
3.10
3.20
Hysteresis
100
V
mV
3
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SLUS462E − SEPTEMBER 2000 − REVISED NOVEMBER 2004
ELECTRICAL CHARACTERISTICS CONTINUED
over recommended operating junction temperature supply and input voltages, and VI (VCC) ≥ VI (IN) ( unless otherwise noted)
HIGHV (RECHARGE) COMPARATOR, 0°C ≤ TJ ≤ 125°C
PARAMETER
TEST CONDITIONS
Start threshold
MIN
TYP
MAX
UNIT
3.80
3.90
4.00
V
OVERV COMPARATOR, 0°C ≤ TJ ≤ 125°C
MIN
TYP
MAX
UNIT
Start threshold
PARAMETER
TEST CONDITIONS
4.35
4.45
4.55
V
Stop threshold
4.25
4.30
4.35
Hysteresis
50
V
mV
TAPERDET COMPARATOR, 0°C ≤ TJ ≤ 125°C
PARAMETER
TEST CONDITIONS
Trip threshold
MIN
TYP
MAX
12
18.5
25
MIN
TYP
MAX
UNIT
mV
EN LOGIC INPUT, 0°C ≤ TJ ≤ 125°C
PARAMETER
TEST CONDITIONS
High-level input voltage
2.25
V
Low-level input voltage
Input pulldown resistance
UNIT
100
0.8
V
200
kΩ
MAX
UNIT
VSEL LOGIC INPUT, 0°C ≤ TJ ≤ 125°C
PARAMETER
TEST CONDITIONS
High-level input voltage
MIN
TYP
2.25
V
Low-level input voltage
Input pulldown resistance
100
0.8
V
200
kΩ
MAX
UNIT
TMR SEL INPUT 0°C ≤ TJ ≤ 125°C
PARAMETER
TEST CONDITIONS
High-level input voltage
MIN
TYP
2.7
V
Low-level input voltage
VI(TMR SEL) ≤ 5V
Input bias current
0.6
V
15
µA
STAT1, STAT2 (bq24001, bq24003), 0°C ≤ TJ ≤ 125°C
PARAMETER
TEST CONDITIONS
Output (low) saturation voltage
MIN
TYP
IO = 10 mA
IO = 4 mA
Output (low) saturation voltage
Output (high) saturation voltage
Output (high) saturation voltage
IO = −10 mA
IO = −4 mA
Output turn on/off time
IO = ± 10 mA, C = 100 p(1)
MAX
UNIT
1.5
V
0.6
V
VCC−1.5
VCC−0.5
V
V
100
µs
MAX
UNIT
(1) Assured by design, not production tested.
POWER-ON RESET (POR), 0°C ≤ TJ ≤ 125°C
PARAMETER
TEST CONDITIONS
MIN
TYP
POR delay
See Note 1
1.2
3
ms
POR falling-edge deglitch
See Note 1
25
75
µs
(1) Assured by design, not production tested.
4
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SLUS462E − SEPTEMBER 2000 − REVISED NOVEMBER 2004
ELECTRICAL CHARACTERISTICS CONTINUED
over recommended operating junction temperature supply and input voltages, and VI (VCC) ≥ VI (IN) ( unless otherwise noted)
APG/THERM DELAY, 0°C ≤ TJ ≤ 125°C
PARAMETER
TEST CONDITIONS
APG/THERM falling-edge deglitch
MIN
See Note 1
TYP
25
MAX
75
UNIT
µs
(1) Assured by design, not production tested.
TIMERS, 0°C ≤ TJ ≤ 125°C
PARAMETER
TEST CONDITIONS
MIN
TA = 25°C
User-selectable timer accuracy
TYP
−15%
UNIT
15%
−20%
Precharge and taper timer
MAX
20%
22.5
minute
THERMAL SHUTDOWN, 0°C ≤ TJ ≤ 125°C
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Thermal trip
See Note 1
165
°C
Thermal hysteresis
See Note 1
10
°C
(1) Assured by design, not production tested.
CR PIN, 0°C ≤ TJ ≤ 125°C
PARAMETER
TEST CONDITIONS
0 < IO(CR) < 100 µA
Output voltage
MIN
TYP
MAX
UNIT
2,816
2.85
2.88
V
PIN ASSIGNMENTS
bq24002, bq24003
PWP PACKAGE
(TOP VIEW)
bq24001
PWP PACKAGE
(TOP VIEW)
N/C
IN
IN
VCC
ISNS
N/C
APG/THERM
EN
VSEL
GND/HEATSINK
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
N/C
OUT
OUT
VSENSE
AGND
N/C
STAT1
TMR SEL
CR
N/C
N/C
IN
IN
VCC
ISNS
N/C
APG/THERM
EN
VSEL
GND/HEATSINK
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
N/C
OUT
OUT
VSENSE
AGND
STAT2
STAT1
TMR SEL
CR
N/C
N/C − Do not connect
5
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1 IN
2 IN
3 VCC
bq24002, bq24003
RGW PACKAGE
(TOP VIEW)
4 ISNS
5 APG/THERM
1 IN
2 IN
3 VCC
bq24001
RGW PACKAGE
(TOP VIEW)
4 ISNS
5 APG/THERM
SLUS462E − SEPTEMBER 2000 − REVISED NOVEMBER 2004
EN 6
20 N/C
EN 6
20 N/C
VSEL 7
19 N/C
VSEL 7
19 N/C
GND 8
18 N/C
GND 8
18 N/C
TMR SEL 11
TMR SEL 11
VSENSE 15
16 OUT
AGND 14
N/C 10
STAT2 13
16 OUT
STAT1 12
N/C 10
VSENSE 15
17 OUT
AGND 14
CR 9
N/C 13
17 OUT
STAT1 12
CR 9
N/C − Do Not Connect
Terminal Functions
TERMINAL
NAME
I/O
DESCRIPTION
NO.
NO.
16
14
APG/THERM
7
5
I
Adapter power good input/thermistor sense input
CR
12
9
I
Internal regulator bypass capacitor
EN
8
6
I
Charge-enable input. Active-high enable input with internal pull down. Low-current stand-by mode
active when EN is low.
GND/HEATSINK
10
8
IN
2, 3
1, 2
I
Input voltage. This input provides the charging voltage for the battery.
I
Current sense input
AGND
ISNS
5
4
N/C
1, 6, 11,
15, 20
10, 13,
18−20
OUT
Ground pin; connect close to the negative battery terminal.
Ground pin; connect to PowerPAD heat-sink layout pattern.
No connect. These pins must be left floating. Pin 15 is N/C on bq24001PWP only. Pin 13 is N/C on
bq24001RGW only.
18, 19
16, 17
O
Charge current output
STAT1
14
12
O
Status display output 1
STAT2
15
13
O
Status display output 2 (for bq24002 and bq24003 only)
TMR SEL
13
11
I
Charge timer selection input
VCC
4
3
I
Supply voltage
VSEL
9
7
I
4.1 V or 4.2 V charge regulation selection input
VSENSE
17
15
I
Battery voltage sense input
6
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SLUS462E − SEPTEMBER 2000 − REVISED NOVEMBER 2004
FUNCTIONAL BLOCK DIAGRAM
OUT
IN
+
VSENSE
TaperDet
−
VCC
−
+
−
Vilim
+
0.2*Vilim
ISNS
Vref
AGND
+
Precharge
−
GND/
HEATSINK
LowV
OverV
ChipEN
−
R8
Vuvlo
LowV
+
+
Vref
−
Power On
Delay
APG/
THERM
−
VSEL
R9
HighV
Bias and
Ref
Generator
+
EN
H: Vreg = 4.2 V/Cell
L: Vreg = 4.1 V/Cell
+
Vuvlo
ChargeOK
UVS
Vref
CLRFLT
−
+
PWRDWN
−
Thermal
Shutdown
UVS
VCC
TaperDet
STAT1
PWRDWN
PWRDWN
OSC
Charge Control, Charge Timer
and
Display Logic
TMR SEL
VCC
STAT2
REG
ChargeOK
CR
Two Open
Drain
Outputs
for
bq24002
7
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SLUS462E − SEPTEMBER 2000 − REVISED NOVEMBER 2004
TYPICAL CHARACTERISTICS
OUTPUT VOLTAGE
vs
OUTPUT CURRENT
OUTPUT VOLTAGE
vs
JUNCTION TEMPERATURE
4.24
4.24
VIN = 5 V
VIN = 5 V
TA = 25°C
4.22
4.22
VSEL = VCC
VSEL = VCC
4.20
VO − Output Voltage − V
VO − Output Voltage − V
4.20
4.18
4.16
4.14
4.12
VSEL = VSS
4.18
4.16
4.14
4.12
VSEL = VSS
4.10
4.10
4.08
4.08
4.06
−50
4.06
0
200
400
600
800
1000
1200
0
Figure 1
150
CURRENT SENSE VOLTAGE
vs
INPUT VOLTAGE
4.24
103
IO = 100 mA
TA = 25°C
IO = 100 mA
TA = 25°C
VSEL = VCC
102
Current Sense Voltage − mV
4.20
VO − Output Voltage − V
100
Figure 2
OUTPUT VOLTAGE
vs
INPUT VOLTAGE
4.22
50
TJ − Junction Temperature − °C
IO − Output Current − mA
4.18
4.16
4.14
4.12
VSEL = VSS
4.10
101
100
99
98
4.08
4.06
97
5
6
7
8
VI − Input Voltage − V
Figure 3
8
9
10
5
6
7
8
VI − Input Voltage − V
Figure 4
9
10
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SLUS462E − SEPTEMBER 2000 − REVISED NOVEMBER 2004
TYPICAL CHARACTERISTICS
CURRENT SENSE VOLTAGE
vs
JUNCTION TEMPERATURE
QUIESCENT CURRENT
vs
INPUT VOLTAGE
103
0.5
IO = 100 mA
TA = 25°C
TA = 25°C
0.4
Quiescent Current − mA
Current Sense Voltage − mV
102
VCC = 10 V
101
100
VCC = 5 V
99
0.3
0.2
0.1
98
−50
0.0
0
50
100
150
5
6
TJ − Junction Temperature − °C
8
9
10
VI − Input Voltage − V
Figure 5
Figure 6
QUIESCENT CURRENT
(POWER DOWN)
vs
INPUT VOLTAGE
DROPOUT VOLTAGE
vs
INPUT VOLTAGE
600
30
TA = 25°C
TA = 25°C
500
Dropout Voltage − mV
25
Quiescent Current − nA
7
20
15
10
400
1200 mA
300
800 mA
200
400 mA
100
5
100 mA
0
5
6
7
8
VI − Input Voltage − V
Figure 7
9
10
0
4.5
5.5
6.5
7.5
8.5
9.5
VI − Input Voltage − V
Figure 8
9
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SLUS462E − SEPTEMBER 2000 − REVISED NOVEMBER 2004
TYPICAL CHARACTERISTICS
DROPOUT VOLTAGE
vs
OUTPUT CURRENT
DROPOUT VOLTAGE
vs
JUNCTION TEMPERATURE
600
800
IO = 1.2 A
TA = 25°C
700
Dropout Voltage − mV
Dropout Voltage − mV
500
400
VCC = 5 V
300
200
VCC = 10 V
100
600
VIN = 5 V
500
400
VIN = 10 V
300
200
0
0
200
400
600
800
1000
100
−50
1200
0
50
100
150
TJ − Junction Temperature − °C
IO − Output Current − mA
Figure 9
Figure 10
REVERSE CURRENT
vs
JUNCTION TEMPERATURE
REVERSE CURRENT LEAKAGE
vs
VOLTAGE ON OUT PIN
6
4.0
VOUT = 4.3 V
TA = 25°C
3.5
IR − Reverse Current Leakage − µA
IR − Reverse Current − µA
5
4
3
2
1
3.0
2.5
2.0
1.5
1.0
0.5
0
−50
0.0
0
50
100
TJ − Junction Temperature − °C
Figure 11
10
150
5
6
7
8
VO − Voltage on Out Pin − V
Figure 12
9
10
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SLUS462E − SEPTEMBER 2000 − REVISED NOVEMBER 2004
APPLICATION INFORMATION
U1
VCC
1
R1
0.1 Ω
2
DC+
C1
10 µF
+
VCC
3
4
DC−
5
6
C2
0.1 µF
7
8
9
10
N/C
IN
N/C
OUT
IN
OUT
VCC
ISNS
VSENSE
AGND
N/C
STAT2
APG/THM
STAT1
EN
TMR SEL
VSEL
GND
CR
N/C
20
19
PACK+
18
+
17
−
16
PACK−
15
C4
1 µF
14
13
TEMP
12
11
VCC
C3
0.22 µF
Battery
Pack
R4
500 Ω
bq24002PWP
D1
R5
500 Ω
R2
18.7 kΩ
D2
R3
95.3 kΩ
Figure 13. Li-Ion/Li-Pol Charger
D If the TMR SEL pin is left floating (3 HR time), a 10-pF capacitor should be installed between TMR SEL and CR.
D If a micro process is monitoring the STAT pins, it may be necessary to add some hysteresis into the feedback
to prevent the STAT pins from cycling while crossing the taper detect threshold (usually less than one half
second). See SLUU083 EVM or SLUU113 EVM for additional resistors used for the STAT pins.
11
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SLUS462E − SEPTEMBER 2000 − REVISED NOVEMBER 2004
APPLICATION INFORMATION
FUNCTIONAL DESCRIPTION
The bq2400x supports a precision current- and voltage-regulated Li-Ion charging system suitable for cells with either coke
or graphite anodes. See Figure 14 for a typical charge profile and Figure 15 for an operational flowchart.
Preconditioning
Phase
Current Regulation
Phase
Voltage Regulation and
Charge TerminationPhase
Regulation Voltage
(VOUT)
Regulation Current
(Ilim)
Charge Voltage
Minimum Charge
Voltage (LowV)
Preconditioning
Current (IPRECHG)
Charge Current
Taper Detect
22.5 Minutes
22.5 Minutes
Charge Timer (3, 4.5 or 6 Hours)
Figure 14. Typical Charge Profile
12
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SLUS462E − SEPTEMBER 2000 − REVISED NOVEMBER 2004
POR
Yes
VI(VSENSE) < V(LOWV)?
Regulate
I (PRECHG)
Reset and Start
22.5 min Timer
Indicate Pre−
Charge
No
Reset All Timers,
Start Charge Timer
(TMR SEL input )
Yes
VI(VSENSE) > V(OVERV)?
No
Regulate Current
or Voltage
Indicate Charge
No
VI(VSENSE) < V(LOWV)?
Yes
VI(VSENSE) > V(OVERV)?
Yes
22.5min Timer
Expired?
No
No
Yes
Yes
Charge timer
Expired?
No
Fault Condition
Yes
Indicate Fault
VI(VSENSE) < V(LOWV)?
No
Taper
Detected?
Start 22.5 minute
Timer
Yes
POR?
or
APG/THERM toggle?
or
EN toggle?
No
Indicate DONE
Yes
No
22.5min Timer
Expired?
Yes
Turn Off Charge
Indicate DONE
VI(VSENSE) < V(HIGHV)?
or
POR?
or
APG/THERM Toggle?
or
EN Toggle?
No
Yes
Figure 15. Operational Flow Chart
13
www.ti.com
SLUS462E − SEPTEMBER 2000 − REVISED NOVEMBER 2004
Charge Qualification and Preconditioning
The bq2400x starts a charge cycle when power is applied
while a battery is present. Charge qualification is based on
battery voltage and the APG/THERM input.
As shown in the block diagram, the internal LowV
comparator output prevents fast-charging a deeply
depleted battery. When set, charging current is provided
by a dedicated precharge current source. The precharge
timer limits the precharge duration. The precharge current
also minimizes heat dissipation in the pass element during
the initial stage of charge.
The APG/THERM input can also be configured to monitor
either the adapter power or the battery temperature using
a thermistor. The bq2400x suspends charge if this input is
outside the limits set by the user. Please refer to the
APG/THERM input section for additional details.
APG/THERM Input
The bq400x continuously monitors temperature or system
input voltage by measuring the voltage between the
APG/THERM (adapter power good/thermistor) and GND.
For temperature, a negative- or a positive- temperature
coefficient thermistor (NTC, PTC) and an external voltage
divider typically develop this voltage (see Figure 16). The
bq2400x compares this voltage against its internal VTP1
and VTP2 thresholds to determine if charging is allowed.
(See Figure 17.)
U1
1
2
3
4
5
6
7
8
9
10
N/C
IN
N/C
OUT
IN
OUT
VCC
VSENSE
ISNS
AGND
N/C
STAT2
APG/THM
STAT1
EN
TMR SEL
VSEL
GND
CR
N/C
20
19
PACK+
18
+
17
−
16
PACK−
15
NTC Thermistor
14
13
TEMP
12
Battery Pack
C3
0.22 µF
11
bq24002PWP
RT1
RT2
Figure 16. Temperature Sensing Circuit
14
www.ti.com
SLUS462E − SEPTEMBER 2000 − REVISED NOVEMBER 2004
If the charger designs incorporate a thermistor, the resistor
divider RT1 and RT2 is calculated by using the following
two equations.
Where:
First, calculate RT2.
RH = Resistance of the thermistor at the desired hot trip
threshold
V B RH R C
RT2 +
RH
ǒ
V
V
B
H
ƪ
1
V
Ǔ
C
*
* 1 * RC
ǒ
1
V
V
ƫ
V
H
B
C
Ǔ
* 1
then use the resistor value to find RT1.
V
RT1 +
V
B
C
1
RT2
* 1
)
VB = VCR (bias voltage)
RC = Resistance of the thermistor at the desired cold trip
threshold
VH = VP2 or the lower APG trip threshold
VC = VP2 or the upper APG trip threshold
RT1 = Top resistor in the divider string
1
R
C
RT2 = Bottom resistor in the divider string
U1
VCC
1
2
DC+
Vcc
3
4
Temp Fault
5
VTP1
R1
6
7
Normal Temp Range
VTP2
8
R2
Temp Fault
9
10
DC−
N/C
N/C
IN
OUT
IN
OUT
VCC
VSENSE
ISNS
AGND
N/C
STAT2
APG/THM
STAT1
EN
TMR SEL
VSEL
CR
GND
N/C
20
19
18
17
16
15
14
13
12
11
GND
bq24002PWP
Figure 17. Temperature Threshold
Figure 18. APG Sensing Circuit
Values of resistors R1 and R2 can be calculated using the following equation:
R2
V APG + VCC
(R1 ) R2)
where VAPG is the voltage at the APG/THM pin.
Current Regulation
The bq2400x provides current regulation while the battery-pack voltage is less than the regulation voltage. The current
regulation loop effectively amplifies the error between a reference signal, Vilim, and the drop across the external sense
resistor, RSNS.
15
www.ti.com
SLUS462E − SEPTEMBER 2000 − REVISED NOVEMBER 2004
U1
VCC
1
RSNS
2
DC+
C1
10 µF
+
VCC
3
4
DC−
5
6
C2
0.1 µF
7
8
9
10
N/C
N/C
IN
OUT
IN
OUT
VCC
VSENSE
ISNS
AGND
N/C
STAT2
APG/THM
STAT1
EN
TMR SEL
VSEL
CR
GND
N/C
20
19
18
17
16
15
14
13
12
11
bq24002PWP
Figure 19. Current Sensing Circuit
Charge current feedback, applied through pin ISNS,
maintains regulation around a threshold of Vilim. The
following formula calculates the value of the sense
resistor:
R SNS + Vilim
I REG
that in the case of a fault condition, such as an out-of-range
signal on the APG/THERM input or a thermal shutdown,
the bq2400x suspends the timer.
where IREG is the desired charging current.
High
4.5 hours
(1) To improve noise immunity, it is recommended that a minimum of
10 pF capacitor be tied to Vss on a floating pin.
Voltage Monitoring and Regulation
Voltage regulation feedback is through pin VSENSE. This
input is tied directly to the positive side of the battery pack.
The bq2400x supports cells with either coke (4.1 V) or
graphite (4.2 V) anode. Pin VSEL selects the charge
regulation voltage.
VSEL State
(see Note)
CHARGE REGULATION
VOLTAGE
Low
4.1 V
High
4.2 V
NOTE: VSEL should not be left floating.
TMRSEL STATE
Floating(1)
CHARGE TIME
Low
6 hours
Minimum Current: The bq2400x monitors the charging
current during the voltage regulation phase. The bq2400x
initiates a 22-minute timer once the current falls below the
taperdet trip threshold. Fast charge is terminated once the
22-minute timer expires.
Charge Status Display
The three available options allow the user to configure the
charge status display for single LED (bq24001), two
individual LEDs (bq24002) or a bicolor LED (bq24003).
The output stage is totem pole for the bq24001 and
bq24003 and open-drain for the bq24002. The following
tables summarize the operation of the three options:
Table 1. bq24001 (Single LED)
Charge Termination
The bq2400x continues with the charge cycle until
termination by one of the two possible termination
conditions:
CHARGE STATE
16
STAT1
Precharge
ON (LOW)
Fast charge
ON (LOW)
FAULT
Maximum Charge Time: The bq2400x sets the maximum
charge time through pin TMRSEL. The TMR SEL pin
allows the user to select between three different total
charge-time timers (3, 4, 5, or 6 hours). The charge timer
is initiated after the preconditioning phase of the charge
and is reset at the beginning of a new charge cycle. Note
3 hours
Flashing (1 Hz, 50% duty cycle)
Done (>90%)
OFF (HIGH)
Sleep-mode
OFF (HIGH)
APG/Therm invalid
OFF (HIGH)
Thermal shutdown
OFF (HIGH)
Battery absent
OFF (HIGH)
www.ti.com
SLUS462E − SEPTEMBER 2000 − REVISED NOVEMBER 2004
Table 2. bq24002 (2 Individual LEDs)
STAT1 (RED)
STAT2
(GREEN)
Precharge
ON (LOW)
OFF
Fast charge
ON (LOW)
OFF
Flashing (1 Hz,
50% duty cycle)
OFF
CHARGE STATE
FAULT
Done (>90%)
OFF
ON (LOW)
Sleep-mode
OFF
OFF
APG/Therm invalid
OFF
OFF
Thermal shutdown
OFF
Battery absent
OFF
OFF
OFF(1)
(1) If thermistor is used, then the Green LED is off.
Table 3. bq24003 (Single Bicolor LED)
LED1 (RED)
LED2
(GREEN)
APPARENT
COLOR
Precharge
ON (LOW)
OFF (HIGH)
RED
Fast charge
ON (LOW)
OFF (HIGH)
RED
FAULT
ON (LOW)
ON (LOW)
YELLOW
CHARGE STATE
Done (>90%)
OFF (HIGH)
ON (LOW)
GREEN
Sleep-mode
OFF (HIGH)
OFF (HIGH)
OFF
APG/Therm
invalid
OFF (HIGH)
OFF (HIGH)
OFF
Thermal
shutdown
OFF (HIGH)
OFF (HIGH)
OFF
Battery absent
OFF (HIGH)
OFF (HIGH)(1)
OFF(1)
(1) If thermistor is used, then the Green LED is off.
Thermal Shutdown
The bq2400x monitors the junction temperature TJ of the DIE and suspends charging if TJ exceeds 165°C. Charging
resumes when TJ falls below 155°C.
DETAILED DESCRIPTION
POWER FET
VOLTAGE SENSE
The integrated transistor is a P-channel MOSFET. The
power FET features a reverse-blocking Schottky diode,
which prevents current flow from OUT to IN.
To achieve maximum voltage regulation accuracy, the
bq2400x uses the feedback on the VSENSE pin.
Externally, this pin should be connected as close to the
battery cell terminals as possible. For additional safety, a
10kΩ internal pullup resistor is connected between the
VSENSE and OUT pins.
An internal thermal-sense circuit shuts off the power FET
when the junction temperature rises to approximately
165°C. Hysteresis is built into the thermal sense circuit.
After the device has cooled approximately 10°C, the
power FET turns back on. The power FET continues to
cycle off and on until the fault is removed.
CURRENT SENSE
The bq2400x regulates current by sensing, on the ISNS
pin, the voltage drop developed across an external sense
resistor. The sense resistor must be placed between the
supply voltage (Vcc) and the input of the IC (IN pins).
ENABLE (EN)
The logic EN input is used to enable or disable the IC. A
high-level signal on this pin enables the bq2400x. A
low-level signal disables the IC and places the device in a
low-power standby mode.
17
www.ti.com
SLUS462E − SEPTEMBER 2000 − REVISED NOVEMBER 2004
THERMAL INFORMATION
THERMALLY ENHANCED TSSOP-20
DIE
The thermally enhanced PWP package is based on the
20-pin TSSOP, but includes a thermal pad (see
Figure 20) to provide an effective thermal contact between
the IC and the PWB.
Traditionally, surface mount and power have been
mutually exclusive terms. A variety of scaled-down
TO220-type packages have leads formed as gull wings to
make them applicable for surface-mount applications.
These packages, however, suffer from several
shortcomings: they do not address the very low profile
requirements (<2 mm) of many of today’s advanced
systems, and they do not offer a pin-count high enough to
accommodate increasing integration. On the other hand,
traditional low-power surface-mount packages require
power-dissipation derating that severely limits the usable
range of many high-performance analog circuits.
Side View (a)
DIE
End View (b)
Thermal
Pad
The PWP package (thermally enhanced TSSOP)
combines fine-pitch surface-mount technology with
thermal performance comparable to much larger power
packages.
The PWP package is designed to optimize the heat
transfer to the PWB. Because of the very small size and
limited mass of a TSSOP package, thermal enhancement
is achieved by improving the thermal conduction paths that
remove heat from the component. The thermal pad is
formed using a lead-frame design (patent pending) and
manufacturing technique to provide the user with direct
connection to the heat-generating IC. When this pad is
soldered or otherwise coupled to an external heat
dissipator, high power dissipation in the ultrathin,
fine-pitch, surface-mount package can be reliably
achieved.
18
Bottom View (c)
Figure 20. Views of Thermally Enhanced
PWP Package
Because the conduction path has been enhanced,
power-dissipation capability is determined by the thermal
considerations in the PWB design. For example, simply
adding a localized copper plane (heat-sink surface), which
is coupled to the thermal pad, enables the PWP package
to dissipate 2.5 W in free air. (Reference Figure 22(a), 8
cm2 of copper heat sink and natural convection.)
Increasing the heat-sink size increases the power
dissipation range for the component. The power
dissipation limit can be further improved by adding airflow
to a PWB/IC assembly (see Figure 22(b) and 22(c)). The
line drawn at 0.3 cm2 in Figures 21 and 22 indicates
performance at the minimum recommended heat-sink
size.
www.ti.com
SLUS462E − SEPTEMBER 2000 − REVISED NOVEMBER 2004
THERMAL INFORMATION
THERMAL RESISTANCE
vs
COPPER HEAT-SINK AREA
150
Natural Convection
R θ JA − Thermal Resistance −
° C/W
125
50 ft/min
100 ft/min
100
150 ft/min
200 ft/min
75
50
250 ft/min
300 ft/min
25
0 0.3
1
2
3
4
5
6
7
8
Copper Heat-Sink Area − cm2
Figure 21
19
www.ti.com
SLUS462E − SEPTEMBER 2000 − REVISED NOVEMBER 2004
THERMAL INFORMATION
3.5
3.5
TA = 55°C
300 ft/min
3
PD − Power Dissipation Limit − W
PD − Power Dissipation Limit − W
TA = 25°C
150 ft/min
2.5
2
Natural Convection
1.5
1
0.5
0
3
300 ft/min
2.5
2
150 ft/min
1.5
Natural Convection
1
0.5
0
0.3
2
4
6
0
8
Copper Heat-Sink Size − cm2
0
0.3
2
4
6
Copper Heat-Sink Size − cm2
(a)
(b)
3.5
TA = 105°C
PD − Power Dissipation Limit − W
3
2.5
2
1.5
150 ft/min
300 ft/min
1
Natural Convection
0.5
0
0
0.3
2
4
6
8
Copper Heat-Sink Size − cm2
(c)
Figure 22. Power Ratings of the PWP Package at Ambient Temperatures of 25°C, 55°C, and 105°C
20
8
PACKAGE OPTION ADDENDUM
www.ti.com
8-Dec-2009
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
BQ24001PWP
ACTIVE
HTSSOP
PWP
20
70
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
BQ24001PWPG4
ACTIVE
HTSSOP
PWP
20
70
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
BQ24001PWPR
ACTIVE
HTSSOP
PWP
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
BQ24001PWPRG4
ACTIVE
HTSSOP
PWP
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
BQ24001RGWR
ACTIVE
VQFN
RGW
20
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
BQ24001RGWRG4
ACTIVE
VQFN
RGW
20
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
BQ24002PWP
ACTIVE
HTSSOP
PWP
20
70
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
BQ24002PWPG4
ACTIVE
HTSSOP
PWP
20
70
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
BQ24002PWPR
ACTIVE
HTSSOP
PWP
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
BQ24002PWPRG4
ACTIVE
HTSSOP
PWP
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
BQ24002RGWR
ACTIVE
VQFN
RGW
20
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
BQ24002RGWRG4
ACTIVE
VQFN
RGW
20
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
BQ24003PWP
ACTIVE
HTSSOP
PWP
20
70
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
BQ24003PWPG4
ACTIVE
HTSSOP
PWP
20
70
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
BQ24003PWPR
ACTIVE
HTSSOP
PWP
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
BQ24003PWPRG4
ACTIVE
HTSSOP
PWP
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
BQ24003RGWR
ACTIVE
VQFN
RGW
20
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
BQ24003RGWRG4
ACTIVE
VQFN
RGW
20
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
8-Dec-2009
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
HTSSOP
PWP
20
2000
330.0
16.4
BQ24001RGWR
VQFN
RGW
20
3000
330.0
BQ24002PWPR
HTSSOP
PWP
20
2000
330.0
BQ24002RGWR
VQFN
RGW
20
3000
BQ24003PWPR
HTSSOP
PWP
20
BQ24003RGWR
VQFN
RGW
20
BQ24001PWPR
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
6.95
7.1
1.6
8.0
16.0
Q1
12.4
5.3
5.3
1.5
8.0
12.0
Q2
16.4
6.95
7.1
1.6
8.0
16.0
Q1
330.0
12.4
5.3
5.3
1.5
8.0
12.0
Q2
2000
330.0
16.4
6.95
7.1
1.6
8.0
16.0
Q1
3000
330.0
12.4
5.3
5.3
1.5
8.0
12.0
Q2
Pack Materials-Page 1
W
Pin1
(mm) Quadrant
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
BQ24001PWPR
HTSSOP
PWP
20
2000
367.0
367.0
38.0
BQ24001RGWR
VQFN
RGW
20
3000
367.0
367.0
35.0
BQ24002PWPR
HTSSOP
PWP
20
2000
367.0
367.0
38.0
BQ24002RGWR
VQFN
RGW
20
3000
367.0
367.0
35.0
BQ24003PWPR
HTSSOP
PWP
20
2000
367.0
367.0
38.0
BQ24003RGWR
VQFN
RGW
20
3000
367.0
367.0
35.0
Pack Materials-Page 2
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