1Gb DDR3L SDRAM
1Gb DDR3L SDRAM
Lead-Free&Halogen-Free
(RoHS Compliant)
H5TC1G83EFR-xxA
H5TC1G83EFR-xxI
H5TC1G63EFR-xxA
H5TC1G63EFR-xxI
*SK hynix Inc. reserves the right to change products or specifications without notice
Rev. 1.0 July. 2012
1
Revision History
Revision No.
History
Date
1.0
Official Version Release
July. 2012
Rev. 1.0 /July. 2012
Remark
2
Description
The H5TC1G83EFR-xxA(I) and H5TC1G63EFR-xxA(I) are a 1Gb low power Double Data Rate III (DDR3L)
Synchronous DRAM, ideally suited for the main memory applications which requires large memory density,
high bandwidth and low power operation at 1.35V. SK Hynix DDR3L SDRAM provides backward compatibility with the 1.5V DDR3 based environment without any changes. (Please refer to the SPD information for
details.)
SK Hynix 1Gb DDR3L SDRAMs offer fully synchronous operations referenced to both rising and falling
edges of the clock. While all addresses and control inputs are latched on the rising edges of the clock (falling edges of the clock), data, data strobes and write data masks inputs are sampled on both rising and
falling edges of it. The data paths are internally pipelined and 8-bit prefetched to achieve very high bandwidth.
Device Features and Ordering Information
FEATURES
• VDD=VDDQ=1.35V + 0.100 / - 0.067V
• BL switch on the fly
• Fully differential clock inputs (CK, CK) operation
• 8banks
• Differential Data Strobe (DQS, DQS)
• Average Refresh Cycle (Tcase of 0 oC~ 95 oC)
- 7.8 µs at 0oC ~ 85 oC
- 3.9 µs at 85oC ~ 95 oC
Commerical Temperature (0oC ~ 85 oC)
Industrial Temperature(-40oC ~ 95 oC)
• On chip DLL align DQ, DQS and DQS transition with CK
transition
• DM masks write data-in at the both rising and falling
edges of the data strobe
• All addresses and control inputs except data,
data strobes and data masks latched on the
rising edges of the clock
• JEDEC standard 78ball FBGA(x8), 96ball FBGA(x16)
• Programmable CAS latency 6, 7, 8, 9, 10, 11, 12 and
13
supported
• Dynamic On Die Termination supported
• Programmable additive latency 0, CL-1, and CL-2
supported
• Programmable CAS Write latency (CWL) = 5, 6, 7, 8
• Driver strength selected by EMRS
• Asynchronous RESET pin supported
• ZQ calibration supported
• TDQS (Termination Data Strobe) supported (x8 only)
• Write Levelization supported
• 8 bit pre-fetch
• Programmable burst length 4/8 with both nibble
sequential and interleave mode
* This product in compliance with the RoHS directive.
Rev. 1.0 /July. 2012
3
ORDERING INFORMATION
Part No.
Configuration
H5TC1G83EFR-*xxA
Temperature
Commercial
128M x 8
H5TC1G83EFR-*xxI
H5TC1G63EFR-*xxA
78ball FBGA
Industrial
Commercial
64M x 16
H5TC1G63EFR-*xxI
Package
96ball FBGA
Industrial
* xx means Speed Bin Grade
OPERATING FREQUENCY
Frequency [MHz]
Speed
Grade
(Marking)
CL5
CL6
CL7
CL8
-G7
667
800
1066
1066
-H9
667
800
1066
1066
1333
1333
-PB
667
800
1066
1066
1333
1333
1600
800
1066
1066
1333
1333
1600
-RD
Rev. 1.0 /July. 2012
CL9
CL10
CL11
CL12
CL13
CL14
Remark
(CL-tRCD-tRP)
DDR3L-1066 7-7-7
DDR3L-1333 9-9-9
DDR3L-1600 11-11-11
1866
DDR3L-1866 13-13-13
4
Package Ballout/Mechanical Dimension
x8 Package Ball out (Top view): 78ball FBGA Package (no support balls)
1
2
3
4
5
6
7
8
9
A
VSS
VDD
NC
NU/TDQS
VSS
VDD
A
B
VSS
VSSQ
DQ0
DM/TDQS
VSSQ
VDDQ
B
C
VDDQ
DQ2
DQS
DQ1
DQ3
VSSQ
C
D
VSSQ
DQ6
DQS
VDD
VSS
VSSQ
D
E
VREFDQ
VDDQ
DQ4
DQ7
DQ5
VDDQ
E
F
NC
VSS
RAS
CK
VSS
NC
F
G
ODT
VDD
CAS
CK
VDD
CKE
G
H
NC
CS
WE
A10/AP
ZQ
NC
H
J
VSS
BA0
BA2
NC
VREFCA
VSS
J
K
VDD
A3
A0
A12/BC
BA1
VDD
K
L
VSS
A5
A2
A1
A4
VSS
L
M
VDD
A7
A9
A11
A6
VDD
M
N
VSS
RESET
A13
NC
A8
VSS
N
1
2
3
7
8
9
1 2 3
4
5
6
7 8 9
A
B
C
D
E
F
G
H
(Top View: See the balls through the Package)
Populated ball
Ball not populated
J
K
L
M
N
Rev. 1.0 /July. 2012
5
x16 Package Ball out (Top view): 96ball FBGA Package (no support balls)
1
2
3
A
VDDQ
DQU5
B
VSSQ
VDD
C
VDDQ
DQU3
D
VSSQ
E
VSS
F
4
5
6
7
8
9
DQU7
DQU4
VDDQ
VSS
A
VSS
DQSU#
DQU6
VSSQ
B
DQU1
DQSU
DQU2
VDDQ
C
VDDQ
DMU
DQU0
VSSQ
VDD
D
VSSQ
DQL0
DML
VSSQ
VDDQ
E
VDDQ
DQL2
DQSL
DQL1
DQL3
VSSQ
F
G
VSSQ
DQL6
DQSL#
VDD
VSS
VSSQ
G
H
VREFDQ
VDDQ
DQL4
DQL7
DQL5
VDDQ
H
J
NC
VSS
RAS#
CK
VSS
NC
J
K
ODT
VDD
CAS#
CK#
VDD
CKE
K
L
NC
CS#
WE#
A10/AP
ZQ
NC
L
M
VSS
BA0
BA2
NC
VREFCA
VSS
M
N
VDD
A3
A0
A12/BC#
BA1
VDD
N
P
VSS
A5
A2
A1
A4
VSS
P
R
VDD
A7
A9
A11
A6
VDD
R
T
VSS
RESET#
NC
NC
A8
VSS
T
1
2
3
7
8
9
1
2
3
7
8
4
5
6
9
A
B
C
D
E
F
G
H
J
(Top View: See the balls through the Package)
Populated ball
Ball not populated
K
L
M
N
P
R
T
Rev. 1.0 /July. 2012
6
Pin Functional Description
Symbol
Type
Function
CK, CK
Input
Clock: CK and CK are differential clock inputs. All address and control input signals are
sampled on the crossing of the positive edge of CK and negative edge of CK.
CKE, (CKE0),
(CKE1)
Input
Clock Enable: CKE HIGH activates, and CKE Low deactivates, internal clock signals and
device input buffers and output drivers. Taking CKE Low provides Precharge Power-Down
and Self-Refresh operation (all banks idle), or Active Power-Down (row Active in any
bank).
CKE is asynchronous for Self-Refresh exit. After VREFCA and VREFDQ have become stable
during the power on and initialization sequence, they must be maintained during all
operations (including Self-Refresh). CKE must be maintained high throughout read and
write accesses. Input buffers, excluding CK, CK, ODT and CKE, are disabled during powerdown. Input buffers, excluding CKE, are disabled during Self-Refresh.
CS, (CS0),
(CS1), (CS2),
(CS3)
Input
Chip Select: All commands are masked when CS is registered HIGH.
CS provides for external Rank selection on systems with multiple Ranks.
CS is considered part of the command code.
ODT, (ODT0),
(ODT1)
Input
On Die Termination: ODT (registered HIGH) enables termination resistance internal to the
DDR3 SDRAM. When enabled, ODT is only applied to each DQ, DQS, DQS and DM/TDQS,
NU/TDQS (When TDQS is enabled via Mode Register A11=1 in MR1) signal for x8
configurations. For x16 configuration, ODT is applied to each DQ, DQSU, DQSU, DQSL,
DQSL, DMU, and DML signal. The ODT pin will be ignored if MR1 is programmed to disable
ODT.
RAS.
CAS. WE
Input
Command Inputs: RAS, CAS and WE (along with CS) define the command being entered.
DM, (DMU),
(DML)
Input
Input Data Mask: DM is an input mask signal for write data. Input data is masked when
DM is sampled HIGH coincident with that input data during a Write access. DM is sampled
on both edges of DQS. For x8 device, the function of DM or TDQS/TDQS is enabled by
Mode Register A11 setting in MR1.
BA0 - BA2
Input
Bank Address Inputs: BA0 - BA2 define to which bank an Active, Read, Write or Precharge
command is being applied. Bank address also determines if the mode register or extended
mode register is to be accessed during a MRS cycle.
Input
Address Inputs: Provide the row address for Active commands and the column address for
Read/Write commands to select one location out of the memory array in the respective
bank. (A10/AP and A12/BC have additional functions, see below).
The address inputs also provide the op-code during Mode Register Set commands.
A10 / AP
Input
Auto-precharge: A10 is sampled during Read/Write commands to determine whether
Autoprecharge should be performed to the accessed bank after the Read/Write operation.
(HIGH: Autoprecharge; LOW: no Autoprecharge).A10 is sampled during a Precharge
command to determine whether the Precharge applies to one bank (A10 LOW) or all
banks (A10 HIGH). If only one bank is to be precharged, the bank is selected by bank
addresses.
A12 / BC
Input
Burst Chop: A12 / BC is sampled during Read and Write commands to determine if burst
chop (on-the-fly) will be performed.
(HIGH, no burst chop; LOW: burst chopped). See command truth table for details.
A0 - A15
Rev. 1.0 /July. 2012
7
Symbol
Type
Function
Active Low Asynchronous Reset: Reset is active when RESET is LOW, and inactive when
RESET is HIGH. RESET must be HIGH during normal operation.
RESET is a CMOS rail-to-rail signal with DC high and low at 80% and 20% of VDD, i.e.
1.20V for DC high and 0.30V for DC low.
RESET
Input
DQ
Input /
Output
Data Input/ Output: Bi-directional data bus.
Input /
Output
Data Strobe: output with read data, input with write data. Edge-aligned with read data,
centered in write data. The data strobe DQS, DQSL, and DQSU are paired with differential
signals DQS, DQSL, and DQSU, respectively, to provide differential pair signaling to the
system during reads and writes. DDR3 SDRAM supports differential data strobe only and
does not support single-ended.
Output
Termination Data Strobe: TDQS/TDQS is applicable for x8 DRAMs only. When enabled via
Mode Register A11 = 1 in MR1, the DRAM will enable the same termination resistance
function on TDQS/TDQS that is applied to DQS/DQS. When disabled via mode register A11
= 0 in MR1, DM/TDQS will provide the data mask function and TDQS is not used. x16
DRAMs must disable the TDQS function via mode register A11 = 0 in MR1.
DQU, DQL,
DQS, DQS,
DQSU, DQSU,
DQSL, DQSL
TDQS, TDQS
NC
No Connect: No internal electrical connection is present.
NF
No Function
VDDQ
Supply
DQ Power Supply: 1.5 V +/- 0.075 V
VSSQ
Supply
DQ Ground
VDD
Supply
Power Supply: 1.5 V +/- 0.075 V
VSS
Supply
Ground
VREFDQ
Supply
Reference voltage for DQ
VREFCA
Supply
Reference voltage for CA
ZQ
Supply
Reference Pin for ZQ calibration
Note:
Input only pins (BA0-BA2, A0-A15, RAS, CAS, WE, CS, CKE, ODT, DM, and RESET) do not supply termination.
Rev. 1.0 /July. 2012
8
ROW AND COLUMN ADDRESS TABLE
1Gb
Configuration
# of Banks
Bank Address
Auto precharge
BL switch on the fly
Row Address
Column Address
Page size 1
128Mb x 8
64Mb x 16
8
BA0 - BA2
A10/AP
A12/BC
A0 - A13
A0 - A9
1 KB
8
BA0 - BA2
A10/AP
A12/BC
A0 - A12
A0 - A9
2 KB
Note1: Page size is the number of bytes of data delivered from the array to the internal sense amplifiers
when an ACTIVE command is registered. Page size is per bank, calculated as follows:
page size = 2 COLBITS * ORG 8
where COLBITS = the number of column address bits, ORG = the number of I/O (DQ) bits
Rev. 1.0 /July. 2012
9
Absolute Maximum Ratings
Absolute Maximum DC Ratings
Absolute Maximum DC Ratings
Symbol
VDD
VDDQ
Parameter
Rating
Units
Notes
Voltage on VDD pin relative to Vss
- 0.4 V ~ 1.975 V
V
1,3
Voltage on VDDQ pin relative to Vss
- 0.4 V ~ 1.975 V
V
1,3
V
1
VIN, VOUT Voltage on any pin relative to Vss
TSTG
- 0.4 V ~ 1.975 V
-55 to +100
Storage Temperature
o
C
1, 2
Notes:
1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2. Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement
conditions, please refer to JESD51-2 standard.
3. VDD and VDDQ must be within 300mV of each other at all times; and VREF must not be greater than
0.6XVDDQ,When VDD and VDDQ are less than 500mV; VREF may be equal to or less than 300mV.
DRAM Component Operating Temperature Range
Temperature Range
Symbol
TOPER
Parameter
Normal Operating Temperature Range
Industrial Temperature Range
Rating
Units
Notes
0 to 85
oC
1,2
-40 to 95
oC
1,3
Notes:
1. Operating Temperature TOPER is the case surface temperature on the center / top side of the DRAM. For measurement conditions, please refer to the JEDEC document JESD51-2.
2. The Normal Temperature Range specifies the temperatures where all DRAM specifications will be supported. During operation, the DRAM case temperature must be maintained between 0 - 85oC under all operating conditions.
3. Some applications require operation of the DRAM in the Extended Temperature Range between 85oC and 95oC
case temperature. Full specifications are guaranteed in this range, but the following additional conditions apply:
a. Refresh commands must be doubled in frequency, therefore reducing the Refresh interval tREFI to 3.9 µs.
b. If Self-Refresh operation is required in the Extended Temperature Range, then it is mandatory to use the Manual Self-Refresh mode with Extended Temperature Range capability (MR2 A6 = 0b and MR2 A7 = 1b).
Rev. 1.0 /July. 2012
10
AC & DC Operating Conditions
Recommended DC Operating Conditions
Recommended DC Operating Conditions - DDR3L (1.35V) operation
Symbol
VDD
VDDQ
Parameter
Rating
Units
Notes
1.45
V
1,2,3,4
1.45
V
1,2,3,4
Min.
Typ.
Max.
Supply Voltage
1.283
1.35
Supply Voltage for Output
1.283
1.35
Notes:
1. Maximum DC value may not be greater than 1.425V. The DC value is the linear average of VDD/VDDQ (t) over a
very long period of time (e.g., 1 sec).
2. If maximum limit is exceeded, input levels shall be governed by DDR3 specifications.
3. Under these supply voltages, the device operates to this DDR3L specification.
4. Once initialized for DDR3L operation, DDR3 operation may only be used if the device is in reset while VDD and
VDDQ are changed for DDR3 operation (see Figure 0).
Recommended DC Operating Conditions - DDR3 (1.5V) operation
Symbol
VDD
VDDQ
Parameter
Rating
Units
Notes
1.575
V
1,2,3
1.575
V
1,2,3
Min.
Typ.
Max.
Supply Voltage
1.425
1.5
Supply Voltage for Output
1.425
1.5
Notes:
1. If minimum limit is exceeded, input levels shall be governed by DDR3L specifications.
2. Under 1.5V operation, this DDR3L device operates to the DDR3 specifications under the same speed timings as
defined for this device.
3. Once initialized for DDR3 operation, DDR3L operation may only be used if the device is in reset while VDD and
VDDQ are changed for DDR3L operation (see Figure 0).
Rev. 1.0 /July. 2012
11
Ta
Tb
Tc
Td
Te
Tf
Tg
Th
Ti
Tj
Tk
CK,CK#
VDD, VDDQ (DDR3)
tCKSRX
Tmin = 10ns
VDD, VDDQ (DDR3L)
Tmin = 10ns
Tmin = 200us
T = 500us
RESET#
Tmin = 10ns
CKE
VALID
tDLLK
tIS
COMMAND
READ
BA
READ
1)
tXPR
tMRD
tMRD
tMRD
tMOD
MRS
MRS
MRS
MRS
MR2
MR3
MR1
MR0
tZQinit
ZQCL
1)
VALID
VALID
tIS
ODT
READ
tIS
Static LOW in case RTT_Nom is enabled at time Tg, otherwise static HIGH or LOW
VALID
RTT
NOTE 1: From time point “Td” until “Tk” NOP or DES commands must be applied
between MRS and ZQCL commands.
TIME BREAK
DON’T CARE
Figure 0 - VDD/VDDQ Voltage Switch Between DDR3L and DDR3
Rev. 1.0 /July. 2012
12
IDD and IDDQ Specification Parameters and Test Conditions
IDD and IDDQ Measurement Conditions
In this chapter, IDD and IDDQ measurement conditions such as test load and patterns are defined. Figure
1. shows the setup and test load for IDD and IDDQ measurements.
•
IDD currents (such as IDD0, IDD1, IDD2N, IDD2NT, IDD2P0, IDD2P1, IDD2Q, IDD3N, IDD3P, IDD4R,
IDD4W, IDD5B, IDD6, IDD6ET, and IDD7) are measured as time-averaged currents with all VDD balls
of the DDR3 SDRAM under test tied together. Any IDDQ current is not included in IDD currents.
•
IDDQ currents (such as IDDQ2NT and IDDQ4R) are measured as time-averaged currents with all
VDDQ balls of the DDR3 SDRAM under test tied together. Any IDD current is not included in IDDQ currents.
Attention: IDDQ values cannot be directly used to calculate IO power of the DDR3 SDRAM. They can
be used to support correlation of simulated IO power to actual IO power as outlined in Figure 2. In
DRAM module application, IDDQ cannot be measured separately since VDD and VDDQ are using one
merged-power layer in Module PCB.
For IDD and IDDQ measurements, the following definitions apply:
•
”0” and “LOW” is defined as VIN <= VILAC(max).
•
”1” and “HIGH” is defined as VIN >= VIHAC(min).
•
“MID_LEVEL” is defined as inputs are VREF = VDD/2.
•
Timing used for IDD and IDDQ Measurement-Loop Patterns are provided in Table 1.
•
Basic IDD and IDDQ Measurement Conditions are described in Table 2.
•
Detailed IDD and IDDQ Measurement-Loop Patterns are described in Table 3 through Table 10.
•
IDD Measurements are done after properly initializing the DDR3 SDRAM. This includes but is not limited to setting
RON = RZQ/7 (34 Ohm in MR1);
Qoff = 0B (Output Buffer enabled in MR1);
RTT_Nom = RZQ/6 (40 Ohm in MR1);
RTT_Wr = RZQ/2 (120 Ohm in MR2);
TDQS Feature disabled in MR1
•
Attention: The IDD and IDDQ Measurement-Loop Patterns need to be executed at least one time
before actual IDD or IDDQ measurement is started.
•
Define D = {CS, RAS, CAS, WE}:= {HIGH, LOW, LOW, LOW}
•
Define D = {CS, RAS, CAS, WE}:= {HIGH, HIGH, HIGH, HIGH}
Rev. 1.0 /July. 2012
13
IDDQ (optional)
IDD
VDD
VDDQ
RESET
CK/CK
DDR3L
SDRAM
CKE
CS
RAS, CAS, WE
DQS, DQS
DQ, DM,
TDQS, TDQS
A, BA
ODT
ZQ
VSS
RTT = 25 Ohm
VDDQ/2
VSSQ
Figure 1 - Measurement Setup and Test Load for IDD and IDDQ (optional) Measurements
[Note: DIMM level Output test load condition may be different from above]
Application specific
memory channel
environment
IDDQ
Test Load
Channel
IO Power
Simulation
IDDQ
Simulation
IDDQ
Simulation
Correction
Channel IO Power
Number
Figure 2 - Correlation from simulated Channel IO Power to actual Channel IO Power supported
by IDDQ Measurement
Rev. 1.0 /July. 2012
14
Table 1 -Timings used for IDD and IDDQ Measurement-Loop Patterns
Symbol
DDR3L-1066
DDR3L-1333
DDR3L-1600
DDR3L-1866
7-7-7
9-9-9
11-11-11
13-13-13
Unit
tCK
1.875
1.5
1.25
1.07
ns
CL
7
9
11
13
nCK
nRCD
7
9
11
13
nCK
nRC
27
33
39
45
nCK
nRAS
20
24
28
32
nCK
nRP
7
9
11
13
nCK
1KB page size
20
20
24
26
nCK
2KB page size
27
30
32
33
nCK
1KB page size
4
4
5
5
nCK
2KB page size
6
5
6
6
nCK
nRFC -512Mb
48
60
72
85
nCK
nRFC-1 Gb
59
74
88
103
nCK
nRFC- 2 Gb
86
107
128
150
nCK
nRFC- 4 Gb
160
200
240
281
nCK
nRFC- 8 Gb
187
234
280
328
nCK
nFAW
nRRD
Table 2 -Basic IDD and IDDQ Measurement Conditions
Symbol
Description
Operating One Bank Active-Precharge Current
CKE: High; External clock: On; tCK, nRC, nRAS, CL: see Table 1; BL: 8a); AL: 0; CS: High between ACT
IDD0
and PRE; Command, Address, Bank Address Inputs: partially toggling according to Table 3; Data IO:
MID-LEVEL; DM: stable at 0; Bank Activity: Cycling with one bank active at a time: 0,0,1,1,2,2,... (see
Table 3); Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Pattern Details:
see Table 3.
Operating One Bank Active-Read-Precharge Current
CKE: High; External clock: On; tCK, nRC, nRAS, nRCD, CL: see Table 1; BL: 8a); AL: 0; CS: High between
IDD1
ACT, RD and PRE; Command, Address; Bank Address Inputs, Data IO: partially toggling according to
Table 4; DM: stable at 0; Bank Activity: Cycling with on bank active at a time: 0,0,1,1,2,2,... (see Table
4); Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Pattern Details: see
Table 4.
Rev. 1.0 /July. 2012
15
Symbol
Description
Precharge Standby Current
CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: stable at 1; Command, Address,
IDD2N
Bank Address Inputs: partially toggling according to Table 5; Data IO: MID-LEVEL; DM: stable at 0; Bank
Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0;
Pattern Details: see Table 5.
Precharge Standby ODT Current
CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: stable at 1; Command, Address,
IDD2NT
Bank Address Inputs: partially toggling according to Table 6; Data IO: MID-LEVEL; DM: stable at 0; Bank
Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: toggling
according to Table 6; Pattern Details: see Table 6.
Precharge Power-Down Current Slow Exit
CKE: Low; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: stable at 1; Command, Address,
IDD2P0
Bank Address Inputs: stable at 0; Data IO: MID-LEVEL; DM: stable at 0; Bank Activity: all banks closed;
Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Precharge Power Down
Mode: Slow Exitc)
Precharge Power-Down Current Fast Exit
CKE: Low; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: stable at 1; Command, Address,
IDD2P1
Bank Address Inputs: stable at 0; Data IO: MID-LEVEL; DM: stable at 0; Bank Activity: all banks closed;
Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Precharge Power Down
Mode: Fast Exitc)
Precharge Quiet Standby Current
IDD2Q
CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: stable at 1; Command, Address,
Bank Address Inputs: stable at 0; Data IO: MID-LEVEL; DM: stable at 0; Bank Activity: all banks closed;
Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0
Active Standby Current
CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: stable at 1; Command, Address,
IDD3N
Bank Address Inputs: partially toggling according to Table 5; Data IO: MID-LEVEL; DM: stable at 0; Bank
Activity: all banks open; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0;
Pattern Details: see Table 5.
Rev. 1.0 /July. 2012
16
Symbol
Description
Active Power-Down Current
IDD3P
CKE: Low; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: stable at 1; Command, Address,
Bank Address Inputs: stable at 0; Data IO: MID-LEVEL; DM: stable at 0; Bank Activity: all banks open;
Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0
Operating Burst Read Current
CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: High between RD; Command,
IDD4R
Address, Bank Address Inputs: partially toggling according to Table 7; Data IO: seamless read data burst
with different data between one burst and the next one according to Table 7; DM: stable at 0; Bank
Activity: all banks open, RD commands cycling through banks: 0,0,1,1,2,2,...(see Table 7); Output Buffer
and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Pattern Details: see Table 7.
Operating Burst Write Current
CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: High between WR; Command,
IDD4W
Address, Bank Address Inputs: partially toggling according to Table 8; Data IO: seamless read data burst
with different data between one burst and the next one according to Table 8; DM: stable at 0; Bank
Activity: all banks open, WR commands cycling through banks: 0,0,1,1,2,2,...(see Table 8); Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at HIGH; Pattern Details: see Table 8.
Burst Refresh Current
CKE: High; External clock: On; tCK, CL, nRFC: see Table 1; BL: 8a); AL: 0; CS: High between REF; Com-
IDD5B
mand, Address, Bank Address Inputs: partially toggling according to Table 9; Data IO: MID-LEVEL; DM:
stable at 0; Bank Activity: REF command every nREC (see Table 9); Output Buffer and RTT: Enabled in
Mode Registersb); ODT Signal: stable at 0; Pattern Details: see Table 9.
Self-Refresh Current: Normal Temperature Range
TCASE: 0 - 85 oC; Auto Self-Refresh (ASR): Disabledd);Self-Refresh Temperature Range (SRT): Normale);
IDD6
CKE: Low; External clock: Off; CK and CK: LOW; CL: see Table 1; BL: 8a); AL: 0; CS, Command, Address,
Bank Address Inputs, Data IO: MID-LEVEL; DM: stable at 0; Bank Activity: Self-Refresh operation; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: MID-LEVEL
Self-Refresh Current: Extended Temperature Range
TCASE: 0 - 95 oC; Auto Self-Refresh (ASR): Disabledd);Self-Refresh Temperature Range (SRT): ExtendIDD6ET
ede); CKE: Low; External clock: Off; CK and CK: LOW; CL: see Table 1; BL: 8a); AL: 0; CS, Command,
Address, Bank Address Inputs, Data IO: MID-LEVEL; DM: stable at 0; Bank Activity: Extended Temperature Self-Refresh operation; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: MIDLEVEL
Rev. 1.0 /July. 2012
17
Symbol
Description
Operating Bank Interleave Read Current
CKE: High; External clock: On; tCK, nRC, nRAS, nRCD, NRRD, nFAW, CL: see Table 1; BL: 8a)f); AL: CL-1;
CS: High between ACT and RDA; Command, Address, Bank Address Inputs: partially toggling according
IDD7
to Table 10; Data IO: read data burst with different data between one burst and the next one according
to Table 10; DM: stable at 0; Bank Activity: two times interleaved cycling through banks (0, 1,...7) with
different addressing, wee Table 10; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal:
stable at 0; Pattern Details: see Table 10.
a) Burst Length: BL8 fixed by MRS: set MR0 A[1,0]=00B
b) Output Buffer Enable: set MR1 A[12] = 0B; set MR1 A[5,1] = 01B; RTT_Nom enable: set MR1 A[9,6,2] = 011B;
RTT_Wr enable: set MR2 A[10,9] = 10B
c) Precharge Power Down Mode: set MR0 A12=0B for Slow Exit or MR0 A12 = 1B for Fast Exit
d) Auto Self-Refresh (ASR): set MR2 A6 = 0B to disable or 1B to enable feature
e) Self-Refresh Temperature Range (SRT): set MR2 A7 = 0B for normal or 1B for extended temperature range
f) Read Burst Type: Nibble Sequential, set MR0 A[3] = 0B
Rev. 1.0 /July. 2012
18
Command
CS
RAS
CAS
WE
ODT
BA[2:0]
A[15:11]
A[10]
A[9:7]
A[6:3]
A[2:0]
0
ACT
0
0
1
1
0
0
00
0
0
0
0
-
1,2
D, D
1
0
0
0
0
0
00
0
0
0
0
-
3,4
D, D
1
1
1
1
0
0
00
0
0
0
0
-
0
0
0
-
Cycle
Number
Datab)
Sub-Loop
CKE
CK, CK
Table 3 - IDD0 Measurement-Loop Patterna)
0
...
nRAS
Static High
toggling
...
repeat pattern 1...4 until nRAS - 1, truncate if necessary
PRE
0
0
1
0
0
0
00
0
repeat pattern 1...4 until nRC - 1, truncate if necessary
1*nRC+0
ACT
0
0
1
1
0
0
00
0
0
F
0
-
1*nRC+1, 2
D, D
1
0
0
0
0
0
00
0
0
F
0
-
1*nRC+3, 4
D, D
1
1
1
1
0
0
00
0
0
F
0
-
...
1*nRC+nRAS
repeat pattern nRC+1...4 until 1*nRC + nRAS - 1, truncate if necessary
PRE
0
0
1
0
0
0
00
0
0
F
...
repeat pattern nRC+1...4 until 2*nRC - 1, truncate if necessary
1
2*nRC
repeat Sub-Loop 0, use BA[2:0] = 1 instead
2
4*nRC
repeat Sub-Loop 0, use BA[2:0] = 2 instead
3
6*nRC
repeat Sub-Loop 0, use BA[2:0] = 3 instead
4
8*nRC
repeat Sub-Loop 0, use BA[2:0] = 4 instead
5
10*nRC
repeat Sub-Loop 0, use BA[2:0] = 5 instead
6
12*nRC
repeat Sub-Loop 0, use BA[2:0] = 6 instead
7
14*nRC
repeat Sub-Loop 0, use BA[2:0] = 7 instead
0
-
a) DM must be driven LOW all the time. DQS, DQS are MID-LEVEL.
b) DQ signals are MID-LEVEL.
Rev. 1.0 /July. 2012
19
CAS
WE
ODT
BA[2:0]
A[15:11]
A[10]
A[9:7]
A[6:3]
A[2:0]
ACT
0
0
1
1
0
0
00
0
0
0
0
-
D, D
1
0
0
0
0
0
00
0
0
0
0
-
3,4
D, D
1
1
1
1
0
0
00
0
0
0
0
-
0
0
00000000
0
0
0
-
0
F
0
-
nRCD
...
nRAS
...
1*nRC+0
Static High
Datab)
1,2
...
toggling
RAS
0
CS
0
Command
Cycle
Number
Sub-Loop
CKE
CK, CK
Table 4 - IDD1 Measurement-Loop Patterna)
repeat pattern 1...4 until nRCD - 1, truncate if necessary
RD
0
1
0
1
0
0
00
0
0
repeat pattern 1...4 until nRAS - 1, truncate if necessary
PRE
0
0
1
0
0
0
00
0
repeat pattern 1...4 until nRC - 1, truncate if necessary
ACT
0
0
1
1
0
0
00
0
1*nRC+1,2
D, D
1
0
0
0
0
0
00
0
0
F
0
-
1*nRC+3,4
D, D
1
1
1
1
0
0
00
0
0
F
0
-
...
1*nRC+nRCD
...
1*nRC+nRAS
repeat pattern nRC + 1,...4 until nRC + nRCD - 1, truncate if necessary
RD
0
1
0
1
0
0
00
0
0
F
0
00110011
repeat pattern nRC + 1,...4 until nRC + nRAS - 1, truncate if necessary
PRE
0
0
1
0
0
0
00
0
0
F
...
repeat pattern nRC + 1,...4 until 2* nRC - 1, truncate if necessary
1
2*nRC
repeat Sub-Loop 0, use BA[2:0] = 1 instead
2
4*nRC
repeat Sub-Loop 0, use BA[2:0] = 2 instead
3
6*nRC
repeat Sub-Loop 0, use BA[2:0] = 3 instead
4
8*nRC
repeat Sub-Loop 0, use BA[2:0] = 4 instead
5
10*nRC
repeat Sub-Loop 0, use BA[2:0] = 5 instead
6
12*nRC
repeat Sub-Loop 0, use BA[2:0] = 6 instead
7
14*nRC
repeat Sub-Loop 0, use BA[2:0] = 7 instead
0
-
a) DM must be driven LOW all the time. DQS, DQS are used according to RD Commands, otherwise MID-LEVEL.
b) Burst Sequence driven on each DQ signal by Read Command. Outside burst operation, DQ signals are MID-LEVEL.
Rev. 1.0 /July. 2012
20
Static High
CS
RAS
CAS
WE
ODT
BA[2:0]
A[15:11]
A[10]
A[9:7]
A[6:3]
A[2:0]
0
D
1
0
0
0
0
0
0
0
0
0
0
-
1
D
1
0
0
0
0
0
0
0
0
0
0
-
2
D
1
1
1
1
0
0
0
0
0
F
0
-
3
D
1
1
1
1
0
0
0
0
0
F
0
-
Cycle
Number
Command
0
toggling
Datab)
Sub-Loop
CKE
CK, CK
Table 5 - IDD2N and IDD3N Measurement-Loop Patterna)
1
4-7
repeat Sub-Loop 0, use BA[2:0] = 1 instead
2
8-11
repeat Sub-Loop 0, use BA[2:0] = 2 instead
3
12-15
repeat Sub-Loop 0, use BA[2:0] = 3 instead
4
16-19
repeat Sub-Loop 0, use BA[2:0] = 4 instead
5
20-23
repeat Sub-Loop 0, use BA[2:0] = 5 instead
6
24-27
repeat Sub-Loop 0, use BA[2:0] = 6 instead
7
28-31
repeat Sub-Loop 0, use BA[2:0] = 7 instead
a) DM must be driven LOW all the time. DQS, DQS are MID-LEVEL.
b) DQ signals are MID-LEVEL.
Static High
CS
RAS
CAS
WE
ODT
BA[2:0]
A[15:11]
A[10]
A[9:7]
A[6:3]
A[2:0]
0
D
1
0
0
0
0
0
0
0
0
0
0
-
1
D
1
0
0
0
0
0
0
0
0
0
0
-
2
D
1
1
1
1
0
0
0
0
0
F
0
-
3
D
1
1
1
1
0
0
0
0
0
F
0
-
Cycle
Number
Command
0
toggling
Datab)
Sub-Loop
CKE
CK, CK
Table 6 - IDD2NT and IDDQ2NT Measurement-Loop Patterna)
1
4-7
repeat Sub-Loop 0, but ODT = 0 and BA[2:0] = 1
2
8-11
repeat Sub-Loop 0, but ODT = 1 and BA[2:0] = 2
3
12-15
repeat Sub-Loop 0, but ODT = 1 and BA[2:0] = 3
4
16-19
repeat Sub-Loop 0, but ODT = 0 and BA[2:0] = 4
5
20-23
repeat Sub-Loop 0, but ODT = 0 and BA[2:0] = 5
6
24-27
repeat Sub-Loop 0, but ODT = 1 and BA[2:0] = 6
7
28-31
repeat Sub-Loop 0, but ODT = 1 and BA[2:0] = 7
a) DM must be driven LOW all the time. DQS, DQS are MID-LEVEL.
b) DQ signals are MID-LEVEL.
Rev. 1.0 /July. 2012
21
1
Static High
CAS
WE
ODT
BA[2:0]
A[15:11]
A[10]
A[9:7]
A[6:3]
A[2:0]
Datab)
RD
0
1
0
1
0
0
00
0
0
0
0
00000000
D
1
0
0
0
0
0
00
0
0
0
0
-
2,3
D,D
1
1
1
1
0
0
00
0
0
0
0
-
4
RD
0
1
0
1
0
0
00
0
0
F
0
00110011
D
1
0
0
0
0
0
00
0
0
F
0
-
D,D
1
1
1
1
0
0
00
0
0
F
0
-
5
toggling
RAS
0
CS
0
Command
Cycle
Number
Sub-Loop
CKE
CK, CK
Table 7 - IDD4R and IDDQ4R Measurement-Loop Patterna)
6,7
1
8-15
repeat Sub-Loop 0, but BA[2:0] = 1
2
16-23
repeat Sub-Loop 0, but BA[2:0] = 2
3
24-31
repeat Sub-Loop 0, but BA[2:0] = 3
4
32-39
repeat Sub-Loop 0, but BA[2:0] = 4
5
40-47
repeat Sub-Loop 0, but BA[2:0] = 5
6
48-55
repeat Sub-Loop 0, but BA[2:0] = 6
7
56-63
repeat Sub-Loop 0, but BA[2:0] = 7
a) DM must be driven LOW all the time. DQS, DQS are used according to RD Commands, otherwise MID-LEVEL.
b) Burst Sequence driven on each DQ signal by Read Command. Outside burst operation, DQ signals are MID-LEVEL.
Rev. 1.0 /July. 2012
22
1
Static High
CAS
WE
ODT
BA[2:0]
A[15:11]
A[10]
A[9:7]
A[6:3]
A[2:0]
Datab)
WR
0
1
0
0
1
0
00
0
0
0
0
00000000
D
1
0
0
0
1
0
00
0
0
0
0
-
2,3
D,D
1
1
1
1
1
0
00
0
0
0
0
-
4
WR
0
1
0
0
1
0
00
0
0
F
0
00110011
D
1
0
0
0
1
0
00
0
0
F
0
-
D,D
1
1
1
1
1
0
00
0
0
F
0
-
5
toggling
RAS
0
CS
0
Command
Cycle
Number
Sub-Loop
CKE
CK, CK
Table 8 - IDD4W Measurement-Loop Patterna)
6,7
1
8-15
repeat Sub-Loop 0, but BA[2:0] = 1
2
16-23
repeat Sub-Loop 0, but BA[2:0] = 2
3
24-31
repeat Sub-Loop 0, but BA[2:0] = 3
4
32-39
repeat Sub-Loop 0, but BA[2:0] = 4
5
40-47
repeat Sub-Loop 0, but BA[2:0] = 5
6
48-55
repeat Sub-Loop 0, but BA[2:0] = 6
7
56-63
repeat Sub-Loop 0, but BA[2:0] = 7
a) DM must be driven LOW all the time. DQS, DQS are used according to WR Commands, otherwise MID-LEVEL.
b) Burst Sequence driven on each DQ signal by Write Command. Outside burst operation, DQ signals are MID-LEVEL.
Command
CS
RAS
CAS
WE
ODT
BA[2:0]
A[15:11]
A[10]
A[9:7]
A[6:3]
A[2:0]
0
0
REF
0
0
0
1
0
0
0
0
0
0
0
-
1
1.2
D, D
1
0
0
0
0
0
00
0
0
0
0
-
D, D
1
1
1
1
0
0
00
0
0
F
0
-
Cycle
Number
Datab)
Sub-Loop
CKE
CK, CK
Table 9 - IDD5B Measurement-Loop Patterna)
Static High
toggling
3,4
2
5...8
repeat cycles 1...4, but BA[2:0] = 1
9...12
repeat cycles 1...4, but BA[2:0] = 2
13...16
repeat cycles 1...4, but BA[2:0] = 3
17...20
repeat cycles 1...4, but BA[2:0] = 4
21...24
repeat cycles 1...4, but BA[2:0] = 5
25...28
repeat cycles 1...4, but BA[2:0] = 6
29...32
repeat cycles 1...4, but BA[2:0] = 7
33...nRFC-1
repeat Sub-Loop 1, until nRFC - 1. Truncate, if necessary.
a) DM must be driven LOW all the time. DQS, DQS are MID-LEVEL.
b) DQ signals are MID-LEVEL.
Rev. 1.0 /July. 2012
23
Table 10 - IDD7 Measurement-Loop Patterna)
0
1
2
3
4
Static High
5
6
7
8
toggling
9
10
0
1
2
...
nRRD
nRRD+1
nRRD+2
...
2*nRRD
3*nRRD
4*nRRD
nFAW
nFAW+nRRD
nFAW+2*nRRD
nFAW+3*nRRD
nFAW+4*nRRD
2*nFAW+0
2*nFAW+1
2*nFAW+2
11
2*nFAW+nRRD
2*nFAW+nRRD+1
2*nFAW+nRRD+2
12
13
2*nFAW+2*nRRD
2*nFAW+3*nRRD
14
2*nFAW+4*nRRD
15
16
17
18
3*nFAW
3*nFAW+nRRD
3*nFAW+2*nRRD
3*nFAW+3*nRRD
19
3*nFAW+4*nRRD
A[2:0]
A[6:3]
A[9:7]
A[10]
A[15:11]
BA[2:0]
ODT
WE
CAS
RAS
CS
Command
Cycle
Number
Sub-Loop
CKE
CK, CK
ATTENTION! Sub-Loops 10-19 have inverse A[6:3] Pattern and Data Pattern than Sub-Loops 0-9
ACT
0
0
1
1
0
0
00
0
0
0
0
RDA
0
1
0
1
0
0
00
1
0
0
0
D
1
0
0
0
0
0
00
0
0
0
0
repeat above D Command until nRRD - 1
ACT
0
0
1
1
0
1
00
0
0
F
0
RDA
0
1
0
1
0
1
00
1
0
F
0
D
1
0
0
0
0
1
00
0
0
F
0
repeat above D Command until 2* nRRD - 1
repeat Sub-Loop 0, but BA[2:0] = 2
repeat Sub-Loop 1, but BA[2:0] = 3
D
1
0
0
0
0
3
00
0
0
F
0
Assert and repeat above D Command until nFAW - 1, if necessary
repeat Sub-Loop 0, but BA[2:0] = 4
repeat Sub-Loop 1, but BA[2:0] = 5
repeat Sub-Loop 0, but BA[2:0] = 6
repeat Sub-Loop 1, but BA[2:0] = 7
D
1
0
0
0
0
7
00
0
0
F
0
Assert and repeat above D Command until 2* nFAW - 1, if necessary
ACT
0
0
1
1
0
0
00
0
0
F
0
RDA
0
1
0
1
0
0
00
1
0
F
0
D
1
0
0
0
0
0
00
0
0
F
0
Repeat above D Command until 2* nFAW + nRRD - 1
ACT
0
0
1
1
0
1
00
0
0
0
0
RDA
0
1
0
1
0
1
00
1
0
0
0
D
1
0
0
0
0
1
00
0
0
0
0
Repeat above D Command until 2* nFAW + 2* nRRD - 1
repeat Sub-Loop 10, but BA[2:0] = 2
repeat Sub-Loop 11, but BA[2:0] = 3
D
1
0
0
0
0
3
00
0
0
0
0
Assert and repeat above D Command until 3* nFAW - 1, if necessary
repeat Sub-Loop 10, but BA[2:0] = 4
repeat Sub-Loop 11, but BA[2:0] = 5
repeat Sub-Loop 10, but BA[2:0] = 6
repeat Sub-Loop 11, but BA[2:0] = 7
D
1
0
0
0
0
7
00
0
0
0
0
Assert and repeat above D Command until 4* nFAW - 1, if necessary
Datab)
00000000
00110011
-
-
00110011
00000000
-
-
-
a) DM must be driven LOW all the time. DQS, DQS are used according to RD Commands, otherwise MID-LEVEL.
b) Burst Sequence driven on each DQ signal by Read Command. Outside burst operation, DQ signals are MID-LEVEL.
Rev. 1.0 /July. 2012
24
IDD Specifications
IDD values are for full operating range of voltage and temperature unless otherwise noted.
IDD Specification
Speed Grade Bin
Symbol
IDD0
IDD1
IDD2N
IDD2NT
IDD2P0
IDD2P1
IDD2Q
IDD3N
IDD3P
IDD4R
IDD4W
IDD5B
IDD6
IDD6ET
IDD6 Low Power
IDD7
DDR3L - 1066
7-7-7
Max.
32
42
40
55
16
18
20
22
12
15
18
18
18
32
10
20
65
108
60
100
75
100
12
15
5
125
196
DDR3L - 1333
9-9-9
Max.
35
44
46
58
18
20
22
26
12
15
18
20
20
35
10
22
80
125
68
115
75
100
12
15
5
150
198
DDR3L - 1600
11-11-11
Max.
40
46
54
60
20
22
24
28
12
15
20
22
22
35
12
22
90
145
80
130
80
105
12
15
5
175
208
DDR3L - 1866
13-13-13
Max.
45
48
58
62
22
24
26
30
12
18
20
24
24
38
12
24
100
165
90
145
85
110
12
15
5
205
225
Unit
Notes
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
x8
x16
x8
x16
x8
x16
x8
x16
x8/x16
x8/x16
x8
x16
x8
x16
x8
x16
x8
x16
x8
x16
x8
x16
x8/x16
x8/x16
x8/x16
x8
x16
Notes:
1. Applicable for MR2 settings A6=0 and A7=0. Temperature range for IDD6 is 0 - 85oC.
2. Applicable for MR2 settings A6=0 and A7=1. Temperature range for IDD6ET is 0 - 95oC.
Rev. 1.0 /July. 2012
25
Input/Output Capacitance
Parameter
Symbol
DDR3L-1066
Input/output capacitance
CIO
(DQ, DM, DQS, DQS,
TDQS, TDQS)
Input capacitance, CK and
CCK
CK
Input capacitance delta
CDCK
CK and CK
Input capacitance delta,
CDDQS
DQS and DQS
Input capacitance
CI
(All other input-only pins)
Input capacitance delta
CDI_CTRL
(All CTRL input-only pins)
Input capacitance delta
CDI_ADD_
(All ADD/CMD input-only
CMD
pins)
Input/output capacitance
CDIO
delta
(DQ, DM, DQS, DQS)
Input/output capacitance
CZQ
of ZQ pin
Notes:
DDR3L-1333
DDR3L-1600 DDR3L-1866 Unit Note
s
s
Min
Max
Min
Max
Min
Max
Min
Max
1.5
2.7
1.5
2.5
1.5
2.3
1.4
2.2
pF 1,2,3
0.8
1.6
0.8
1.4
0.8
1.4
0.8
1.3
pF
0
0.15
0
0.15
0
0.15
0
0.15
pF 2,3,4
0
0.20
0
0.15
0
0.15
0
0.15
pF 2,3,5
0.75
1.35
0.75
1.3
0.75
1.3
0.75
1.2
pF 2,3,6
-0.5
0.3
-0.4
0.2
-0.4
0.2
-0.4
0.2
pF
2,3,7,
8
-0.5
0.5
-0.4
0.4
-0.4
0.4
-0.4
0.4
pF
2,3,9,
10
-0.5
0.3
-0.5
0.3
-0.5
0.3
-0.5
0.3
pF
2,3,
11
-
3
-
3
-
3
-
3
pF
2,3,
12
2,3
1. Although the DM, TDQS and TDQS pins have different functions, the loading matches DQ and DQS.
2. This parameter is not subject to production test. It is verified by design and characterization. The capacitance is
measured according to JEP147(“PROCEDURE FOR MEASURING INPUT CAPACITANCE USING A VECTOR NETWORK
ANALYZER(VNA)”) with VDD, VDDQ, VSS,VSSQ applied and all other pins floating (except the pin under test, CKE,
RESET and ODT as necessary). VDD=VDDQ=1.5V, VBIAS=VDD/2 and on-die termination off.
3. This parameter applies to monolithic devices only; stacked/dual-die devices are not covered here
4. Absolute value of CCK-CCK.
5. Absolute value of CIO(DQS)-CIO(DQS).
6. CI applies to ODT, CS, CKE, A0-A15, BA0-BA2, RAS, CAS, WE.
7. CDI_CTR applies to ODT, CS and CKE.
8. CDI_CTRL=CI(CNTL) - 0.5 * CI(CLK) + CI(CLK))
9. CDI_ADD_CMD applies to A0-A15, BA0-BA2, RAS, CAS and WE.
10. CDI_ADD_CMD=CI(ADD_CMD) - 0.5*(CI(CLK)+CI(CLK))
11. CDIO=CIO(DQ) - 0.5*(CIO(DQS)+CIO(DQS))
12. Maximum external load capacitance an ZQ pin: 5 pF.
Rev. 1.0 /July. 2012
26
Standard Speed Bins
DDR3L SDRAM Standard Speed Bins include tCK, tRCD, tRP, tRAS and tRC for each corresponding bin.
DDRL3-1066 Speed Bins
For specific Notes see “Speed Bin Table Notes” on page 31.
Speed Bin
CL - nRCD - nRP
Parameter
DDR3L-1066 G7
Unit
7-7-7
Symbol
min
max
Internal read command to first
data
tAA
13.125
20
ns
ACT to internal read or write
delay time
tRCD
13.125
—
ns
PRE command period
tRP
13.125
—
ns
ACT to ACT or REF command
period
tRC
50.625
—
ns
ACT to PRE command period
tRAS
37.5
9 * tREFI
ns
CWL = 5
tCK(AVG)
3.0
3.3
ns
CWL = 6
tCK(AVG)
CWL = 5
tCK(AVG)
CWL = 6
tCK(AVG)
CWL = 5
tCK(AVG)
CWL = 6
tCK(AVG)
CWL = 5
tCK(AVG)
CWL = 6
tCK(AVG)
CL = 5
CL = 6
CL = 7
CL = 8
1,2,3,4,6,
ns
10,11
4
ns
1,2,3,6
Reserved
ns
1,2,3,4
Reserved
ns
4
ns
1,2,3,4
ns
4
ns
1,2,3
13
Reserved
2.5
3.3
1.875
< 2.5
Reserved
1.875
< 2.5
Supported CL Settings
5, 6, 7, 8
nCK
Supported CWL Settings
5, 6
nCK
Rev. 1.0 /July. 2012
Note
27
DDR3L-1333 Speed Bins
For specific Notes see “Speed Bin Table Notes” on page 31.
Speed Bin
CL - nRCD - nRP
Parameter
DDR3L-1333 H9
Symbol
Internal read command to first
data
tAA
ACT to internal read or write
delay time
tRCD
PRE command period
tRP
ACT to ACT or REF command
period
tRC
ACT to PRE command period
tRAS
CWL = 5
tCK(AVG)
CWL = 6, 7
tCK(AVG)
CWL = 5
tCK(AVG)
CWL = 6
tCK(AVG)
CWL = 7
CL = 5
CL = 6
CL = 7
CL = 8
CL = 9
CL = 10
Unit
9-9-9
min
13.5
Note
max
20
ns
—
ns
—
ns
—
ns
36
9 * tREFI
ns
3.0
3.3
ns
(13.125)11
13.5
(13.125)11
13.5
(13.125)11
49.5
(49.125)11
1,2,3,4,7,
ns
10,11
4
ns
1,2,3,7
Reserved
ns
1,2,3,4,7
tCK(AVG)
Reserved
ns
4
CWL = 5
tCK(AVG)
Reserved
ns
4
CWL = 6
tCK(AVG)
(Optional)
ns
1,2,3,4,7
CWL = 7
tCK(AVG)
Note 5,11
Reserved
ns
1,2,3,4
CWL = 5
tCK(AVG)
CWL = 6
tCK(AVG)
CWL = 7
tCK(AVG)
CWL = 5, 6
tCK(AVG)
CWL = 7
tCK(AVG)
CWL = 5, 6
tCK(AVG)
CWL = 7
tCK(AVG)
Reserved
2.5
3.3
1.875
< 2.5
ns
4
ns
1,2,3,7
Reserved
ns
1,2,3,4
Reserved
ns
4
ns
1,2,3,4
ns
4
(Optional)
ns
ns
1,2,3
5
Supported CL Settings
5,6,(7),9,(10)
nCK
Supported CWL Settings
5, 6, 7
nCK
Rev. 1.0 /July. 2012
Reserved
1.875
< 2.5
1.5
<1.875
Reserved
1.5
<1.875
28
DDR3L-1600 Speed Bins
For specific Notes see “Speed Bin Table Notes” on page 31.
Speed Bin
CL - nRCD - nRP
Parameter
DDR3L-1600 PB
Symbol
Internal read command to first
data
tAA
ACT to internal read or write
delay time
tRCD
PRE command period
tRP
ACT to ACT or REF command
period
tRC
ACT to PRE command period
tRAS
CWL = 5
tCK(AVG)
CWL = 6, 7, 8
CWL = 5
CWL = 6
CWL = 7, 8
CWL = 5
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
CWL = 6
tCK(AVG)
CL = 5
CL = 6
CL = 7
CL = 8
CL = 9
CL = 10
CL = 11
CWL = 7
CWL = 8
CWL = 5
CWL = 6
CWL = 7
CWL = 8
CWL = 5, 6
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
CWL = 7
tCK(AVG)
min
13.75
20
ns
—
ns
—
ns
—
ns
35
9 * tREFI
ns
3.0
3.3
ns
(13.125)11
13.75
(13.125)11
48.75
(48.125)11
2.5
ns
1,2,3,4,8
ns
ns
ns
ns
ns
ns
ns
1,2,3,4,8
4
4
1,2,3,8
1,2,3,4,8
1,2,3,4
4
ns
1,2,3,4,8
<1.875
ns
ns
ns
ns
ns
1,2,3,4
4
1,2,3,8
1,2,3,4
4
<1.5
ns
1,2,3
Reserved
Reserved
Reserved
< 2.5
(Optional)
Note 5,11
Reserved
Reserved
Reserved
1.875
< 2.5
Reserved
Reserved
Reserved
1.5
<1.875
(Optional)
Note 5,11
Reserved
Reserved
1.5
CWL = 8
tCK(AVG)
1.25
Rev. 1.0 /July. 2012
10,11
4
1,2,3,8
1,2,3,4,8
4
4
3.3
1.875
1,2,3,4,8,
ns
ns
ns
ns
ns
Reserved
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
Note
max
(13.125)11
13.75
CWL = 8
CWL = 5, 6
CWL = 7
CWL = 8
CWL = 5, 6,7
Supported CL Settings
Supported CWL Settings
Unit
11-11-11
Reserved
Reserved
5,6,(7),8,(9),10,11
5, 6, 7, 8
nCK
nCK
29
DDR3L-1866 Speed Bins
For specific Notes See "Speed Bin Table Notes" on page 31.
Speed Bin
DDR3L-1866 RD
CL - nRCD - nRP
13-13-13
Parameter
Symbol
Internal read command to
first data
tAA
ACT to internal read or
write delay time
tRCD
PRE command period
tRP
ACT to PRE command
period
ACT to ACT or PRE
command period
CWL = 5
CL = 5
CWL = 6,7,8,9
tRAS
CWL = 5
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
CWL = 6
tCK(AVG)
CWL = 7,8,9
CWL = 5, 6
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
CWL = 7
tCK(AVG)
CWL = 8
CWL = 5,6,7
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
CWL = 8
tCK(AVG)
CWL = 9
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
CWL = 5
CL = 6
CWL = 6
CWL = 7,8,9
CL = 7
CWL = 5
CL = 8
CWL = 6
CWL = 7
CWL = 8,9
CL = 9
CWL = 9
CWL = 5, 6
CL = 10
CWL = 7
CWL = 8
CL = 11
CL = 12
CL = 13
tRC
CWL = 5,6,7,8
CWL = 9
CWL = 5,6,7,8
CWL = 9
Unit
min
13.91(13.125)
(Optional Note 5,11)
max
20
ns
—
ns
—
ns
9 * tREFI
ns
-
ns
13.91(13.125)
(Optional Note 5,11)
13.91(13.125)
(Optional Note 5,11)
34
47.91(47.125)
(Optional Note 5,11)
Reserved
Reserved
2.5
3.3
ns
1, 2, 3, 4, 9
ns
4
ns
1, 2, 3, 9
Reserved
ns
1, 2, 3, 4, 9
Reserved
ns
4
Reserved
ns
4
1, 2, 3, 4,
9,11
4
1.875 (Optional)
< 2.5 (Optional)
Reserved
ns
ns
Reserved
ns
4
ns
1, 2, 3, 9
Reserved
ns
1, 2, 3, 4, 9
Reserved
ns
4
Reserved
ns
4
1, 2, 3, 4,
9,11
1, 2, 3, 4, 9
1.875
< 2.5
1.5 (Optional)
<1.875 (Optional)
ns
Reserved
ns
Reserved
Reserved
ns
4
ns
4
1.5
<1.875
Reserved
Reserved
1.25 (Optional)
<1.5 (Optional)
ns
1, 2, 3, 9
ns
1, 2, 3, 4, 9
ns
4
1, 2, 3, 4,
9,11
1, 2, 3, 4
ns
Reserved
ns
Reserved
ns
4
Reserved
ns
1,2,3,4
Reserved
ns
4
ns
1, 2, 3
1.07
<1.25
Supported CL Settings
6, (7), 8, (9), 10, (11), 13
nCK
Supported CWL Settings
5, 6, 7, 8, 9
nCK
Rev. 1.0 /July. 2012
Note
30
Speed Bin Table Notes
Absolute Specification (TOPER; VDDQ = VDD = 1.5V +/- 0.075 V);
1. The CL setting and CWL setting result in tCK(AVG).MIN and tCK(AVG).MAX requirements. When making a selection of tCK(AVG), both need to be fulfilled: Requirements from CL setting as well as requirements from CWL setting.
2. tCK(AVG).MIN limits: Since CAS Latency is not purely analog - data and strobe output are synchronized by the DLL - all possible intermediate frequencies may not be guaranteed. An application should
use the next smaller JEDEC standard tCK(AVG) value (3.0, 2.5, 1.875, 1.5, or 1.25 ns) when calculating CL [nCK] = tAA [ns] / tCK(AVG) [ns], rounding up to the next ‘Supported CL’, where tCK(AVG) =
3.0 ns should only be used for CL = 5 calculation.
3. tCK(AVG).MAX limits: Calculate tCK(AVG) = tAA.MAX / CL SELECTED and round the resulting tCK(AVG)
down to the next valid speed bin (i.e. 3.3ns or 2.5ns or 1.875 ns or 1.25 ns). This result is
tCK(AVG).MAX corresponding to CL SELECTED.
4. ‘Reserved’ settings are not allowed. User must program a different value.
5. ‘Optional’ settings allow certain devices in the industry to support this setting, however, it is not a mandatory feature. Refer to SK hynix Inc. DIMM data sheet and/or the DIMM SPD information if and how
this setting is supported.
6. Any DDR3-1066 speed bin also supports functional operation at lower frequencies as shown in the
table which are not subject to Production Tests but verified by Design/Characterization.
7. Any DDR3-1333 speed bin also supports functional operation at lower frequencies as shown in the
table which are not subject to Production Tests but verified by Design/Characterization.
8. Any DDR3-1600 speed bin also supports functional operation at lower frequencies as shown in the
table which are not subject to Production Tests but verified by Design/Characterization.
9. Any DDR3-1866 speed bin also supports functional operation at lower frequencies as shown in the
table which are not subject to Production Tests but verified by Design/Characterization.
10. Any DDR3-2133 speed bin also supports functional operation at lower frequencies as shown in the
table which are not subject to Production Tests but verified by Design/Characterization.
11. SK hynix Inc. DDR3 SDRAM devices supporting optional down binning to CL=7, 9 and CL=11, and tAA/
tRCD/tRP must be 13.125 ns. SPD settings must be programmed to match. For example, DDR3-1866
RD devices supporting down binning to DDR3-1600K or DDR3-1333 H9 or 1066 G7 should program
13.125 ns in SPD bytes for tAAmin (Byte 16), tRCDmin (Byte 18), and tRPmin (Byte 20). Once tRP
(Byte 20) is programmed to 13.125ns, tRCmin (Byte 21,23) also should be programmed accordingly.
For example, 49.125ns (tRASmin + tRPmin = 36 ns + 13.125 ns) for DDR3-1333 H9 and 48.125ns
(tRASmin + tRPmin = 35 ns + 13.125 ns) for DDR3-1600 PB.
12. For CL5 support, refer to DIMM SPD information. DRAM is required to support CL5. CL5 is not mandatory in SPD coding.
Rev. 1.0 /July. 2012
31
Package Dimensions
Package Dimension(x8): 78Ball Fine Pitch Ball Grid Array Outline
Rev. 1.0 /July. 2012
32
Package Dimension(x16): 96Ball Fine Pitch Ball Grid Array Outline
Rev. 1.0 /July. 2012
33