PRELIMINARY Am186 EM/EMLV and Am188 EM/EMLV TM TM High Performance, 80C186-/80C188-Compatible and 80L186-/80L188-Compatible, 16-Bit Embedded Microcontrollers DISTINCTIVE CHARACTERISTICS TM n E86 family 80C186- and 80C188-compatible microcontrollers with enhanced bus interface — Lower system cost with higher performance — 3.3- V ±.3 -V ope ra tio n (A m1 86E MLV and Am188EMLV microcontrollers) n High performance — 20-, 25-, 33-, and 40-MHz operating frequencies — Supports zero-wait-state operation at 25 MHz with 110-ns static memory (Am186TMEMLV and Am188 TM EMLV microcontrollers) and 40 MHz with 70-ns static memory (Am186 TM EM and Am188TMEM microcontrollers) — 1-Mbyte memory address space — 64-Kbyte I/O space n New features provide faster access to memory and remove the requirement for a 2x clock input — Nonmultiplexed address bus — Phase-locked loop (PLL) allows processor to operate at the clock input frequency n New integrated peripherals provide increased functionality while reducing system cost — Thirty-two programmable I/O (PIO) pins n n n n — Asynchronous serial port allows full-duplex, 7-bit or 8-bit data transfers — Synchronous serial interface allows half-duplex, bidirectional data transfer to and from ASICs — Pseudo static RAM (PSRAM) controller includes auto refresh capability — Reset configuration register Familiar 80C186/80L186 peripherals — Two independent DMA channels — Programmable interrupt controller with six external interrupts — Three programmable 16-bit timers—timer 1 can be used as a watchdog interrupt timer — Programmable memory and peripheral chip-select logic — Programmable wait state generator — Power-save clock divider Software-compatible with the 80C186/80C188 and 80L186 /80L188 microcontrollers Widely available native development tools, applications, and system software Available in the following packages: — 100-pin, thin quad flat pack (TQFP) — 100-pin, plastic quad flat pack (PQFP) GENERAL DESCRIPTION The Am186TMEM/EMLV and Am188TMEM/EMLV microcontrollers are the ideal upgrade for 80C186/188 and 80L186/188 microcontroller designs requiring 80C186/ 188 and 80L186/188 microcontroller compatibility, increased performance, serial communications, and a direct bus interface. The Am186EM/EMLV and Am188EM/EMLV microcontrollers increase the performance of existing 80C186/188 and 80L186/188 systems while decreasing their cost. The Am186EM/EMLV and Am188EM/EMLV microcontrollers are part of the AMD E86 family of embedded microcontrollers and microprocessors based on the x86 architecture. The E86 family includes the 16- and 32-bit microcontrollers and microprocessors described on page 8 The Am186EM/EMLV and Am188EM/EMLV microcontrollers integrate the functions of the CPU, nonmultiplexed address bus, timers, chip selects, interrupt controller, DMA controller, PSRAM controller, asynchronous serial port, synchronous serial interface, and programmable I/O (PIO) pins on one chip. Compared to the 80C186/188 and 80L186/188 microcontrollers, the Am186EM/EMLV and Am188EM/EMLV microcontrollers enable designers to reduce the size, power consumption, and cost of embedded systems, while increasing functionality and performance. The Am186EM/EMLV and Am188EM/EMLV microcontrollers have been designed to meet the most common requirements of embedded products developed for the office automation, mass storage, communications, and general embedded markets. Specific applications include disk drives, hand-held terminals and desktop terminals, fax machines, printers, photocopiers, feature phones, cellular phones, PBXs, multiplexers, modems, and industrial controls. This document contains information on a product under development at Advanced Micro Devices. The information is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed product without notice. Publication# 19168 Rev: E Amendment/0 Issue Date: February 1997 P R E L I M I N A R Y Am186EM MICROCONTROLLER BLOCK DIAGRAM INT2/INTA0 INT3/INTA1/IRQ CLKOUTA INT1/SELECT INT4 TMROUT0 INT0 CLKOUTB TMRIN0 NMI VCC Interrupt Control Unit GND Control Registers TMRIN1 Timer Control Unit 0 1 (WDT) Max Count B Registers Max Count A Registers 16-Bit Count Registers Control Registers X2 X1 Clock and Power Management Unit TMROUT1 DRQ1 DMA Unit 2 0 1 20-Bit Source Pointers 20-Bit Destination Pointers 16-Bit Count Registers Control Registers Control Registers Control Registers DRQ0 RES Control Registers ARDY SRDY Refresh Control Unit PSRAM Control Unit Control Registers Bus Interface Unit DEN Asynchronous Serial Port HOLD Chip-Select Unit Execution Unit PIO31– PIO0* Control Registers S2–S0 DT/R PIO Unit TXD RXD Control Registers HLDA S6/ CLKDIV2 UZI Synchronous Serial Interface RD WHB A19–A0 WLB AD15–AD0 WR BHE/ADEN SCLK PCS6/A2 LCS/ONCE0 SDATA SDEN0 SDEN1 PCS5/A1 MCS3/RFSH MCS2–MCS0 PCS3–PCS0 UCS/ONCE1 ALE Note: * All PIO signals are shared with other physical pins. See the pin descriptions beginning on page 25 and Table 2 on page 30 for information on shared functions. 2 Am186/188EM and Am186/188EMLV Microcontrollers P R E L I M I N A R Y Am188EM MICROCONTROLLER BLOCK DIAGRAM INT2/INTA0 INT3/INTA1/IRQ CLKOUTA INT1/SELECT INT4 TMROUT0 INT0 CLKOUTB TMRIN0 NMI VCC Interrupt Control Unit GND Control Registers TMRIN1 Timer Control Unit 0 1 (WDT) Max Count B Registers Max Count A Registers 16-Bit Count Registers Control Registers X2 X1 Clock and Power Management Unit TMROUT1 DRQ1 DMA Unit 2 0 1 20-Bit Source Pointers 20-Bit Destination Pointers 16-Bit Count Registers Control Registers Control Registers Control Registers DRQ0 RES Control Registers PSRAM Control Unit Refresh Control Unit ARDY SRDY Control Registers PIO Unit Control Registers Asynchronous Serial Port S2–S0 DT/R Bus Interface Unit DEN HOLD Chip-Select Unit Execution Unit PIO31– PIO0* TXD RXD Control Registers HLDA S6/ CLKDIV2 UZI Synchronous Serial Interface RD A19–A0 SCLK PCS6/A2 LCS/ONCE0 AO15–AO8 WB AD7–AD0 WR RFSH2/ADEN SDATA SDEN0 SDEN1 PCS5/A1 MCS3/RFSH MCS2–MCS0 PCS3–PCS0 UCS/ONCE1 ALE Note: * All PIO signals are shared with other physical pins. See the pin descriptions beginning on page 25 and Table 2 on page 30 for information on shared functions. Am186/188EM and Am186/188EMLV Microcontrollers 3 P R E L I M I N A R Y ORDERING INFORMATION Standard Products AMD standard products are available in several packages and operating ranges. The order numbers (valid combinations) are formed by a combination of the elements below. Am186EM V –40 C \W LEAD FORMING \W=Trimmed and Formed TEMPERATURE RANGE C=EM Commercial (TC =0°C to +100°C) C=EMLV Commercial (TA =0°C to +70°C) I=EM Industrial (TA =–40°C to +85°C) (5-V only) Where: TC = case temperature TA = ambient temperature PACKAGE TYPE V=100-pin, thin quad flat pack (TQFP) K=100-pin, plastic quad flat pack (PQFP) SPEED OPTION –20 = 20 MHz –25 = 25 MHz –33 = 33 MHz –40 = 40 MHz DEVICE NUMBER/DESCRIPTION Am186EM High-Performance, 80C186-Compatible, 16-Bit Embedded Microcontroller Am188EM High-Performance, 80C188-Compatible, 16-Bit Embedded Microcontroller Am186EMLV High-Performance, 80L186-Compatible, Low-Voltage, 16-Bit Embedded Microcontroller Am188EMLV High-Performance, 80L188-Compatible, Low-Voltage, 16-Bit Embedded Microcontroller Valid Combinations 4 Valid Combinations Valid combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations. Am186EM–20 Am186EM–25 Am186EM–33 Am186EM–40 VC\W or KC\W Am188EM–20 Am188EM–25 Am188EM–33 Am188EM–40 VC\W or KC\W Am186EM–20 Am186EM–25 KI\W Notes: 1. The Am186EM and Am188EM industrial microcontrollers, as well as the Am186EMLV and Am188EMLV commercial microcontrollers, are available in 20- and 25-MHz operating frequencies only. Am188EM–20 Am188EM–25 KI\W 2. The Am186EM and Am188EM industrial microcontrollers are not offered in a low-voltage operating range. Am186EMLV–20 Am186EMLV–25 VC\W or KC\W Am188EMLV–20 Am188EMLV–25 VC\W or KC\W 3. The Am186EM, Am188EM, Am186EMLV, and Am188EMLV microcontrollers are all functionally the same except for their DC characteristics and available frequencies. Am186/188EM and Am186/188EMLV Microcontrollers P R E L I M I N A R Y TABLE OF CONTENTS Distinctive Characteristics ............................................................................................................ 1 General Description ..................................................................................................................... 1 Am186EM Microcontroller Block Diagram .................................................................................... 2 Am188EM Microcontroller Block Diagram .................................................................................... 3 Ordering Information .................................................................................................................... 4 Related AMD Products ................................................................................................................ 8 Key Features and Benefits ........................................................................................................ 10 TQFP Connection Diagrams and Pinouts .................................................................................. 11 PQFP Connection Diagrams and Pinouts ................................................................................. 17 Logic Symbol—Am186EM Microcontroller ................................................................................ 23 Logic Symbol—Am188EM Microcontroller ................................................................................ 24 Pin Descriptions Pins that Are Used by Emulators ................................................................................... 25 A19–A0 ........................................................................................................................... 25 AD7–AD0 ....................................................................................................................... 25 AD15–AD8 (Am186EM Microcontroller) ......................................................................... 25 AO15–AO8 (Am188EM Microcontroller) ........................................................................ 25 ALE ................................................................................................................................ 25 ARDY ............................................................................................................................. 25 BHE/ADEN (Am186EM Microcontroller Only) ............................................................... 26 CLKOUTA ...................................................................................................................... 26 CLKOUTB ...................................................................................................................... 26 DEN/PIO5 ...................................................................................................................... 26 DRQ1–DRQ0 .................................................................................................................. 26 DT/R/PIO4 ..................................................................................................................... 26 GND ............................................................................................................................... 27 HLDA ............................................................................................................................. 27 HOLD ............................................................................................................................. 27 INT0 ............................................................................................................................... 27 INT1/SELECT ................................................................................................................ 27 INT2/INTA0/PIO31 ......................................................................................................... 27 INT3/INTA1/IRQ ............................................................................................................. 27 INT4/PIO30 .................................................................................................................... 28 LCS/ONCE0 ................................................................................................................... 28 MCS3/RFSH/PIO25 ....................................................................................................... 28 MCS2–MCS0 .................................................................................................................. 28 NMI ................................................................................................................................ 28 PCS3–PCS0 ................................................................................................................... 29 PCS5/A1/PIO3 ............................................................................................................... 29 PCS6/A2/PIO2 ............................................................................................................... 29 PIO31–PIO0 (Shared) .................................................................................................... 29 RD .................................................................................................................................. 31 RES ................................................................................................................................ 31 RFSH2/ADEN (Am188EM Microcontroller Only) ........................................................... 31 RXD/PIO28 .................................................................................................................... 31 S2–S0 ............................................................................................................................ 31 S6/CLKDIV2/PIO29 ....................................................................................................... 31 SCLK/PIO20 .................................................................................................................. 32 SDATA/PIO21 ................................................................................................................ 32 SDEN1/PIO23, SDEN0/PIO22 ....................................................................................... 32 SRDY/PIO6 .................................................................................................................... 32 TMRIN0/PIO11 .............................................................................................................. 32 Am186/188EM and Am186/188EMLV Microcontrollers 5 P R E L I M I N A R Y TMRIN1/PIO0 ................................................................................................................ 32 TMROUT0/PIO10 .......................................................................................................... 32 TMROUT1/PIO1 ............................................................................................................ 32 TXD/PIO27 ..................................................................................................................... 32 UCS/ONCE1 .................................................................................................................. 32 UZI/PIO26 ...................................................................................................................... 33 VCC ................................................................................................................................. 33 WHB (Am186EM Microcontroller Only) ......................................................................... 33 WLB (Am186EM Microcontroller Only) ........................................................................... 33 WB (Am188EM Microcontroller Only) ............................................................................ 33 WR ................................................................................................................................. 33 X1 ................................................................................................................................... 33 X2 ................................................................................................................................... 33 Functional Description ............................................................................................................... 34 Bus Operation ............................................................................................................................ 35 Bus Interface Unit ....................................................................................................................... 37 Peripheral Control Block (PCB) ................................................................................................. 38 Clock and Power Management .................................................................................................. 41 Chip-Select Unit.......................................................................................................................... 43 Refresh Control Unit .................................................................................................................. 45 Interrupt Control Unit ................................................................................................................. 45 Timer Control Unit ...................................................................................................................... 46 Direct Memory Access (DMA) ................................................................................................... 46 Asynchronous Serial Port .......................................................................................................... 48 Synchronous Serial Interface ..................................................................................................... 48 Programmable I/O (PIO) Pins .................................................................................................... 50 Absolute Maximum Ratings ....................................................................................................... 51 Operating Ranges ...................................................................................................................... 51 DC Characteristics Over Commercial Operating Range ........................................................... 51 Commercial Switching Characteristics and Waveforms ............................................................ 60 6 Am186/188EM and Am186/188EMLV Microcontrollers P R E L I M I N A R Y LIST OF FIGURES Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Example System Design ........................................................................................ 10 Two-Component Address ...................................................................................... 34 Am186EM Microcontroller Address Bus—Normal Read and Write Operation ...... 35 Am186EM Microcontroller—Read and Write with Address Bus Disable In Effect ..................................................................................................... 36 Am188EM Microcontroller Address Bus—Normal Read and Write Operation ...... 36 Am188EM Microcontroller—Read and Write with Address Bus Disable In Effect ..................................................................................................... 37 Peripheral Control Block Register Map .................................................................. 39 Am186EM and Am188EM Microcontrollers Oscillator Configurations ................... 41 Clock Organization ................................................................................................ 42 DMA Unit Block Diagram ....................................................................................... 47 Synchronous Serial Interface Multiple Write .......................................................... 49 Synchronous Serial Interface Multiple Read .......................................................... 49 Typical ICC Versus Frequency for the Am186EMLV and Am188EMLV ................ 53 Typical ICC Versus Frequency for the Am186EM and Am188EM ......................... 53 Thermal Resistance(°C/Watt) ................................................................................ 54 Thermal Characteristics Equations ........................................................................ 54 Typical Ambient Temperatures for PQFP with 2-Layer Board ............................... 56 Typical Ambient Temperatures for TQFP with 2-Layer Board ............................... 57 Typical Ambient Temperatures for PQFP with 4-Layer to 6-Layer Board ............. 58 Typical Ambient Temperatures for TQFP with 4-Layer to 6-Layer Board .............. 59 LIST OF TABLES Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Data Byte Encoding ............................................................................................... 26 Numeric PIO Pin Assignments .............................................................................. 30 Alphabetic PIO Pin Assignments ........................................................................... 30 Bus Cycle Encoding ............................................................................................... 31 Segment Register Selection Rules ........................................................................ 34 Am186EM Microcontroller Maximum DMA Transfer Rates ................................... 46 Typical Power Consumption Calculation for the Am186EMLV and Am188EMLV ............................................................................ 53 Thermal Characteristics (°C/Watt) ......................................................................... 54 Typical Power Consumption Calculation ............................................................... 55 Junction Temperature Calculation ......................................................................... 55 Typical Ambient Temperatures for PQFP with 2-Layer Board ............................... 56 Typical Ambient Temperatures for TQFP with 2-Layer Board ............................... 57 Typical Ambient Temperatures for PQFP with 4-Layer to 6-Layer Board ............. 58 Typical Ambient Temperatures for TQFP with 4-Layer to 6-Layer Board .............. 59 Am186/188EM and Am186/188EMLV Microcontrollers 7 P R E L I M I N A R Y K86™ Future Microprocessors AMD-K5™ Microprocessor AT Peripheral Microcontrollers Am486DX Microprocessor 186 Peripheral Microcontrollers 32-bit Future ÉlanSC400 Microcontroller Am386SX/DX Microprocessors Am186ER and Am188ER Microcontrollers ÉlanSC310 Microcontroller Am186 and Am188 Future Am186ES and Am188ES Microcontrollers ÉlanSC300 Microcontroller 80C186 and 80C188 Microcontrollers Am486 Future Am186EM and Am188EM Microcontrollers Am186ESLV & Am188ESLV Microcontrollers Am186EMLV & Am188EMLV Microcontrollers 80L186 and 80L188 Microcontrollers Time The E86 Family of Embedded Microprocessors and Microcontrollers RELATED AMD PRODUCTS E86™ Family Devices Device 80C186 80C188 80L186 80L188 Am186EM Am188EM Am186EMLV Am188EMLV Description 16-bit microcontroller 16-bit microcontroller with 8-bit external data bus Low-voltage, 16-bit microcontroller Low-voltage, 16-bit microcontroller with 8-bit external data bus High-performance, 80C186-compatible, 16-bit embedded microcontroller High-performance, 80C188-compatible, 16-bit embedded microcontroller with 8-bit external data bus High-performance, 80C186-compatible, low-voltage, 16-bit embedded microcontroller High-performance, 80C188-compatible, low-voltage, 16-bit embedded microcontroller with 8-bit external data bus Am186ES High-performance, 80C186-compatible, 16-bit embedded microcontroller Am188ES High-performance, 80C188-compatible, 16-bit embedded microcontroller with 8-bit external data bus Am186ESLV High-performance, 80C186-compatible, low-voltage, 16-bit embedded microcontroller Am188ESLV High-performance, 80C188-compatible, low-voltage, 16-bit embedded microcontroller with 8-bit external data bus Am186ER High-performance, 80C186-compatible, low-voltage, 16-bit embedded microcontroller with 32 Kbyte of internal RAM Am188ER High-performance, 80C188-compatible, low-voltage, 16-bit embedded microcontroller with 8-bit external data bus and 32 Kbyte of internal RAM Élan™SC300 High-performance, highly integrated, low-voltage, 32-bit embedded microcontroller ÉlanSC310 High-performance, single-chip, 32-bit embedded PC/AT microcontroller ÉlanSC400 Single-chip, low-power, PC/AT-compatible microcontroller Am386®DX Am386SX High-performance, 32-bit embedded microprocessor with 32-bit external data bus High-performance, 32-bit embedded microprocessor with 16-bit external data bus Am486®DX High-performance, 32-bit embedded microprocessor with 32-bit external data bus 8 Am186/188EM and Am186/188EMLV Microcontrollers P R E L I M I N A R Y Related Documents Corporate Applications Hotline The following documents provide additional information regarding the Am186EM and Am188EM microcontrollers. 800-222-9323 Toll-free for U.S. and Canada 44-(0) 1276-803-299 U.K. and Europe hotline n The Am186EM and Am188EM Microcontrollers User’s Manual, order# 19713 World Wide Web Home Page and FTP Site n The Am186 and Am188 Family Instruction Set Manual, order# 21267 To a c c e s s t h e A M D h o m e pa g e g o t o h tt p : / / www.amd.com. n The FusionE86SM Catalog, order# 19255 To downl oad d ocu ments and s oftwar e, ftp t o ftp.amd.com and log on as anonymous using your E-mail address as a password. Or via your web browser, go to ftp://ftp.amd.com. Third-Party Development Support Products The FusionE86 Program of Partnerships for Application Solutions provides the customer with an array of products designed to meet critical time-to-market needs. Products and solutions available from the AMD FusionE86 partners include emulators, hardware and software debuggers, board-level products, and software development tools, among others. In addition, mature development tools and applications for the x86 platform are widely available in the general marketplace. Customer Service Questions, requests, and input concerning AMD’s WWW pages can be sent via E-mail to [email protected]. Documentation and Literature Free E86 family information such as data books, user’s man ual s , data sh eets , ap pl ic ati on n otes , th e FusionE86 Partner Solutions Catalog, and other literature is available with a simple phone call. Internationally, contact your local AMD sales office for complete E86 family literature. The AMD customer service network includes U.S. offices, international offices, and a customer training center. Expert technical assistance is available from the AMD worldwide staff of field application engineers and factory support staff who can answer E86 family hardware and software development questions. 800-222-9323 Toll-free for U.S. and Canada 512-602-5651 Direct dial worldwide Hotline and World Wide Web Support 800-222-9323 AMD Facts-On-Demand™ fax information service, toll-free for U.S. and Canada Literature Ordering For answers to technical questions, AMD provides a toll-free number for direct access to our corporate applications hotline. Also available is the AMD World Wide Web home page and FTP site, which provides the latest E86 family product information, including technical information and data on upcoming product releases. Am186/188EM and Am186/188EMLV Microcontrollers 9 P R E L I M I N A R Y KEY FEATURES AND BENEFITS The Am186EM and Am188EM microcontrollers extend the AMD family of microcontrollers based on the industry-standard x86 architecture. The Am186EM and Am188EM microcontrollers are higher-performance, more integrated versions of the 80C186/188 microprocessors, offering a migration path that was previously unava ilabl e. Upgr adi ng to the Am 186EM and Am188EM microcontrollers is an attractive solution for several reasons: n Minimized total system cost—New peripherals and on-chip system interface logic on the Am186EM and Am188EM microcontrollers reduce the cost of existing 80C186/188 designs. n X86 software compatibility—80C186/188-compatible and upward-compatible with the other members of the AMD E86 family. n Enhanced performance—The Am186EM and Am188EM microcontrollers increase the performance of 80C186/188 systems, and the demultiplexed address bus offers faster, unbuffered access to memory. n Enhanced functionality—The new and enhanced on-chip peripherals of the Am186EM and Am188EM microcontrollers include an asynchronous serial port, 32 PIOs, a watchdog timer, an additional interrupt pin, a synchronous serial interface, a PSRAM controller, a 16-bit reset configuration register, and enhanced chip-select functionality. Application Considerations The integration enhancements of the Am186EM and Am188EM microcontrollers provide a high-performance, low-system-cost solution for 16-bit embedded microcontroller designs. The nonmultiplexed address bus eliminates the need for system-support logic to interface memory devices, while the multiplexed address/data bus maintains the value of previously engineered, customer-specific peripherals and circuits within the upgraded design. Figure 1 illustrates an example system design that uses the integrated peripheral set to achieve high performance with reduced system cost. dress latch enable (ALE) signal is no longer needed. Individual byte-write-enable signals are provided to eliminate the need for external high/low byte-write-enable circuitry. The maximum bank size that is programmable for the memory chip-select signals has been increased to facilitate the use of high-density memory devices. The improved memory timing specifications for the Am186EM and Am188EM microcontrollers allow no wait-state operation with 70-ns memory access times at a 40-MHz CPU clock speed. This reduces overall system cost significantly by allowing the use of a more commonly available memory speed and technology. Direct Memory Interface Example Figure 1 illustrates the Am186EM microcontroller direct memory interface. The processor A19–A0 bus connects to the memory address inputs, the AD bus connects to the data inputs and outputs, and the chip selects connect to the memory chip-select inputs. The RD output connects to the SRAM Output Enable (OE) pin for read operations. Write operations use the byte write enables connected to the SRAM Write Enable (WE) pins. The example design uses 2-Mbit memory technology (256 Kbytes) to fully populate the available address space. Two flash PROM devices provide 512 Kbytes of nonvolatile program storage and two static RAM devices provide 512 Kbytes of data storage area. Figure 1 also shows an implementation of an RS-232 console or modem communications port. The RS-232to-CMOS voltage-level converter is required for the electrical interface with the external device. Am186EM Microcontroller X2 X1 40-MHz Crystal WHB WLB A19–A0 AD15–AD0 Clock Generation The integrated clock generation circuitry of the Am186EM and Am188EM microcontrollers allows the use of a times-one crystal frequency. The design in Figure 1 achieves 40-MHz CPU operation while using a 40-MHz crystal. 10 WE WE Address Data RD OE UCS CS Static RAM WE Serial Port RS-232 Level Converter WE TXD Address RXD Data Memory Interface The integrated memory controller logic of the Am186EM and Am188EM microcontrollers provides a direct address bus interface to memory devices. The use of an external address latch controlled by the ad- Flash PROM OE LCS Figure 1. CS Example System Design Am186/188EM and Am186/188EMLV Microcontrollers P R E L I M I N A R Y RES GND MCS3/ RFSH MCS2 VCC PCS 0 PCS 1 GND PCS 2 PCS 3 VCC PCS 5/A1 PCS 6/A2 LCS / ONCE 0 UCS / ONCE1 INT0 INT1/ SELECT INT2/INTA0 INT3/INTA1/IRQ 94 93 92 91 90 89 88 87 86 85 83 82 81 80 79 78 77 76 84 TMROUT1 TMRIN1 96 95 DRQ0 DRQ1 TMRIN0 TMROUT0 100 99 98 97 TQFP CONNECTION DIAGRAMS AND PINOUTS Am186EM Microcontroller Top Side View—100-Pin Thin Quad Flat Pack (TQFP) AD0 AD8 1 75 INT4 2 74 AD1 AD9 3 4 MCS1 MCS0 AD2 AD10 5 6 73 72 71 70 DEN DT/R NMI AD3 AD11 7 8 AD4 AD12 9 10 69 68 67 SRDY HOLD HLDA 66 AD5 GND 11 12 AD13 AD6 13 14 65 64 63 WLB WHB GND A0 62 A1 61 60 59 VCC A2 A3 58 A4 57 56 55 A5 A6 A7 54 A8 53 52 51 A9 A10 A11 VCC AD14 15 16 AD7 AD15 17 18 S6/CLKDIV2 19 20 38 39 40 41 42 43 44 45 46 47 48 49 50 CLKOUTB GND A19 A18 VCC A17 A16 A15 A14 A13 A12 32 33 S2 S1 VCC CLKOUTA 30 31 SCLK BHE/ADEN WR RD ALE ARDY 36 37 25 34 35 SDEN0 S0 23 24 26 27 SDATA SDEN1 GND X1 X2 21 22 28 29 UZI TXD RXD Am186EM Microcontroller Note: Pin 1 is marked for orientation. Am186/188EM and Am186/188EMLV Microcontrollers 11 P R E L I M I N A R Y TQFP PIN ASSIGNMENTS—Am186EM Microcontroller (Sorted by Pin Number) Pin No. Name 12 Pin No. Name Pin No. Name Pin No. Name 1 AD0 26 SCLK/PIO20 51 A11 76 INT3/INTA1/IRQ 2 AD8 27 BHE/ADEN 52 A10 77 INT2/INTA0 3 AD1 28 WR 53 A9 78 INT1/SELECT 4 AD9 29 RD 54 A8 79 INT0 5 AD2 30 ALE 55 A7 80 UCS/ONCE1 6 AD10 31 ARDY 56 A6 81 LCS/ONCE0 7 AD3 32 S2 57 A5 82 PCS6/A2/PIO2 8 AD11 33 S1 58 A4 83 PCS5/A1/PIO3 9 AD4 34 S0 59 A3 84 VCC 10 AD12 35 GND 60 A2 85 PCS3/PIO19 11 AD5 36 X1 61 VCC 86 PCS2/PIO18 12 GND 37 X2 62 A1 87 GND 13 AD13 38 VCC 63 A0 88 PCS1/PIO17 14 AD6 39 CLKOUTA 64 GND 89 PCS0/PIO16 15 VCC 40 CLKOUTB 65 WHB 90 VCC 16 AD14 41 GND 66 WLB 91 MCS2 17 AD7 42 A19/PIO9 67 HLDA 92 MCS3/RFSH 18 AD15 43 A18/PIO8 68 HOLD 93 GND 19 S6/CKLDIV2/PIO29 44 VCC 69 SRDY/PIO6 94 RES 20 UZI/PIO26 45 A17/PIO7 70 NMI 95 TMRIN1/PIO0 21 TXD 46 A16 71 DT/R/PIO4 96 TMROUT1/PIO1 22 RXD 47 A15 72 DEN/PIO5 97 TMROUT0/PIO10 23 SDATA/PIO21 48 A14 73 MCS0/PIO14 98 TMRIN0/PIO11 24 SDEN1/PIO23 49 A13 74 MCS1/PIO15 99 DRQ1/PIO13 25 SDEN0/PIO22 50 A12 75 INT4 100 DRQ0/PIO12 Am186/188EM and Am186/188EMLV Microcontrollers P R E L I M I N A R Y TQFP PIN ASSIGNMENTS—Am186EM Microcontroller (Sorted by Pin Name) Pin Name No. Pin Name No. Pin Name No. Pin Name No. A0 63 AD5 11 GND 93 S2 32 A1 62 AD6 14 HLDA 67 S6/CLKDIV2/PIO29 19 A2 60 AD7 17 HOLD 68 SCLK/PIO20 26 A3 59 AD8 2 INT0 79 SDATA/PIO21 23 A4 58 AD9 4 INT1/SELECT 78 SDEN0/PIO22 25 A5 57 AD10 6 INT2/INTA0 77 SDEN1/PIO23 24 A6 56 AD11 8 INT3/INTA1/IRQ 76 SRDY/PIO6 69 A7 55 AD12 10 INT4 75 TMRIN0/PIO11 98 A8 54 AD13 13 LCS/ONCE0 81 TMRIN1/PIO0 95 A9 53 AD14 16 MCS0/PIO14 73 TMROUT0/PIO10 97 A10 52 AD15 18 MCS1/PIO15 74 TMROUT1/PIO1 96 A11 51 ALE 30 MCS2 91 TXD 21 A12 50 ARDY 31 MCS3/RFSH 92 UCS/ONCE1 80 A13 49 BHE/ADEN 27 NMI 70 UZI/PIO26 20 A14 48 CLKOUTA 39 PCS0/PIO16 89 VCC 15 A15 47 CLKOUTB 40 PCS1/PIO17 88 VCC 38 A16 46 DEN/PIO5 72 PCS2/PIO18 86 VCC 44 A17/PIO7 45 DRQ0/PIO12 100 PCS3/PIO19 85 VCC 61 A18/PIO8 43 DRQ1/PIO13 99 PCS5/A1/PIO3 83 VCC 84 A19/PIO9 42 DT/R/PIO4 71 PCS6/A2/PIO2 82 VCC 90 AD0 1 GND 12 RD 29 WHB 65 AD1 3 GND 35 RES 94 WLB 66 AD2 5 GND 41 RXD 22 WR 28 AD3 7 GND 64 S0 34 X1 36 AD4 9 GND 87 S1 33 X2 37 Am186/188EM and Am186/188EMLV Microcontrollers 13 P R E L I M I N A R Y PCS 5/A1 PCS 6/A2 LCS / ONCE 0 83 82 81 INT3/INTA1/IRQ GND PCS 2 PCS 3 VCC 76 PCS 1 87 86 85 UCS / ONCE1 PCS 0 88 INT0 INT1/ SELECT INT2/INTA0 MCS2 VCC 91 90 89 79 78 77 MCS3/ RFSH 92 80 RES GND 94 93 84 TMROUT1 TMRIN1 96 95 DRQ0 DRQ1 TMRIN0 TMROUT0 100 99 98 97 CONNECTION DIAGRAM Am188EM Microcontroller Top Side View—100-Pin Thin Quad Flat Pack (TQFP) AD0 AO8 1 75 INT4 2 74 AD1 AO9 3 4 MCS1 MCS0 AD2 AO10 5 6 73 72 71 70 DEN DT/R NMI AD3 AO11 7 8 AD4 AO12 9 10 69 68 67 SRDY HOLD HLDA 66 AD5 GND 11 12 AO13 AD6 13 14 65 64 63 WB GND GND A0 62 A1 VCC AO14 15 16 AD7 AO15 17 18 61 60 59 VCC A2 A3 58 A4 S6/CLKDIV2 19 20 57 56 55 A5 A6 A7 54 A8 53 52 51 A9 A10 A11 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 VCC CLKOUTA CLKOUTB GND A19 A18 VCC A17 A16 A15 A14 A13 A12 34 35 S0 32 33 S2 S1 GND X1 X2 30 31 25 28 29 SDEN0 26 23 24 27 SDATA SDEN1 SCLK 21 22 RFSH2/ADEN WR RD ALE ARDY UZI TXD RXD Am188EM Microcontroller Note: Pin 1 is marked for orientation. 14 Am186/188EM and Am186/188EMLV Microcontrollers P R E L I M I N A R Y TQFP PIN ASSIGNMENTS—Am188EM Microcontroller (Sorted by Pin Number) Pin No. Name Pin No. Name Pin No. Name Pin No. Name 1 AD0 26 SCLK/PIO20 51 A11 76 INT3/INTA1/IRQ 2 AO8 27 RFSH2/ADEN 52 A10 77 INT2/INTA0/PIO31 3 AD1 28 WR 53 A9 78 INT1/SELECT 4 AO9 29 RD 54 A8 79 INT0 5 AD2 30 ALE 55 A7 80 UCS/ONCE1 6 AO10 31 ARDY 56 A6 81 LCS/ONCE0 7 AD3 32 S2 57 A5 82 PCS6/A2/PIO2 8 AO11 33 S1 58 A4 83 PCS5/A1/PIO3 9 AD4 34 S0 59 A3 84 VCC 10 AO12 35 GND 60 A2 85 PCS3/PIO19 11 AD5 36 X1 61 VCC 86 PCS2/PIO18 12 GND 37 X2 62 A1 87 GND 13 AO13 38 VCC 63 A0 88 PCS1/PIO17 14 AD6 39 CLKOUTA 64 GND 89 PCS0/PIO16 15 VCC 40 CLKOUTB 65 GND 90 VCC 16 AO14 41 GND 66 WB 91 MCS2/PIO24 17 AD7 42 A19/PIO9 67 HLDA 92 MCS3/RFSH/PIO25 18 AO15 43 A18/PIO8 68 HOLD 93 GND 19 S6/CLKDIV2/PIO29 44 VCC 69 SRDY/PIO6 94 RES 20 UZI/PIO26 45 A17/PIO7 70 NMI 95 TMRIN1/PIO0 21 TXD/PIO27 46 A16 71 DT/R/PIO4 96 TMROUT1/PIO1 22 RXD/PIO28 47 A15 72 DEN/PIO5 97 TMROUT0/PIO10 23 SDATA/PIO21 48 A14 73 MCS0/PIO14 98 TMRIN0/PIO11 24 SDEN1/PIO23 49 A13 74 MCS1/PIO15 99 DRQ1/PIO13 25 SDEN0/PIO22 50 A12 75 INT4/PIO30 100 DRQ0/PIO12 Am186/188EM and Am186/188EMLV Microcontrollers 15 P R E L I M I N A R Y TQFP PIN ASSIGNMENTS—Am188EM Microcontroller (Sorted by Pin Name) Pin Name No. Pin Name No. Pin Name No. Pin Name No. A0 63 AD5 11 GND 93 S1 33 A1 62 AD6 14 HLDA 67 S2 32 A2 60 AD7 17 HOLD 68 S6/CLKDIV2/PIO29 19 A3 59 ALE 30 INT0 79 SCLK/PIO20 26 A4 58 AO8 2 INT1/SELECT 78 SDATA/PIO21 23 A5 57 AO9 4 INT2/INTA0/PIO31 77 SDEN0/PIO22 25 A6 56 AO10 6 INT3/INTA1/IRQ 76 SDEN1/PIO23 24 A7 55 AO11 8 INT4/PIO30 75 SRDY/PIO6 69 A8 54 AO12 10 LCS/ONCE0 81 TMRIN0/PIO11 98 A9 53 AO13 13 MCS0/PIO14 73 TMRIN1/PIO0 95 A10 52 AO14 16 MCS1/PIO15 74 TMROUT0/PIO10 97 A11 51 AO15 18 MCS2/PIO24 91 TMROUT1/PIO1 96 A12 50 ARDY 31 MCS3/RFSH/PIO25 92 TXD/PIO27 21 A13 49 CLKOUTA 39 NMI 70 UCS/ONCE1 80 A14 48 CLKOUTB 40 PCS0/PIO16 89 UZI/PIO26 20 A15 47 DEN/PIO5 72 PCS1/PIO17 88 VCC 15 A16 46 DRQ0/PIO12 100 PCS2/PIO18 86 VCC 38 A17/PIO7 45 DRQ1/PIO13 99 PCS3/PIO19 85 VCC 44 A18/PIO8 43 DT/R/PIO4 71 PCS5/A1/PIO3 83 VCC 61 A19/PIO9 42 GND 12 PCS6/A2/PIO2 82 VCC 84 AD0 1 GND 35 RD 29 VCC 90 AD1 3 GND 41 RES 94 WB 66 AD2 5 GND 64 RFSH2/ADEN 27 WR 28 AD3 7 GND 65 RXD/PIO28 22 X1 36 AD4 9 GND 87 S0 34 X2 37 16 Am186/188EM and Am186/188EMLV Microcontrollers P R E L I M I N A R Y 81 AD10 AD2 AD9 83 82 AD11 AD3 85 84 AD12 AD4 87 86 GND AD5 89 88 AD6 VCC 92 AD13 AD7 AD14 94 90 AD15 95 91 S6/CLKDIV 2 96 93 UZI 97 98 50 47 NMI DT/R 49 46 SRDY 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 AD1 AD8 AD0 DRQ0 DRQ1 TMRIN0 TMROUT0 TMROUT1 TMRIN1 RES GND MCS3/RFSH MCS2 VCC PCS0 PCS1 GND PCS2 PCS3 VCC PCS5/A1 PCS6/A2 LCS/ONCE0 UCS/ONCE1 INT0 INT1/SELECT INT2/INTA0 INT3/INTA1/IRQ INT4 MCS1 DEN MCS0 45 48 44 HLDA HOLD 43 42 WHB WLB 41 40 A0 GND 39 38 A3 A2 VCC A1 36 37 35 A4 Am186EM Microcontroller 34 X1 X2 VCC CLKOUTA CLKOUTB GND A19 A18 VCC A17 A16 A15 A14 A13 A12 A11 A10 A9 33 S0 GND A5 S2 S1 A6 ARDY 32 RD ALE 31 BHE/ADEN WR 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 A8 A7 SDEN1 SDEN0 SCLK 99 100 SDATA RXD TXD PQFP CONNECTION DIAGRAMS AND PINOUTS Am186EM Microcontroller Top Side View—100-Pin Plastic Quad Flat Pack (PQFP) Note: Pin 1 is marked for orientation. Am186/188EM and Am186/188EMLV Microcontrollers 17 P R E L I M I N A R Y PQFP PIN ASSIGNMENTS—Am186EM Microcontroller (Sorted by Pin Number) Pin No. Name 18 Pin No. Name Pin No. Name Pin No. Name 1 SDEN1/PIO23 26 A13 51 MCS1/PIO15 76 DRQ1/PIO13 2 SDEN0/PIO22 27 A12 52 INT4/PIO30 77 DRQ0/PIO12 3 SCLK/PIO20 28 A11 53 INT3/INTA1/IRQ 78 AD0 4 BHE/ADEN 29 A10 54 INT2/INTA0/PIO31 79 AD8 5 WR 30 A9 55 INT1/SELECT 80 AD1 6 RD 31 A8 56 INT0 81 AD9 7 ALE 32 A7 57 UCS/ONCE1 82 AD2 8 ARDY 33 A6 58 LCS/ONCE0 83 AD10 9 S2 34 A5 59 PCS6/A2/PIO2 84 AD3 10 S1 35 A4 60 PCS5/A1/PIO3 85 AD11 11 S0 36 A3 61 VCC 86 AD4 12 GND 37 A2 62 PCS3/PIO19 87 AD12 13 X1 38 VCC 63 PCS2/PIO18 88 AD5 14 X2 39 A1 64 GND 89 GND 15 VCC 40 A0 65 PCS1/PIO17 90 AD13 16 CLKOUTA 41 GND 66 PCS0/PIO16 91 AD6 17 CLKOUTB 42 WHB 67 VCC 92 VCC 18 GND 43 WLB 68 MCS2/PIO24 93 AD14 19 A19/PIO9 44 HLDA 69 MCS3/RFSH/PIO25 94 AD7 20 A18/PIO8 45 HOLD 70 GND 95 AD15 21 VCC 46 SRDY/PIO6 71 RES 96 S6/CLKDIV2/PIO29 22 A17/PIO7 47 NMI 72 TMRIN1/PIO0 97 UZI/PIO26 23 A16 48 DT/R/PIO4 73 TMROUT1/PIO1 98 TXD/PIO27 24 A15 49 DEN/PIO5 74 TMROUT0/PIO10 99 RXD/PIO28 25 A14 50 MCS0/PIO14 75 TMRIN0/PIO11 100 SDATA/PIO21 Am186/188EM and Am186/188EMLV Microcontrollers P R E L I M I N A R Y PQFP PIN ASSIGNMENTS—Am186EM Microcontroller (Sorted by Pin Name) Pin Name No. Pin Name No. Pin Name No. Pin Name A0 40 AD5 88 GND 89 S2 9 A1 39 AD6 91 HLDA 44 S6/CLKDIV2/PIO29 96 A2 37 AD7 94 HOLD 45 SCLK/PIO20 3 A3 36 AD8 79 INT0 56 SDATA/PIO21 100 A4 35 AD9 81 INT1/SELECT 55 SDEN0/PIO22 2 A5 34 AD10 83 INT2/INTA0/PIO31 54 SDEN1/PIO23 1 A6 33 AD11 85 INT3/INTA1/IRQ 53 SRDY/PIO6 46 A7 32 AD12 87 INT4/PIO30 52 TMRIN0/PIO11 75 A8 31 AD13 90 LCS/ONCE0 58 TMRIN1/PIO0 72 A9 30 AD14 93 MCS0/PIO14 50 TMROUT0/PIO10 74 A10 29 AD15 95 MCS1/PIO15 51 TMROUT1/PIO1 73 A11 28 ALE 7 MCS2/PIO24 68 TXD/PIO27 98 A12 27 ARDY 8 MCS3/RFSH/PIO25 69 UCS/ONCE1 57 A13 26 BHE/ADEN 4 NMI 47 UZI/PIO26 97 A14 25 CLKOUTA 16 PCS0/PIO16 66 VCC 15 A15 24 CLKOUTB 17 PCS1/PIO17 65 VCC 21 A16 23 DEN/PIO5 49 PCS2/PIO18 63 VCC 38 A17/PIO7 22 DRQ0/PIO12 77 PCS3/PIO19 62 VCC 61 A18/PIO8 20 DRQ1/PIO13 76 PCS5/A1/PIO3 60 VCC 67 A19/PIO9 19 DT/R/PIO4 48 PCS6/A2/PIO2 59 VCC 92 AD0 78 GND 12 RD 6 WHB 42 AD1 80 GND 18 RES 71 WLB 43 AD2 82 GND 41 RXD/PIO28 99 WR 5 AD3 84 GND 64 S0 11 X1 13 AD4 86 GND 70 S1 10 X2 14 Am186/188EM and Am186/188EMLV Microcontrollers No. 19 P R E L I M I N A R Y 50 47 NMI DT/R 49 46 SRDY DEN MCS0 45 48 44 HLDA HOLD 43 42 GND WB 41 40 A0 GND 39 38 A3 A2 VCC A1 36 37 35 A4 Note: Pin 1 is marked for orientation. 20 81 AD10 AD2 AD9 83 82 AD11 AD3 85 84 AD12 AD4 87 86 GND AD5 89 88 AD6 VCC 92 AD13 AD7 AD14 94 90 AD15 95 91 S6/CLKDIV 2 96 93 UZI 97 98 Am188EM Microcontroller 34 X1 X2 VCC CLKOUTA CLKOUTB GND A19 A18 VCC A17 A16 A15 A14 A13 A12 A11 A10 A9 33 S0 GND A5 S2 S1 A6 ARDY 32 RD ALE 31 RFSH2/ADEN WR 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 A8 A7 SDEN1 SDEN0 SCLK 99 100 SDATA RXD TXD CONNECTION DIAGRAM Am188EM Microcontroller Top Side View—100-Pin Plastic Quad Flat Pack (PQFP) Am186/188EM and Am186/188EMLV Microcontrollers 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 AD1 AD8 AD0 DRQ0 DRQ1 TMRIN0 TMROUT0 TMROUT1 TMRIN1 RES GND MCS3/RFSH MCS2 VCC PCS0 PCS1 GND PCS2 PCS3 VCC PCS5/A1 PCS6/A2 LCS/ONCE0 UCS/ONCE1 INT0 INT1/SELECT INT2/INTA0 INT3/INTA1/IRQ INT4 MCS1 P R E L I M I N A R Y PQFP PIN ASSIGNMENTS—Am188EM Microcontroller (Sorted by Pin Number) Pin No. Name Pin No. Name Pin No. Name Pin No. Name 1 SDEN1/PIO23 26 A13 51 MCS1/PIO15 76 DRQ1/PIO13 2 SDEN0/PIO22 27 A12 52 INT4/PIO30 77 DRQ0/PIO12 3 SCLK/PIO20 28 A11 53 INT3/INTA1/IRQ 78 AD0 4 RFSH2/ADEN 29 A10 54 INT2/INTA0/PIO31 79 AO8 5 WR 30 A9 55 INT1/SELECT 80 AD1 6 RD 31 A8 56 INT0 81 AO9 7 ALE 32 A7 57 UCS/ONCE1 82 AD2 8 ARDY 33 A6 58 LCS/ONCE0 83 AO10 9 S2 34 A5 59 PCS6/A2/PIO2 84 AD3 10 S1 35 A4 60 PCS5/A1/PIO3 85 AO11 11 S0 36 A3 61 VCC 86 AD4 12 GND 37 A2 62 PCS3/PIO19 87 AO12 13 X1 38 VCC 63 PCS2/PIO18 88 AD5 14 X2 39 A1 64 GND 89 GND 15 VCC 40 A0 65 PCS1/PIO17 90 AO13 16 CLKOUTA 41 GND 66 PCS0/PIO16 91 AD6 17 CLKOUTB 42 GND 67 VCC 92 VCC 18 GND 43 WB 68 MCS2/PIO24 93 AO14 19 A19/PIO9 44 HLDA 69 MCS3/RFSH/PIO25 94 AD7 20 A18/PIO8 45 HOLD 70 GND 95 AO15 21 VCC 46 SRDY/PIO6 71 RES 96 S6/CLKDIV2/PIO29 22 A17/PIO7 47 NMI 72 TMRIN1/PIO0 97 UZI/PIO26 23 A16 48 DT/R/PIO4 73 TMROUT1/PIO1 98 TXD/PIO27 24 A15 49 DEN/PIO5 74 TMROUT0/PIO10 99 RXD/PIO28 25 A14 50 MCS0/PIO14 75 TMRIN0/PIO11 100 SDATA/PIO21 Am186/188EM and Am186/188EMLV Microcontrollers 21 P R E L I M I N A R Y PQFP PIN ASSIGNMENTS—Am188EM Microcontroller (Sorted by Pin Name) Pin Name No. Pin Name No. Pin Name No. Pin Name No. A0 40 AD5 88 GND 89 S1 10 A1 39 AD6 91 HLDA 44 S2 9 A2 37 AD7 94 HOLD 45 S6/CLKDIV2/PIO29 96 A3 36 ALE 7 INT0 56 SCLK/PIO20 3 A4 35 AO8 79 INT1/SELECT 55 SDATA/PIO21 100 A5 34 AO9 81 INT2/INTA0/PIO31 54 SDEN0/PIO22 2 A6 33 AO10 83 INT3/INTA1/IRQ 53 SDEN1/PIO23 1 A7 32 AO11 85 INT4/PIO30 52 SRDY/PIO6 46 A8 31 AO12 87 LCS/ONCE0 58 TMRIN0/PIO11 75 A9 30 AO13 90 MCS0/PIO14 50 TMRIN1/PIO0 72 A10 29 AO14 93 MCS1/PIO15 51 TMROUT0/PIO10 74 A11 28 AO15 95 MCS2/PIO24 68 TMROUT1/PIO1 73 A12 27 ARDY 8 MCS3/RFSH/PIO25 69 TXD/PIO27 98 A13 26 CLKOUTA 16 NMI 47 UCS/ONCE1 57 A14 25 CLKOUTB 17 PCS0/PIO16 66 UZI/PIO26 97 A15 24 DEN/PIO5 49 PCS1/PIO17 65 VCC 15 A16 23 DRQ0/PIO12 77 PCS2/PIO18 63 VCC 21 A17/PIO7 22 DRQ1/PIO13 76 PCS3/PIO19 62 VCC 38 A18/PIO8 20 DT/R/PIO4 48 PCS5/A1/PIO3 60 VCC 61 A19/PIO9 19 GND 12 PCS6/A2/PIO2 59 VCC 67 AD0 78 GND 18 RD 6 VCC 92 AD1 80 GND 41 RES 71 WB 43 AD2 82 GND 42 RFSH2/ADEN 4 WR 5 AD3 84 GND 64 RXD/PIO28 99 X1 13 AD4 86 GND 70 S0 11 X2 14 22 Am186/188EM and Am186/188EMLV Microcontrollers P R E L I M I N A R Y LOGIC SYMBOL—Am186EM MICROCONTROLLER X1 RES X2 INT4 * Clocks CLKOUTA INT3/INTA1/IRQ CLKOUTB INT2/INTA0 * Reset Control and Interrupt Service INT1/SELECT INT0 * Address and Address/Data Buses 20 A19–A0 16 AD15–AD0 * S6/CLKDIV2 * UZI NMI PCS6/A2 * PCS5/A1 3 ALE PCS3–PCS0 S2–S0 LCS/ONCE0 HOLD MCS3/RFSH HLDA MCS2–MCS0 RD UCS/ONCE1 * 4 * Memory and Peripheral Control * 3 * WR Bus Control * DT/R * DEN ARDY SRDY * BHE/ADEN WHB 2 WLB Timer Control Programmable I/O Control * TMRIN0 * TMROUT0 * TMRIN1 * TMROUT1 * DMA Control TXD * RXD * Asynchronous Serial Port Control SDEN1–SDEN0 32 shared ** DRQ1–DRQ0 PIO32–PIO0 2 * SCLK * SDATA * Synchronous Serial Port Control Notes: * These signals are the normal function of a pin that can be used as a PIO. See the pin descriptions beginning on page 25 and Table 2 on page 30 for information on shared function. ** All PIO signals are shared with other physical pins. Am186/188EM and Am186/188EMLV Microcontrollers 23 P R E L I M I N A R Y LOGIC SYMBOL—Am188EM MICROCONTROLLER X1 RES X2 INT4 * Clocks CLKOUTA INT3/INTA1/IRQ CLKOUTB INT2/INTA0 * Reset Control and Interrupt Service INT1/SELECT INT0 * Address and Address/Data Buses 20 A19–A0 8 AO15–AO8 8 AD7–AD0 * S6/CLKDIV2 * UZI NMI PCS6/A2 PCS5/A1 PCS3–PCS0 ALE 3 S2–S0 HOLD HLDA * * 4 * Memory and Peripheral Control LCS/ONCE0 MCS3/RFSH MCS2–MCS0 * 3 * UCS/ONCE1 RD WR Bus Control * DT/R * DEN ARDY SRDY * RFSH2/ADEN WB Timer Control Programmable I/O Control * TMRIN0 * TMROUT0 * TMRIN1 * TMROUT1 ** DMA Control TXD * RXD * Asynchronous Serial Port Control SDEN1–SDEN0 32 shared PIO31–PIO0 2 * DRQ1–DRQ0 2 * SCLK * SDATA * Synchronous Serial Port Control Notes: * These signals are the normal function of a pin that can be used as a PIO. See the pin descriptions beginning on page 25 and Table 2 on page 30 for information on shared function. ** All PIO signals are shared with other physical pins. 24 Am186/188EM and Am186/188EMLV Microcontrollers P R E L I M I N A R Y PIN DESCRIPTIONS Pins That Are Used by Emulators The following pins are used by emulators: A19–A0, AO15–AO8, AD7–AD0, ALE, BHE/ADEN (on the Am186EM), CLKOUTA, R F S H 2/A D E N (on the Am188EM), RD, S2–S0, S6/CLKDIV2, and UZI. During a power-on reset, the address and data bus pins (AD15–AD0 for the 186, AO15–AO8 and AD7– AD0 for the 188) can also be used to load system configuration information into the internal reset configuration register. Emulators require that S6/CLKDIV2 and UZI be configured in their normal functionality, that is as S6 and UZI. AD15–AD8 (Am186EM Microcontroller) AO15–AO8 (Am188EM Microcontroller) If BHE/ADEN (on the 186) or RFSH2/ADEN (on the 188) is held Low during the rising edge of RES, S6 and UZI are configured in their normal functionality. Address and Data Bus (input/output, three-state, synchronous, level-sensitive) Address-Only Bus (output, three-state, synchronous, level-sensitive) Pin Terminology The following terms are used to describe the pins: Input—An input-only pin. Output—An output-only pin. Input/Output—A pin that can be either input or output. Synchronous—Synchronous inputs must meet setup and hold times in relation to CLKOUTA. Synchronous outputs are synchronous to CLKOUTA. Asynchronous—Inputs or outputs that are asynchronous to CLKOUTA. A19–A0 (A19/PIO9, A18/PIO8, A17/PIO7) Address Bus (output, three-state, synchronous) These pins supply nonmultiplexed memory or I/O addresses to the system one-half of a CLKOUTA period earlier than the multiplexed address and data bus (AD15–AD0 on the 186 or AO15–AO8 and AD7–AD0 on the 188). During a bus hold or reset condition, the address bus is in a high-impedance state. AD7–AD0 Address and Data Bus (input/output, three-state, synchronous, level-sensitive) These time-multiplexed pins supply partial memory or I/O addresses, as well as data, to the system. This bus supplies the low-order 8 bits of an address to the system during the first period of a bus cycle (t1), and it supplies data to the system during the remaining periods of that cycle (t2, t3, and t4). The address phase of these pins can be disabled. See the ADEN description with the BHE/ADEN pin. When WLB is negated, these pins are three-stated during t2, t3, and t4. During a bus hold or reset condition, the address and data bus is in a high-impedance state. AD15–AD8—On the Am186EM microcontroller, these time-multiplexed pins supply memory or I/O addresses and data to the system. This bus can supply an address to the system during the first period of a bus cycle (t1). It supplies data to the system during the remaining periods of that cycle (t2, t3, and t4). The address phase of these pins can be disabled. See the ADEN description with the BHE/ADEN pin. When WHB is negated, these pins are three-stated during t2, t3, and t4. During a bus hold or reset condition, the address and data bus is in a high-impedance state. During a power-on reset, the address and data bus pins (AD15–AD0 for the 186, AO15–AO8 and AD7– AD0 for the 188) can also be used to load system configuration information into the internal reset configuration register. AO15–AO8—On the Am188EM microcontroller, the address-only bus (AO15–AO8) contains valid highorder address bits from bus cycles t1–t4. These outputs are floated during a bus hold or reset. On the Am188EM microcontroller, AO15–AO8 combine with AD7–AD0 to form a complete multiplexed address bus while AD7–AD0 is the 8-bit data bus. ALE Address Latch Enable (output, synchronous) This pin indicates to the system that an address appears on the address and data bus (AD15–AD0 for the 186 or AO15–AO8 and AD7–AD0 for the 188). The address is guaranteed valid on the trailing edge of ALE. This pin is three-stated during ONCE mode. This pin is not three-stated during a bus hold or reset. ARDY Asynchronous Ready (input, asynchronous, level-sensitive) This pin indicates to the microcontroller that the addressed memory space or I/O device will complete a data transfer. The ARDY pin accepts a rising edge that is asynchronous to CLKOUTA and is active High. The Am186/188EM and Am186/188EMLV Microcontrollers 25 P R E L I M I N A R Y falling edge of ARDY must be synchronized to CLKOUTA. To always assert the ready condition to the microcontroller, tie ARDY High. If the system does not use ARDY, tie the pin Low to yield control to SRDY. BHE/ADEN (Am186EM Microcontroller Only) Bus High Enable (three-state, output, synchronous) Address Enable (input, internal pullup) BHE—During a memory access, this pin and the leastsignificant address bit (AD0 or A0) indicate to the system which bytes of the data bus (upper, lower, or both) participate in a bus cycle. The BHE/ADEN and AD0 pins are encoded as shown in Table 1. BHE is asserted during t 1 and remains asserted through t3 and tW. BHE does not need to be latched. BHE floats during bus hold and reset. On the Am186EM and Am188EM microcontrollers, WLB and WHB implement the functionality of BHE and AD0 for high and low byte write enables. Table 1. Data Byte Encoding BHE AD0 Type of Bus Cycle 0 0 Word Transfer 0 1 High Byte Transfer (Bits 15–8) 1 0 Low Byte Transfer (Bits 7–0) 1 1 Refresh BHE/ADEN also signals DRAM refresh cycles when using the multiplexed address and data (AD) bus. A refresh cycle is indicated when both BHE/ADEN and AD0 are High. During refresh cycles, the A bus and the AD bus are not guaranteed to provide the same address during the address phase of the AD bus cycle. For this reason, the A0 signal cannot be used in place of the AD0 signal to determine refresh cycles. PSRAM refreshes also provide an additional RFSH signal (see the MCS3/RFSH pin description on page 28). ADEN—If BHE/ADEN is held High or left floating during power-on reset, the address portion of the AD bus (AD15–AD0 for the 186 or AO15–AO8 and AD7–AD0 for the 188) is enabled or disabled during LCS and UCS bus cycles based on the DA bit in the LMCS and UMCS registers. If the DA bit is set, the memory address is accessed on the A19–A0 pins. There is a weak internal pullup resistor on BHE/ADEN so no external pullup is required. This mode of operation reduces power consumption. 26 If BHE/ADEN is held Low on power-on reset, the AD bus drives both addresses and data, regardless of the DA bit setting. This pin is sampled on the rising edge of RES. (S6 and UZI also assume their normal functionality in this instance. See Table 2 on page 30.) Note: On the Am188EM microcontroller, AO15–AO8 are driven during the entire bus cycle, regardless of the setting of the DA bit in the UMCS and LMCS registers. CLKOUTA Clock Output A (output, synchronous) This pin supplies the internal clock to the system. Depending on the value of the power-save control register (PDCON), CLKOUTA operates at either the crystal input frequency (X1), the power-save frequency, or is three-stated. CLKOUTA remains active during reset and bus hold conditions. CLKOUTB Clock Output B (output, synchronous) This pin supplies an additional clock to the system. Depending upon the value of the power-save control register (PDCON), CLKOUTB operates at either the crystal input frequency (X1), the power-save frequency, or is three-stated. CLKOUTB remains active during reset and bus hold conditions. DEN/PIO5 Data Enable (output, three-state, synchronous) This pin supplies an output enable to an external databus transceiver. DEN is asserted during memory, I/O, and interrupt acknowledge cycles. DEN is deasserted when DT/R changes state. DEN floats during a bus hold or reset condition. DRQ1–DRQ0 (DRQ1/PIO13, DRQ0/PIO12) DMA Requests (input, synchronous, level-sensitive) These pins indicate to the microcontroller that an external device is ready for DMA channel 1 or channel 0 to perform a transfer. DRQ1–DRQ0 are level-triggered and internally synchronized. The DRQ signals are not latched and must remain active until serviced. DT/R/PIO4 Data Transmit or Receive (output, three-state, synchronous) This pin indicates which direction data should flow through an external data-bus transceiver. When DT/R is asserted High, the microcontroller transmits data. When this pin is deasserted Low, the microcontroller receives data. DT/R floats during a bus hold or reset condition. Am186/188EM and Am186/188EMLV Microcontrollers P R E L I M I N A R Y GND INT1/SELECT Ground Maskable Interrupt Request 1 (input, asynchronous) Slave Select (input, asynchronous) The ground pins connect the system ground to the microcontroller. HLDA Bus Hold Acknowledge (output, synchronous) This pin is asserted High to indicate to an external bus master that the microcontroller has released control of the local bus. When an external bus master requests control of the local bus (by asserting HOLD), the microcontroller completes the bus cycle in progress and then relinquishes control of the bus to the external bus master by asserting HLDA and floating DEN, RD, WR, S2– S0, AD15–AD0, S6, A19–A0, BHE, WHB, WLB, and DT/R, and then driving the chip selects UCS, LCS, MCS3–MCS0, PCS6–PCS5, and PCS3–PCS0 High. When the external bus master has finished using the local bus, it indicates this to the microcontroller by deasserting HOLD. The microcontroller responds by deasserting HLDA. If the microcontroller requires access to the bus (i.e. for refresh), it will deassert HLDA before the external bus master deasserts HOLD. The external bus master must be able to deassert HOLD and allow the microcontroller access to the bus. See the timing diagrams for bus hold on page 92. HOLD Bus Hold Request (input, synchronous, level-sensitive) This pin indicates to the microcontroller that an external bus master needs control of the local bus. The Am186EM and Am188EM microcontrollers’ HOLD latency time is a function of the activity occurring in the processor when the HOLD request is received. A DRAM request will delay a HOLD request when both requests are made at the same time. In addition, if locked transfers are performed, the HOLD latency time is increased by the length of the locked transfer. For more information, see the HLDA pin description. INT0 Maskable Interrupt Request 0 (input, asynchronous) This pin indicates to the microcontroller that an interrupt request has occurred. If the INT0 pin is not masked, the microcontroller transfers program execution to the location specified by the INT0 vector in the microcontroller interrupt vector table. Interrupt requests are synchronized internally and can be edge-triggered or level-triggered. To guarantee interrupt recognition, the requesting device must continue asserting INT0 until the request is acknowledged. INT1—This pin indicates to the microcontroller that an interrupt request has occurred. If INT1 is not masked, the microcontroller transfers program execution to the location specified by the INT1 vector in the microcontroller interrupt vector table. Interrupt requests are synchronized internally and can be edge-triggered or level-triggered. To guarantee interrupt recognition, the requesting device must continue asserting INT1 until the request is acknowledged. SELECT—When the microcontroller interrupt control unit is operating as a slave to an external interrupt controller, this pin indicates to the microcontroller that an interrupt type appears on the address and data bus. The INT0 pin must indicate to the microcontroller that an interrupt has occurred before the SELECT pin indicates to the microcontroller that the interrupt type appears on the bus. INT2/INTA0/PIO31 Maskable Interrupt Request 2 (input, asynchronous) Interrupt Acknowledge 0 (output, synchronous) INT2—This pin indicates to the microcontroller that an interrupt request has occurred. If the INT2 pin is not masked, the microcontroller transfers program execution to the location specified by the INT2 vector in the microcontroller interrupt vector table. Interrupt requests are synchronized internally and can be edge-triggered or level-triggered. To guarantee interrupt recognition, the requesting device must continue asserting INT2 until the request is acknowledged. INT2 becomes INTA0 when INT0 is configured in cascade mode. INTA0—When the microcontroller interrupt control unit is operating in cascade mode, this pin indicates to the system that the microcontroller needs an interrupt type to process the interrupt request on INT0. The peripheral issuing the interrupt request must provide the microcontroller with the corresponding interrupt type. INT3/INTA1/IRQ Maskable Interrupt Request 3 (input, asynchronous) Interrupt Acknowledge 1 (output, synchronous) Slave Interrupt Request (output, synchronous) INT3—This pin indicates to the microcontroller that an interrupt request has occurred. If the INT3 pin is not masked, the microcontroller then transfers program execution to the location specified by the INT3 vector in the microcontroller interrupt vector table. Am186/188EM and Am186/188EMLV Microcontrollers 27 P R E L I M I N A R Y Interrupt requests are synchronized internally, and can be edge-triggered or level-triggered. To guarantee interrupt recognition, the requesting device must continue asserting INT3 until the request is acknowledged. INT3 becomes INTA1 when INT1 is configured in cascade mode. INTA1—When the microcontroller interrupt control unit is operating in cascade mode or special fully-nested mode, this pin indicates to the system that the microcontroller needs an interrupt type to process the interrupt request on INT1. In both modes, the peripheral issuing the interrupt request must provide the microcontroller with the corresponding interrupt type. MCS3/RFSH/PIO25 Midrange Memory Chip Select 3 (output, synchronous, internal pullup) Automatic Refresh (output, synchronous) MCS3—This pin indicates to the system that a memory access is in progress to the fourth region of the midrange memory block. The base address and size of the midrange memory block are programmable. MCS3 is held High during a bus hold condition. In addition, this pin has a weak internal pullup resistor that is active during reset. INT4/PIO30 RFSH—This pin provides a signal timed for auto refresh to PSRAM devices. It is only enabled to function as a refresh pulse when the PSRAM mode bit is set in the LMCS Register. An active Low pulse is generated for 1.5 clock cycles with an adequate deassertion period to ensure that overall auto refresh cycle time is met. This pin is not three-stated during a bus hold condition. Maskable Interrupt Request 4 (input, asynchronous) MCS2–MCS0 (MCS2/PIO24, MCS1/PIO15, MCS0/PIO14) This pin indicates to the microcontroller that an interrupt request has occurred. If the INT4 pin is not masked, the microcontroller then transfers program execution to the location specified by the INT4 vector in the microcontroller interrupt vector table. Midrange Memory Chip Selects (output, synchronous, internal pullup) IRQ—When the microcontroller interrupt control unit is operating as a slave to an external master interrupt controller, this pin lets the microcontroller issue an interrupt request to the external master interrupt controller. Interrupt requests are synchronized internally, and can be edge-triggered or level-triggered. To guarantee interrupt recognition, the requesting device must continue asserting INT4 until the request is acknowledged. These pins indicate to the system that a memory access is in progress to the corresponding region of the midrange memory block. The base address and size of the midrange memory block are programmable. MCS2–MCS0 are held High during a bus hold condition. In addition, they have weak internal pullup resistors that are active during reset. LCS/ONCE0 NMI Lower Memory Chip Select (output, synchronous, internal pullup) ONCE Mode Request 0 (input) Nonmaskable Interrupt (input, synchronous, edgesensitive) LCS—This pin indicates to the system that a memory access is in progress to the lower memory block. The base address and size of the lower memory block are programmable up to 512 Kbytes. LCS is held High during a bus hold condition. ONCE0—During reset this pin and ONCE1 indicate to the microcontroller the mode in which it should operate. ONCE0 and ONCE1 are sampled on the rising edge of RES. If both pins are asserted Low, the microcontroller enters ONCE mode; otherwise, it operates normally. In ONCE mode, all pins assume a high-impedance state and remain in that state until a subsequent reset occurs. To guarantee that the microcontroller does not inadvertently enter ONCE mode, ONCE0 has a weak internal pullup resistor that is active only during reset. This pin is not three-stated during a bus hold condition. 28 This pin indicates to the microcontroller that an interrupt request has occurred. The NMI signal is the highest priority hardware interrupt and, unlike the INT4– INT0 pins, cannot be masked. The microcontroller always transfers program execution to the location specified by the nonmaskable interrupt vector in the microcontroller interrupt vector table when NMI is asserted. Although NMI is the highest priority interrupt source, it does not participate in the priority resolution process of the maskable interrupts. There is no bit associated with NMI in the interrupt in-service or interrupt request registers. This means that a new NMI request can interrupt an executing NMI interrupt service routine. As with all hardware interrupts, the IF (interrupt flag) is cleared when the processor takes the interrupt, disabling the maskable interrupt sources. However, if maskable interrupts are re-enabled by software in the NMI interrupt service routine, via the STI instruction for example, the fact that an NMI is currently in service will not have any Am186/188EM and Am186/188EMLV Microcontrollers P R E L I M I N A R Y effect on the priority resolution of maskable interrupt requests. For this reason, it is strongly advised that the interrupt service routine for NMI does not enable the maskable interrupts. An NMI transition from Low to High is latched and synchronized internally, and it initiates the interrupt at the next instruction boundary. To guarantee that the interrupt is recognized, the NMI pin must be asserted for at least one CLKOUTA period. PCS3–PCS0 (PCS3/PIO19, PCS2/PIO18, PCS1/PIO17, PCS0/PIO16) Peripheral Chip Selects (output, synchronous) These pins indicate to the system that a memory access is in progress to the corresponding region of the peripheral memory block (either I/O or memory address space). The base address of the peripheral memory block is programmable. PCS3–PCS0 are held High during a bus hold condition. They are also held High during reset. PCS4 is not available on the Am186EM and Am188EM microcontrollers. Unlike the UCS and LCS chip selects, the PCS outputs assert with the multiplexed AD address bus. Note also that each peripheral chip select asserts over a 256-byte address range, which is twice the address range covered by peripheral chip selects in the 80C186 and 80C188 microcontrollers. dress bit 1 to the system. During a bus hold condition, A1 retains its previously latched value. PCS6/A2/PIO2 Peripheral Chip Select 6 (output, synchronous) Latched Address Bit 2 (output, synchronous) PCS6—This pin indicates to the system that a memory access is in progress to the seventh region of the peripheral memory block (either I/O or memory address space). The base address of the peripheral memory block is programmable. PCS6 is held High during a bus hold condition or reset. Unlike the UCS and LCS chip selects, the PCS outputs assert with the multiplexed AD address bus. Note also that each peripheral chip select asserts over a 256byte address range, which is twice the address range covered by peripheral chip selects in the 80C186 and 80C188 microcontrollers. A2—When the EX bit in the MCS and PCS Auxiliary Register is 0, this pin supplies an internally latched address bit 2 to the system. During a bus hold condition, A2 retains its previously latched value. PIO31–PIO0 (Shared) Programmable I/O Pins (input/output, asynchronous, open-drain) PCS5/A1/PIO3 The Am186EM and Am188EM microcontrollers provide 32 individually programmable I/O pins. Each PIO can be programmed with the following attributes: PIO function (enabled/disabled), direction (input/output), and weak pullup or pulldown. Peripheral Chip Select 5 (output, synchronous) Latched Address Bit 1 (output, synchronous) The pins that are multiplexed with PIO31–PIO0 are listed in Table 2 and Table 3. PCS5—This pin indicates to the system that a memory access is in progress to the sixth region of the peripheral memory block (either I/O or memory address space). The base address of the peripheral memory block is programmable. PCS5 is held High during a bus hold condition. It is also held High during reset. After power-on reset, the PIO pins default to various configurations. The column titled Power-On Reset Status in Table 2 and Table 3 lists the defaults for the PIOs. The system initialization code must reconfigure any PIOs as required. Unlike the UCS and LCS chip selects, the PCS outputs assert with the multiplexed AD address bus. Note also that each peripheral chip select asserts over a 256byte address range, which is twice the address range covered by peripheral chip selects in the 80C186 and 80C188 microcontrollers. The A19–A17 address pins default to normal operation on power-on reset, allowing the processor to correctly begin fetching instructions at the boot address FFFF0h. The DT/R, DEN, and SRDY pins also default to normal operation on power-on reset. A1—When the EX bit in the MCS and PCS auxiliary register is 0, this pin supplies an internally latched ad- Am186/188EM and Am186/188EMLV Microcontrollers 29 P R E L I M I N A R Y Table 2. Numeric PIO Pin Assignments PIO No Associated Pin Power-On Reset Status Table 3. Alphabetic PIO Pin Assignments Associated Pin PIO No Power-On Reset Status 0 TMRIN1 Input with pullup A17 7 Normal operation(3) 1 TMROUT1 Input with pulldown A18(1) 8 Normal operation(3) 2 PCS6/A2 Input with pullup A19(1) 9 Normal operation(3) 3 PCS5/A1 Input with pullup DEN 5 Normal operation(3) 4 DT/R Normal operation(3) DRQ0 12 Input with pullup DEN (3) DRQ1 13 Input with pullup SRDY (4) Normal operation DT/R 4 Normal operation(3) A17 Normal operation(3) INT2 31 Input with pullup A18 (3) INT4 30 Input with pullup A19 (3) Normal operation MCS0 14 Input with pullup 10 TMROUT0 Input with pulldown MCS1 15 Input with pullup 11 TMRIN0 Input with pullup MCS2 24 Input with pullup 12 DRQ0 Input with pullup MCS3/RFSH 25 Input with pullup 13 DRQ1 Input with pullup PCS0 16 Input with pullup 14 MCS0 Input with pullup PCS1 17 Input with pullup 15 MCS1 Input with pullup PCS2 18 Input with pullup 16 PCS0 Input with pullup PCS3 19 Input with pullup 17 PCS1 Input with pullup PCS5/A1 3 Input with pullup 18 PCS2 Input with pullup PCS6/A2 2 Input with pullup 19 PCS3 Input with pullup RXD 28 Input with pullup 29 Input with pullup 5 6 7(1) 8 (1) 9 (1) Normal operation Normal operation (1) 20 SCLK Input with pullup S6/CLKDIV2(1,2) 21 SDATA Input with pullup SCLK 20 Input with pullup 22 SDEN0 Input with pulldown SDATA 21 Input with pullup 23 SDEN1 Input with pulldown SDEN0 22 Input with pulldown 24 MCS2 Input with pullup SDEN1 23 Input with pulldown 25 MCS3/RFSH Input with pullup SRDY 6 Normal operation(4) 26(1,2) UZI Input with pullup TMRIN0 11 Input with pullup 27 TXD Input with pullup TMRIN1 0 Input with pullup 28 RXD Input with pullup TMROUT0 10 Input with pulldown S6/CLKDIV2 Input with pullup TMROUT1 1 Input with pulldown 30 INT4 Input with pullup TXD 27 Input with pullup 31 INT2 Input with pullup UZI(1,2) 26 Input with pullup 29(1,2) Notes: Notes: 1. These pins are used by emulators. (Emulators also use S2–S0, RES, NMI, CLKOUTA, BHE, ALE, AD15–AD0, and A16–A0.) 2. These pins revert to normal operation if BHE/ADEN (186) or RFSH2/ADEN (188) is held Low during power-on reset. 3. When used as a PIO, input with pullup option available. 4. When used as a PIO, input with pulldown option available. 1. These pins are used by emulators. (Emulators also use S2–S0, RES, NMI, CLKOUTA, BHE, ALE, AD15–AD0, and A16–A0.) 2. These pins revert to normal operation if BHE/ADEN (186) or RFSH2/ADEN (188) is held Low during power-on reset. 3. When used as a PIO, input with pullup option available. 4. When used as a PIO, input with pulldown option available. 30 Am186/188EM and Am186/188EMLV Microcontrollers P R E L I M I N A R Y RD RXD/PIO28 Read Strobe (output, synchronous, three-state) Receive Data (input, asynchronous) This pin indicates to the system that the microcontroller is performing a memory or I/O read cycle. RD is guaranteed not to be asserted before the address and data bus is floated during the address-to-data transition. RD floats during a bus hold condition. This pin supplies asynchronous serial receive data from the system to the internal UART of the microcontroller. S2–S0 Bus Cycle Status (output, three-state, synchronous) RES Reset (input, asynchronous, level-sensitive) This pin requires the microcontroller to perform a reset. When RES is asserted, the microcontroller immediately terminates its present activity, clears its internal logic, and CPU control is transferred to the reset address FFFF0h. RES must be held Low for at least 1 ms. RES can be asserted asynchronously to CLKOUTA because RES is synchronized internally. For proper initialization, VCC must be within specifications, and CLKOUTA must be stable for more than four CLKOUTA periods during which RES is asserted. The microcontroller begins fetching instructions approximately 6.5 CLKOUTA periods after RES is deasserted. This input is provided with a Schmitt trigger to facilitate power-on RES generation via an RC network. RFSH2/ADEN (Am188EM Microcontroller Only) Refresh 2 (three-state, output, synchronous) Address Enable (input, internal pullup) RFSH2—Asserted Low to signify a DRAM refresh bus cycle. The use of RFSH2/ADEN to signal a refresh is not valid when PSRAM mode is selected. Instead, the MCS3/RFSH signal is provided to the PSRAM. ADEN—If RFSH2/ADEN is held High or left floating on power-on reset, the AD bus (AO15–AO8 and AD7– AD0) is enabled or disabled during the address portion of LCS and UCS bus cycles based on the DA bit in the LMCS and UMCS registers. If the DA bit is set, the memory address is accessed on the A19–A0 pins. This mode of operation reduces power consumption. For more information, see the “Bus Operation” section on page 37. There is a weak internal pullup resistor on RFSH2/ADEN so no external pullup is required. If RFSH2/ADEN is held Low on power-on reset, the AD bus drives both addresses and data regardless of the DA bit setting. The pin is sampled one crystal clock cycle after the rising edge of RES. RFSH2/ADEN is three-stated during bus holds and ONCE mode. These pins indicate to the system the type of bus cycle in progress. S2 can be used as a logical memory or I/O indicator, and S1 can be used as a data transmit or receive indicator. S2–S0 float during bus hold and hold acknowledge conditions. The S2–S0 pins are encoded as shown in Table 4. Table 4. Bus Cycle Encoding S2 S1 S0 0 0 0 Bus Cycle Interrupt acknowledge 0 0 1 Read data from I/O 0 1 0 Write data to I/O 0 1 1 Halt 1 0 0 Instruction fetch 1 0 1 Read data from memory 1 1 0 Write data to memory 1 1 1 None (passive) S6/CLKDIV2/PIO29 Bus Cycle Status Bit 6 (output, synchronous) Clock Divide by 2 (input, internal pullup) S6—During the second and remaining periods of a cycle (t2, t3, and t4), this pin is asserted High to indicate a DMA-initiated bus cycle. During a bus hold or reset condition, S6 floats. CLKDIV2—If S6/CLKDIV2/PIO29 is held Low during power-on reset, the chip enters clock divided by 2 mode where the processor clock is derived by dividing the external clock input by 2. If this mode is selected, the PLL is disabled. The pin is sampled on the rising edge of RES. If S6 is to be used as PIO29 in input mode, the device driving PIO29 must not drive the pin Low during poweron reset. S6/CLKDIV2/PIO29 defaults to a PIO input with pullup, so the pin does not need to be driven High externally. Am186/188EM and Am186/188EMLV Microcontrollers 31 P R E L I M I N A R Y SCLK/PIO20 TMRIN1/PIO0 Serial Clock (output, synchronous) Timer Input 1 (input, synchronous, edge-sensitive) This pin supplies the synchronous serial interface (SSI) clock to a slave device, allowing transmit and receive operations to be synchronized between the microcontroller and the slave. SCLK is derived from the microcontroller internal clock and then divided by 2, 4, 8, or 16 depending on register settings. This pin supplies a clock or control signal to the internal microcontroller timer 1. After internally synchronizing a Low-to-High transition on TMRIN1, the microcontroller increments the timer. TMRIN1 must be tied High if not being used. An access to any of the SSR or SSD registers activates SCLK for eight SCLK cycles (see Figure 11 and Figure 12 on page 49). When SCLK is inactive, it is held High by the microcontroller. SDATA/PIO21 Serial Data (input/output, synchronous) This pin transmits synchronous serial interface (SSI) data to and from a slave device. When SDATA is inactive, a weak keeper holds the last value of SDATA on the pin. SDEN1/PIO23, SDEN0/PIO22 Serial Data Enables (output, synchronous) These pins enable data transfers on port 1 and port 0 of the synchronous serial interface (SSI). The microcontroller asserts either SDEN1 or SDEN0 at the beginning of a transfer and deasserts it after the transfer is complete. When SDEN1–SDEN0 are inactive, they are held Low by the microcontroller. SRDY/PIO6 Synchronous Ready (input, synchronous, level-sensitive) This pin indicates to the microcontroller that the addressed memory space or I/O device will complete a data transfer. The SRDY pin accepts an active High input synchronized to CLKOUTA. Using SRDY instead of ARDY allows a relaxed system timing because of the elimination of the one-half clock period required to internally synchronize ARDY. To always assert the ready condition to the microcontroller, tie SRDY High. If the system does not use SRDY, tie the pin Low to yield control to ARDY. TMRIN0/PIO11 Timer Input 0 (input, synchronous, edge-sensitive) This pin supplies a clock or control signal to the internal microcontroller timer 0. After internally synchronizing a Low-to-High transition on TMRIN0, the microcontroller increments the timer. TMRIN0 must be tied High if not being used. 32 TMROUT0/PIO10 Timer Output 0 (output, synchronous) This pin supplies the system with either a single pulse or a continuous waveform with a programmable duty cycle. TMROUT0 is floated during a bus hold or reset. TMROUT1/PIO1 Timer Output 1 (output, synchronous) This pin supplies the system with either a single pulse or a continuous waveform with a programmable duty cycle. TMROUT1 can also be programmed as a watchdog timer. TMROUT1 is floated during a bus hold or reset. TXD/PIO27 Transmit Data (output, asynchronous) This pin supplies asynchronous serial transmit data to the system from the internal UART of the microcontroller. UCS/ONCE1 Upper Memory Chip Select (output, synchronous) ONCE Mode Request 1 (input, internal pullup) UCS—This pin indicates to the system that a memory access is in progress to the upper memory block. The base address and size of the upper memory block are programmable up to 512 Kbytes. UCS is held High during a bus hold condition. After power-on reset, UCS is asserted because the processor begins executing at FFFF0h and the default configuration for the UCS chip select is 64 Kbytes from F0000h to FFFFFh. ONCE1—During reset, this pin and ONCE0 indicate to the microcontroller the mode in which it should operate. ONCE0 and ONCE1 are sampled on the rising edge of RES. If both pins are asserted Low, the microcontroller enters ONCE mode. Otherwise, it operates normally. In ONCE mode, all pins assume a high-impedance state and remain in that state until a subsequent reset occurs. To guarantee that the microcontroller does not inadvertently enter ONCE mode, ONCE1 has a weak internal pullup resistor that is active only during a reset. This pin is not three-stated during a bus hold condition. Am186/188EM and Am186/188EMLV Microcontrollers P R E L I M I N A R Y UZI/PIO26 X1 Upper Zero Indicate (output, synchronous) Crystal Input (input) UZI—This pin lets the designer determine if an access to the interrupt vector table is in progress by ORing it with bits 15–10 of the address and data bus (AD15– AD10 on the 186 and AO15–AO10 on the 188). UZI is the logical OR of the inverted A19–A16 bits, and it asserts in the first period of a bus cycle and is held throughout the cycle. This pin and the X2 pin provide connections for a fundamental mode or third-overtone parallel-resonant crystal used by the internal oscillator circuit. To provide the microcontroller with an external clock source, connect the source to the X1 pin and leave the X2 pin unconnected. This signal should be pulled High or allowed to float at reset. If this pin is Low at the negation of reset, the Am186EM and Am188EM microcontrollers will enter a reserved clock test mode. VCC Power Supply (input) These pins supply power (+5 V) to the microcontroller. X2 Crystal Output (output) This pin and the X1 pin provide connections for a fundamental mode or third-overtone parallel-resonant crystal used by the internal oscillator circuit. To provide the microcontroller with an external clock source, leave the X2 pin unconnected and connect the source to the X1 pin. WHB (Am186EM Microcontroller Only) Write High Byte (output, three-state, synchronous) This pin and WLB indicate to the system which bytes of the data bus (upper, lower, or both) participate in a write cycle. In 80C186 designs, this information is provided by BHE, AD0, and WR. However, by using WHB and WLB, the standard system interface logic and external address latch that were required are eliminated. WHB is asserted with AD15–AD8. WHB is the logical OR of BHE and WR. This pin floats during reset. WLB (Am186EM Microcontroller Only) WB (Am188EM Microcontroller Only) Write Low Byte (output, three-state, synchronous) Write Byte (output, three-state, synchronous) WLB—This pin and WHB indicate to the system which bytes of the data bus (upper, lower, or both) participate in a write cycle. In 80C186 designs, this information is provided by BHE, AD0, and WR. However, by using WHB and WLB, the standard system interface logic and external address latch that were required are eliminated. WLB is asserted with AD7–AD0. WLB is the logical OR of AD0 and WR. This pin floats during reset. WB—On the Am188EM microcontroller, this pin indicates a write to the bus. WB uses the same early timing as the nonmultiplexed address bus. WB is associated with AD7–AD0. This pin floats during reset. WR Write Strobe (output, synchronous) This pin indicates to the system that the data on the bus is to be written to a memory or I/O device. WR floats during a bus hold or reset condition. Am186/188EM and Am186/188EMLV Microcontrollers 33 P R E L I M I N A R Y FUNCTIONAL DESCRIPTION Shift Left 4 Bits AMD’s Am186 and Am188 family of microcontrollers and microprocessors is based on the architecture of the original 8086 and 8088 microcontrollers and currently includes the 80C186, 80C188, 80L186, 80L188, Am186EM, Am188EM, Am186EMLV, Am188EMLV, Am186ES, Am188ES, Am186ESLV, Am188ESLV, Am186ER, and Am188ER microcontrollers. All family members contain the same basic set of registers, instructions, and addressing modes and are compatible with the industry-standard 80C186/188 microcontrollers. A full description of all the Am186EM and Am188EM microcontroller registers is included in the Am186EM and Am188EM Microcontrollers User’s Manual, order# 19713. The instruction set for the Am186EM and Am188EM microcontrollers is documented in the Am186 and Am188 Family Instruction Set Manual, order# 21267. Memory Organization 2 A 4 19 2 A 0 15 0 2 4 Segment Logical 0 Base Address 2 Offset 0 0 0 0 0 15 0 1 2 A 2 6 19 2 0 2 Physical Address 0 To Memory Figure 2. Two-Component Address Memory is organized in sets of segments. Each segment is a linear contiguous sequence of 64K (216) 8-bit bytes. Memory is addressed using a two-component address that consists of a 16-bit segment value and a 16-bit offset. The 16-bit segment values are contained in one of four internal segment registers (CS, DS, SS, or ES). The physical address is calculated by shifting the segment value left by 4 bits and adding the 16-bit offset value to yield a 20-bit physical address (see Figure 3). This allows for a 1-Mbyte physical address size. All instructions that address operands in memory must specify the segment value and the 16-bit offset value. For speed and compact instruction encoding, the segment register used for physical address generation is implied by the addressing mode used (see Table 5). Table 5. 34 1 1 15 I/O Space The I/O space consists of 64K 8-bit or 32K 16-bit ports. Separate instructions (IN, INS and OUT, OUTS) address the I/O space with either an 8-bit port address specified in the instruction, or a 16-bit port address in the DX register. Eight-bit port addresses are zero-extended so that A15–A8 are Low. I/O port addresses 00F8h through 00FFh are reserved. The Am186EM and Am188EM microcontrollers provide specific instructions for addressing I/O space. Segment Register Selection Rules Memory Reference Needed Instructions Local Data Segment Register Used Code (CS) Data (DS) Stack Stack (SS) External Data (Global) Extra (ES) Implicit Segment Selection Rule Instructions (including immediate data) All data references All stack pushes and pops; any memory references that use BP Register All string instruction references that use the DI Register as an index Am186/188EM and Am186/188EMLV Microcontrollers P R E L I M I N A R Y BUS OPERATION The industry-standard 80C186 and 80C188 microcontrollers use a multiplexed address and data (AD) bus. The address is present on the AD bus only during the t1 clock phase. The Am186EM and Am188EM microcontrollers continue to provide the multiplexed AD bus and, in addition, provide a nonmultiplexed address (A) bus. The A bus provides an address to the system for the complete bus cycle (t1–t4). For systems where power consumption is a concern, it is possible to disable the address from being driven on the AD bus on the Am186EM microcontroller and on the AD and AO buses on the Am188EM microcontroller during the normal address portion of the bus cycle for accesses to UCS and/or LCS address spaces. In this mode, the affected bus is placed in a high impedance state during the address portion of the bus cycle. This feature is enabled through the DA bits in the UMCS and LMCS registers. When address disable is in effect, the number of signals that assert on the bus during all normal bus cycles to the associated address space is reduced, decreasing power consumption and reducing processor switching noise. On the Am188EM microcontroller, the address is driven on A015–A08 during the data portion of the bus cycle, regardless of the setting of the DA bits. If the ADEN pin is pulled Low during processor reset, the value of the DA bits in the UMCS and LMCS registers is ignored and the address is driven on the AD bus for all ac- t1 cesses, thus preserving the industry-standard 80C186 and 80C188 microcontrollers’ multiplexed address bus and providing support for existing emulation tools. The following diagrams show the Am186EM and Am188EM microcontroller bus cycles when the address bus disable feature is in effect. Figure 3 shows the affected signals during a normal read or write operation for an Am186EM microcontroller. The address and data will be multiplexed onto the AD bus. Figure 4 shows an Am186EM microcontroller bus cycle when address bus disable is in effect. This results in having the AD bus operate in a nonmultiplexed address/data mode. The A bus will have the address during a read or write operation. Figure 5 shows the affected signals during a normal read or write operation for an Am188EM microcontroller. The multiplexed address/data mode is compatible with the 80C186 and 80C188 microcontrollers and might be used to take advantage of existing logic or peripherals. Figure 6 shows an Am188EM microcontroller bus cycle when address bus disable is in effect. The address and data is not multiplexed. The AD7–AD0 signals will have only data on the bus, while the AO bus will have the address during a read or write operation. t2 Address Phase t3 t4 Data Phase CLKOUTA Address A19–A0 AD15–AD0 (Read) Address AD15–AD0 (Write) Address Data Data LCS or UCS MCSx, PCSx Figure 3. Am186EM Microcontroller Address Bus—Normal Read and Write Operation Am186/188EM and Am186/188EMLV Microcontrollers 35 P R E L I M I N A R Y t1 Address Phase t2 t3 Data Phase t4 CLKOUTA A19–A0 Address AD7–AD0 (Read) Data AD15–AD8 (Read) Data AD15–AD0 (Write) Data LCS, UCS Figure 4. Am186EM Microcontroller—Read and Write with Address Bus Disable In Effect t1 t2 t3 Address Phase t4 Data Phase CLKOUTA Address A19–A0 AD7–AD0 (Read) Address AO15–AO8 (Read or Write) AD7–AD0 (Write) Data Address Address Data LCS or UCS MCSx, PCSx Figure 5. 36 Am188EM Microcontroller Address Bus—Normal Read and Write Operation Am186/188EM and Am186/188EMLV Microcontrollers P R E L I M I N A R Y t1 t2 Address Phase t3 t4 Data Phase CLKOUTA A19–A0 Address AD7–AD0 (Read) Data AO15–AO8 Address AD7–AD0 (Write) Data LCS, UCS Figure 6. Am188EM Microcontroller—Read and Write with Address Bus Disable In Effect BUS INTERFACE UNIT Byte Write Enables The bus interface unit controls all accesses to external peripherals and memory devices. External accesses include those to memory devices, as well as those to memory-mapped and I/O-mapped peripherals and the p er i p h e r a l c o n tr o l b l o c k . T h e A m 1 8 6 E M a nd Am188EM microcontrollers provide an enhanced bus interface unit with the following features: The Am186EM microcontroller provides the WHB (Write High Byte) and WLB (Write Low Byte) signals, which act as byte write enables. n A nonmultiplexed address bus n Separate byte write enables for high and low bytes in the Am186EM microcontroller only n Pseudo Static RAM (PSRAM) support WHB is the logical OR of BHE and WR. WHB is Low when BHE and WR are both Low. WLB is the logical OR of AD0 and WR. WLB is Low when AD0 and WR are both Low. WB is Low whenever a byte is written on the Am188EM microcontroller. The byte write enables are driven in conjunction with the nonmultiplexed address bus as required for the write timing requirements of common SRAMs. The standard 80C186/188 multiplexed address and data bus requires system interface logic and an external address latch. On the Am186EM and Am188EM microcontrollers, new byte write enables, PSRAM control logic, and a new nonmultiplexed address bus can reduce design costs by eliminating this external logic. Nonmultiplexed Address Bus The nonmultiplexed address bus (A19–A0) is valid one-half CLKOUTA cycle in advance of the address on the AD bus. When used in conjunction with the modified UCS and LCS outputs and the byte write enable signals, the A19–A0 bus provides a seamless interface to SRAM, PSRAM, and Flash/EPROM memory systems. Am186/188EM and Am186/188EMLV Microcontrollers 37 P R E L I M I N A R Y Pseudo Static RAM (PSRAM) Support PERIPHERAL CONTROL BLOCK (PCB) The Am186EM and Am188EM microcontrollers support the use of PSRAM devices in low memory chip-select (LCS) space only. When PSRAM mode is enabled, the timing for the LCS signal is modified by the chip-select control unit to provide a CS precharge period during PSRAM accesses. The 40-MHz timing of the Am186EM and Am188EM microcontrollers is appropriate to allow 70-ns PSRAM to run with one wait state. PSRAM mode is enabled through a bit in the Low Memory Chip-Select (LMCS) Register. The PSRAM feature is disabled on CPU reset. The integrated peripherals of the Am186EM and Am188EM microcontrollers are controlled by 16-bit read/write registers. The peripheral registers are contained within an internal 256-byte control block. The registers are physically located in the peripheral devices they control, but they are addressed as a single 256-byte block. Figure 7 shows a map of these registers. In addition to the LCS timing changes for PSRAM precharge, the PSRAM devices also require periodic refresh of all internal row addresses to retain their data. Although refresh of PSRAM can be accomplished several ways, the Am186EM and Am188EM microcontrollers implement auto refresh only. The Am186EM and Am188EM microcontrollers generate RFSH, a refresh signal, to the PSRAM devices when PSRAM mode is enabled. No refresh address is required by the PSRAM when using the auto refresh mechanism. The RFSH signal is multiplexed with the MCS3 signal pin. When PSRAM mode is enabled, MCS3 is not available for use as a chip-select signal. The refresh control unit must be programmed before accessing PSRAM in LCS space. The refresh counter in the Clock Prescaler (CDRAM) Register must be configured with the required refresh interval value. The ending address of LCS space and the ready and waitstate generation in the LMCS Register must also be programmed. The refresh counter reload value in the CDRAM Register should not be set to less than 18 (12h) in order to provide time for processor cycles within refresh. The refresh address counter must be set to 000000h to prevent another chip select from asserting. Reading and Writing the PCB Code that is intended to execute on the Am188EM microcontroller should perform all writes to the PCB registers as byte writes. These writes will transfer 16 bits of data to the PCB register even if an 8-bit register is named in the instruction. For example, out dx, al results in the value of ax being written to the port address in dx. Reads to the PCB should be done as word reads. Code written in this manner will run correctly on the Am188EM microcontroller and on the Am186EM microcontroller. Unaligned reads and writes to the PCB result in unpredi cta ble beh av ior on both the A m18 6E M an d Am188EM microcontrollers. For a complete description of all the registers in the PCB, see the Am186EM and Am188EM Microcontrollers User’s Manual, order# 19713. LCS is held High during a refresh cycle. The A bus is not used during refresh cycles. The LMCS Register must be configured to external ready ignored (R2=1) with one wait state (R1–R0=01b), and the PSRAM mode enable bit (SE) must be set. 38 Am186/188EM and Am186/188EMLV Microcontrollers P R E L I M I N A R Y Offset (Hexadecimal) Register Name FE Peripheral Control Block Relocation Register w w F6 Reset Configuration Register F4 Processor Release Level Register F0 PDCON Register w w E4 Enable RCU Register E2 Clock Prescaler Register E0 Memory Partition Register w w DA DMA 1 Control Register D8 DMA 1 Transfer Count Register D6 DMA 1 Destination Address High Register D4 DMA 1 Destination Address Low Register D2 DMA 1 Source Address High Register D0 DMA 1 Source Address Low Register CA DMA 0 Control Register C8 DMA 0 Transfer Count Register C6 DMA 0 Destination Address High Register C4 DMA 0 Destination Address Low Register C2 DMA 0 Source Address High Register C0 DMA 0 Source Address Low Register w w A8 PCS and MCS Auxiliary Register A6 Midrange Memory Chip Select Register A4 Peripheral Chip Select Register A2 Low Memory Chip Select Register A0 Upper Memory Chip Select Register 88 w w Serial Port Baud Rate Divisor Register 86 Serial Port Receive Register 84 Serial Port Transmit Register 82 Serial Port Status Register 80 Serial Port Control Register Figure 7. Changed from 80C186 microcontroller. Note: Gaps in offset addresses indicate reserved registers. Peripheral Control Block Register Map Am186/188EM and Am186/188EMLV Microcontrollers 39 P R E L I M I N A R Y Offset (Hexadecimal) w Register Name 7A PIO Data 1 Register 78 PIO Direction 1 Register 76 74 PIO Mode 1 Register PIO Data 0 Register 72 PIO Direction 0 Register 70 PIO Mode 0 Register w w 66 Timer 2 Mode/Control Register 62 Timer 2 Maxcount Compare A Register Timer 2 Count Register 60 5E Timer 1 Mode/Control Register 5C Timer 1 Maxcount Compare B Register Timer 1 Maxcount Compare A Register 5A 58 Timer 1 Count Register 56 54 52 Timer 0 Mode/Control Register Timer 0 Maxcount Compare B Register 50 Timer 0 Count Register Timer 0 Maxcount Compare A Register w w 44 Serial Port Interrupt Control Register 42 Watchdog Timer Control Register 40 INT4 Control Register 3E INT3 Control Register 3C INT2 Control Register INT1 Control Register 3A INT0 Control Register DMA 1 Interrupt Control Register 38 36 34 32 DMA 0 Interrupt Control Register Timer Interrupt Control Register Interrupt Status Register Interrupt Request Register 30 2E 2C In-service Register 2A Priority Mask Register 28 Interrupt Mask Register 26 Poll Status Register 24 22 Poll Register End-of-Interrupt Register 20 Interrupt Vector Register 18 Synchronous Serial Receive Register 16 14 Synchronous Serial Transmit 0 Register 12 Synchronous Serial Enable Register 10 Synchronous Serial Status Register Synchronous Serial Transmit 1 Register Figure 7. 40 w Changed from 80C186 microcontroller. Note: Gaps in offset addresses indicate reserved registers. Peripheral Control Block Register Map (continued) Am186/188EM and Am186/188EMLV Microcontrollers P R E L I M I N A R Y CLOCK AND POWER MANAGEMENT The clock and power management unit of the Am186EM and Am188EM microcontrollers includes a phase-locked loop (PLL) and a second programmable system clock output (CLKOUTB). fect the operation of the clock generator. Values for the loading on X1 and X2 must be chosen to provide the necessary phase shift and crystal operation. Phase-Locked Loop (PLL) When selecting a crystal, the load capacitance should always be specified (CL). This value can cause variance in the oscillation frequency from the desired specified value (resonance). The load capacitance and the loading of the feedback network have the following relationship: In a traditional 80C186/188 design, the crystal frequency is twice that of the desired internal clock. Because of the internal PLL on the Am186EM and Am188EM microcontrollers, the internal clock generated by the Am186EM and Am188EM microcontrollers (CLKOUTA) is the same frequency as the crystal. The PLL takes the crystal inputs (X1 and X2) and generates a 45/55% (worst case) duty cycle intermediate system clock of the same frequency. This removes the need for an external 2x oscillator, reducing system cost. The PLL is reset by an on-chip power-on reset (POR) circuit. Crystal-Driven Clock Source The internal oscillator circuit of the Am186EM and Am188EM microcontrollers is designed to function with a parallel-resonant fundamental or third-overtone crystal. Because of the PLL, the crystal frequency should be equal to the processor frequency. Do not replace a crystal with an LC or RC equivalent. The signals X1 and X2 are connected to an internal inverting amplifier (oscillator) which provides, along with the external feedback loading, the necessary phase shift (Figure 8). In such a positive feedback circuit, the inverting amplifier has an output signal (X2) 180 degrees out of phase of the input signal (X1). The external feedback network provides an additional 180-degree phase shift. In an ideal system, the input to X1 will have 360 or zero degrees of phase shift. The external feedback network is designed to be as close to ideal as possible. If the feedback network is not providing necessary phase shift, negative feedback will dampen the output of the amplifier and negatively af- Selecting a Crystal CL = (C1 ⋅ C2) + CS (C1 + C2) where CS is the stray capacitance of the circuit. Placing the crystal and CL in series across the inverting amplifier and tuning these values (C1, C2) allows the crystal to oscillate at resonance. This relationship is true for both fundamental and third-overtone operation. Finally, there is a relationship between C1 and C2. To enhance the oscillation of the inverting amplifier, these values need to be offset with the larger load on the output (X2). Equal values of these loads will tend to balance the poles of the inverting amplifier. The characteristics of the inverting amplifier set limits on the following parameters for crystals: ESR (Equivalent Series Resistance)........... 80 ohm max Drive Level ..................................................................................... 1 mW max The recommended range of values for C1 and C2 are as follows: C1 .............................................................................................................. 15 pF ± 20% C2 .............................................................................................................. 22 pF ± 20% The specific values for C1 and C2 must be determined by the designer and are dependent on the characteristics of the chosen crystal and board design. C1 X1 Crystal X2 Crystal C1 C2 C2 a. Inverting Amplifier Configuration Figure 8. Note 1 Note 1: Use for Third Overtone Mode XTAL Frequency L1 Value (Max) 20 MHz 12 µH ±20% 25 MHz 8.2 µH ±20% 33 MHz 4.7 µH ±20% 40 MHz 3.0 µH ±20% Am186EM Microcontroller 200 pF b. Crystal Configuration Am186EM and Am188EM Microcontrollers Oscillator Configurations Am186/188EM and Am186/188EMLV Microcontrollers 41 P R E L I M I N A R Y External Source Clock CLKOUTB operate at either the processor frequency or the crystal input frequency. The output drivers for both clocks are individually programmable for disable. Figure 9 shows the organization of the clocks. Alternately, the internal oscillator can be driven from an external clock source. This source should be connected to the input of the inverting amplifier (X1), with the output (X2) not connected. The second clock output (CLKOUTB) allows one clock to run at the crystal input frequency and the other clock to run at the power-save frequency. Individual drive enable bits allow selective enabling of just one or both of these clock outputs. System Clocks The base system clock of the 80C186 and 80C188 microcontrollers is renamed CLKOUTA and the additional output is called CLKOUTB. CLKOUTA and Processor Internal Clock Power-Save Divisor (/2 to /128) PLL X1, X2 CLKOUTA Mux Drive Enable Mux Time Delay 6 ± 2.5ns CLKOUTB Drive Enable Figure 9. Clock Organization Power-Save Operation The power-save mode of the Am186EM and Am188EM microcontrollers reduces power consumption and heat dissipation, thereby extending battery life in portable systems. In power-save mode, operation of the CPU and internal peripherals continues at a slower clock frequency. When an interrupt occurs, the microcontroller automatically returns to its normal operating frequency on the internal clock’s next rising edge of t3. In order for an interrupt to be recognized, it must be valid before the internal clock’s rising edge of t3. Note: Power-save operation requires that clock-dependent devices be reprogrammed for clock frequency changes. Software drivers must be aware of clock frequency. Initialization and Processor Reset Processor initialization or startup is accomplished by driving the RES input pin Low. RES must be held Low for 1 ms during power-up to ensure proper device initialization. RES forces the Am186EM and Am188EM microcontrollers to terminate all execution and local bus activity. No instruction or bus activity occurs as long as RES is active. 42 After RES becomes inactive and an internal processing interval elapses, the microcontroller begins execution with the instruction at physical location FFFF0h. RES also sets some registers to predefined values. The Reset Configuration Register When the RES input is asserted Low, the contents of the address/data bus (AD15–AD0) are written into the Reset Configuration register. The system can place configuration information on the address/data bus using weak external pullup or pulldown resistors, or using an external driver that is enabled during reset. The processor does not drive the address/data bus during reset. For example, the Reset Configuration register could be used to provide the software with the position of a configuration switch in the system. Using weak external pullup and pulldown resistors on the address and data bus, the system would provide the microcontroller with a value corresponding to the position of the jumper during a reset. Am186/188EM and Am186/188EMLV Microcontrollers P R E L I M I N A R Y CHIP-SELECT UNIT Chip-Select Overlap The Am186EM and Am188EM microcontrollers contain logic that provides programmable chip-select generation for both memories and peripherals. The logic can be programmed to provide ready and wait-state generation and latched address bits A1 and A2. The chip-select lines are active for all memory and I/O cycles in their programmed areas, whether they are generated by the CPU or by the integrated DMA unit. Although programming the various chip selects on the Am186EM and Am188EM microcontrollers so that multiple chip select signals are asserted for the same physical address is not recommended, it may be unavoidable in some systems. In such systems, the chip selects whose assertions overlap must have the same configuration for ready (external ready required or not required) and the number of wait states to be inserted into the cycle by the processor. The Am186EM and Am188EM microcontrollers provide six chip-select outputs for use with memory devices and six more for use with peripherals in either memory space or I/O space. The six chip selects for memory devices can be used to address three memory ranges. Each of the six peripheral chip selects addresses a 256-byte block that is offset from a programmable base address. A read or write access to the corresponding chip select register activates the chip selects. Chip-Select Timing The timing for the UCS and LCS outputs is modified from the original 80C186 microcontroller. These outputs now assert in conjunction with the nonmultiplexed address bus for normal memory timing. To allow these outputs to be available earlier in the bus cycle, the number of programmable memory size selections has been reduced. Ready and Wait-State Programming The Am186EM and Am188EM microcontrollers can be programmed to sense a ready signal for each of the peripheral or memory chip-select lines. The ready signal can be either the ARDY or SRDY signal. Each chip-select control register (UMCS, LMCS, MMCS, PACS, and MPCS) contains a single-bit field that determines whether the external ready signal is required or ignored. The number of wait states to be inserted for each access to a peripheral or memory region is programmable. The chip-select control registers for UCS, LCS, MCS3–MCS0, PCS6, and PCS5 contain a two-bit field that determines the number of wait states from zero to three to be inserted. PCS3–PCS0 use three bits to provide additional values of 5, 7, 9, and 15 wait states. When external ready is required, internally programmed wait states will always complete before external ready can terminate or extend a bus cycle. For example, if the internal wait states are set to insert two wait states, the processor samples the external ready pin during the first wait cycle. If external ready is asserted at that time, the access completes after six cycles (four cycles plus two wait states). If external ready is not asserted during the first wait state, the access is extended until ready is asserted, which is followed by one more wait state followed by t4. The peripheral control block (PCB) is accessed using internal signals. These internal signals function as chip selects configured with zero wait states and no external ready. Therefore, the PCB can be programmed to addresses that overlap external chip select signals if those external chip selects are programmed to zero wait states with no external ready required. When overlapping an additional chip select with either the LCS or UCS chip selects, it must be noted that setting the Disable Address (DA) bit in the LMCS or UMCS register will disable the address from being driven on the AD bus for all accesses for which the associated chip select is asserted, including any accesses for which multiple chip selects assert. The MCS and PCS chip select pins can be configured as either chip selects (normal function) or as PIO inputs or outputs. It should be noted; however, that the ready and wait state generation logic for these chip selects is in effect regardless of their configurations as chip selects or PIOs. This means that if these chip selects are enabled (by a read or write to the MMCS and MPCS for the MCS chip selects, or by a read or write to the PACS and MPCS registers for the PCS chip selects), the ready and wait state programming for these signals must agree with the programming for any other chip selects with which their assertion would overlap if they were configured as chip selects. Although the PCS4 signal is not available on an external pin, the ready and wait state logic for this signal still exists internal to the part. For this reason, the PCS4 address space must follow the rules for overlapping chip selects. The ready and wait-state logic for PCS6– PCS5 is disabled when these signals are configured as address bits A2–A1. Failure to configure overlapping chip selects with the same ready and wait state requirements may cause the processor to hang with the appearance of waiting for a ready signal. This behavior may occur even in a system in which ready is always asserted (ARDY or SRDY tied High). Am186/188EM and Am186/188EMLV Microcontrollers 43 P R E L I M I N A R Y Configuring PCS in I/O space with LCS or any other chip select configured for memory address 0 is not considered overlapping of the chip selects. Overlapping chip selects refers to configurations where more than one chip select asserts for the same physical address. Upper Memory Chip Select The Am186EM and Am188EM microcontrollers provide a UCS chip select for the top of memory. On reset, the Am186EM and Am188EM microcontrollers begin fetching and executing instructions starting at memory location FFFF0h. Therefore, upper memory is usually used as instruction memory. To facilitate this usage, UCS defaults to active on reset, with a default memory range of 64 Kbytes from F0000h to FFFFFh, with external ready required and three wait states automatically inserted. The UCS memory range always ends at FFFFFh. The lower boundary is programmable. Low Memory Chip Select The Am186EM and Am188EM microcontrollers provide an LCS chip select for the bottom of memory. Since the interrupt vector table is located at the bottom of memory starting at 00000h, the LCS pin is usually used to control data memory. The LCS pin is not active on reset. Midrange Memory Chip Selects The Am186EM and Am188EM microcontrollers provide four chip selects, MCS3–MCS0, for use in a userlocatable memory block. The base address of the memory block can be located anywhere within the 1-Mbyte memory address space, exclusive of the areas associated with the UCS and LCS chip selects, as well as the address range of the Peripheral Chip Selects, PCS6, PCS5, and PCS3–PCS0, if they are mapped to memory. The MCS address range can overlap the PCS address range if the PCS chip selects are mapped to I/O space. Unlike the UCS and LCS chip selects, the MCS outputs assert with the multiplexed AD address bus. Peripheral Chip Selects The Am186EM and Am188EM microcontrollers provide six chip selects, PCS6–PCS5 and PCS3–PCS0, for use within a user-locatable memory or I/O block. PCS4 is not available on the Am186EM and Am188EM microcontrollers. The base address of the memory block can be located anywhere within the 1-Mbyte memory address space, exclusive of the areas associated with the UCS, LCS, and MCS chip selects, or they can be configured to access the 64 Kbyte I/O space. The PCS pins are not active on reset. PCS6–PCS5 can have from zero to three wait states. PCS3–PCS0 can have four additional wait-state values—5, 7, 9, and 15. Unlike the UCS and LCS chip selects, the PCS outputs assert with the multiplexed AD address bus. Note also that each peripheral chip select asserts over a 256-byte address range, which is twice the address range covered by peripheral chip selects in the 80C186 and 80C188 microcontrollers. 44 Am186/188EM and Am186/188EMLV Microcontrollers P R E L I M I N A R Y REFRESH CONTROL UNIT INTERRUPT CONTROL UNIT The Refresh Control Unit (RCU) automatically generates refresh bus cycles. After a programmable period of time, the RCU generates a memory read request to the bus interface unit. The RCU is fixed to three wait states for the PSRAM auto refresh mode. The Am186EM and Am188EM microcontrollers can receive interrupt requests from a variety of sources, both internal and external. The internal interrupt controller arranges these requests by priority and presents them one at a time to the CPU. If the HLDA pin is active when a refresh request is generated (indicating a bus hold condition), then the Am186EM and Am188EM microcontrollers deactivate the HLDA pin in order to perform a refresh cycle. The external bus master must remove the HOLD signal for at least one clock in order to allow the refresh cycle to execute. The sequence of HLDA going inactive while HOLD is being held active can be used to signal a pending refresh request. There are six external interrupt sources on the Am186EM and Am188EM microcontrollers—five maskable interrupt pins and one nonmaskable interrupt pin. In addition, there are six total internal interrupt sources—three timers, two DMA channels, and the asynchronous serial port—that are not connected to external pins. The Am186EM and Am188EM microcontrollers provide three interrupt sources not present on the Am186 and Am188 microcontrollers. The first is an additional external interrupt pin (INT4). This pin operates much like the already existing interrupt pins (INT3–INT0). The second is an internal watchdog timer interrupt. The third is an internal interrupt from the asynchronous serial port. The five maskable interrupt request pins can be used as direct interrupt requests, or they can be cascaded with an 82C59A-compatible external interrupt controller if more inputs are needed. An external interrupt contr ol l er c an be u s ed as the s ys te m m as te r by programming the internal interrupt controller to operate in slave mode. In all cases, nesting can be enabled so that interrupt service routines for lower priority interrupts are interrupted by a higher priority interrupt. Am186/188EM and Am186/188EMLV Microcontrollers 45 P R E L I M I N A R Y TIMER CONTROL UNIT DIRECT MEMORY ACCESS (DMA) There are three 16-bit programmable timers in the Am186EM and Am188EM microcontrollers. Timer 0 and timer 1 are connected to four external pins (each one has an input and an output). These two timers can be used to count or time external events, or to generate nonrepetitive or variable-duty-cycle waveforms. In addition, timer 1 can be configured as a watchdog timer interrupt. Direct memory access (DMA) permits transfer of data between memory and peripherals without CPU involvement. The DMA unit in the Am186EM and Am188EM microcontrollers, shown in Figure 10, provides two high-speed DMA channels. Data transfers can occur between memory and I/O spaces (e.g., memory to I/O) or within the same space (e.g., memory-to-memory or I/O-toI/O). In addition, either bytes or words can be transferred to or from even or odd addresses on the Am186EM microcontroller. The Am188EM microcontroller does not support word transfers. Only two bus cycles (a minimum of eight clocks) are necessary for each data transfer. The watchdog timer interrupt provides a mechanism for detecting software crashes or hangs. The TMROUT1 output is internally connected to the watchdog timer interrupt. The TIMER1 count register must then be reloaded at intervals less than the TIMER1 max count to assure the watchdog interrupt is not taken. If the code crashes or hangs, the TIMER1 countdown will cause a watchdog interrupt. Timer 2 is not connected to any external pins. It can be used for real-time coding and time-delay applications. It can also be used as a prescale to timers 0 and 1 or as a DMA request source. The timers are controlled by eleven 16-bit registers in the peripheral control block. A timer’s timer-count register contains the current value of that timer. The timercount register can be read or written with a value at any time, regardless of whether the timer is running. The microcontroller increments the value of the timer-count register each time a timer event occurs. Each timer also has a maximum-count register that defines the maximum value the timer will reach. When the timer reaches the maximum value, it resets to 0 during the same clock cycle—the value in the maximum-count register is never stored in the timer-count register. Also, timers 0 and 1 have a secondary maximum-count register. Using both the primary and secondary maximum-count registers lets the timer alternate between two maximum values. If the timer is programmed to use only the primary maximum-count register, the timer output pin switches Low for one clock cycle after the maximum value is reached. If the timer is programmed to use both of its maximum-count registers, the output pin indicates which maximum-count register is currently in control, thereby creating a waveform. The duty cycle of the waveform depends on the values in the maximumcount registers. Each channel accepts a DMA request from one of three sources—the channel request pin (DRQ1– DRQ0), timer 2, or the system software. The channels can be programmed with different priorities in the event of a simultaneous DMA request or if there is a need to interrupt transfers on the other channel. DMA Operation Each channel has six registers in the peripheral control block that define specific channel operations. The DMA registers consist of a 20-bit source address (2 registers), a 20-bit destination address (2 registers), a 16-bit transfer count register, and a 16-bit control register. The DMA transfer count register (DTC) specifies the number of DMA transfers to be performed. Up to 64K byte or word transfers can be performed with automatic termination. The DMA control registers define the channel operation. All registers can be modified during any DMA activity. Any changes made to the DMA registers are reflected immediately in DMA operation. Table 6. Am186EM Microcontroller Maximum DMA Transfer Rates Type of Synchronization Selected Unsynchronized 10 8.25 6.25 5 Source Synch 10 8.25 6.25 5 6.6 5.5 4.16 3.3 8 6.6 5 4 Destination Synch (CPU needs bus) Destination Synch (CPU does not need bus) Each timer is serviced every fourth clock cycle, so a timer can operate at a speed of up to one-quarter the internal clock frequency. A timer can be clocked externally at this same frequency; however, because of internal synchronization and pipelining of the timer circuitry, the timer output may take up to six clock cycles to respond to the clock or gate input. 46 Maximum DMA Transfer Rate (Mbyte/s) 40 33 25 20 MHz MHz MHz MHz Am186/188EM and Am186/188EMLV Microcontrollers P R E L I M I N A R Y Adder Control Logic 20-bit Adder/Subtractor Timer Request DRQ1 20 Request Selection Logic Transfer Counter Ch. 1 Destination Address Ch. 1 Source Address Ch. 1 Transfer Counter Ch. 0 Destination Address Ch. 0 Source Address Ch. 0 DRQ0 DMA Control Logic Interrupt Request Channel Control Register 1 Channel Control Register 0 20 16 Internal Address/Data Bus Figure 10. DMA Unit Block Diagram DMA Channel Control Registers DMA Priority Each DMA control register determines the mode of operation for the particular DMA channel. This register specifies the following: The DMA channels can be programmed so that one channel is always given priority over the other, or they can be programmed to alternate cycles when both have DMA requests pending. DMA cycles always have priority over internal CPU cycles, except between locked memory accesses or word accesses to odd memory locations. However, an external bus hold takes priority over an internal DMA cycle. n The mode of synchronization n Whether bytes or words are transferred n If an interrupt is generated after the last transfer n If DMA activity ceases after a programmed number of DMA cycles n The relative priority of the DMA channel with respect to the other DMA channel n Whether the source address is incremented, decremented, or maintained constant after each transfer Because an interrupt request cannot suspend a DMA operation and the CPU cannot access memory during a DMA cycle, interrupt latency time suffers during sequences of continuous DMA cycles. An NMI request, however, causes all internal DMA activity to halt. This allows the CPU to respond quickly to the NMI request. n Whether the source address addresses memory or I/O space n Whether the destination address is incremented, decremented, or maintained constant after transfers n Whether the destination address addresses memory or I/O space Am186/188EM and Am186/188EMLV Microcontrollers 47 P R E L I M I N A R Y ASYNCHRONOUS SERIAL PORT SYNCHRONOUS SERIAL INTERFACE The Am186EM and Am188EM microcontrollers provide an asynchronous serial port. The asynchronous serial port is a two-pin interface that permits full-duplex bidirectional data transfer. The asynchronous serial port supports the following features: The synchronous serial interface (SSI) lets the Am186EM and Am188EM microcontrollers communicate with application-specific integrated circuits (ASICs) that require reprogrammability but are short on pins. This four-pin interface permits half-duplex, bidirectional data transfer at speeds of up to 20 Mbits/sec. n Full-duplex operation n 7-bit or 8-bit data transfers n Odd, even, or no parity n 1 or 2 stop bits If additional RS-232 signals are required, they can be created with available PIO pins. The asynchronous serial port transmit and receive sections are double buffered. Break character, framing, parity, and overrun error detection are provided. Exception interrupt generation is programmable by the user. The transmit/receive clock is based on the internal processor clock, which is divided down internally to the serial port operating frequency. The serial port permits 7bit and 8-bit data transfers. DMA transfers through the serial port are not supported. The serial port generates one interrupt for any of three serial port events—transmit complete, data received, and error. Unlike the asynchronous serial port, the SSI operates in a master/slave configuration. The Am186EM and Am188EM microcontrollers are the master port. The SSI interface provides four pins for communicating with system components: two enables (SDEN0 and SDEN1), a clock (SCLK), and a data pin (SDATA). Five registers are used to control and monitor the interface. Four-Pin Interface The two enable pins SDEN1–SDEN0 can be used directly as enables for up to two peripheral devices. Transmit and receive operations are synchronized between the master (Am186EM and Am188EM microcontrollers) and slave (peripheral) by means of the SCLK output. SCLK is derived from the internal processor clock and is the processor clock divided by 2, 4, 8, or 16. The serial port can be used in power-save mode, but the software must adjust the transfer rate to correctly reflect the new internal operating frequency and must ensure that the serial port does not receive any information while the frequency is being changed. 48 Am186/188EM and Am186/188EMLV Microcontrollers P R E L I M I N A R Y PB=0 DR/DT=0 PB=1 DR/DT=0 PB=0 DR/DT=1 PB=1 DR/DT=0 PB=0 DR/DT=1 PB=1 DR/DT=0 PB=0 DR/DT=1 PB=0 DR/DT=0 SDEN SCLK SDATA Poll SSS for PB=0 Poll SSS for PB=0 Write to SSD Write to SSC, bit DE=1 Write to SSD PB=1 DR/DT=0 Write to SSD Write to SSC, bit DE=0 Figure 11. PB=0 DR/DT=0 Poll SSS for PB=0 PB=0 DR/DT=1 Synchronous Serial Interface Multiple Write PB=1 DR/DT=0 PB=0 DR/DT=1 PB=1 DR/DT=0 PB=0 DR/DT=1 PB=0 DR/DT=0 SDEN SCLK SDATA Poll SSS for PB=0 Write to SSD Poll SSS for PB=0 Read from SSR (dummy) Write to SSC, bit DE=1 Figure 12. Poll SSS for PB=0 Read from SSR Write to SSC, bit DE=0 Read from SSR Synchronous Serial Interface Multiple Read Am186/188EM and Am186/188EMLV Microcontrollers 49 P R E L I M I N A R Y PROGRAMMABLE I/O (PIO) PINS There are 32 pins on the Am186EM and Am188EM microcontrollers that are available as user multipurpose signals. Table 2 and Table 3 on page 30 list the PIO pins. Each of these pins can be used as a user-programmable input or output signal if the normal shared function is not needed. If a pin is enabled to function as a PIO signal, the preassigned signal function is disabled and does not affect the level on the pin. A PIO signal can be configured to operate as an input or output with or without a weak pullup or pulldown, or as an open-drain output. After power-on reset, the PIO pins default to various configurations. The column titled Power-On Reset Status in Table 2 and Table 3 on page 30 lists the defaults for the PIOs. The system initialization code must reconfigure the PIOs as required. The A19–A17 address pins default to normal operation on power-on reset, allowing the processor to correctly begin fetching instructions at the boot address FFFF0h. The DT/R, DEN, and SRDY pins also default to normal operation on power-on reset. Note that emulators use A19, A18, A17, S6, and UZI. If the AD15–AD0 bus override is enabled on power-on reset, then S6/CLKDIV2 and UZI revert to normal operation instead of PIO input with pullup. If BHE/ADEN (186) or RFSH2/ADEN (188) is held Low during power-on reset the AD15–AD0 bus override is enabled. 50 Am186/188EM and Am186/188EMLV Microcontrollers P R E L I M I N A R Y ABSOLUTE MAXIMUM RATINGS the functionality of the device is guaranteed. Storage temperature Am186EM/Am188EM ..................... –65°C to +125°C Am186EMLV/Am188EMLV............. –65°C to +125°C Am186EM/Am188EM Microcontrollers Commercial (TC) .................................0°C to +100°C Industrial* (TA)...................................–40°C to +85°C VCC up to 33 MHz ..................................... 5 V ± 10% VCC greater than 33 MHz............................ 5 V ± 5% Voltage on any pin with respect to ground Am186/188EM ........................... –0.5 V to Vcc +0.5 V Am186/188EMLV ....................... –0.5 V to V cc +0.5 V Note: Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to absolute maximum ratings for extended periods may affect device reliability. OPERATING RANGES Operating Ranges define those limits between which Am186EMLV/Am188EMLV Microcontrollers Commercial (TA) ................................... 0°C to +70°C VCC up to 25 MHz ................................. 3.3 V ± 0.3 V Where: TC = case temperature TA = ambient temperature *Industrial versions of Am186EM and Am188EM microcontrollers are available in 20 and 25 MHz operating frequencies only. DC CHARACTERISTICS OVER COMMERCIAL OPERATING RANGE Preliminary Symbol Min Max Unit VIL Input Low Voltage (Except X1) Parameter Description –0.5 0.8 V VIL1 Clock Input Low Voltage (X1) –0.5 0.8 V VIH Input High Voltage (Except RES and X1) 2.0 VCC + 0.5 V VIH1 Input High Voltage (RES) 2.4 VCC + 0.5 V VIH2 Clock Input High Voltage (X1) VCC – 0.8 VCC + 0.5 V IOL = 2.5 mA (S2–S0) IOL = 2.0 mA (others) 0.45 V IOL = 1.5 mA (S2–S0) IOL = 1.0 mA (others) 0.45 V Output Low Voltage Am186EM and Am188EM VOL Am186EMLV and Am188EMLV Output High Voltage(a) Am186EM and Am188EM Test Conditions 2.4 VCC +0.5 V IOH = –200 µA @ VCC –0.5 VCC –0.5 VCC V Am186EMLV and Am188EMLV IOH = –200 µA @ VCC –0.5 VCC –0.5 VCC V Power Supply Current @ 0°C Am186EM and Am188EM VCC = 5.5 V (b) 5.9 Am186EMLV and Am188EMLV VCC = 3.6 V (b) 2.75 mA/ MHz mA/ MHz Output Low Voltage IOL = 2.5 mA (S2–S0) IOL = 2.0 mA (others) 0.45 V ILI Input Leakage Current @ 0.5 MHz 0.45 V ≤ VIN ≤ VCC ±10 µA ILO Output Leakage Current @ 0.5 MHz 0.45 V ≤ VOUT ≤ VCC(d) ±10 µA VCLO Clock Output Low ICLO = 4.0 mA 0.45 V VCHO Clock Output High ICHO = –500 µA VOH IOH = –2.4 mA @ 2.4 V ICC VOL VCC – 0.5 V Notes: a The LCS/ONCE0, MCS3–MCS0, UCS/ONCE1, and RD pins have weak internal pullup resistors. Loading the LCS/ONCE0 and UCS/ONCE1 pins in excess of IOH = –200 µA during reset can cause the device to go into ONCE mode. b Current is measured with the device in RESET with X1 and X2 driven, and all other non-power pins open but held High or Low. c Power supply current for the Am186EMLV and Am188EMLV microcontrollers, which are available in 20 and 25 MHz operating frequencies only. d Testing is performed with the pins floating, either during HOLD or by invoking the ONCE mode. Am186/188EM and Am186/188EMLV Microcontrollers 51 P R E L I M I N A R Y DC CHARACTERISTICS OVER COMMERCIAL OPERATING RANGE (continued) Preliminary Symbol Parameter Description Test Conditions Nominal Typical Power Supply Current @ 25°C VCC = 5.5 V (a) ICC Nominal Am186EMLV and Am188EMLV Typical Power Supply Current @ 25°C VCC = 3.6 V (a) (b) ICC Typical 4.5 3.0 Peak ICC Measured Peak ICC VCC = 5.5 V (c) 5.9 Peak ICC Am186EMLV and Am188EMLV Measured Peak ICC VCC = 3.6 V(b) (c) 4.0 a Measured with a device running. Not tested and not guaranteed. b Power supply current for the Am186EMLV and Am188EMLV microcontrollers, which are available in 20 and 25 MHz operating frequencies only. c Power is measured while device is operating. Not tested and not guaranteed. Unit mA/ MHz mA/ MHz mA/ MHz mA/ MHz Capacitance Symbol Parameter Description CIN Input Capacitance CIO Output or I/O Capacitance Test Conditions @ 1 MHz @ 1 MHz Note: Capacitance limits are guaranteed by characterization. 52 Am186/188EM and Am186/188EMLV Microcontrollers Preliminary Min Max 10 20 Unit pF pF P R E L I M I N A R Y Power Supply Current Table 7 shows the variables that are used to calculate the typical power consumption value for each version of the Am186EMLV and Am188EMLV microcontrollers. For the typical system specification shown in Figure 13, ICC has been measured at 3.0 mA per MHz of system clock. For the typical system specification shown in Figure 14, ICC has been measured at 4.5 mA per MHz of system clock. The typical system is measured while the system is executing code in a typical application with maximum voltage and at room temperature. Actual power supply current is dependent on system design and may be greater or less than the typical ICC figure presented here. Table 7. Typical Power Consumption Calculation for the Am186EMLV and Am188EMLV MHz ⋅ ICC ⋅ Volts / 1000 = P MHz Typical ICC Volts 16 3.0 3.6 20 3.0 3.6 25 3.0 3.6 Typical current in Figure 13 is given by: ................. ICC = 3.0 mA ⋅ freq(MHz). Typical Power in Watts 0.173 0.216 0.270 Typical current in Figure 14 is given by: ................. ICC = 4.5 mA ⋅ freq(MHz). Please note that dynamic ICC measurements are dependent upon chip activity, operating frequency, output buffer logic, and capacitive/resistive loading of the outputs. For these ICC measurements, the devices were set to the following modes: 140 120 100 n No DC loads on the output buffers 80 n Output capacitive load set to 35 pF ICC (mA) n AD bus set to data only 25 MHz 20 MHz 16 MHz 60 40 n PIOs are disabled 20 n Timer, serial port, refresh, and DMA are enabled 0 10 20 30 Clock Frequency (MHz) Figure 13. Typical ICC Versus Frequency for the Am186EMLV and Am188EMLV 280 240 200 40 MHz 160 ICC (mA) 33 MHz 120 20 MHz 80 25 MHz 40 0 10 20 30 40 Clock Frequency (MHz) Figure 14. Typical ICC Versus Frequency for the Am186EM and Am188EM Am186/188EM and Am186/188EMLV Microcontrollers 53 P R E L I M I N A R Y THERMAL CHARACTERISTICS TQFP Package The Am186EM and Am188EM microcontrollers are specified for operation with case temperature ranges from 0°C to +100°C for a commercial temperature device. Case temperature is measured at the top center of the package as shown in Figure 15. The various temperatures and thermal resistances can be determined using the equations in Figure 16 with information given in Table 8. The variable P is power in watts. Typical power supply current (ICC) for the Am186EM and Am188EM microcontrollers is 5.9 mA per MHz of clock frequency. θJA is the sum of θJC and θCA. θJC is the internal thermal resistance of the assembly. θCA is the case to ambient thermal resistance. θJA θCA TC θJA = θJC + θCA Figure 15. Thermal Resistance(°C/Watt) θJA = θJC + θCA P=5.9 mA ⋅ freq (MHz) ⋅VCC TJ =TC +( P ⋅ θJC ) TJ =TA + (P ⋅ θJA ) TC =TJ –( P ⋅ θJC ) TC =TA +( P ⋅ θCA ) TA =TJ –( P ⋅ θJA ) TA =TC –( P ⋅ θCA ) Figure 16. Table 8. Thermal Characteristics Equations Thermal Characteristics (°C/Watt) Package/Board PQFP/2-Layer TQFP/2-Layer PQFP/4-Layer to 6-Layer TQFP/4-Layer to 6-Layer 54 Airflow (Linear Feet per Minute) 0 fpm 200 fpm 400 fpm 600 fpm 0 fpm 200 fpm 400 fpm 600 fpm 0 fpm 200 fpm 400 fpm 600 fpm 0 fpm 200 fpm 400 fpm 600 fpm θJC θJC θCA θJA 7 7 7 7 10 10 10 10 5 5 5 5 6 6 6 6 38 32 28 26 46 36 30 28 18 16 14 12 24 22 20 18 45 39 35 33 56 46 40 38 23 21 19 17 30 28 26 24 Am186/188EM and Am186/188EMLV Microcontrollers P R E L I M I N A R Y Typical Ambient Temperatures Table 10. Junction Temperature Calculation TJ = TC + ( P ⋅ θJC ) Speed/ Pkg/ Board TC P θJC TJ 40/P2 100 1.239 7 108.7 40/T2 100 1.239 10 112.4 40/P4–6 100 1.239 5 106.2 40/T4–6 100 1.239 6 107.4 The 40-MHz microcontroller is specified as 5.0 V, plus or minus 5%. Therefore, 5.25 V is used for calculating typical power consumption on the 40-MHz microcontroller. 33/P2 100 1.07085 7 107.5 33/T2 100 1.07085 10 110.7 33/P4–6 100 1.07085 5 105.3 33/T4–6 100 1.07085 6 106.4 Microcontrollers up to 33 MHz are specified as 5.0 V, plus or minus 10%. Therefore, 5.5 V is used for calculating typical power consumption up to 33 MHz. 25/P2 100 0.81125 7 105.7 25/T2 100 0.81125 10 108.1 25/P4–6 100 0.81125 5 104.1 Typical power supply current (ICC) in normal usage is estimated at 5.9 mA per MHz of microcontroller clock rate. 25/T4–6 100 0.81125 6 104.9 20/P2 100 0.649 7 104.5 Typical power consumption (watts) = (5.9 mA/MHz) times microcontroller clock rate times voltage divided by 1000. 20/T2 100 0.649 10 106.5 20/P4–6 100 0.649 5 103.2 20/T4–6 100 0.649 6 103.9 The typical ambient temperature specifications are based on the following assumptions and calculations: The commercial operating range of the Am186EM and Am188EM microcontrollers is a case temperature TC of 0 to 100 degrees Centigrade. TC is measured at the top center of the package. An increase in the ambient temperature causes a proportional increase in TC. Table 9 shows the variables that are used to calculate the typical power consumption value for each version of the Am186EM and Am188EM microcontrollers. Table 9. Typical Power Consumption Calculation P = MHz ⋅ ICC ⋅ Volts / 1000 MHz Typical ICC Volts Typical Power (P) in Watts 40 5.9 5.25 1.239 33 5.9 5.5 1.07085 25 5.9 5.5 0.81125 20 5.9 5.5 0.649 Thermal resistance is a measure of the ability of a package to remove heat from a semiconductor device. A safe operating range for the device can be calculated using the following formulas from Figure 16 and the variables in Table 8. By using the maximum case rating T C , the typical power consumption value from Table 9, and θJC from Table 8, the junction temperature TJ can be calculated by using the following formula from Figure 16. TJ = TC + ( P ⋅ θJC ) By using TJ from Table 10, the typical power consumption value from Table 9, and a θJA value from Table 8, the typical ambient temperature TA can be calculated using the following formula from Figure 16. TA = TJ – ( P ⋅ θJA ) For example, TA for a 40-MHz PQFP design with a 2layer board and 0 fpm airflow is calculated as follows: TA = 108.673 – ( 1.239 ⋅ 45 ) TA = 52.918 In this calculation, TJ comes from Table 10, P comes from Table 9, and θJA comes from Table 8. See Table 11. TA for a 33-MHz TQFP design with a 4-layer to 6-layer board and 200 fpm airflow is calculated as follows: TA = 106.4251 – ( 1.07085 ⋅ 28 ) TA = 76.4413 See Table 14 for the result of this calculation. Table 11 through Table 14 and Figure 17 through Figure 20 show TA based on the preceding assumptions and calculations for a range of θJA values with airflow from 0 linear feet per minute to 600 linear feet per minute. Table 10 shows TJ values for the various versions of the Am186EM and Am188EM microcontrollers. The column titled Speed/Pkg/Board in Table 10 indicates the clock speed in MHz, the type of package (P for PQFP and T for TQFP), and the type of board (2 for 2-layer and 4–6 for 4layer to 6-layer). Am186/188EM and Am186/188EMLV Microcontrollers 55 P R E L I M I N A R Y Table 11 shows typical maximum ambient temperatures in degrees Centigrade for a PQFP package used with a 2-layer board. The typical ambient temperatures are based on a 100-degree Centigrade maximum case temperature. Figure 17 illustrates the typical temperatures in Table 11. Table 11. Typical Ambient Temperatures for PQFP with 2-Layer Board Microcontroller Speed 40 MHz 33 MHz 25 MHz 20 MHz Typical Power (Watts) 1.239 1.07085 0.81125 0.649 0 fpm 52.918 59.3077 69.1725 75.338 Linear Feet per Minute Airflow 200 fpm 400 fpm 60.352 65.308 65.7328 70.0162 74.04 77.285 79.232 81.828 600 fpm 67.786 72.1579 78.9075 83.126 Typical Ambient Temperature (Degrees C) 90 Legend: ■ 80 ■ ■ ◆ ◆ ■ ◆ ✶ 70 ✶ ◆ ● ✶ 60 ● ● ✶ ● 50 ● 40 MHz ✵ 33 MHz ◆ 25 Mhz ■ 20 MHz 40 0 fpm 200 fpm 400 fpm Airflow (Linear Feet Per Minute) Figure 17. 56 Typical Ambient Temperatures for PQFP with 2-Layer Board Am186/188EM and Am186/188EMLV Microcontrollers 600 fpm P R E L I M I N A R Y Table 12 shows typical maximum ambient temperatures in degrees Centigrade for a TQFP package used with a 2-layer board. The typical ambient temperatures are based on a 100-degree Centigrade maximum case temperature. Figure 18 illustrates the typical temperatures in Table 12. Table 12. Typical Ambient Temperatures for TQFP with 2-Layer Board Microcontroller Speed 40 MHz 33 MHz 25 MHz 20 MHz Typical Power (Watts) 1.239 1.07085 0.81125 0.649 Linear Feet per Minute Airflow 200 fpm 400 fpm 55.396 62.83 61.4494 67.8745 70.795 75.6625 76.636 80.53 0 fpm 43.006 50.7409 62.6825 70.146 600 fpm 65.308 70.0162 77.285 81.828 Typical Ambient Temperature (Degrees C) 90 ■ ■ 80 ◆ ■ 70 ◆ ◆ ■ ✶ ✶ ● ✶ ◆ ● 60 ● ✶ Legend: ● 40 MHz ✵ 33 MHz 50 ● ◆ 25 Mhz ■ 20 MHz 40 0 fpm 200 fpm 400 fpm 600 fpm Airflow (Linear Feet Per Minute) Figure 18. Typical Ambient Temperatures for TQFP with 2-Layer Board Am186/188EM and Am186/188EMLV Microcontrollers 57 P R E L I M I N A R Y Table 13 shows typical maximum ambient temperatures in degrees Centigrade for a PQFP package used with a 4-layer to 6-layer board. The typical ambient temperatures are based on a 100-degree Centigrade maximum case temperature. Figure 19 illustrates the typical temperatures in Table 13. Table 13. Typical Ambient Temperatures for PQFP with 4-Layer to 6-Layer Board Microcontroller Speed 40 MHz 33 MHz 25 MHz 20 MHz Typical Power (Watts) 1.239 1.07085 0.81125 0.649 Linear Feet per Minute Airflow 200 fpm 400 fpm 80.176 82.654 82.8664 85.0081 87.02 88.6425 89.616 90.914 0 fpm 77.698 80.7247 85.3975 88.318 600 fpm 85.132 87.1498 90.265 92.212 95 Typical Ambient Temperature (Degrees C) ■ Legend: ● 40 MHz ✵ 33 MHz ■ 90 ■ ◆ ◆ ■ ✶ ◆ 85 ◆ ✶ ✶ ✶ 80 ● ● ● ● 75 ◆ 25 Mhz ■ 20 MHz 70 0 fpm 200 fpm 400 fpm 600 fpm Airflow (Linear Feet Per Minute) Figure 19. 58 Typical Ambient Temperatures for PQFP with 4-Layer to 6-Layer Board Am186/188EM and Am186/188EMLV Microcontrollers P R E L I M I N A R Y Table 14 shows typical maximum ambient temperatures in degrees Centigrade for a TQFP package used with a 4-layer to 6-layer board. The typical ambient temperatures are based on a 100-degree Centigrade maximum case temperature. Figure 20 illustrates the typical temperatures in Table 14. Table 14. Typical Ambient Temperatures for TQFP with 4-Layer to 6-Layer Board Microcontroller Speed 40 MHz 33 MHz 25 MHz 20 MHz Typical Power (Watts) 1.239 1.07085 0.81125 0.649 Linear Feet per Minute Airflow 200 fpm 400 fpm 72.742 75.22 76.4413 78.583 82.1525 83.775 85.722 87.02 0 fpm 70.264 74.2996 80.53 84.424 600 fpm 77.698 80.7247 85.3975 88.318 Typical Ambient Temperature (Degrees C) 95 Legend: ● 40 MHz ✵ 33 MHz 90 ■ ■ ■ 85 ◆ ■ ◆ ◆ ✶ ◆ 80 ✶ ● ✶ ● 75 ✶ ● ◆ 25 Mhz ■ 20 MHz 70 ● 0 fpm 200 fpm 400 fpm 600 fpm Airflow (Linear Feet Per Minute) Figure 20. Typical Ambient Temperatures for TQFP with 4-Layer to 6-Layer Board Am186/188EM and Am186/188EMLV Microcontrollers 59 P R E L I M I N A R Y COMMERCIAL SWITCHING CHARACTERISTICS AND WAVEFORMS In the switching waveforms that follow, several abbreviations are used to indicate the specific periods of a bus cycle. These periods are referred to as time states. A typical bus cycle is composed of four consecutive time states: t1, t2, t3, and t4. Wait states, which represent multiple t3 states, are referred to as tw states. When no bus cycle is pending, an idle (ti) state occurs. In the switching parameter descriptions, the multiplexed address is referred to as the AD address bus; the demultiplexed address is referred to as the A address bus. Key to Switching Waveforms WAVEFORM 60 INPUT OUTPUT Must be Steady Will be Steady May Change from H to L Will be Changing from H to L May Change from L to H Will be Changing from L to H Don’t Care, Any Change Permitted Changing, State Unknown Does Not Apply Center Line is HighImpedance Off State Invalid Invalid Am186/188EM and Am186/188EMLV Microcontrollers P R E L I M I N A R Y Alphabetical Key to Switching Parameter Symbols Parameter Symbol No. Description Parameter Symbol No. tARYCH 49 ARDY Resolution Transition Setup Time tCLDX 2 Data in Hold tARYCHL 51 ARDY Inactive Holding Time tCLEV 71 CLKOUTA Low to SDEN Valid tARYLCL 52 ARDY Setup Time tCLHAV 62 HLDA Valid Delay tAVBL 87 A Address Valid to WHB, WLB Low tCLRF 82 CLKOUTA High to RFSH Invalid tAVCH 14 AD Address Valid to Clock High tCLRH 27 RD Inactive Delay tAVLL 12 AD Address Valid to ALE Low tCLRL 25 RD Active Delay tAVRL 66 A Address Valid to RD Low tCLSH 4 Status Inactive Delay tAVWL 65 A Address Valid to WR Low tAZRL 24 AD Address Float to RD Active tCH1CH2 45 tCHAV 68 tCHCK Description tCLSL 72 CLKOUTA Low to SCLK Low tCLSRY 48 SRDY Transition Hold Time CLKOUTA Rise Time tCLTMV 55 Timer Output Delay CLKOUTA High to A Address Valid tCOAOB 83 CLKOUTA to CLKOUTB Skew 38 X1 High Time tCVCTV 20 Control Active Delay 1 tCHCL 44 CLKOUTA High Time tCVCTX 31 Control Inactive Delay tCHCSV 67 CLKOUTA High to LCS/UCS Valid tCVDEX 21 DEN Inactive Delay tCHCSX 18 MCS/PCS Inactive Delay tCXCSX 17 MCS/PCS Hold from Command Inactive tCHCTV 22 Control Active Delay 2 tDVCL 1 Data in Setup tCHCV 64 Command Lines Valid Delay (after Float) tDVSH 75 Data Valid to SCLK High tCHCZ 63 Command Lines Float Delay tDXDL 19 DEN Inactive to DT/R Low tCHDX 8 Status Hold Time tHVCL 58 HOLD Setup tCHLH 9 ALE Active Delay tINVCH 53 Peripheral Setup Time tCHLL 11 ALE Inactive Delay tINVCL 54 DRQ Setup Time tCHRFD 79 CLKOUTA High to RFSH valid tLCRF 86 LCS Inactive to RFSH Active Delay tCHSV 3 Status Active Delay tLHAV 23 ALE High to Address Valid tCICOA 69 X1 to CLKOUTA Skew tLHLL 10 ALE Width tCICOB 70 X1 to CLKOUTB Skew tLLAX 13 AD Address Hold from ALE Inactive tCKHL 39 X1 Fall Time tLOCK 61 Maximum PLL Lock Time tCKIN 36 X1 Period tLRLL 84 LCS Precharge Pulse Width tCKLH 40 X1 Rise Time tRESIN 57 RES Setup Time tCL2CL1 46 CLKOUTA Fall Time tRFCY 85 RFSH Cycle Time tCLARX 50 ARDY Active Hold Time tRHAV 29 RD Inactive to AD Address Active tCLAV 5 AD Address Valid Delay tRHDX 59 RD High to Data Hold on AD Bus tCLAX 6 Address Hold tRHLH 28 RD Inactive to ALE High tCLAZ 15 AD Address Float Delay tRLRH 26 RD Pulse Width tCLCH 43 CLKOUTA Low Time tSHDX 77 SCLK High to SPI Data Hold tCLCK 37 X1 Low Time tSLDV 78 SCLK Low to SPI Data Valid tCLCL 42 CLKOUTA Period tSRYCL 47 SRDY Transition Setup Time tCLCLX 80 LCS Inactive Delay tWHDEX 35 WR Inactive to DEN Inactive tCLCSL 81 LCS Active Delay tWHDX 34 Data Hold after WR tCLCSV 16 MCS/PCS Active Delay tWHLH 33 WR Inactive to ALE High tCLDOX 30 Data Hold Time tWLWH 32 WR Pulse Width tCLDV 7 Data Valid Delay Note: The following parameters are not defined or used as this time: 41, 56, 60, 73, 74, 76. Am186/188EM and Am186/188EMLV Microcontrollers 61 P R E L I M I N A R Y Numerical Key to Switching Parameter Symbols Number 1 2 3 4 5 6 7 8 9 10 11 12 Parameter Symbol tDVCL tCLDX tCHSV tCLSH tCLAV tCLAX tCLDV tCHDX tCHLH tLHLL tCHLL tAVLL 13 tLLAX 14 15 16 tAVCH tCLAZ tCLCSV 17 tCXCSX 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 42 tCHCSX tDXDL tCVCTV tCVDEX tCHCTV tLHAV tAZRL tCLRL tRLRH tCLRH tRHLH tRHAV tCLDOX tCVCTX tWLWH tWHLH tWHDX tWHDEX tCKIN tCLCK tCHCK tCKHL tCKLH tCLCL Description Data in Setup Data in Hold Status Active Delay Status Inactive Delay AD Address Valid Delay Address Hold Data Valid Delay Status Hold Time ALE Active Delay ALE Width ALE Inactive Delay AD Address Valid to ALE Low AD Address Hold from ALE Inactive AD Address Valid to Clock High AD Address Float Delay MCS/PCS Active Delay MCS/PCS Hold from Command Inactive MCS/PCS Inactive Delay DEN Inactive to DT/R Low Control Active Delay 1 DEN Inactive Delay Control Active Delay 2 ALE High to Address Valid AD Address Float to RD Active RD Active Delay RD Pulse Width RD Inactive Delay RD Inactive to ALE High RD Inactive to AD address Active Data Hold Time Control Inactive Delay WR Pulse Width WR Inactive to ALE High Data Hold after WR WR Inactive to DEN Inactive X1 Period X1 Low Time X1 High Time X1 Fall Time X1 Rise Time CLKOUTA Period Number 43 44 45 46 47 48 49 50 51 52 53 54 Parameter Symbol tCLCH tCHCL tCH1CH2 tCL2CL1 tSRYCL tCLSRY tARYCH tCLARX tARYCHL tARYLCL tINVCH tINVCL 55 tCLTMV Timer Output Delay 57 58 59 tRESIN tHVCL tRHDX RES Setup Time HOLD Setup RD High to Data Hold on AD Bus 61 tLOCK Maximum PLL Lock Time 62 63 64 65 66 67 68 69 70 71 72 75 77 78 79 80 81 82 83 84 85 86 87 tCLHAV tCHCZ tCHCV tAVWL tAVRL tCHCSV tCHAV tCICOA tCICOB tCLEV tCLSL tDVSH tSHDX tSLDV tCHRFD tCLCLX tCLCSL tCLRF tCOAOB tLRLL tRFCY tLCRF tAVBL Description CLKOUTA Low Time CLKOUTA High Time CLKOUTA Rise Time CLKOUTA Fall Time SRDY Transition Setup Time SRDY Transition Hold Time ARDY Resolution Transition Setup Time ARDY Active Hold Time ARDY Inactive Holding Time ARDY Setup Time Peripheral Setup Time DRQ Setup Time HLDA Valid Delay Command Lines Float Delay Command Lines Valid Delay (after Float) A Address Valid to WR Low A Address Valid to RD Low CLKOUTA High to LCS/UCS Valid CLKOUTA High to Address Valid X1 to CLKOUTA Skew X1 to CLKOUTB Skew CLKOUTA Low to SDEN Valid CLKOUTA Low to SCLK Low Data Valid to SCLK High SCLK High to SPI Data Hold SCLK Low to SPI Data Valid CLKOUTA High to RFSH Valid LCS Inactive Delay LCS Active Delay CLKOUTA High to RFSH Invalid CLKOUTA to CLKOUTB Skew LCS Precharge Pulse Width RFSH Cycle Time LCS Inactive to RFSH Active Delay A Address Valid to WHB, WLB Low Note: The following parameters are not defined or used at this time: 41, 56, 60, 73, 74, and 76. 62 Am186/188EM and Am186/188EMLV Microcontrollers P R E L I M I N A R Y SWITCHING CHARACTERISTICS over COMMERCIAL operating range Read Cycle (20 MHz and 25 MHz) Parameter No. Symbol Description General Timing Requirements 1 tDVCL Data in Setup 2 tCLDX Data in Hold(c) General Timing Responses 3 tCHSV Status Active Delay 4 tCLSH Status Inactive Delay 5 tCLAV AD Address Valid Delay and BHE 6 tCLAX Address Hold 8 tCHDX Status Hold Time 9 tCHLH ALE Active Delay 10 tLHLL 11 12 tCHLL tAVLL ALE Width Preliminary 20 MHz 25 MHz Min Max Min Max 10 3 0 0 0 0 0 10 3 25 25 25 25 25 20 20 20 20 20 25 ns ns ns ns ns ns ns tCLCH –2 tCLCH –2 ns ns tCHCL –2 tCHCL –2 ns 0 tCLAX =0 0 25 25 tCLCH –2 0 0 0 0 0 20 0 0 26 tRLRH RD Pulse Width 27 28 tCLRH tRHLH 29 tRHAV 59 tRHDX RD Inactive Delay 0 RD Inactive to ALE High(a) tCLCH –3 RD Inactive to AD Address tCLCL –10=40 Active(a) (c) RD High to Data Hold on AD Bus 0 66 tAVRL A Address Valid to RD Low(a) 67 68 tCHCSV tCHAV CLKOUTA High to LCS/UCS Valid CLKOUTA High to A Address Valid ns ns tCLCL –10= 30 tCLCL –10=40 ALE Inactive Delay AD Address Valid to ALE Low(a) AD Address Hold from ALE 13 tLLAX Inactive(a) 14 tAVCH AD Address Valid to Clock High 15 tCLAZ AD Address Float Delay 16 tCLCSV MCS/PCS Active Delay MCS/PCS Hold from Command 17 tCXCSX Inactive(a) 18 tCHCSX MCS/PCS Inactive Delay 19 tDXDL DEN Inactive to DT/R Low(a) 20 tCVCTV Control Active Delay 1(b) 21 tCVDEX DEN Inactive Delay 22 tCHCTV Control Active Delay 2(b) 23 tLHAV ALE High to Address Valid Read Cycle Timing Responses 24 tAZRL AD Address Float to RD Active 25 tCLRL RD Active Delay 0 0 0 0 0 Unit 0 tCLAX =0 0 20 20 tCLCH –2 25 0 0 0 0 0 15 25 25 25 25 2tCLCL –15=85 25 2tCLCL –15=85 0 0 20 25 25 0 0 2tCLCL –15= 65 0 tCLCH –3 tCLCL –10= 30 0 2tCLCL –15= 65 0 0 ns ns ns ns 20 20 20 20 20 ns ns ns ns ns ns ns ns ns 20 ns ns ns ns ns 20 20 ns ns Note: All timing parameters are measured at 1.5 V with 50 pF loading on CLKOUTA unless otherwise noted. All output test conditions are with CL = 50 pF. For switching tests, VIL = 0.45 V and VIH = 2.4 V, except at X1 where VIH = VCC – 0.5 V. a Equal loading on referenced pins. b This parameter applies to the DEN, INTA1–INTA0, WR, WHB, and WLB signals. c If either spec 2 or spec 59 is met with respect to data hold time, the part will function correctly. Am186/188EM and Am186/188EMLV Microcontrollers 63 P R E L I M I N A R Y SWITCHING CHARACTERISTICS over COMMERCIAL operating range Read Cycle (33 MHz and 40 MHz) Parameter No. Symbol Description General Timing Requirements 1 tDVCL Data in Setup 2 tCLDX Data in Hold(c) General Timing Responses 3 tCHSV Status Active Delay 4 tCLSH Status Inactive Delay 5 tCLAV AD Address Valid Delay and BHE 6 tCLAX Address Hold 7 tCLDV Data Valid Delay 8 tCHDX Status Hold Time 9 tCHLH ALE Active Delay 10 tLHLL 11 12 tCHLL tAVLL ALE Width Preliminary 33 MHz 40 MHz Min Max Min Max 8 3 0 0 0 0 0 0 5 2 15 15 15 25 15 0 0 0 0 0 0 15 ALE Inactive Delay AD Address Valid to ALE Low(a) tCLCH –2 AD Address Hold from ALE 13 tLLAX tCHCL–2 Inactive(a) 14 tAVCH AD Address Valid to Clock High 0 15 tCLAZ AD Address Float Delay tCLAX =0 16 tCLCSV MCS/PCS Active Delay 0 MCS/PCS Hold from Command 17 tCXCSX tCLCH –2 Inactive(a) 18 tCHCSX MCS/PCS Inactive Delay 0 19 tDXDL DEN Inactive to DT/R Low(a) 0 20 tCVCTV Control Active Delay 1(b) 0 21 tCVDEX DEN Inactive Delay 0 (b) 22 tCHCTV Control Active Delay 2 0 23 tLHAV ALE High to Address Valid 10 Read Cycle Timing Responses 24 tAZRL AD Address Float to RD Active 0 25 tCLRL RD Active Delay 0 26 tRLRH RD Pulse Width 2tCLCL –15=45 27 tCLRH RD Inactive Delay 0 28 tRHLH RD Inactive to ALE High(a) tCLCH –3 RD Inactive to AD Address 29 tRHAV tCLCL –10=20 Active(a) 59 tRHDX RD High to Data Hold on AD Bus(c) 0 66 tAVRL A Address Valid to RD Low(a) 2tCLCL –15=45 67 tCHCSV CLKOUTA High to LCS/UCS Valid 0 68 tCHAV CLKOUTA High to A Address Valid 0 ns ns 12 12 12 20 12 12 tCLCL –5 =20 tCLCL –10=20 15 tCLCH –2 ns ns tCHCL –2 ns 0 tCLAX =0 0 12 12 tCLCH –2 15 0 0 0 0 0 7.5 15 15 15 15 15 15 15 ns ns ns ns ns ns ns ns 12 15 15 Unit 0 0 2tCLCL –10=40 0 tCLCH –2 tCLCL –5 =20 0 2tCLCL –10=40 0 0 ns ns ns ns 12 12 12 12 10 12 ns ns ns ns ns ns ns ns ns ns ns ns 10 10 ns ns ns ns Notes: All timing parameters are measured at 1.5 V with 50 pF loading on CLKOUTA unless otherwise noted. All output test conditions are with CL = 50 pF. For switching tests, VIL = 0.45 V and VIH = 2.4 V, except at X1 where VIH = VCC – 0.5 V. a Equal loading on referenced pins. b This parameter applies to the DEN, INTA1–INTA0, WR, WHB, and WLB signals. c If either spec 2 or spec 59 is met with respect to data hold time, the part will function correctly. 64 Am186/188EM and Am186/188EMLV Microcontrollers P R E L I M I N A R Y Read Cycle Waveforms t1 t2 t3 t4 tW CLKOUTA 66 A19–A0 Address 8 68 S6 S6 S6 14 1 6 AD15–AD0*, AD7–AD0** Address Data 2 Address AO15–AO8** 23 29 11 9 59 ALE 15 10 RD 28 24 26 12 5 27 25 BHE* BHE 67 18 13 LCS, UCS 16 MCS1–MCS0, PCS6–PCS5, PCS3–PCS0 17 20 21 DEN 19 DT/R *** 22 4 S2–S0 *** 22 Status 3 UZI Notes: * Am186EM microcontroller only ** Am188EM microcontroller only Changes in t4 phase of the clock preceding next bus cycle if followed by read, INTA, or halt *** Am186/188EM and Am186/188EMLV Microcontrollers 65 P R E L I M I N A R Y SWITCHING CHARACTERISTICS over COMMERCIAL operating range Write Cycle (20 MHz and 25 MHz) Preliminary 20 MHz 25 MHz Min Max Min Max Parameter No. Symbol Description General Timing Responses Unit 3 tCHSV Status Active Delay 0 25 0 20 ns 4 tCLSH Status Inactive Delay 0 25 0 20 ns 5 tCLAV AD Address Valid Delay and BHE 0 25 0 20 ns 6 tCLAX Address Hold 0 25 0 20 ns 7 tCLDV Data Valid Delay 0 25 0 20 ns 8 tCHDX Status Hold Time 0 9 tCHLH ALE Active Delay 10 tLHLL ALE Width 11 tCHLL ALE Inactive Delay 12 0 25 tCLCL –10= 40 tCLCL –10= 30 25 Low(a) tAVLL AD Address Valid to ALE 13 tLLAX AD Address Hold from ALE Inactive(a) 14 tAVCH 16 ns 20 ns ns 20 ns tCLCH tCLCH ns tCHCL tCHCL ns AD Address Valid to Clock High 0 0 ns tCLCSV MCS/PCS Active Delay 0 17 tCXCSX MCS/PCS Hold from Command Inactive(a) 18 tCHCSX MCS/PCS Inactive Delay 19 tDXDL DEN Inactive to DT/R Low(a) 1(b) 25 tCLCH 0 0 20 tCLCH 25 0 0 ns ns 20 0 ns ns 20 tCVCTV Control Active Delay 0 25 0 20 ns 22 tCHCTV Control Active Delay 2 0 25 0 20 ns 23 tLHAV ALE High to Address Valid 20 15 ns Write Cycle Timing Responses 30 tCLDOX Data Hold Time 0 31 tCVCTX Control Inactive Delay(b) 0 32 tWLWH WR Pulse Width 33 tWHLH WR Inactive to ALE High(a) 0 25 2tCLCL –10 =90 0 ns 20 ns 2tCLCL –10 =70 ns tCLCH –2 tCLCH –2 ns tCLCL –10= 40 tCLCL –10= 30 ns tCLCH –3 tCLCH –3 ns tCLCL +tCHCL –3 tCLCL +tCHCL –3 ns 34 tWHDX Data Hold after WR(a) 35 tWHDEX WR Inactive to DEN Inactive(a) 65 tAVWL A Address Valid to WR Low 67 tCHCSV CLKOUTA High to LCS/UCS Valid 0 25 0 20 ns 68 tCHAV CLKOUTA High to A Address Valid 0 25 0 20 ns 87 tAVBL A Address Valid to WHB, WLB Low tCHCL –3 25 tCHCL –3 20 ns Notes: All timing parameters are measured at 1.5 V with 50 pF loading on CLKOUTA unless otherwise noted. All output test conditions are with CL = 50 pF. For switching tests, VIL = 0.45 V and VIH = 2.4 V, except at X1 where VIH = VCC – 0.5 V. a Equal loading on referenced pins. b This parameter applies to the DEN, INTA1–INTA0, WR, WHB, and WLB signals. 66 Am186/188EM and Am186/188EMLV Microcontrollers P R E L I M I N A R Y SWITCHING CHARACTERISTICS over COMMERCIAL operating range Write Cycle (33 MHz and 40 MHz) Preliminary 33 MHz 40 MHz Min Max Min Max Parameter No. Symbol Description General Timing Responses Unit 3 tCHSV Status Active Delay 0 15 0 12 ns 4 tCLSH Status Inactive Delay 0 15 0 12 ns 5 tCLAV AD Address Valid Delay and BHE 0 15 0 12 ns 6 tCLAX Address Hold 0 25 0 20 ns 7 tCLDV Data Valid Delay 0 15 0 12 ns 8 tCHDX Status Hold Time 0 9 tCHLH ALE Active Delay 10 tLHLL ALE Width 11 tCHLL ALE Inactive Delay 12 0 15 tCLCL –10= 20 tCLCL –5 =20 15 Low(a) tAVLL AD Address Valid to ALE 13 tLLAX AD Address Hold from ALE Inactive(a) 14 tAVCH 16 ns 12 ns ns 12 ns tCLCH tCLCH ns tCHCL tCHCL ns AD Address Valid to Clock High 0 0 ns tCLCSV MCS/PCS Active Delay 0 17 tCXCSX MCS/PCS Hold from Command Inactive(a) 18 tCHCSX MCS/PCS Inactive Delay 19 tDXDL DEN Inactive to DT/R Low(a) 1(b) 15 tCLCH 0 0 12 tCLCH 15 0 0 ns ns 12 0 ns ns 20 tCVCTV Control Active Delay 0 15 0 12 ns 22 tCHCTV Control Active Delay 2 0 15 0 12 ns 23 tLHAV ALE High to Address Valid 10 7.5 ns Write Cycle Timing Responses 30 tCLDOX Data Hold Time 0 31 tCVCTX Control Inactive Delay(b) 0 32 tWLWH WR Pulse Width 33 tWHLH WR Inactive to ALE High(a) 0 15 2tCLCL –10 =50 0 ns 12 ns 2tCLCL –10 =40 ns tCLCH –2 tCLCH –2 ns tCLCL –10= 20 tCLCL –10= 15 ns tCLCH –5 tCLCH ns tCLCL +tCHCL –3 tCLCL +tCHCL –1.25 ns 34 tWHDX Data Hold after WR(a) 35 tWHDEX WR Inactive to DEN Inactive(a) 65 tAVWL A Address Valid to WR Low 67 tCHCSV CLKOUTA High to LCS/UCS Valid 0 15 0 10 ns 68 tCHAV CLKOUTA High to A Address Valid 0 15 0 10 ns 87 tAVBL A Address Valid to WHB, WLB Low tCHCL –3 15 tCHCL –1.25 12 ns Notes: All timing parameters are measured at 1.5 V with 50 pF loading on CLKOUTA unless otherwise noted. All output test conditions are with CL = 50 pF. For switching tests, VIL = 0.45 V and VIH = 2.4 V, except at X1 where VIH = VCC – 0.5 V. a Equal loading on referenced pins. b This parameter applies to the DEN, INTA1–INTA0, WR, WHB, and WLB signals. Am186/188EM and Am186/188EMLV Microcontrollers 67 P R E L I M I N A R Y Write Cycle Waveforms t1 t2 t3 t4 tW CLKOUTA 65 A19–A0 Address 68 8 S6 S6 S6 14 7 AD15–AD0*, AD7–AD0** 30 Address Data 6 AO15–AO8** Address 23 11 9 34 13 ALE 31 10 33 32 WR 12 20 20 31 87 WHB*, WLB* WB** 5 BHE BHE* 67 LCS, UCS 18 16 MCS3–MCS0, PCS6–PCS5, PCS3–PCS0 17 35 20 31 DEN 19 DT/R 22 *** 22 Status S2–S0 3 4 UZI Note: * Am186EM microcontroller only ** Am188EM microcontroller only Changes in t4 phase of the clock preceding next bus cycle if followed by read, INTA, or halt. *** 68 Am186/188EM and Am186/188EMLV Microcontrollers *** P R E L I M I N A R Y SWITCHING CHARACTERISTICS over COMMERCIAL operating range PSRAM Read Cycle (20 MHz and 25 MHz) Preliminary 20 MHz 25 MHz Min Max Min Max Parameter No. Symbol Description General Timing Requirements 1 2 tDVCL tCLDX Data in Setup Data in Hold (b) Unit 10 10 ns 3 3 ns General Timing Responses 5 tCLAV AD Address Valid Delay and BHE 0 25 0 20 ns 7 tCLDV Data Valid Delay 0 25 0 20 ns 8 tCHDX Status Hold Time 0 9 tCHLH ALE Active Delay 10 tLHLL ALE Width 11 tCHLL ALE Inactive Delay 23 tLHAV ALE High to Address Valid 20 80 tCLCLX LCS Inactive Delay 0 25 81 tCLCSL LCS Active Delay 0 25 84 tLRLL 0 25 tCLCL –10= 40 tCLCL –10= 30 25 ns ns 20 15 tCLCL + tCLCH –3 LCS Precharge Pulse Width ns 20 ns ns 0 20 ns 0 20 ns tCLCL + tCLCH –3 ns Read Cycle Timing Responses 24 tAZRL AD Address Float to RD Active 0 25 tCLRL RD Active Delay 0 26 tRLRH RD Pulse Width 2tCLCL –15 =85 27 tCLRH RD Inactive Delay 28 tRHLH RD Inactive to ALE High(a) 59 tRHDX RD High to Data Hold on AD 0 0 25 66 tAVRL A Address Valid to RD Low 68 tCHAV CLKOUTA High to A Address Valid ns 20 2tCLCL –15 =65 25 tCLCH –3 Bus(b) 0 0 ns ns 20 ns tCLCH –3 ns 0 0 ns 2tCLCL –15 =85 2tCLCL –15 =65 ns 0 25 0 20 ns Notes: All timing parameters are measured at 1.5 V with 50 pF loading on CLKOUTA unless otherwise noted. All output test conditions are with CL = 50 pF. For switching tests, VIL = 0.45 V and VIH = 2.4 V, except at X1 where VIH = VCC – 0.5 V. a Equal loading on referenced pins. b If either spec 2 or spec 59 is met with respect to data hold time, the part will function correctly. Am186/188EM and Am186/188EMLV Microcontrollers 69 P R E L I M I N A R Y SWITCHING CHARACTERISTICS over Commercial operating range PSRAM Read Cycle (33 MHz and 40 MHz) Preliminary 33 MHz 40 MHz Min Max Min Max Parameter No. Symbol Description General Timing Requirements 1 2 tDVCL tCLDX Data in Setup Data in Hold (b) Unit 8 5 ns 3 2 ns General Timing Responses 5 tCLAV AD Address Valid Delay and BHE 0 15 0 12 ns 7 tCLDV Data Valid Delay 0 15 0 12 ns 8 tCHDX Status Hold Time 0 9 tCHLH ALE Active Delay 10 tLHLL ALE Width 11 tCHLL ALE Inactive Delay 23 tLHAV ALE High to Address Valid 10 80 tCLCLX LCS Inactive Delay 0 15 81 tCLCSL LCS Active Delay 0 15 84 tLRLL 0 15 tCLCL –10= 20 tCLCL –5= 20 15 ns ns 12 7.5 tCLCL + tCLCH –3 LCS Precharge Pulse Width ns 12 ns ns 0 12 ns 0 12 ns tCLCL + tCLCH –1.25 ns Read Cycle Timing Responses 24 tAZRL AD Address Float to RD Active 0 25 tCLRL RD Active Delay 0 26 tRLRH RD Pulse Width 2tCLCL –15 =45 27 tCLRH RD Inactive Delay 28 tRHLH RD Inactive to ALE High(a) 59 tRHDX RD High to Data Hold on AD 0 0 15 66 tAVRL A Address Valid to RD Low 68 tCHAV CLKOUTA High to A Address Valid ns 10 2tCLCL –10 =40 15 tCLCH –3 Bus(b) 0 0 ns ns 12 ns tCLCH –1.25 ns 0 0 ns 2tCLCL –15 =45 2tCLCL –10 =40 ns 0 15 0 10 ns Notes: All timing parameters are measured at 1.5 V with 50 pF loading on CLKOUTA unless otherwise noted. All output test conditions are with CL = 50 pF. For switching tests, VIL = 0.45 V and VIH = 2.4 V, except at X1 where VIH = VCC – 0.5 V. a Equal loading on referenced pins. b If either spec 2 or spec 59 is met with respect to data hold time, the part will function correctly. 70 Am186/188EM and Am186/188EMLV Microcontrollers P R E L I M I N A R Y PSRAM Read Cycle Waveforms t1 t3 t2 t4 t1 tW CLKOUTA 66 Address A19–A0 8 68 S6 S6 S6 1 7 AD15–AD0*, AD7–AD0** Address Data Address 2 Address AO15–AO8** 23 9 11 59 ALE 10 28 24 26 RD 27 5 25 27 LCS 80 81 80 84 Notes: * Am186EM microcontroller only ** Am188EM microcontroller only Am186/188EM and Am186/188EMLV Microcontrollers 71 P R E L I M I N A R Y SWITCHING CHARACTERISTICS over COMMERCIAL operating range PSRAM Write Cycle (20 MHz and 25 MHz) Parameter No. Symbol Description General Timing Responses AD Address Valid Delay and 5 tCLAV BHE Preliminary 20 MHz 25 MHz Min Max Min Max 0 25 0 20 ns 25 0 20 ns 7 tCLDV Data Valid Delay 0 8 tCHDX Status Hold Time 0 9 tCHLH ALE Active Delay 10 tLHLL ALE Width 11 tCHLL ALE Inactive Delay 23 tLHAV ALE High to Address Valid tCLCL –10=40 20 tCVCTV Control Active Delay 80 tCLCLX LCS Inactive Delay 81 tCLCSL LCS Active Delay 84 tLRLL 0 25 LCS Precharge Pulse Width ns 20 tCLCL –10=30 25 1(b) Unit 20 ns ns 20 15 ns ns 0 25 0 20 ns 0 25 0 20 ns 0 25 0 20 ns tCLCL + tCLCH tCLCL + tCLCH – 3 –3 Write Cycle Timing Responses 30 tCLDOX Data Hold Time 0 31 tCVCTX Control Inactive Delay(b) 0 32 tWLWH WR Pulse Width 33 tWHLH WR Inactive to ALE High(a) 34 tWHDX Data Hold after WR(a) 65 tAVWL A Address Valid to WR Low tCLCL +tCHCL –3 68 tCHAV 87 tAVBL CLKOUTA High to A Address Valid A Address Valid to WHB, WLB Low 0 25 2tCLCL–10 =90 0 ns 20 ns 2tCLCL –10 =70 ns tCLCH –2 tCLCH –2 ns tCLCL –10=40 tCLCL –10=30 ns tCLCL +tCHCL –3 ns 0 25 0 20 ns tCHCL –3 25 tCHCL –3 20 ns Notes: All timing parameters are measured at 1.5 V with 50 pF loading on CLKOUTA unless otherwise noted. All output test conditions are with CL = 50 pF. For switching tests, VIL = 0.45 V and VIH = 2.4 V, except at X1 where VIH = VCC – 0.5 V. a Equal loading on referenced pins. b This parameter applies to the DEN, WR, WHB, and WLB signals. 72 Am186/188EM and Am186/188EMLV Microcontrollers P R E L I M I N A R Y SWITCHING CHARACTERISTICS over COMMERCIAL operating range PSRAM Write Cycle (33 MHz and 40 MHz) Parameter No. Symbol Description General Timing Responses AD Address Valid Delay and 5 tCLAV BHE Preliminary 33 MHz 40 MHz Min Max Min Max 0 15 0 12 ns 15 0 12 ns 7 tCLDV Data Valid Delay 0 8 tCHDX Status Hold Time 0 9 tCHLH ALE Active Delay 10 tLHLL ALE Width 11 tCHLL ALE Inactive Delay 20 tCVCTV 0 15 tCLCL –10=20 15 Control Active Delay 1(b) 0 15 tLHAV ALE High to Address Valid 10 80 tCLCLX LCS Inactive Delay 0 15 81 tCLCSL LCS Active Delay 0 15 tLRLL LCS Precharge Pulse Width ns 12 tCLCL –5=20 23 84 Unit 0 ns ns 12 ns 12 ns 7.5 ns 0 12 ns 0 12 ns tCLCL + tCLCH tCLCL + tCLCH –3 –1.25 Write Cycle Timing Responses 30 tCLDOX Data Hold Time 0 31 tCVCTX Control Inactive Delay(b) 0 32 tWLWH WR Pulse Width 33 tWHLH WR Inactive to ALE High(a) 34 tWHDX Data Hold after WR(a) 65 tAVWL A Address Valid to WR Low tCLCL +tCHCL –3 68 tCHAV 87 tAVBL CLKOUTA High to A Address Valid A Address Valid to WHB, WLB Low 0 15 2tCLCL –10 =50 0 ns 12 ns 2tCLCL –10 =40 ns tCLCH –2 tCLCH –2 ns tCLCL –10=20 tCLCL –10=15 ns tCLCL +tCHCL –1.25 ns 0 15 0 10 ns tCHCL –3 15 tCHCL –1.25 12 ns Notes: All timing parameters are measured at 1.5 V with 50 pF loading on CLKOUTA unless otherwise noted. All output test conditions are with CL = 50 pF. For switching tests, VIL = 0.45 V and VIH = 2.4 V, except at X1 where VIH = VCC – 0.5 V. a Equal loading on referenced pins. b This parameter applies to the DEN, WR, WHB, and WLB signals. Am186/188EM and Am186/188EMLV Microcontrollers 73 P R E L I M I N A R Y PSRAM Write Cycle Waveforms t1 t2 t3 t1 t4 tW CLKOUTA 65 Address A19–A0 68 8 S6 S6 S6 7 AD15–AD0*, AD7–AD0** 30 Address Data Address AO15–AO8** 23 11 9 ALE 34 10 33 32 WR 31 5 20 20 WHB*, WLB* WB** LCS 87 80 84 81 Notes: * Am186EM microcontroller only ** Am188EM microcontroller only 74 31 Am186/188EM and Am186/188EMLV Microcontrollers 80 P R E L I M I N A R Y SWITCHING CHARACTERISTICS over COMMERCIAL operating range PSRAM Refresh Cycle (20 MHz and 25 MHz) Parameter No. Symbol Description General Timing Responses 9 tCHLH ALE Active Delay 10 tLHLL ALE Width 11 tCHLL ALE Inactive Delay Preliminary 20 MHz 25 MHz Min Max Min Max 25 tCLCL –10= 40 20 tCLCL –10= 30 25 Unit ns ns 20 ns 20 ns Read/Write Cycle Timing Responses 25 tCLRL RD Active Delay 0 2tCLCL –15 =85 26 tRLRH RD Pulse Width 27 tCLRH RD Inactive Delay 0 High(a) 25 0 2tCLCL –15 =65 25 tCLCH –3 0 ns 20 tCLCH –3 ns 28 tRHLH RD Inactive to ALE 80 tCLCLX LCS Inactive Delay 0 25 0 20 ns ns 81 tCLCSL LCS Active Delay 0 25 0 20 ns Refresh Timing Cycle Parameters 79 tCLRFD CLKOUTA Low to RFSH Valid 0 25 0 20 ns 82 tCLRF CLKOUTA High to RFSH Invalid 0 25 0 20 ns 85 tRFCY RFSH Cycle Time 6 • tCLCL 6 • tCLCL 86 tLCRF LCS Inactive to RFSH Active Delay 2tCLCL –3 2tCLCL –3 ns Note: All timing parameters are measured at 1.5 V with 50 pF loading on CLKOUTA unless otherwise noted. All output test conditions are with CL = 50 pF. For switching tests, VIL = 0.45 V and VIH = 2.4 V, except at X1 where VIH = VCC – 0.5 V. a Equal loading on referenced pins. Am186/188EM and Am186/188EMLV Microcontrollers 75 P R E L I M I N A R Y SWITCHING CHARACTERISTICS over COMMERCIAL operating range PSRAM Refresh Cycle (33 MHz and 40 MHz) Parameter No. Symbol Description General Timing Responses 9 tCHLH ALE Active Delay 10 tLHLL ALE Width 11 tCHLL ALE Inactive Delay Preliminary 33 MHz 40 MHz Min Max Min Max 15 12 tCLCL –5 =20 tCLCL –10=20 15 Unit ns ns 12 ns 10 ns Read/Write Cycle Timing Responses 25 tCLRL RD Active Delay 0 2tCLCL –15 =45 26 tRLRH RD Pulse Width 27 tCLRH RD Inactive Delay 0 High(a) 15 0 2tCLCL –10 =40 15 tCLCH –3 0 ns 12 tCLCH –2 ns 28 tRHLH RD Inactive to ALE 80 tCLCLX LCS Inactive Delay 0 15 0 12 ns ns 81 tCLCSL LCS Active Delay 0 15 0 12 ns Refresh Timing Cycle Parameters 79 tCLRFD CLKOUTA Low to RFSH Valid 0 15 0 12 ns 82 tCLRF CLKOUTA High to RFSH Invalid 0 15 0 12 ns 85 tRFCY RFSH Cycle Time 6 • tCLCL 6 • tCLCL 86 tLCRF LCS Inactive to RFSH Active Delay 2tCLCL –3 2tCLCL –1.25 ns Note: All timing parameters are measured at 1.5 V with 50 pF loading on CLKOUTA unless otherwise noted. All output test conditions are with CL = 50 pF. For switching tests, VIL = 0.45 V and VIH = 2.4 V, except at X1 where VIH = VCC – 0.5 V. a 76 Equal loading on referenced pins. Am186/188EM and Am186/188EMLV Microcontrollers P R E L I M I N A R Y PSRAM Refresh Cycle Waveforms t1 t2 t3 t4 t1 tW * CLKOUTA Address A19–A0 11 9 ALE 27 10 28 26 RD 80 27 25 81 LCS 79 RFSH 82 85 86 Note: * The period tw is fixed at 3 wait states for PSRAM auto refresh only. Am186/188EM and Am186/188EMLV Microcontrollers 77 P R E L I M I N A R Y SWITCHING CHARACTERISTICS over COMMERCIAL operating range Interrupt Acknowledge Cycle (20 MHz and 25 MHz) Preliminary 20 MHz 25 MHz Min Max Min Max Parameter No. Symbol Description General Timing Requirements Unit 1 tDVCL Data in Setup 10 10 ns 2 tCLDX Data in Hold 3 3 ns General Timing Responses 3 tCHSV Status Active Delay 0 25 0 20 ns 4 tCLSH Status Inactive Delay 0 25 0 20 ns 7 tCLDV Data Valid Delay 0 25 0 20 ns 8 tCHDX Status Hold Time 0 9 tCHLH ALE Active Delay 10 tLHLL ALE Width 11 tCHLL ALE Inactive Delay 12 tAVLL AD Address Invalid to ALE Low(a) 15 tCLAZ AD Address Float Delay 19 tDXDL DEN Inactive to DT/R Low(a) 0 25 tCLCL –10=40 20 tCVCTV Control Active Delay 21 tCVDEX 22 tCHCTV 20 tCLCL –10=30 25 tCLCH tCLAX =0 1(b) ns ns 20 tCLCH 25 0 tCLAX =0 ns ns ns 20 0 ns ns 0 25 0 20 ns DEN Inactive Delay 0 25 0 20 ns Control Active Delay 2(c) 0 25 0 20 ns 23 tLHAV ALE High to Address Valid 20 31 tCVCTX Control Inactive Delay(b) 0 25 15 0 20 ns ns 68 tCHAV CLKOUTA High to A Address Valid 0 25 0 20 ns Notes: All timing parameters are measured at 1.5 V with 50 pF loading on CLKOUTA unless otherwise noted. All output test conditions are with CL = 50 pF. For switching tests, VIL = 0.45 V and VIH = 2.4 V, except at X1 where VIH = VCC – 0.5 V. a Equal loading on referenced pins. b This parameter applies to the INTA1–INTA0 signals. c This parameter applies to the DEN and DT/R signals. 78 Am186/188EM and Am186/188EMLV Microcontrollers P R E L I M I N A R Y SWITCHING CHARACTERISTICS over COMMERCIAL operating range Interrupt Acknowledge Cycle (33 MHz and 40 MHz) Preliminary 33 MHz 40 MHz Min Max Min Max Parameter No. Symbol Description General Timing Requirements Unit 1 tDVCL Data in Setup 8 5 ns 2 tCLDX Data in Hold 3 2 ns General Timing Responses 3 tCHSV Status Active Delay 0 15 0 12 ns 4 tCLSH Status Inactive Delay 0 15 0 12 ns 7 tCLDV Data Valid Delay 0 15 0 12 ns 8 tCHDX Status Hold Time 0 9 tCHLH ALE Active Delay 10 tLHLL ALE Width 11 tCHLL ALE Inactive Delay 12 tAVLL AD Address Invalid to ALE Low(a) 15 tCLAZ AD Address Float Delay 19 tDXDL DEN Inactive to DT/R Low(a) 0 15 tCLCL –10=20 20 tCVCTV Control Active Delay 21 tCVDEX 22 tCHCTV 12 tCLCL –5=20 15 tCLCH tCLAX =0 1(b) ns ns 12 tCLCH 15 0 tCLAX =0 ns ns ns 12 0 ns ns 0 15 0 12 ns DEN Inactive Delay 0 15 0 12 ns Control Active Delay 2(c) 0 15 0 12 ns 23 tLHAV ALE High to Address Valid 10 31 tCVCTX Control Inactive Delay(b) 0 15 7.5 0 12 ns ns 68 tCHAV CLKOUTA High to A Address Valid 0 15 0 10 ns Notes: All timing parameters are measured at 1.5 V with 50 pF loading on CLKOUTA unless otherwise noted. All output test conditions are with CL = 50 pF. For switching tests, VIL = 0.45 V and VIH = 2.4 V, except at X1 where VIH = VCC – 0.5 V. a Equal loading on referenced pins. b This parameter applies to the INTA1–INTA0 signals. c This parameter applies to the DEN and DT/R signals. Am186/188EM and Am186/188EMLV Microcontrollers 79 P R E L I M I N A R Y Interrupt Acknowledge Cycle Waveforms t1 t2 t3 t4 tW CLKOUTA 68 A19–A0 Address 7 S6 8 S6 S6 1 AD15–AD0*, AD7–AD0** 2 (b) 12 Ptr 15 AO15–AO8** Address 23 9 ALE 10 11 BHE BHE* 31 INTA1–INTA0 20 DEN 22 19 (c) 21 22 DT/R 4 (a) 3 22 (d) Status S2–S0 Notes: * Am186EM microcontroller only ** Am188EM microcontroller only a The status bits become inactive in the state preceding t4. b The data hold time lasts only until the interrupt acknowledge signal deasserts, even if the interrupt acknowledge transition occurs prior to tCLDX (min). c This parameter applies for an interrupt acknowledge cycle that follows a write cycle. d If followed by a write cycle, this change occurs in the state preceding that write cycle. 80 Am186/188EM and Am186/188EMLV Microcontrollers P R E L I M I N A R Y SWITCHING CHARACTERISTICS over COMMERCIAL operating range Software Halt Cycle (20 MHz and 25 MHz) Preliminary 20 MHz 25 MHz Min Max Min Max Parameter No. Symbol Description General Timing Responses Unit 3 tCHSV Status Active Delay 0 25 0 20 ns 4 tCLSH Status Inactive Delay 0 25 0 20 ns 5 tCLAV AD Address Invalid Delay and BHE 0 25 0 20 ns 9 tCHLH ALE Active Delay 20 ns 10 tLHLL ALE Width 11 tCHLL ALE Inactive Delay 19 tDXDL DEN Inactive to DT/R Low(a) 22 68 25 tCLCL –10=40 tCLCL –10=30 25 2(b) tCHCTV Control Active Delay tCHAV CLKOUTA High to A Address Invalid 0 ns 20 0 ns ns 0 25 0 20 ns 0 25 0 20 ns Notes: All timing parameters are measured at 1.5 V with 50 pF loading on CLKOUTA unless otherwise noted. All output test conditions are with CL = 50 pF. For switching tests, VIL = 0.45 V and VIH = 2.4 V, except at X1 where VIH = VCC – 0.5 V. a Equal loading on referenced pins. b This parameter applies to the DEN signal. Am186/188EM and Am186/188EMLV Microcontrollers 81 P R E L I M I N A R Y SWITCHING CHARACTERISTICS over COMMERCIAL operating range Software Halt Cycle (33 MHz and 40 MHz) Preliminary 33 MHz 40 MHz Min Max Min Max Parameter No. Symbol Description General Timing Responses Unit 3 tCHSV Status Active Delay 0 15 0 12 ns 4 tCLSH Status Inactive Delay 0 15 0 12 ns 5 tCLAV AD Address Invalid Delay and BHE 0 15 0 12 ns 9 tCHLH ALE Active Delay 12 ns 10 tLHLL ALE Width 11 tCHLL ALE Inactive Delay 19 tDXDL DEN Inactive to DT/R Low(a) 22 68 15 tCLCL –10=20 tCLCL –5=20 15 2(b) tCHCTV Control Active Delay tCHAV CLKOUTA High to A Address Invalid 0 ns 12 0 ns ns 0 15 0 12 ns 0 15 0 10 ns Notes: All timing parameters are measured at 1.5 V with 50 pF loading on CLKOUTA unless otherwise noted. All output test conditions are with CL = 50 pF. For switching tests, VIL = 0.45 V and VIH = 2.4 V, except at X1 where VIH = VCC – 0.5 V. a Equal loading on referenced pins. b This parameter applies to the DEN signal. 82 Am186/188EM and Am186/188EMLV Microcontrollers P R E L I M I N A R Y Software Halt Cycle Waveforms t1 t2 ti ti CLKOUTA 68 A19–A0 Invalid Address 5 S6, AD15–AD0*, AD7–AD0**, AO15-AO8** Invalid Address 10 ALE 9 11 DEN 19 DT/R 22 4 Status S2–S0 3 Notes: * Am186EM microcontroller only ** Am188EM microcontroller only Am186/188EM and Am186/188EMLV Microcontrollers 83 P R E L I M I N A R Y SWITCHING CHARACTERISTICS over COMMERCIAL operating range Clock (20 MHZ and 25 MHz) Preliminary 20 MHz 25 MHz Min Max Min Max Parameter No. Symbol Description CLKIN Requirements 36 tCKIN X1 Period(a) 50 (a) 60 40 60 Unit ns 37 tCLCK X1 Low Time (1.5 V) 15 15 ns 38 tCHCK X1 High Time (1.5 V)(a) 15 15 ns 39 40 tCKHL tCKLH X1 Fall Time (3.5 to 1.0 V)(a) X1 Rise Time (1.0 to 3.5 V) (a) 5 5 ns 5 5 ns CLKOUT Timing 42 43 44 45 46 tCLCL CLKOUTA Period CLKOUTA Low Time (CL =50 pF) CLKOUTA High Time tCHCL (CL =50 pF) CLKOUTA Rise Time tCH1CH2 (1.0 to 3.5 V) CLKOUTA Fall Time tCL2CL1 (3.5 to 1.0 V) tCLCH 50 40 0.5tCLCL –2 =23 0.5tCLCL –2 =23 0.5tCLCL –2 =18 0.5tCLCL –2 =18 ns ns ns 3 3 ns 3 3 ns 61 tLOCK Maximum PLL Lock Time 1 1 ms 69 tCICOA X1 to CLKOUTA Skew 15 15 ns 70 tCICOB X1 to CLKOUTB Skew 21 21 ns Notes: All timing parameters are measured at 1.5 V with 50 pF loading on CLKOUTA unless otherwise noted. All output test conditions are with CL = 50 pF. For switching tests, VIL = 0.45 V and VIH = 2.4 V, except at X1 where VIH = VCC – 0.5 V. a The specifications for CLKIN are applicable to the normal PLL and CLKDIV2 modes. The PLL should be used for operations from 16.667 MHz to 40 MHz. For operations below 16.667 MHz, the CLKDIV2 mode should be used. Because the CLKDIV2 input frequency is two times the system frequency, the specifications for twice the frequency should be used for CLKDIV2 mode. For example, use the 20 MHz CLKIN specifications for 10 MHz operation. 84 Am186/188EM and Am186/188EMLV Microcontrollers P R E L I M I N A R Y SWITCHING CHARACTERISTICS over COMMERCIAL operating range Clock (33 MHZ and 40 MHz) Preliminary 33 MHz 40 MHz Min Max Min Max Parameter No. Symbol Description CLKIN Requirements 36 tCKIN X1 Period(a) 30 (a) 60 25 60 Unit ns 37 tCLCK X1 Low Time (1.5 V) 10 7.5 ns 38 tCHCK X1 High Time (1.5 V)(a) 10 7.5 ns 39 40 tCKHL tCKLH X1 Fall Time (3.5 to 1.0 V)(a) X1 Rise Time (1.0 to 3.5 V) (a) 5 5 ns 5 5 ns CLKOUT Timing 42 43 44 45 46 tCLCL CLKOUTA Period CLKOUTA Low Time (CL =50 pF) CLKOUTA High Time tCHCL (CL =50 pF) CLKOUTA Rise Time tCH1CH2 (1.0 to 3.5 V) CLKOUTA Fall Time tCL2CL1 (3.5 to 1.0 V) tCLCH 30 25 0.5tCLCL –1.5 =13.5 0.5tCLCL –1.5 =13.5 0.5tCLCL –1.25 =11.25 0.5tCLCL –1.25 =11.25 ns ns ns 3 3 ns 3 3 ns 61 tLOCK Maximum PLL Lock Time 1 1 ms 69 tCICOA X1 to CLKOUTA Skew 15 15 ns 70 tCICOB X1 to CLKOUTB Skew 21 21 ns Notes: All timing parameters are measured at 1.5 V with 50 pF loading on CLKOUTA unless otherwise noted. All output test conditions are with CL = 50 pF. For switching tests, VIL = 0.45 V and VIH = 2.4 V, except at X1 where VIH = VCC – 0.5 V. a The specifications for CLKIN are applicable to the normal PLL and CLKDIV2 modes. The PLL should be used for operations from 16.667 MHz to 40 MHz. For operations below 16.667 MHz, the CLKDIV2 mode should be used. Because the CLKDIV2 input frequency is two times the system frequency, the specifications for twice the frequency should be used for CLKDIV2 mode. For example, use the 20 MHz CLKIN specifications for 10 MHz operation. Am186/188EM and Am186/188EMLV Microcontrollers 85 P R E L I M I N A R Y Clock Waveforms—Active Mode X2 37 36 38 X1 39 40 45 46 CLKOUTA (Active, F=000) 69 42 43 44 CLKOUTB 70 Clock Waveforms—Power-Save Mode X2 X1 CLKOUTA(a) CLKOUTB(b) CLKOUTB(c) Notes: a The Clock Divisor Select (F2–F0) bits in the Power Save Control Register (PDCON) are set to 010 (divide by 4). b The CLKOUTB Output Frequency (CBF) bit in the Power Save Control Register (PDCON) is set to 1. c The CLKOUTB Output Frequency (CBF) bit in the Power Save Control Register (PDCON) is set to 0. 86 Am186/188EM and Am186/188EMLV Microcontrollers P R E L I M I N A R Y SWITCHING CHARACTERISTICS over COMMERCIAL operating range Ready and Peripheral Timing (20 MHz and 25 MHz) Preliminary 20 MHz Min Max Parameter No. Symbol Description Ready and Peripheral Timing Requirements 47 48 49 tSRYCL SRDY Transition Setup Time(a) (a) tCLSRY SRDY Transition Hold Time tARYCH ARDY Resolution Transition Setup Time(b) (a) 50 tCLARX ARDY Active Hold Time 51 tARYCHL ARDY Inactive Holding Time 52 tARYLCL 53 tINVCH 54 tINVCL ARDY Setup Time (a) Peripheral Setup Time(b) DRQ Setup Time(b) Preliminary 25 MHz Min Max Unit 10 10 ns 3 3 ns 10 10 ns 4 4 ns 6 6 ns 15 15 ns 10 10 ns 10 10 ns Peripheral Timing Responses 55 tCLTMV Timer Output Delay 25 20 ns Notes: All timing parameters are measured at 1.5 V with 50 pF loading on CLKOUTA unless otherwise noted. All output test conditions are with CL = 50 pF. For switching tests, VIL = 0.45 V and VIH = 2.4 V, except at X1 where VIH = VCC – 0.5 V. a This timing must be met to guarantee proper operation. b This timing must be met to guarantee recognition at the clock edge. Am186/188EM and Am186/188EMLV Microcontrollers 87 P R E L I M I N A R Y SWITCHING CHARACTERISTICS over COMMERCIAL operating range Ready and Peripheral Timing (33 MHz and 40 MHz) Preliminary 33 MHz 40 MHz Min Max Min Max Parameter No. Symbol Description Ready and Peripheral Timing Requirements 47 tSRYCL 48 49 SRDY Transition Setup Time(a) (a) tCLSRY SRDY Transition Hold Time tARYCH ARDY Resolution Transition Setup Time(b) 50 tCLARX 51 tARYCHL ARDY Inactive Holding Time 52 tARYLCL 53 tINVCH 54 tINVCL ARDY Active Hold Time (a) ARDY Setup Time (a) Peripheral Setup Time(b) DRQ Setup Time(b) Unit 8 5 ns 3 2 ns 8 5 ns 4 3 ns 6 5 ns 10 5 ns 8 5 ns 8 5 ns Peripheral Timing Responses 55 tCLTMV Timer Output Delay 15 12 ns Notes: All timing parameters are measured at 1.5 V with 50 pF loading on CLKOUTA unless otherwise noted. All output test conditions are with CL = 50 pF. For switching tests, VIL = 0.45 V and VIH = 2.4 V, except at X1 where VIH = VCC – 0.5 V. a This timing must be met to guarantee proper operation. b This timing must be met to guarantee recognition at the clock edge. Synchronous Ready Waveforms Case 1 tW tW tW t4 Case 2 t3 tW tW t4 Case 3 t2 t3 tW t4 Case 4 t1 t2 t3 t4 CLKOUTA 47 SRDY 48 88 Am186/188EM and Am186/188EMLV Microcontrollers P R E L I M I N A R Y Asynchronous Ready Waveforms Case 1 tW tW tW t4 Case 2 t3 tW tW t4 Case 3 t2 t3 tW t4 Case 4 t1 t2 t3 t4 CLKOUTA 49 50 ARDY (Normally NotReady System) 49 ARDY (Normally Ready System) 50 51 52 Peripheral Waveforms CLKOUTA 53 INT4–INT0, NMI, TMRIN1–TMRIN0 54 DRQ1–DRQ0 55 TMROUT1– TMROUT0 Am186/188EM and Am186/188EMLV Microcontrollers 89 P R E L I M I N A R Y SWITCHING CHARACTERISTICS over COMMERCIAL operating range Reset and Bus Hold (20 MHz and 25 MHz) Parameter No. Symbol Description Reset and Bus Hold Timing Requirements 5 tCLAV AD Address Valid Delay and BHE 15 tCLAZ 57 tRESIN 58 tHVCL Preliminary 20 MHz 25 MHz Min Max Min Max Unit 0 25 AD Address Float Delay 0 25 RES Setup Time 10 10 ns 10 10 ns HOLD Setup(a) 0 20 ns 0 20 ns Reset and Bus Hold Timing Responses 62 tCLHAV HLDA Valid Delay 20 ns 63 tCHCZ Command Lines Float Delay 0 25 25 0 20 ns 64 tCHCV Command Lines Valid Delay (after Float) 25 20 ns Note: All timing parameters are measured at 1.5 V with 50 pF loading on CLKOUTA unless otherwise noted. All output test conditions are with CL = 50 pF. For switching tests, VIL = 0.45 V and VIH = 2.4 V, except at X1 where VIH = VCC – 0.5 V. a This timing must be met to guarantee recognition at the next clock. Reset and Bus Hold (33 MHz and 40 MHz) Parameter No. Symbol Description Reset and Bus Hold Timing Requirements 5 Preliminary 33 MHz 40 MHz Min Max Min Max Unit tCLAV AD Address Valid Delay and BHE 0 15 0 12 ns 15 tCLAZ AD Address Float Delay 0 15 0 12 ns 57 tRESIN RES Setup Time 8 5 ns 8 5 ns 58 tHVCL HOLD Setup(a) Reset and Bus Hold Timing Responses 62 tCLHAV HLDA Valid Delay 12 ns 63 tCHCZ Command Lines Float Delay 0 15 15 0 12 ns 64 tCHCV Command Lines Valid Delay (after Float) 15 12 ns Note: All timing parameters are measured at 1.5 V with 50 pF loading on CLKOUTA unless otherwise noted. All output test conditions are with CL = 50 pF. For switching tests, VIL = 0.45 V and VIH = 2.4 V, except at X1 where VIH = VCC – 0.5 V. a 90 This timing must be met to guarantee recognition at the next clock. Am186/188EM and Am186/188EMLV Microcontrollers P R E L I M I N A R Y Reset Waveforms X1 57 57 RES CLKOUTA Signals Related to Reset Waveforms RES CLKOUTA BHE/ADEN, RFSH2/ADEN, S6/CLKDIV2, and UZI AD15–AD0 (186) AO15–AO8, AD7–AD0 (188) three-state three-state Am186/188EM and Am186/188EMLV Microcontrollers 91 P R E L I M I N A R Y Bus Hold Waveforms—Entering Case 1 ti ti ti Case 2 t4 ti ti CLKOUTA 58 HOLD 62 HLDA 15 AD15–AD0, DEN 63 A19–A0, S6, RD, WR, BHE, DT/R, S2–S0 WHB, WLB Bus Hold Waveforms—Leaving Case 1 ti ti ti t1 Case 2 ti ti t4 t1 CLKOUTA 58 HOLD 62 HLDA 5 AD15–AD0, DEN 64 A19–A0, S6, RD, WR, BHE, DT/R, S2–S0 WHB, WLB 92 Am186/188EM and Am186/188EMLV Microcontrollers P R E L I M I N A R Y SWITCHING CHARACTERISTICS over COMMERCIAL operating range Synchronous Serial Interface (SSI) (20 MHz and 25 MHz) Parameter No. Symbol Description Synchronous Serial Port Timing Requirements Preliminary 20 MHz 25 MHz Min Max Min Max Unit 75 tDVSH Data Valid to SCLK High 10 10 ns 77 tSHDX SCLK High to SPI Data Hold 3 3 ns Synchronous Serial Port Timing Responses 71 tCLEV CLKOUTA Low to SDEN Valid 25 20 ns 72 tCLSL CLKOUTA Low to SCLK Low 25 20 ns 78 tSLDV SCLK Low to Data Valid 25 20 ns Note: All timing parameters are measured at 1.5 V with 50 pF loading on CLKOUTA unless otherwise noted. All output test conditions are with CL = 50 pF. For switching tests, VIL = 0.45 V and VIH = 2.4 V, except at X1 where VIH = VCC – 0.5 V. Synchronous Serial Interface (SSI) (33 MHz and 40 MHz) Preliminary Parameter No. Symbol Description Synchronous Serial Port Timing Requirements 33 MHz Min Max 40 MHz Min Max Unit 75 tDVSH Data Valid to SCLK High 8 5 ns 77 tSHDX SCLK High to SPI Data Hold 2 2 ns Synchronous Serial Port Timing Responses 71 tCLEV CLKOUTA Low to SDEN Valid 0 15 0 12 ns 72 tCLSL CLKOUTA Low to SCLK Low 0 15 0 12 ns 78 tSLDV SCLK Low to Data Valid 0 15 0 12 ns Note: All timing parameters are measured at 1.5 V with 50 pF loading on CLKOUTA unless otherwise noted. All output test conditions are with CL = 50 pF. For switching tests, VIL = 0.45 V and VIH = 2.4 V, except at X1 where VIH = VCC – 0.5 V. Am186/188EM and Am186/188EMLV Microcontrollers 93 P R E L I M I N A R Y Synchronous Serial Interface (SSI) Waveforms CLKOUTA 71 SDEN 72 72 SCLK SDATA (RX) DATA 75 SDATA (TX) 77 DATA 78 Note: SDATA is bidirectional and used for either transmit (TX) or receive (RX). Timing is shown separately for each case. 94 Am186/188EM and Am186/188EMLV Microcontrollers P R E L I M I N A R Y TQFP PHYSICAL DIMENSIONS PQL 100, Trimmed and Formed Thin Quad Flat Pack Pin 100 Pin 75 Pin 1 ID 12.00 Ref –B– –A– 13.80 14.20 15.80 16.20 Pin 25 –D– Pin 50 12.00 Ref 13.80 14.20 15.80 16.20 Top View See Detail X 1.35 1.45 S 1.60 Max –A– –C– Seating Plane S 0.50 Basic 1.00 Ref Side View Notes: 1. All measurements are in millimeters unless otherwise noted. 2. Not to scale; for reference only. Am186/188EM and Am186/188EMLV Microcontrollers pql100 4-15-94 95 P R E L I M I N A R Y PQL 100 (continued) 0° Min 1.60 Max Gage Plane 0.05 0.15 0.13 R 0.20 0.25 Seating Plane 0.45 0.75 0°–7° 0.17 0.27 Max 0.08 Lead Coplanarity 0.20 Detail X 0.17 0.27 0.14 0.18 Section S-S Notes: 1. All measurements are in millimeters unless otherwise noted. 2. Not to scale; for reference only. 96 Am186/188EM and Am186/188EMLV Microcontrollers pql100 4-15-94 P R E L I M I N A R Y PQFP PHYSICAL DIMENSIONS PQR 100, Trimmed and Formed Plastic Quad Flat Pack 17.00 17.40 13.90 14.10 Pin 100 12.35 REF Pin 80 Pin 1 I.D. 18.85 REF –B– -–A– 19.90 20.10 23.00 23.40 Pin 30 - –D– Pin 50 Top View See Detail X 0.65 BASIC S 2.70 2.90 3.35 Max 0.25 Min –A– Seating –C– S Side View Notes: 1. All measurements are in millimeters unless otherwise noted. 2. Not to scale; for reference only. Am186/188EM and Am186/188EMLV Microcontrollers pqr100 4-15-94 97 P R E L I M I N A R Y PQFP PQR 100 (continued) 0.20 Min. Flat Shoulder 7° Typ. 0° Min. 0.30±0.05 R Gage Plane 3.35 Max 0.25 0.73 1.03 7° Typ. 0°–7° Detail X 0.22 0.38 0.15 0.23 0.22 0.38 0.15 0.23 Section S-S Note: Not to scale; for reference only. pqr100 4-15-94 Trademarks AMD, the AMD logo, and combinations thereof are trademarks of Advanced Micro Devices, Inc. Am386 and Am486 are registered trademarks of Advanced Micro Devices, Inc. Am186, Am188, E86, K86, Élan, and AMD Facts-On-Demand are trademarks of Advanced Micro Devices, Inc. FusionE86 is a service mark of Advanced Micro Devices, Inc. Product names used in this publication are for identification purposes only and may be trademarks of their respective companies. 98 Am186/188EM and Am186/188EMLV Microcontrollers