MC10ELT21, MC100ELT21 5 VDifferential PECL to TTL Translator Description • • • • • • 3.5 ns Typical Propagation Delay 24 mA TTL Output Flow Through Pinouts Operating Range: VCC = 4.75 V to 5.25 V with GND = 0 V Q Output Will Default LOW with Inputs Left Open or < 1.3 V Pb−Free Packages are Available MARKING DIAGRAMS* 8 8 1 SOIC−8 D SUFFIX CASE 751 1 8 HLT21 ALYW G 8 8 1 TSSOP−8 DT SUFFIX CASE 948R 1 KLT21 ALYW G 1 8 HT21 ALYWG G 1 KT21 ALYWG G DFN8 MN SUFFIX CASE 506AA H K 5C 2Q M = MC10 = MC100 = MC10 = MC100 = Date Code 2Q MG G Features http://onsemi.com 5C MG G The MC10ELT/100ELT21 is a differential PECL to TTL translator. Because PECL (Positive ECL) levels are used, only +5 V and ground are required. The small outline 8-lead package and the single gate of the ELT21 makes it ideal for those applications where space, performance and low power are at a premium. The VBB pin, an internally generated voltage supply, is available to this device only. For single-ended input conditions, the unused differential input is connected to VBB as a switching reference voltage. VBB may also rebias AC coupled inputs. When used, decouple VBB and VCC via a 0.01 mF capacitor and limit current sourcing or sinking to 0.5 mA. When not used, VBB should be left open. The 100 Series contains temperature compensation. 1 4 1 4 A L Y W G = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package (Note: Microdot may be in either location) *For additional marking information, refer to Application Note AND8002/D. ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 5 of this data sheet. © Semiconductor Components Industries, LLC, 2006 December, 2006 − Rev. 11 1 Publication Order Number: MC10ELT21/D MC10ELT21, MC100ELT21 NC D0 1 8 TTL 2 Table 1. PIN DESCRIPTION VCC 7 Q0 6 NC Pin PECL D0 VBB 3 4 5 GND Function Q0 TTL Outputs D0, DO PECL Differential Outputs VBB Reference Voltage Output VCC Positive Supply GND Ground NC No Connect EP Exposed pad must be connected to a sufficient thermal conduit. Electrically connect to the most negative supply or leave floating open. Figure 1. 8−Lead Pinout and Logic Diagram (Top View) Table 2. ATTRIBUTES Characteristics Value Internal Input Pulldown Resistor 50 kW Internal Input Pullup Resistor N/A ESD Protection Human Body Model > 2 kV Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1) SOIC−8 TSSOP−8 DFN8 Flammability Rating Pb Pkg Pb−Free Pkg Level 1 Level 1 Level 1 Level 1 Level 3 Level 1 Oxygen Index: 28 to 34 UL 94 V−0 @ 0.125 in Transistor Count 81 Devices Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional information, see Application Note AND8003/D. Table 3. MAXIMUM RATINGS Symbol Parameter Condition 1 Rating Unit 7 V 0 to 6 V ± 0.5 mA Operating Temperature Range −40 to +85 °C Tstg Storage Temperature Range −65 to +150 °C qJA Thermal Resistance (Junction−to−Ambient) 0 lfpm 500 lfpm SOIC−8 SOIC−8 190 130 °C/W °C/W qJC Thermal Resistance (Junction−to−Case) Standard Board SOIC−8 41 to 44 °C/W qJA Thermal Resistance (Junction−to−Ambient) 0 lfpm 500 lfpm TSSOP−8 TSSOP−8 185 140 °C/W °C/W qJA Thermal Resistance (Junction−to−Ambient) 0 lfpm 500 lfpm DFN8 DFN8 129 84 °C/W °C/W Tsol Wave Solder <2 to 3 sec @ 248°C <2 to 3 sec @ 260°C 265 265 °C VCC PECL Power Supply GND = 0 V VIN PECL Input Voltage GND = 0 V IBB VBB Sink/Source TA Pb Pb−Free Condition 2 VI VCC Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. http://onsemi.com 2 MC10ELT21, MC100ELT21 Table 4. 10ELT SERIES PECL INPUT DC CHARACTERISTICS VCC = 5.0 V; GND = 0.0 V (Note 2) −40°C Max Min Max Min Max Unit Input HIGH Voltage (Single−Ended) 3770 4110 3870 4190 3930 4265 mV VIL Input LOW Voltage (Single−Ended) 3050 3500 3050 3520 3050 3555 mV VBB Output Voltage Reference 3.57 3.7 3.65 3.75 3.69 3.81 V VIHCMR Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 3) 2.2 5.0 2.2 5.0 2.2 5.0 V IIH Input HIGH Current 175 mA IIL Input LOW Current Characteristic Typ Typ 85°C VIH Symbol Min 25°C 255 0.5 Typ 175 0.5 0.3 mA NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 2. Output parameters vary 1:1 with VCC. VCC can vary ± 0.25 V. 3. VIHCMR min varies 1:1 with GND, VIHCMR max varies 1:1 with VCC. Table 5. 100ELT SERIES PECL INPUT DC CHARACTERISTICS VCC = 5.0 V; GND = 0.0 V (Note 4) −40°C Symbol Characteristic Min Typ 25°C Max Min Typ 85°C Max Min Typ Max Unit VIH Input HIGH Voltage (Single−Ended) 3835 4120 3835 4120 3835 4120 mV VIL Input LOW Voltage (Single−Ended) 3190 3525 3190 3525 3190 3525 mV VBB Output Voltage Reference 3.62 3.74 3.62 3.74 3.62 3.745 V VIHCMR Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 5) 2.2 5.0 2.2 5.0 2.2 5.0 V IIH Input HIGH Current 175 mA IIL Input LOW Current 255 0.5 175 0.5 0.5 mA NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket o printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 4. Input parameters vary 1:1 with VCC. VCC can vary ± 0.25 V. 5. VIHCMR min varies 1:1 with GND, VIHCMR max varies 1:1 with VCC. Table 6. TTL OUTPUT DC CHARACTERISTICS VCC = 4.75 V to 5.25 V; TA = −40°C to 85°C) Symbol Characteristic Condition Min Typ 2.4 Max Unit (Note 6) V VOH Output HIGH Voltage IOH = −3.0 mA VOL Output LOW Voltage IOL = 24 mA 0.5 V ICCH Power Supply Current 20 29 mA ICCL Power Supply Current 22 32 mA IOS Output Short Circuit Current −60 mA −150 NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 6. Maximum level is VCC − 0.7 by design. http://onsemi.com 3 MC10ELT21, MC100ELT21 AC CHARACTERISTICS VCC = 4.75 V to 5.25 V; GND = 0.0 V (Note 7) −40°C Symbol Characteristic Min Typ 25°C Max Min Typ 85°C Max Min Typ Max Unit fmax Maximum Toggle Frequency 100 MHz tJITTER Random Clock Jitter (RMS) 35 ps tPLH Propagation Delay @ 1.5 V 2.0 5.5 2.0 5.5 2.0 5.5 ns tPHL Propagation Delay @ 1.5 V 2.0 5.5 2.0 5.5 2.0 5.5 ns VPP Input Swing (Note 8) 200 1000 200 1000 200 1000 mV tr/tf Output Rise/Fall Time (10−90%) 750 ps NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 7. RL = 500 W to GND and CL = 20 pF to GND. Refer to Figure 2. 8. VPP(min) is the minimum input swing for which AC parameters are guaranteed. The device has a DC gain of ≈ 40. APPLICATION TTL RECEIVER CHARACTERISTIC TEST *CL includes fixture capacitance CL * RL AC TEST LOAD GND Figure 2. TTL Output Loading Used for Device Evaluation http://onsemi.com 4 MC10ELT21, MC100ELT21 ORDERING INFORMATION Package Shipping† SOIC−8 98 Units / Rail MC10ELT21DG SOIC−8 (Pb−Free) 98 Units / Rail MC10ELT21DR2 SOIC−8 2500 / Tape & Reel MC10ELT21DR2G SOIC−8 (Pb−Free) 2500 / Tape & Reel MC10ELT21DT TSSOP−8 100 Units / Rail MC10ELT21DTG TSSOP−8 (Pb−Free) 100 Units / Rail MC10ELT21DTR2 TSSOP−8 2500 / Tape & Reel MC10ELT21DTR2G TSSOP−8 (Pb−Free) 2500 / Tape & Reel MC10ELT21MNR4 DFN8 1000 / Tape & Reel DFN8 (Pb−Free) 1000 / Tape & Reel SOIC−8 98 Units / Rail MC100ELT21DG SOIC−8 (Pb−Free) 98 Units / Rail MC100ELT21DR2 SOIC−8 2500 / Tape & Reel MC100ELT21DR2G SOIC−8 (Pb−Free) 2500 / Tape & Reel MC100ELT21DT TSSOP−8 100 Units / Rail MC100ELT21DTG TSSOP−8 (Pb−Free) 100 Units / Rail MC100ELT21DTR2 TSSOP−8 2500 / Tape & Reel MC100ELT21DTR2G TSSOP−8 (Pb−Free) 2500 / Tape & Reel MC100ELT21MNR4 DFN8 1000 / Tape & Reel DFN8 (Pb−Free) 1000 / Tape & Reel Device MC10ELT21D MC10ELT21MNR4G MC100ELT21D MC100ELT21MNR4G †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. Resource Reference of Application Notes AN1405/D − ECL Clock Distribution Techniques AN1406/D − Designing with PECL (ECL at +5.0 V) AN1503/D − ECLinPSt I/O SPiCE Modeling Kit AN1504/D − Metastability and the ECLinPS Family AN1568/D − Interfacing Between LVDS and ECL AN1672/D − The ECL Translator Guide AND8001/D − Odd Number Counters Design AND8002/D − Marking and Date Codes AND8020/D − Termination of ECL Logic Devices AND8066/D − Interfacing with ECLinPS AND8090/D − AC Characteristics of ECL Devices http://onsemi.com 5 MC10ELT21, MC100ELT21 PACKAGE DIMENSIONS SOIC−8 NB CASE 751−07 ISSUE AH −X− NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. 751−01 THRU 751−06 ARE OBSOLETE. NEW STANDARD IS 751−07. A 8 5 S B 1 0.25 (0.010) M Y M 4 −Y− K G C N DIM A B C D G H J K M N S X 45 _ SEATING PLANE −Z− H 0.10 (0.004) D 0.25 (0.010) M Z Y S X M J S SOLDERING FOOTPRINT* 1.52 0.060 7.0 0.275 4.0 0.155 0.6 0.024 1.270 0.050 SCALE 6:1 mm Ǔ ǒinches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 6 MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 BSC 0.10 0.25 0.19 0.25 0.40 1.27 0_ 8_ 0.25 0.50 5.80 6.20 INCHES MIN MAX 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 BSC 0.004 0.010 0.007 0.010 0.016 0.050 0 _ 8 _ 0.010 0.020 0.228 0.244 MC10ELT21, MC100ELT21 PACKAGE DIMENSIONS TSSOP−8 DT SUFFIX PLASTIC TSSOP PACKAGE CASE 948R−02 ISSUE A 8x 0.15 (0.006) T U 0.10 (0.004) S 2X L/2 L 8 5 1 PIN 1 IDENT 0.15 (0.006) T U K REF S M T U V S 0.25 (0.010) B −U− 4 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH. PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 6. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE −W−. S M A −V− F DETAIL E C 0.10 (0.004) −T− SEATING PLANE D −W− G DETAIL E http://onsemi.com 7 DIM A B C D F G K L M MILLIMETERS MIN MAX 2.90 3.10 2.90 3.10 0.80 1.10 0.05 0.15 0.40 0.70 0.65 BSC 0.25 0.40 4.90 BSC 0_ 6_ INCHES MIN MAX 0.114 0.122 0.114 0.122 0.031 0.043 0.002 0.006 0.016 0.028 0.026 BSC 0.010 0.016 0.193 BSC 0_ 6_ MC10ELT21, MC100ELT21 PACKAGE DIMENSIONS DFN8 CASE 506AA−01 ISSUE D 1 D NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994 . 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.25 AND 0.30 MM FROM TERMINAL. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. A B PIN ONE REFERENCE 2X 0.10 C 2X 0.10 C ÇÇÇ ÇÇÇ ÇÇÇ ÇÇÇ TOP VIEW 0.08 C SEATING PLANE MILLIMETERS MIN MAX 0.80 1.00 0.00 0.05 0.20 REF 0.20 0.30 2.00 BSC 1.10 1.30 2.00 BSC 0.70 0.90 0.50 BSC 0.20 −−− 0.25 0.35 A 0.10 C 8X DIM A A1 A3 b D D2 E E2 e K L E (A3) SIDE VIEW A1 C D2 e e/2 4 1 8X L E2 K 8 5 8X b 0.10 C A B 0.05 C NOTE 3 BOTTOM VIEW ECLinPS is a trademark of Semiconductor Components Industries, LLC (SCILLC). ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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