Data Sheet May 2001 L8576B Dual Ringing SLIC Features Applications ■ Two SLIC channels for multiple tip/ring interfaces ■ POTS for ISDN ■ On-chip balanced ringing generator, no ring relay required ■ Terminal adapters (TA) ■ Digital loop carrier (DLC) systems ■ Single battery operation or optional automatic battery switch ■ PABX ■ Quiet battery reversal for on-hook signaling ■ Disconnect state ■ Distortion-free, on-hook transmission ■ 24 mA loop current limiter ■ Ring trip detector ■ Switchhook detector ■ Immune to channel crosstalk and impulse noise ■ Allows rail overvoltages for ease of protection ■ Thermal protection ■ 44-pin, surface-mount, plastic package (PLCC) Description The Agere Systems Inc. L8576B electronic dual subscriber line interface circuit (SLIC) provides all the functions that are necessary to interface a codec to the tip and ring of a subscriber loop, integrating two battery feeds and ringing generators in one low-cost package. The L8576B device is optimized to meet the needs of short loop, customer premises applications and features balanced ringing from the single battery supply. The device is built using a 90 V complementary bipolar (CBIC) process. It is available in a 44-pin PLCC package. Data Sheet May 2001 L8576B Dual Ringing SLIC Table of Contents Contents Page Features ......................................................................1 Applications .................................................................1 Description...................................................................1 Pin Information ............................................................5 Functional Description .................................................7 General .....................................................................7 Protection..................................................................7 Tip/Ring Drivers ........................................................7 Battery Operation......................................................7 Transmit and Receive Interface ................................7 Data Interface ...........................................................8 Loop Current Detector ..............................................8 Operating States..........................................................8 Absolute Maximum Ratings ........................................9 Electrical Characteristics ...........................................10 Test Configurations .................................................. 14 Applications ..............................................................15 Characteristic Curves..............................................15 dc Design ................................................................17 Power Ringing.........................................................18 ac Design ................................................................19 Use of an Auxiliary Battery Supply..........................24 Outline Diagram ........................................................25 44-Pin PLCC ...........................................................25 Ordering Information .................................................26 Tables Page Table 1. Pin Descriptions ............................................5 Table 2. Input State Coding ........................................9 Table 3. Operating Conditions and Powering ...........10 Table 4. Ring Trip Detector ......................................10 Table 5. Battery Feed ...............................................11 Table 6. Analog Signal Pins .....................................12 Table 7. ac Feed Characteristics ..............................12 Table 8. Isolation Between Channels .......................13 Table 9. Data Interface and Logic ............................13 2 Figures Page Figure 1. Architectural Diagram ................................. 3 Figure 2. Typical 600 Ω Application Circuit (Only One Channel Shown) ................................. 4 Figure 3. 44-Pin PLCC Pin Diagram .......................... 5 Figure 4. Pretrip Circuit ............................................ 11 Figure 5. Basic Test Circuit ..................................... 14 Figure 6. Metallic PSRR .......................................... 14 Figure 7. Longitudinal PSRR ................................... 14 Figure 8. Longitudinal Balance ................................ 15 Figure 9. Longitudinal Impedance ........................... 15 Figure 10. ac Gains ................................................. 15 Figure 11. Receive Gain and Hybrid Balance vs. Frequency .............................................. 15 Figure 12. Transmit Gain and Return Loss vs. Frequency .............................................. 15 Figure 13. Loop Current vs. Loop Voltage ............... 16 Figure 14. Loop Current vs. Loop Resistance ......... 16 Figure 15. SLIC Power Dissipation vs. Loop Resistance (VBAT = –48 V) ...................... 16 Figure 16. SLIC Power Dissipation vs. Loop Resistance (VBAT = –65 V) ...................... 16 Figure 17. Loop Current vs. Loop Voltage ............... 17 Figure 18. Ringing Waveform Crest Factor = 1.6 .... 18 Figure 19. Ringing Waveform Crest Factor = 1.2 .... 18 Figure 20. ac Equivalent Circuit Using a T8503 Codec ..................................................... 20 Figure 21. ac Interface Circuit Using FirstGeneration Codec (Blocking Capacitors Not Shown) ............................................. 22 Figure 22. ac Interface Circuit Using FirstGeneration Codec (Including Blocking Capacitors) ............................................. 23 Agere Systems Inc. Data Sheet May 2001 L8576B Dual Ringing SLIC CF2 CF1 AGND VCC BGND VBAT Description (continued) POWER CONDITIONING & REFERENCE RTTH RING TRIP RTFLT RECTIFIER DCOUT ac CONDITIONING VITR AX TG1 TG2 PT – A=6 + X1 RCVN RCVP B2 PR –X1 BATTERY FEED STATE CONTROL RNGNG NDISC VCC RPWR VCC IPROG CURRENT-LIMIT CIRCUIT DCOUT LOOP CLOSURE DETECTOR + – NSTAT 12-3362(F).c Figure 1. Architectural Diagram Agere Systems Inc. 3 Data Sheet May 2001 L8576B Dual Ringing SLIC B2a VBAT NDISCa RNGNGa Description (continued) RDCT* 300 kΩ VCC VBAT RPWRa 2.2 kΩ 5%, 2W CVCC 0.1 µF 10 V CF1a, 0.22 µF, 100 V 10% POLYESTER 43 40 38 41 24 1 37 RGX1a RGX2a 16.9 kΩ 7.5 kΩ 32 TG1 CTG1a 470 pF 10 V CBa 0.33 µF 10 V 33 TG2 GAIN = 125 V/A CF2a, 0.22 µF, 100 V 10% POLYESTER 44 ac CONDITIONER + AX – 1/2 L8576 SLIC 34 VITRa RECTIFIER TIP RPT1a 30 PTa X1 36 8 1 CH 0 7 2 6 L7591 3 VBAT 5 4 FGND PRa 35 RING + – –X1 VCCa 75 µA (130 µA RINGING) DCOUTa 29 CPROGa 0.056 µF 50 V RRCVa 143 kΩ CC1A 0.1 µF 10 V – + RHBa 309 kΩ CC2a 33 nF 10 V RGNa 27.4 kΩ 19 GSX1 VFXIN1 20 +2.4 V VFRO1 17 RGa 27.4 kΩ RPR1a 30 RPROGa 51.1 kΩ RT2a 40.2 kΩ RCVNa 26 VCC TO DTMF RECEIVER RXa 154 kΩ RT1a 41.2 kΩ 27 RCVPa + – A=6 CVBATa 0.1 µF 100 V RGX3a 10 kΩ LCTHa 23 1/2 T8503 CODEC RRNG 28.7 kΩ GNDA1 18 RRNG NSTATa 39 + – NSTATa VDD VCC +5 V VBAT –65 V 6 DX 11 DR 12 MCLK 9 FSX1 13 VDD DX DR MCLK FS0 FSR1 14 10 DGND IPROGa 28 30 RTTHa 31 RTFLTa 25 42 BGNDa RDCR* 300 kΩ RTTHa 52.3 kΩ VBAT RTFLTa 383 kΩ CRTa 0.1 µF 50 V AGNDa AGND BGND DGND FGND GND 5-8414a (F) * RDCT and RDCR (optional) are only required to keep the NSTAT output at a steady state during the disconnect state. Notes: TX = –2 dB. RX = –4 dB. Termination = 600 Ω. Hybrid balance = 600 Ω. Ring trip optimized for 20 Hz. Figure 2. Typical 600 Ω Application Circuit (Only One Channel Shown) 4 Agere Systems Inc. Data Sheet May 2001 L8576B Dual Ringing SLIC RNGNGb B2b BGNDb CF1b CF2b VBAT CF2a CF1a BGNDa B2a RNGNGa Pin Information 6 5 4 3 2 1 44 43 42 41 40 RPWRa PTb 10 36 PTa PRb 11 35 PRa VITRb 12 34 VITRa TG2b 13 33 TG2a TG1b 14 32 TG1a RTFLTb 15 31 RTFLTa RTTHb 16 30 RTTHa DCOUTb 17 29 DCOUTa 18 19 20 21 22 23 24 25 26 27 28 IPROGa 37 RCVPa 9 RCVNa RPWRb AGNDa NDISCa VCCa 38 RRNG 8 VCCb NDISCb AGNDb NSTATa RCVNb 39 RCVPb 7 IPROGb NSTATb 12-3361(F).a Figure 3. 44-Pin PLCC Pin Diagram Table 1. Pin Descriptions Pin, Pin, Circuit Circuit Symbol Type a b 1 44 43 42 41 1 2 3 4 5 VBAT* CF2 CF1 BGND* B2 — — — — Iu Name/Function Office Battery Supply. Negative high-voltage power supply, nominally –65 V. Filter Capacitor 2. Connect 0.22 µF capacitor to AGND. Filter Capacitor 1. Connect 0.22 µF capacitor to AGND. Battery Ground. Ground return for the battery supply and fault ground. State Input. Refer to Operating States section. A pull-up device is included. * On the printed-wiring board (PWB), make the leads to BGND and VBAT as wide as possible for thermal and electrical reasons. Also, maximize the amount of PWB copper on all leads connected to this device for the lowest operating temperature. Note: Iu and Ou indicate a pull-up device is included on this lead. Agere Systems Inc. 5 Data Sheet May 2001 L8576B Dual Ringing SLIC Pin Information (continued) Table 1. Pin Descriptions (continued) Pin, Pin, Circuit Circuit Symbol Type a b 40 6 RNGNG Iu 39 7 NSTAT Ou 38 8 NDISC Iu 37 9 RPWR — 36 10 PT I/O 35 11 PR I/O 34 12 VITR O 33 13 TG2 — 32 14 TG1 — 31 15 RTFLT — 30 16 RTTH — 29 17 DCOUT O 28 18 IPROG I 27 19 RCVP I 26 20 RCVN I 25 24 23 21 22 23 AGND VCC RRNG — — — Name/Function Ringing Input. Refer to Operating States section. A pull-up device is included. Loop Detector Output/Ring Trip Detector Output. When low, this lead indicates an off-hook condition. When in ringing mode, a low output on this lead indicates a ring trip. A pull-up device is included. Disconnect Input. Refer to Operating States section. A pull-up device is included. Power Resistor. Connect a resistor between this pin and VBAT. A 2.2 kΩ, 2 W resistor should be used for a VBAT of –68.5 V. See the Applications section to calculate resistor values for other VBAT potentials. Protected Tip. The input to the tip fault protection and output of tip current drive amplifier. Connect this pin to the tip of the loop through a 30 Ω overvoltage protection resistor. Protected Ring. The input to the ring fault protection and output of ring current drive amplifier. Connect this pin to the ring of the loop through a 30 Ω overvoltage protection resistor. Transmit ac Output Voltage. This output is a voltage that is directly proportional to the differential tip/ring current. Transmit Gain 2. Transmit gain and current limiting for ringing is set by the value of RGX2. RGX2 is connected between TG2 and VITR. Transmit Gain 1. Transmit gain is set by the series resistor combination of RGX1 and RGX2 from this lead to TG2. Ring Trip Filter. Connect this lead to RTTH via a resistor and to AGND with a capacitor to filter the ring trip circuit to prevent spurious responses. Ring Trip Threshold. Connect this lead to DCOUT via a resistor to set the ring trip threshold. dc Voltage Out. This output is a voltage that is directly proportional to the absolute value of the differential tip/ring current. Current-Limit Program Input. A resistor to DCOUT sets the dc current limit of the circuit. Receive Signal Input (+). This high-impedance input controls the ac differential voltage on tip/ring. Receive Signal Input (–). This high-impedance input controls the ac differential voltage on tip/ring. Analog Signal Ground. Analog 5 V Power Supply. Ringing Slope Resistor. Connect this lead to AGND with a resistor to set the slope of the ringing waveform. Note that this pin is shared with both sections. * On the printed-wiring board (PWB), make the leads to BGND and VBAT as wide as possible for thermal and electrical reasons. Also, maximize the amount of PWB copper on all leads connected to this device for the lowest operating temperature. Note: Iu and Ou indicate a pull-up device is included on this lead. 6 Agere Systems Inc. Data Sheet May 2001 L8576B Dual Ringing SLIC Functional Description Tip/Ring Drivers Refer to the architectural and application diagrams (Figures 1 and 2, respectively). The L8576B has two tip/ring drivers whose outputs are PT and PR. Each driver operates as a current source capable of sinking or sourcing adequate ac signal bias current. In the normal talk operating mode, these drivers are current-limited at a nominal 24 mA to minimize the power dissipation of short loops. These amplifiers are also used to drive balanced ringing. During ringing, the current limit is raised to approximately 85 mA. General The L8576B is a dual subscriber line interface circuit with each half of the device providing battery feed, supervision, and balanced ringing. It is designed to support short loops, typically on customer premises. The use of a single battery for both battery feed and ringing makes this device particularly advantageous where it is desirable to minimize power supply costs in small systems, such as terminal adapters. The tip and ring drive amplifiers are used with a very relaxed current limit to develop a trapezoidal, balanced ringing signal. Use of a nominal –65 V power supply allows for ringing of normal phones, whether equipped with a mechanical ringer, or a peak-detection type of ringing detector. While balanced ringing is not the norm worldwide, its use in short, customer premises loops is gaining popularity. In addition to the ringing and battery functions, the L8576B device provides the ac receive and transmit paths. Also, integral within the device is an off-hook detection circuit and a ring trip detection circuit that have their outputs multiplexed on a single lead. Thermal protection within the device is also provided, and an external resistor is used to drop the high battery voltage before applying loop current, thus allowing a significant portion of the power to be dissipated outside of the device. Removing much of this power makes it possible to incorporate two complete circuits in a 44-pin, surface-mount package. Protection The L8576B contains some overvoltage protection in addition to the thermal protection within the device. This protection, along with the associated tip and ring protection resistors, may be sufficient in some benign environments. However, if power line cross or lightning protection is desired, the use of an external protection circuit (such as the L7591 device from Agere) is highly recommended. The integrated thermal protection consists of a thermal shutdown circuit which places the tip/ring drivers in a high-impedance state when the temperature of the die exceeds 160 °C. In thermal shutdown, all supervision states are undefined. Agere Systems Inc. The external resistor connected to the RPWR pin is used to dissipate power externally and also to drop the battery voltage which is higher than normal in order to support balanced ringing. Note that this external power dissipation is present during both ringing or normal battery feed operation. Power limitations restrict the dual device to actively ringing only one channel at a time; thus, ringing cadence must be used to ensure that only one channel is actively ringing at any given instant of time. In other words, to ring both channels at the same time, ring each channel during the quiet interval of the other channel. Battery Operation There are two VBAT inputs to the device. Pin 1 (VBAT) provides voltage to the entire SLIC and pins 9 and 37 (RPWR) provide voltage to the individual tip and ring amplifiers of each channel through RPWR resistors. A shared current sourcing scheme is employed within the device. For loop currents below 20 mA, the V BAT applied to pin 1 sources all of the loop current in addition to driving internal circuitry. For loop currents greater than 20 mA, loop current is primarily provided through the RPWR resistors and the pin 1 VBAT mainly powers internal circuitry. The RPWR resistors can be replaced by a lower-voltage auxiliary battery. Operation with an auxiliary battery is described in the Applications section of this document. Transmit and Receive Interface The interface is suitable for direct coupling to a ±5 V only codec. When interfacing a 5 V only codec, coupling capacitors are required. The transmit interface circuitry couples the differential voltage on tip and ring to transmit output VITR. The inverting input of the driving amplifier is available on lead TG1, so connecting a resistance between VITR and TG1 allows adjustment of the transmit gain (transconductance). 7 Data Sheet May 2001 L8576B Dual Ringing SLIC Functional Description (continued) Operating States Transmit and Receive Interface (continued) The L8576B device has four operating states: ■ Talk state—normal battery: — Normal talk state. — Battery feed is connected to the battery supply (VBAT). — Both receive and transmit transmission paths are powered up. — dc loop and instantaneous current limiters are powered up and active. — NSTAT reflects the status of the switchhook detector. — PR is negative with respect to PT. ■ Talk state—reverse battery: — Normal talk state. — Battery feed is connected to the battery supply (VBAT). — Both receive and transmit transmission paths are powered up. — dc loop current limiter is powered up and active. — NSTAT reflects the status of the switchhook detector. — PR is positive with respect to PT. ■ Ringing state: — Normal ringing state. — Both receive and transmit transmission paths are inactive. — Balanced ringing is applied to PR and PT, in accordance with B2. — Current limiter is set for ringing limit. — NSTAT reflects the status of the ring trip detector. — Only one channel should be in this state at a time to control power dissipation. ■ Disconnect state: — Tip and ring drive amplifiers are powered down. — Pins PT and PR are high impedance (>100 kΩ). — NSTAT is undefined. — PT and PR voltage is undefined. A second gain setting is provided to accommodate ring trip. A switch is built into TG2. In ringing mode, TG1 and TG2 are internally connected, thus shorting out the external gain resistor RGX1. This provides a lower transmit gain for ringing since ring trip is accomplished by monitoring the voltage at DCOUT. This lower gain sets DCOUT at the appropriate level to accommodate the higher currents of the ring trip. The receive interface circuitry couples the differential signal on receive inputs RCVP and RCVN to the tip/ring drivers. Data Interface A 4-wire parallel interface (B2, RNGNG, NDISC, and NSTAT) is provided for each channel to control signals to and from the system controller. B2 controls the forward/reverse battery in normal talk mode while RNGNG enables the balanced ringing mode of operation, and NDISC performs a disconnect state. NSTAT reflects either the loop detector output or the ring trip detector output, depending on the mode of the section. It is the responsibility of the system controller to recognize ring trip detection and set RNGNG to a logic 0 state to terminate ringing. The system controller should also use RNGNG to set ringing cadence. Loop Current Detector Each section of the device has an integral loop current detector set at a nominal 12 mA of dc current. This is used to detect off-hook transitions in the normal talk state. When current less than the current threshold (including no current) is flowing, NSTAT is at logic 1. When loop current exceeds 12 mA, the output NSTAT switches to a logic 0. No hysteresis is included. 8 Agere Systems Inc. Data Sheet May 2001 L8576B Dual Ringing SLIC Operating States (continued) These states are selected using three logic inputs, B2, RNGNG, and NDISC. B2 sets normal operation, either with forward or reverse battery. RNGNG overrides B2 and applies ringing with the polarity of tip and ring reversed on edges of the B2 signal. The slope of the waveform is determined by a resistor from RRNG to AGND. Logic input NDISC puts the device into a loop current denial state (disconnect). Tip and ring amplifiers are saturated against ground with about a 100 µA current source. This creates a level in the loop current sensing circuitry that approaches a loop closed state. Some conditions on the tip and ring could cause the circuit to indicate loop closed even though the loop is open. This situation can be prevented by connecting a 300 k Ω resistor from VBAT to each of the outputs of the tip and ring amplifiers (see Figure 2). This will pull the amplifier output to about 30 V above VBAT, keeping the NSTAT output at a steady high (on-hook indication) level. If the disconnect state is not used or the NSTAT output during the disconnect state is not recognized or used, then the resistors are not needed. Table 2 below summarizes the operating input state coding. Table 2. Input State Coding NDISC RNGNG B2 1 1 1 0 0 1 1 1 0 0/1 State 1 Forward Battery, Normal Talk, and Feed State. Pin PT is positive with respect to PR. 0 Reverse Battery, Normal Talk, and Feed State. Pin PT is negative with respect to PR. 1 ↑ Ringing Is Applied to PT and PR. On the transition, PT starts towards a positive voltage (with respect to PR). The endpoint of this state is PT at BGND and PR at VBAT. 0 ↓ Ringing Is Applied to PT and PR. On the transition, PT starts towards a negative voltage (with respect to PR). The endpoint of this state is PT at VBAT and PR at BGND. 0/1 Disconnect State. The tip and ring amplifiers are turned off, and the SLIC goes into a high-impedance state (>100 kΩ). Absolute Maximum Ratings (at TA = 25 °C) Stresses in excess of the absolute maximum ratings can cause permanent damage to the device. These are absolute stress ratings only. Functional operation of the device is not implied at these or any other conditions in excess of those given in the operational sections of the data sheet. Exposure to absolute maximum ratings for extended periods can adversely affect device reliability. Parameter Symbol Min Typ Max Unit 5 V dc Supplies Office Battery Supply Logic Input Voltage Logic Input Clamp Diode Current, per Pin Logic Output Voltage Logic Output Current, per Pin Analog Input Voltage Maximum Junction Temperature Storage Temperature Range Relative Humidity Range (noncondensing) Ground Potential Difference (BGND to AGND) PT or PR Fault Voltage (dc) PT or PR Fault Voltage (10 µs x 1000 µs) VCC VBAT — — — — — — Tstg — — — — –0.5 –75 –0.5 — –0.5 — –7.0 — –40 5 — VBAT – 5 VBAT – 15 — — — ±20 — ±35 — 165 — — ±3 — — 7.0 0.5 VCC + 0.5 — VCC + 0.5 — 7.0 — 125 95 — 3 15 V V V mA V mA V °C °C % V V V Note: The IC can be damaged unless all ground connections are applied before, and removed after, all other connections. Furthermore, when powering the device, the user must guarantee that no external potential creates a voltage on any pin of the device that exceeds its ratings. For example, inductance in a supply lead could resonate with the supply filter capacitor to cause a destructive overvoltage. Agere Systems Inc. 9 Data Sheet May 2001 L8576B Dual Ringing SLIC Electrical Characteristics Generally, minimum and maximum values are testing requirements. However, some parameters may not be tested in production because they are guaranteed by design and device characterization. Typical values reflect the design center or nominal value of the parameter; they are for information only and are not a requirement. Minimum and maximum values apply across the entire temperature range (0 °C to 70 °C) and entire battery range (to –72 V). Unless otherwise specified, typical values are defined as 20 °C, VCC = 5.0 V, VBAT = –68.5 V. Positive currents flow into the device. Table 3. Operating Conditions and Powering Parameter Temperature Range Humidity Range Supply Voltages: VCC VBAT Loop Closure Threshold—Detection Range ac Termination Impedance Programming Range On- and Off-hook 2-wire Signal Level Power Supply—Powerup, No Loop Current (per section): ICC IBAT (VBAT = –65 V) Total power (one channel, VBAT = –65 V) Power-supply Rejection (See Figures 6 and 7.): VCC (1 kHz) VBAT (500 Hz—3 kHz) Thermal4: Thermal Resistance (still air) Tj Operating Tj Thermal Shutdown Temperature 1. 2. 3. 4. Min Typ Max Unit 0 5 — — 70 951 °C %RH 4.75 –242 9.5 300 — 5.0 –65 12 600 3.14 5.25 –72 14.5 10003 — V V mA Ω dBm — — — 4.5 3.0 230 5.5 4.0 290 mA mA mW 35 45 — — — — dB dB — — — 47 — 160 — 150 — °C/W °C °C Noncondensing. The L8576B will operate below –24 V; –24 V is used for production test. The termination impedance can be programmed up to 1200 Ω; 1000 Ω are used for production test. This parameter is not tested in production. It is guaranteed by design and device characterization. Table 4. Ring Trip Detector1 Parameter2 Ringing Source: Frequency (ƒ) RRNG = 28.7 kΩ, RTTH = 52.3 kΩ Frequency (ƒ) Contact Agere for Specific Component Values C-message Weighted Noise (900 Ω) REN Load (1386 Ω + 40 µF) with Loop Resistance = 30 Ω, RPT = 30 Ω, RPR = 30 Ω Detection Interval: 20 Hz ≥25 Hz Min Typ Max Unit 17 20 — — 20 — — — 23 50 90 40 Hz Hz dBrnC Vrms — — — — 200 150 ms ms 1. This table is provided for information purposes only. 2. These parameters are not tested in production. 10 Agere Systems Inc. Data Sheet May 2001 L8576B Dual Ringing SLIC Electrical Characteristics (continued) Pretrip will not occur for the circuits shown below, per GR-909, 4.5.9. 200 Ω TIP RING SWITCH CLOSES FOR LESS THAN 12 ms 6 µF TIP RING 10 kΩ 12-2572(F).d Figure 4. Pretrip Circuit Table 5. Battery Feed Parameter Min Typ Max Unit — 15 — — Ω mArms 24 60 — — — 28 70 — — — mA mA mA mArms V — — 60 1 — 70 mA kΩ Ω 67 62 — — dB dB — — dB 1 Loop Resistance Range (3.17 dBm overload into 600 Ω): 1000 ILOOP = 20 mA at VBAT = –65 V 8.5 Longitudinal Current Capability per Wire2 3 RLOOP = 100 Current Limit Ω: 20 dc Loop 50 Instantaneous 4 Tip or Ring Drive Current = dc + Longitudinal + Signal Currents 65 Signal Current 5 |VBAT + 10| Powerup Open Loop Voltage Level Differential Voltage (RNGNG = 0, NDISC = 1, B2 = 1, VBAT = –65 V) Disconnect State: –1 PT or PR Current (VBAT < VPT < 0 V) 100 PT or PR Resistance (VBAT < VPT < 0 V) dc Feed Resistance — 5 6 Longitudinal to Metallic Balance—IEEE Standard 455 : 200 Hz to 1 kHz 54 1 kHz to 3 kHz 48 Metallic to Longitudinal (Harm) Balance7: 200 Hz to 4 kHz 35 1. Assumes 2 x 30 Ω external protection resistors. Note the useful range of the device may be determined by the ringing or supervision range rather than the ac characteristics. 2. The longitudinal current is independent of dc loop current. 3. Current limit ILIM is programmed by a resistor, RPROG, from pin IPROG to pin DCOUT RPROG (kΩ) = 3.5 x (ILIM – 9.2) mA. The current limit has a slope vs. loop voltage of 6 kΩ. To control power dissipation, it is recommended that the default current limits be utilized, i.e., RPROG = 51.1 kΩ for 24 mA nominal loop current limit. 4. Instantaneous current limit minimizes inrush current at the onset of an off-hook condition. Inrush current is only limited when in the forward battery state. The device will settle into a dc loop current-limit value within 400 ms after off-hook. 5. IEEE is a registered trademark of The Institute of Electrical and Electronics Engineers, Inc. 6. Assumes the external protection resistors are matched to 1%. 7. This parameter is not tested during production. It is guaranteed by design and device characterization. Agere Systems Inc. 11 Data Sheet May 2001 L8576B Dual Ringing SLIC Electrical Characteristics (continued) Table 6. Analog Signal Pins Parameter Differential PT/PR Current Sense (DCOUT) Gain (PT/PR to DCOUT): Forward Battery (RGX1 = 16.9 kΩ, RGX2 = 7.5 kΩ) Reverse Battery (RGX1 = 16.9 kΩ, RGX2 = 7.5 kΩ) PT/PR to VITR Gain with RGX1 = 16.9 kΩ, RGX2 = 7.5 kΩ: Forward Battery Reverse Battery Loop Closure Detector Threshold: Programming Accuracy RCVN, RCVP: Input Bias Current Gain RCVP to PT/PR Gain RCVN to PT/PR RCVN, RCVP Input Compliance Min Typ Max Unit –235 235 –250 250 –265 265 V/A V/A –121 121 –125 125 –129 129 V/A V/A — — ±20 % — 11.62 –11.62 –2.5 — 12 –12 — –1.0 12.38 –12.38 VCC µA — — V Min Typ Max Unit 300 600 1000 Ω — — — — 0.3 1.0 % % –3.0 –0.24 0 0 3.0 0.24 % dB –3.0 –0.24 — 0 0 — 3.0 0.24 3.14 % dB dBm –1.00 –0.30 –3.0 — 0 0 –0.1 — 0.05 0.05 2.0 2.0 dB dB dB dB Table 7. ac Feed Characteristics Parameter1 ac Termination Impedance2 Total Harmonic Distortion (200 Hz—4 kHz)3: Off-hook On-hook Transmit Gain (ƒ = 1 kHz) (See Figure 5.): Transmit Accuracy in Percent Transmit Accuracy in dB (relative to 2/3) Receive Gain (ƒ = 1 kHz) (See Figure 5.): Receive Accuracy in Percent Receive Accuracy in dB Tip/Ring Signal Level (600 Ω reference) Gain vs. Frequency (transmit and receive; 1 kHz reference)3: 200 Hz—3.4 kHz 300 Hz—3.4 kHz 3.4 kHz—20 kHz 3.4 kHz—266 kHz 1. Requires external components connected as shown in the Applications section. Transmission characteristics are specified assuming a 600 Ω resistive termination and ±1% external resistors. 2. Transmission characteristics are specified assuming a 600 Ω resistive termination; however, feedback using external components allows the user to adjust the termination impedance from 600 Ω. Any complex impedance R1 + R2 || C between 300 Ω and 1000 Ω can be synthesized using external components. 3. This parameter is not tested in production. It is guaranteed by design and device characterization. 12 Agere Systems Inc. Data Sheet May 2001 L8576B Dual Ringing SLIC Electrical Characteristics (continued) Table 7. ac Feed Characteristics (continued) Parameter1 Gain vs. Level (transmit and receive; 0 dBV reference)2: –50 dB to +3 dB Return Loss3: 200 Hz—500 Hz 500 Hz—3400 Hz Transhybrid Loss3: 200 Hz—500 Hz 500 Hz—2500 Hz 2500 Hz—3400 Hz Idle-channel Noise (Tip/Ring): Psophometric2 C-message 3 kHz Flat2 Idle-channel Noise (XMT): Psophometric2 C-message 3 kHz Flat2 Min Typ Max Unit –0.05 0 0.05 dB 20 26 24 29 — — dB dB 20 26 26 24 29 29 — — — dB dB dB — — — — — — –77 12 20 dBmp dBrnC dBrn — — — — — — –77 12 20 dBmp0 dBrnC0 dBrn0 1. Requires external components connected as shown in Figure 2. Transmission characteristics are specified assuming a 600 Ω resistive termination and ±1% external resistors. 2. This parameter is not tested in production. It is guaranteed by design and device characterization. 3. Return loss and transhybrid loss are functions of device gain accuracies and the external hybrid circuit. Guaranteed performance assumes 1% tolerance components. Table 8. Isolation Between Channels Parameter1 Min Typ Max Unit Interchannel Small-signal Crosstalk. (Both channels in forward or reverse battery state.) (2-wire to 2-wire, 2-wire to 4-wire, 4-wire to 4-wire.) Impulse Noise. (One channel ringing, other channel in forward or reverse battery state.) — –90 –80 dB — 40 47 dBrnC0 1. These parameters are not tested in production. They are guaranteed by design and device characterization. Table 9. Data Interface and Logic Parameter1 Symbol Min Typ Max Unit High-level Input Voltage (B2, RNGNG, and NDISC) Low-level Input Voltage (B2, RNGNG, and NDISC) Input Bias Current (high) (B2, RNGNG, and NDISC) Input Bias Current (low) (B2, RNGNG, and NDISC) High-level Output Voltage (NSTAT, open collector with internal pull-up resistor): (IOUT = –20 µA) (IOUT = –1 µA) Low-level Output Voltage (NSTAT, open collector with internal pull-up resistor) (IOUT = 200 µA) VIH VIL IIH IIL 2 0 –40 –75 — — — — VCC 0.7 –100 –200 V V µA µA VOH VOH VOL 2.4 — 0 4.3 5.0 0.2 VCC — 0.4 V V V 1. All logic voltages are referenced to AGND. Agere Systems Inc. 13 Data Sheet May 2001 L8576B Dual Ringing SLIC Test Configurations VBAT VCC 0.1 µF 0.1 µF VBAT TIP BGND VCC RPT 25 Ω RPR 25 Ω RGX3 10 kΩ CTG 100 pF RGX2 RGX1 TG1 PT RLOOP 600 Ω AGND 16.9 kΩ 7.5 kΩ TG2 0.22 µF VITR XMT RT1 127 kΩ PR RING L8576 DCOUT RCVP RRCV 442 kΩ RCVN RG 88.7 kΩ RCV SLIC RPROG 51.1 kΩ IPROG RTTH 52.3 kΩ RTFLT 383 kΩ RTTH RTFLT RNGNG RPWR VBAT 0.056 µF B2 RPWR NSTAT 2.2 kΩ 0.1 µF CF1 RRNG RRNG 28.7 kΩ CF1 0.22 µF CF2 CF2 0.22 µF 12-3360(F)a Figure 5. Basic Test Circuit V BAT OR VCC 100 Ω V BAT OR VCC 100 Ω 4.7 µF DISCONNECT BYPASS CAPACITOR 4.7 µF VS VS VBAT OR VCC V BAT OR VCC 67.5 Ω PT PT + 900 Ω VT/R – DISCONNECT BYPASS CAPACITOR 10 µF BASIC TEST CIRCUIT + VM – PR PSRR = 20log VS VT/R BASIC TEST CIRCUIT 67.5 Ω 56.3 Ω 10 µF PR PSRR = 20log VS VM 12-2583a(F) 12-2582a(F) Figure 6. Metallic PSRR 14 Figure 7. Longitudinal PSRR Agere Systems Inc. Data Sheet May 2001 L8576B Dual Ringing SLIC Test Configurations (continued) Applications Characteristic Curves 100 µF Figures 11—16 display typical room temperature readings. TIP VS 365 Ω + BASIC TEST CIRCUIT VM 365 Ω – 0 RING VS LONGITUDINAL BALANCE = 20log ------VM 12-2584(F)b Figure 8. Longitudinal Balance DECIBELS (dB) 100 µF RECEIVE GAIN –10 –20 HYBRID BALANCE –30 –40 –50 –60 0.1k ILONG 10k 1k FREQUENCY (Hz) PT + 12-3507(F) VPT – Note: Gain is normalized to 0 dB. BASIC TEST CIRCUIT – ILONG 100k Figure 11. Receive Gain and Hybrid Balance vs. Frequency VPR + PR ZLONG = ∆ VPR ∆ VPT OR ∆ ILONG ∆ ILONG 0 12-2585(F).r1 –5 Figure 9. Longitudinal Impedance TRANSMIT GAIN –10 DECIBELS (dB) –15 XMT PT – RETURN LOSS –30 –35 –45 BASIC TEST CIRCUIT VT/R –25 –40 + 600 Ω –20 PR –50 –55 0.1k RCV VS 1k 10k 100k FREQUENCY (Hz) 12-3508 Note: Gain is normalized to 0 dB. VXMT GXMT = VT/R VT/R GRCV = VRCV 12-2587(F) Figure 12. Transmit Gain and Return Loss vs. Frequency Figure 10. ac Gains Agere Systems Inc. 15 Data Sheet May 2001 L8576B Dual Ringing SLIC Applications (continued) Characteristic Curves (continued) 50 1500 SLIC POWER DISSIPATION (mW) 45 LOOP CURRENT (mA) 40 35 30 VBAT = –65 V 25 20 15 VBAT = –48 V 10 2 CH 1000 500 1 CH 5 0 0 0 10 20 30 40 0 60 50 200 400 600 800 1000 1200 1400 1600 1800 2000 LOOP RESISTANCE (Ω) LOOP VOLTAGE (V) 12-3504 (F) 12-3503 (F) Note: RPROG = 51.1 kΩ. Figure 13. Loop Current vs. Loop Voltage Figure 15. SLIC Power Dissipation vs. Loop Resistance (VBAT = –48 V) SLIC POWER DISSIPATION (mW) 50 45 LOOP CURRENT (mA) 40 35 30 VBAT = –65 V 25 20 15 VBAT = –48 V 10 5 1500 2 CH 1000 1 CH 500 0 0 0 0 200 400 600 200 400 600 800 1000 1200 1400 1600 1800 2000 800 1000 1200 1400 1600 1800 2000 LOOP RESISTANCE (Ω) LOOP RESISTANCE (Ω) 12-3505 (F) 12-3506 (F) Note: RPROG = 51.1 kΩ. Figure 16. SLIC Power Dissipation vs. Loop Resistance (VBAT = –65 V) Figure 14. Loop Current vs. Loop Resistance 16 Agere Systems Inc. Data Sheet May 2001 L8576B Dual Ringing SLIC Applications (continued) Region 2: Current limit. The dc current is limited to a value determined by external resistor RPROG. This region of the dc template has a high resistance (6 kΩ). dc Design Calculate the external resistor as follows: Battery Feed RPROG (kΩ) = 3.5 x (ILIM – 9.2) mA* The dc feed characteristic can be described by: V T/R = IL = To control power dissipation, it is recommended that a 51.1 kΩ RPROG resistor be used to set a default currentlimit value of 24 mA. ( V B AT – V O H ) × R L -------------------------------------------R L + 2R P + R d c RPWR VBAT – VOH ---------------------------------R L + 2R P + R dc Where: IL = dc loop current. VT/R = dc loop voltage. |VBAT| = battery voltage magnitude. VOH = overhead voltage. This is the difference between the battery voltage and the open loop tip/ring voltage. RL = loop resistance, not including protection resistors. RP = protection resistor value. Rdc = SLIC internal dc feed resistance. The design begins by drawing the desired dc template. An example is shown in Figure 17. 50 45 RPWR = V B AT – 22.3 ----------------------------I L I M – 0.003 Power dissipation of the resistor is: WRPWR = (ILIM – 0.003)2 RPWR. For the recommended –68.5 V VBAT and 24 mA ILIM design, a 2.2 kΩ, 2 W resistor is suitable. 2 W resistors are available as surface-mount components. Overhead Voltage 40 LOOP CURRENT (mA) The RPWR resistors dissipate the excess power associated with a single power supply, short-loop application. The resistor provides VBAT to tip and ring amplifiers. There is one resistor associated with each channel. The value of RPWR is dependent upon the battery potential and the current-limit value. The value of RPWR can be determined by using the following equation: In order to drive an on-hook ac signal, the SLIC must set up the tip and ring voltage to a value less than the battery voltage. The amount that the open loop voltage is decreased relative to the battery is referred to as the overhead voltage and is expressed as: 35 30 1 6 kΩ 25 VBAT = –65 V 20 VOH = |VBAT| – (VPT – VPR) 15 VBAT = –48 V 10 –1 Rdc 5 0 0 10 20 30 40 50 60 LOOP VOLTAGE (V) 12-3503.a (F) Figure 17. Loop Current vs. Loop Voltage Starting from the on-hook condition and going through to a short circuit, the curve passes through two regions: Region 1: On-hook and low loop currents. In this region, the slope corresponds to the dc resistance of the SLIC, Rdc (typically 60 Ω). The open circuit voltage is the battery voltage less the overhead voltage of the device, VOH (default is 7.1 V typical). These values are suitable for most applications. Agere Systems Inc. Without this buffer voltage, amplifier saturation will occur and the signal will be clipped. The L8576 is automatically set at the factory to allow undistorted on-hook transmission of a 3.17 dBm signal into a 900 Ω loop impedance. The drive amplifiers are capable of 4 Vrms minimum (VAMP). So, the maximum signal the device can guarantee is: Z T/R V T/R = 4 V -------------------------- Z T/R + 2R P For normal forward or reverse battery operation, overhead voltage is internally set to about 8 V. In ringing mode, the overhead voltage is automatically decreased to about 4 V to permit passage of a larger ring signal. * During the balanced ringing mode, the current limit is increased from the value predicted by this equation by a factor of 3.5. 17 Data Sheet May 2001 L8576B Dual Ringing SLIC dc Design (continued) Off-Hook Detection The loop closure comparator has built-in longitudinal rejection, eliminating the need for an external 60 Hz filter. The loop closure detection threshold is internally set at 12 mA. Power Ringing CF1 and CF2 must exhibit a stable capacitance value over its voltage range to ensure a properly shaped waveform. Do not use a ceramic capacitor for CF1 and CF2; use a capacitor with a polyester, polypropylene, polycarbonate, or polystyrene dielectric. 80 60 VOLTS (V) Applications (continued) 40 20 0 –20 –40 The L8576B is designed to generate a balanced trapezoidal power ring signal to tip and ring. Because the L8576B generates the power ringing signal, no ring relay is needed in this mode of operation. Alternatively, the L8576B SLIC can be used in a battery-backed, unbalanced ringing application. In this case, the ring signal is generated by a central ring generator and is bused to individual tip/ring pairs. A ringing relay is used during ringing to disconnect the L8576B from, and apply the ring generator to, the tip and ring pair. This section discusses in detail the use of the L8576B in the balanced mode of operation. –60 –80 0.00 0.04 0.08 0.12 0.16 0.20 0.02 0.06 0.10 0.14 0.18 TIME (s) 12-3346a (F) Notes: Slew rate = 5.65 V/ms. trise = tfall = 23 ms. pwidth = 2 ms. period = 50 ms. Figure 18. Ringing Waveform Crest Factor = 1.6 Crest Factor 80 18 60 VOLTS (V) The balanced ring signal is generated by simply toggling between the powerup forward and reverse battery states. The state change is done by applying a square wave (whose frequency is the desired ring frequency) to logic input B2. Capacitors CF1 and CF2 and resistor RRNG are used to control or ramp the speed of the transition of the battery reverse, thus shaping the balanced ring signal. Setting capacitor CF1 = CF2 = 0.22 µF and setting RRNG to 28.7 kΩ provides a crest factor of 1.3 for a 20 Hz ring frequency. This satisfies the Telcordia* GR-909 requirement of ringing waveform crest factor between 1.2 and 1.6. Crest factor is defined as the peak to rms voltage ratio of the ring signal. Ringing waveforms of crest factors 1.6 and 1.2 are shown in Figures 18 and 19. The crest factor can be adjusted by the value of RRNG and will be influenced slightly by the value of VBAT. The CF1 and CF2 capacitors should not be changed because these affect the dc feedback loop stability in current limit. An RRNG value of 22.6 kΩ will lower the crest factor to about 1.2 with a –65 V or –72 V battery for a 20 Hz ring frequency. Likewise, an RRNG value of 34.8 kΩ will raise the crest factor to about 1.4. For ring frequencies greater than 20 Hz, the RRNG value should be lowered until the desirable crest factor is achieved. Note the RRNG is common to both sections of the device. 40 20 0 –20 –40 –60 –80 0.00 0.04 0.08 0.12 0.16 0.20 0.02 0.06 0.10 0.14 0.18 TIME (s) 12-3347a (F) Notes: Slew rate = 10.83 V/ms. trise = tfall = 12 ms. pwidth = 13 ms. period = 50 ms. Figure 19. Ringing Waveform Crest Factor = 1.2 * Telcordia is a registered trademark of Telcordia Technologies, Inc. Agere Systems Inc. Data Sheet May 2001 Applications (continued) L8576B Dual Ringing SLIC To determine the low-pass pole: 1 f(Hz) = ----------------------------------------------2π ( R TFLT ) ( C RT ) Power Ringing (continued) Power Ringing Load Telcordia GR-909 specifies that a minimum 40 Vrms must be delivered to a 5 REN ringing load of 1386 Ω + 40 µF. For 5 REN load, it is recommended that VBAT be set to –68.5 Vdc. During the power ring state, the dc current limit is automatically boosted by a factor of 3.5 over the current limit set by resistor RPROG. Both of these factors are necessary to ensure delivery of 40 Vrms to the North American 5 REN ringing load of 1386 Ω + 40 µF. Ring Trip Ring trip is accomplished by filtering the voltage seen at node DCOUT and applying it to the integrated ring trip comparator. DCOUT is a voltage proportional to the tip/ ring current, and under short dc loop conditions, onhook ringing current and off-hook current provide sufficient voltage differential at DCOUT to distinguish that a ring trip condition has occurred. The ring trip comparator threshold is set via a resistor between the ring trip comparator and DCOUT. The output of NSTAT is automatically set to detect ring trip during the balanced ring mode. During quiet intervals of ringing, the output of NSTAT is automatically determined by the loop closure detector. Refer to Figure 2 for the following discussion. Capacitor CRT in conjunction with resistor RTFLT form a single-pole, low-pass filter that smooths the voltage seen at DCOUT. The pole of the filter will influence both the ripple seen at DCOUT and the speed of the transition of the voltage at DCOUT from the pretrip to the tripped level. Agere Systems Inc. Using the recommended 383 kΩ RTFLT resistor and the 0.1 µF CRT capacitor, the low-pass pole is set at 4.15 Hz. The loop current at ring trip is given by: R TTH ILOOP(TRIP) = 7.76 mA --------------- R GX2 Using the recommended 52.3 kΩ RTTH resistor and the 7.5 kΩ RGX2 resistor in a 20 Hz ringing application, the ring trip threshold current is set for 54 mA. Reference Design for ISDN TA Applications For a complete reference design, please refer to the POTS for ISDN, WLL, and FITL/FITH Applications, Featuring Ringing SLIC Solutions Application Note, which provides a detailed discussion of the reference design functionality. The design presented utilizes a dc to dc converter and requires only a +5 V and a +12 V supply to operate. The schematic in Figure 2 of this document portrays the SLIC and codec portions of that design. ac Design There are four key ac design parameters. Termination impedance is the impedance looking into the 2-wire port of the line card. It is set to match the impedance of the telephone loop in order to minimize signal reflections back to the telephone set. Transmit gain is measured from the 2-wire port to the PCM highway, while receive gain is measured from the PCM highway to the 2-wire port or telephone loop. Finally, the hybrid balance circuit cancels the unwanted amount of the received signal that appears at the transmit port. 19 Data Sheet May 2001 L8576B Dual Ringing SLIC Applications (continued) Transmit gain: V GSX G TX = --------------V T/R ac Design (continued) R X 125 G TX = ---------- × ----------R T2 Z T/R Example 1, Real Termination The following design equations refer to the circuit in Figure 20. Use these to synthesize real termination impedance. Hybrid balance: V G SX h bal = 20 log ----------- V T/R Termination impedance: V T/R To optimize the hybrid balance, the sum of the currents at the VFXIN input of the codec op amp should be set to 0. The following expressions assume the hybrid balance network is the same as the termination impedance: ---------– I T/R Zt = 1500 Z t = 2R P + ----------------------------------RT1 RT1 1 + --------- + -----------RGP RRCV RHB = Receive gain: GRCV = G RC V = V T/R VFRO ----------- RX G RC V × G T X -------------------------- RX h ba l = 20 log -------- RHB – G R C V × G TX 12 -----------------------------------------------------------------Zt R CV RRCV 1 + R + ------------ 1 + --------- ---------- RT1 RGP Z T/R RX GSX TG 1/2 L8576 SLIC 125 V/A AX ZT/R VS ZT RP PT IT/R + VT/R – RP PR RT2 VITR – – AV = 1 + AV = 6 + CURRENT SENSE RGX VFXIN – + RT1 RCVN RHB RRCV RCVP +2.4 V VFRO RGP + AV = –1 – 1/2 T8503 CODEC 12-2554.o (F) Figure 20. ac Equivalent Circuit Using a T8503 Codec 20 Agere Systems Inc. Data Sheet May 2001 L8576B Dual Ringing SLIC Applications (continued) RX/RT2: With other components set, the transmit gain (for complex and resistive terminations) RX and RT2 are varied to give specified transmit gain. ac Design (continued) Example 2, Complex Termination The gain shaping required of a complex termination impedance can be synthesized using the internal AX amplifier. The following discussion and equations present a method for selecting proper component values for the SLIC/codec interface when using a complex termination. Complex termination is usually of the form: R2 RT1/RRCV/RGP: For both complex and resistive terminations, the ratio of these resistors set the receive gain. For resistive terminations, the ratio of these resistors set the return loss characteristic. For complex terminations, the ratio of these resistors set the low-frequency return loss characteristic. CN/RN1/RN2: For complex terminations, these components provide high-frequency compensation to the return loss characteristic. For resistive terminations, these components are not used. RCVN is connected to ground via a resistor. RHB: Sets hybrid balance for all terminations. R1 Set ZTG — gain shaping: C 5-6396(F) To work with this application, convert termination to the form: R1´ R 2´ ZTG = RTGP || RTGS + CTGS which is a scaled version of ZT/R (the specified termination resistance) in the R1´ || R2´ + C´ form. RTGP must be 24.4 kΩ to set SLIC transconductance to 125 V/A. RTGP = 24.4 kΩ C´ 5-6397(F) where: At dc, CTGS and C´ are open. R1´ = R1 + R2 RTGP = M x R1´ R1 R2´ = ------- (R1 + R2) R2 where M is the scale factor. 2 R2 C´ = --------------------- C R1 + R2 For the following discussion, refer to Figure 21. RTGP/RTGS/CTGS (ZTG): These components give gain shaping to get good gain flatness. These components are a scaled version of the specified complex termination impedance. Note for pure (600 Ω) resistive terminations, components RTGS and CTGS are not used. Resistor RTGP is used and is the series resistance combination of RGX1 and RGX2 or 24.4 kΩ. Agere Systems Inc. 24.4 kΩ M = -----------------------R1′ It can be shown: RTGS = M x R2´ and CTGS = C′ -----M 21 Data Sheet May 2001 L8576B Dual Ringing SLIC Applications (continued) ac Design (continued) RTGS CTGS Rx RTGP = 24.4 kΩ –IT/R 195 RT2 – + AX VITR CODEC OP AMP CN RN1 RT1 RHB RCVN RRCV RCVP RN2 RGP CODEC OUTPUT DRIVE AMP 5-6400a(F) Figure 21. ac Interface Circuit Using First-Generation Codec (Blocking Capacitors Not Shown) Transmit Gain Transmit gain will be specified as a gain from T/R to PCM, TX (dB). Since PCM is referenced to 600 Ω and assumed to be 0 dB, and in the case of T/R being referenced to some complex impedance other than 600 Ω resistive, the effects of the impedance transformation must be taken into account. Again specified complex termination impedance at T/R is of the form: 600 ----------- represents the power loss/gain R EQ due to the impedance transformation. Note in the case of a 600 Ω pure resistive termination 600 ----------- = 20log R EQ 600 ---------- = 0. 600 at T/R 20log C Thus, there is no power loss/gain due to impedance transformation and TX (dB) = TX (specified[dB]). 5-6396(F) First calculate the equivalent resistance of this network at the midband frequency of 1000 Hz. REQ = Finally, convert TX (dB) to a ratio, GTX: TX (dB) = 20log GTX The ratio of RX/RT2 is used to set the transmit gain: 2 + R1 + 2 (---------------------------------------------------------------------------- + -------------------------------------------------- 1 + ( 2 πf ) 2 R 2 2 C 1 2 1 + ( 2 πf ) 2 R 2 2 C 1 2 πf R 2 2 C 1 R 2 2 2 Using REQ, calculate the desired transmit gain, taking into account the impedance transformation: TX (dB) = TX (specified[dB]) + 20log 22 the T/R. 20log R2 R1 πf ) 2 C 1 2 R 1 R 2 2 TX (specified[dB]) is the specified transmit gain. 600 Ω is the impedance at the PCM and R EQ is the impedance at 600 ----------R EQ RX R T2 195 M ---------- = GTX x ---------- with a dual Agere codec such as T8503 RX < 200 kΩ Agere Systems Inc. Data Sheet May 2001 L8576B Dual Ringing SLIC Applications (continued) ZTER(low) is the specified termination impedance assuming low frequency (C or C´ is open). ac Design (continued) RP is the series protection resistor. Receive Gain These two equations are best solved using a computer spreadsheet. Ratios of RRCV, RT1, RGP will set both the low-frequency termination and receive gain for the complex case. In the complex case, additional high-frequency compensation, via CN, RN1, and RN2, is needed for the return loss characteristic. For resistive termination, CN, RN1, and RN2 are not used and RCVN is tied to ground and a resistor. Next, solve for the high-frequency return loss compensation circuit, CN, RN1, and RN2: 2R P CN x RN2 = ------------- CTGS x RTGP 1500 1500 R TGS RN1 = RN2 ------------- -------------- – 1 2R P R TGP Determine the receive gain, GRCV, taking into account the impedance transformation in a manner similar to transmit gain. RX (dB) = RX (specified[dB]) + 20log There is an input offset voltage associated with nodes RCVN, RCVP. To minimize the effect of the mismatch of this voltage at T/R, the equivalent resistance to ac ground at RCVN should be approximately equal to that at RCVP. Refer to Figure 22 (schematic with dc blocking capacitors). To meet this requirement, RN2 = RGP || RT1. R EQ ----------600 RX (dB) = 20log GRCV Then: 6 GRCV = -----------------------------------------------R RCV R RCV 1 + --------------- + --------------R T1 R GP Hybrid Balance Set the hybrid cancellation via RHB. RX RHB = ---------------------------------G RCV × G TX and low-frequency termination 1500 ZTER(low) = -------------------------------------------- + 2RP R T1 R T1 1 + ------------ + --------------R GP R RCV RTGS If a +5 V only codec such as an Agere T8503 is used, dc blocking capacitors must be added as shown in Figure 22. This is because the codec is referenced to +2.5 V and the SLIC to ground. With the ac coupling, a dc bias at T/R is eliminated and power associated with this bias is not consumed. CTGS RX –IT/R 195 RTSP = 24.4 kΩ CB RT2 CC1 AX VITR – + CODEC OP AMP CN RN1 RT1 RN2 RGP RHB RCVN RCVP RRCV CC2 CODEC OUTPUT DRIVE AMP 5-8413 (F) Figure 22. ac Interface Circuit Using First-Generation Codec (Including Blocking Capacitors) Agere Systems Inc. 23 Data Sheet May 2001 L8576B Dual Ringing SLIC Applications (continued) ac Design (continued) Typically, values of 0.1 µF to 0.47 µF capacitors are used for dc blocking. The addition of blocking capacitors will cause a shift in the return loss and hybrid balance frequency response toward higher frequencies, degrading the lower-frequency response. The lower the value of the blocking capacitor, the more pronounced the effect is, but the cost of the capacitor is lower. It may be necessary to scale resistor values higher to compensate for the low-frequency response. This effect is best evaluated via simulation. A PSPICE * model for the L8576B is available. Design equation calculations seldom yield standard component values. Conversion from the calculated value to standard value may have an effect on the ac parameters. This effect should be evaluated and optimized via simulation. Use of an Auxiliary Battery Supply A second lower-voltage battery supply can be used with the L8576B in order to lower the overall power consumption on a short-loop design. For long loops, any power savings will be negated, since long loops are supplied by the main battery voltage. The auxiliary battery would be connected to pins 9 and 37 in lieu of the RPWR resistors. When the external RPWR resistors are removed, more power will be dissipated in the SLIC so internal SLIC power dissipation must be examined. First, determine the auxiliary battery voltage: The auxiliary battery should be set 8 V greater than the maximum tip/ring loop voltage on the longest allowed loop, when both channels are off-hook and in current limit. Aux Bat(MAX) = [(ILIM x RLOOP) + VOH] TOLVBAT Where: ILIM = dc current limit set by RPROG (usually 0.024). RLOOP = maximum loop resistance supported (telephone plus line resistance plus protection resistors). VOH = overhead voltage. TOLVBAT = battery tolerance, for a battery tolerance of ±5%, use 1.1. For example, using the recommended 24 mA current limit, an overhead voltage of 8 V, and a maximum loop length of 550 Ω, the maximum auxiliary battery voltage is 23.3 V. 24 Next, calculate the power dissipated in the SLIC: Components of the SLIC power dissipation are quiescent power of VCC and VBAT and loop current associated with VBAT and Aux Bat. These can be calculated as follows: WVCC(quiescent) = VCC x ICC(Max)(quiescent) x 2 channels. WVBAT(quiescent) = |VBAT(Max)| x IBAT(Max)(quiescent) x 2 channels. WVBAT(loop current) = (|VBAT(Max)| – 4 V) x 3 mA x 2 channels. WAux Bat(loop current) = (|Aux Bat(Max)| – 4 V) x (ILIM – 3 mA) x 2 channels. Where: 4 V is the minimum overhead voltage, and 3 mA is VBAT’s contribution to loop current. For example, substituting values from the data sheet: VCC = 5 V ICC(Max)(quiescent) = 5.5 mA VBAT(Max) = –70 V IBAT(Max)(quiescent) = 4 mA Aux Bat(Max) = –23.3 V ILIM = 24 mA The following powers are calculated: WVCC(quiescent) = 5 x 0.0055 x 2 = 0.055 WVBAT(quiescent) = |–70| x 0.004 x 2 = 0.56 WVBAT(loop current) = (|–70| – 4) x 0.003 x 2 = 0.396 WAux Bat(loop current) = (|–23.3| – 4) x (0.024 – 0.003) x 2 = 0.8106 The sum of the four powers is 1.822 W. Finally, calculate the maximum ambient temperature allowed for the calculated power dissipation: TA(max) = Tj – (RθJA x PDISS SLIC(max)) The L8576’s 44-pin PLCC exhibits a 43 °C/W thermal resistance if in an enclosure with natural airflow. The maximum operating temperature of the SLIC is 150 °C. Thermal shutdown occurs typically at 160 °C. For example: TA(max) = 150 – (43 x 1.822) = 150 – 78.4 = 71.7 °C The above scenario would allow operation up to 70 °C. * PSPICE is a registered trademark of Cadence Design Systems, Inc. Agere Systems Inc. Data Sheet May 2001 L8576B Dual Ringing SLIC Outline Diagram 44-Pin PLCC Dimensions are in millimeters. 17.65 MAX 16.66 MAX PIN #1 IDENTIFIER ZONE 6 1 40 7 39 16.66 MAX 17.65 MAX 29 17 18 28 4.57 MAX 1.27 TYP 0.53 MAX 0.51 MIN TYP SEATING PLANE 0.10 5-2506(F).r8 Agere Systems Inc. 25 Data Sheet May 2001 L8576B Dual Ringing SLIC Ordering Information Device Part No. LUCL8576BP-D LUCL8576BP-DT Description Dual SLIC Dual SLIC Package 44-Pin PLCC (Dry-bagged) 44-Pin PLCC (Tape and Reel, Dry-bagged) Comcode 108131285 108131293 For additional information, contact your Agere Systems Account Manager or the following: INTERNET: http://www.agere.com E-MAIL: [email protected] N. AMERICA: Agere Systems Inc., 555 Union Boulevard, Room 30L-15P-BA, Allentown, PA 18109-3286 1-800-372-2447, FAX 610-712-4106 (In CANADA: 1-800-553-2448, FAX 610-712-4106) ASIA PACIFIC: Agere Systems Singapore Pte. Ltd., 77 Science Park Drive, #03-18 Cintech III, Singapore 118256 Tel. (65) 778 8833, FAX (65) 777 7495 CHINA: Agere Systems (Shanghai) Co., Ltd., 33/F Jin Mao Tower, 88 Century Boulevard Pudong, Shanghai 200121 PRC Tel. (86) 21 50471212, FAX (86) 21 50472266 JAPAN: Agere Systems Japan Ltd., 7-18, Higashi-Gotanda 2-chome, Shinagawa-ku, Tokyo 141, Japan Tel. (81) 3 5421 1600, FAX (81) 3 5421 1700 EUROPE: Data Requests: DATALINE: Tel. (44) 7000 582 368, FAX (44) 1189 328 148 Technical Inquiries: GERMANY: (49) 89 95086 0 (Munich), UNITED KINGDOM: (44) 1344 865 900 (Ascot), FRANCE: (33) 1 40 83 68 00 (Paris), SWEDEN: (46) 8 594 607 00 (Stockholm), FINLAND: (358) 9 3507670 (Helsinki), ITALY: (39) 02 6608131 (Milan), SPAIN: (34) 1 807 1441 (Madrid) Agere Systems Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liab ility is assumed as a result of their use or application. Copyright © 2001 Agere Systems Inc. All Rights Reserved May 2001 DS01-199ALC (Replaces DS01-112ALC)