ICS8701I LOW SKEW ¸1, ¸2 Integrated Circuit Systems, Inc. CLOCK GENERATOR GENERAL DESCRIPTION FEATURES • 20 LVCMOS outputs, 7W typical output impedance The ICS8701I is a low skew, ÷1, ÷2 Clock Generator and a member of the HiPerClockS™ HiPerClockS™ family of High Performance Clock Solutions from ICS. The low impedance LVCMOS outputs are designed to drive 50W series or parallel terminated transmission lines. The effective fanout can be increased from 20 to 40 by utilizing the ability of the outputs to drive two series terminated lines. ,&6 • Output frequency up to 250MHz • 200ps bank skew, 250ps output skew, 300ps multiple frequency skew, 600ps part-to-part skew • LVCMOS / LVTTL clock input • LVCMOS control inputs The divide select inputs, DIV_SELx, control the output frequency of each bank. The outputs can be utilized in the ÷1, ÷2 or a combination of ÷1 and ÷2 modes. The bank enable inputs, BANK_EN0:1, support enabling and disabling each bank of outputs individually. The master reset input, nMR/ OE, resets the internal frequency dividers and also controls the active and high impedance states of all outputs. • Bank enable logic allows unused banks to be disabled in reduced fanout applications The ICS8701I is characterized at 3.3V and mixed 3.3V input supply, and 2.5V output supply operating modes. Guaranteed bank, output and part-to-part skew characteristics make the ICS8701I ideal for those clock distribution applications demanding well defined performance and repeatability. • -40°C to 85°C ambient operating temperature BLOCK DIAGRAM PIN ASSIGNMENT ¸1 1 ¸2 0 • 48 lead low-profile QFP (LQFP), 7mm x 7mm x 1.4mm package body, 0.5mm package lead pitch • Other divide values available on request GND QB2 GND QB3 VDDO QB4 QC0 VDDO QC1 GND QC2 GND LVCMOS_CLK • 3.3V or mixed 3.3V input, 2.5V output operating supply modes QAO - QA4 QC3 VDDO QC4 QD0 VDDO QD1 GND QD2 GND QD3 VDDO QD4 DIV_SELA 1 QB0 - QB4 0 DIV_SELB 1 QC0 - QC4 0 DIV_SELC 1 QD0 - QD4 0 ICS8701I QB1 VDDO QB0 QA4 VDDO QA3 GND QA2 GND QA1 VDDO QA0 DIV_SELA DIV_SELB LVCMOS_CLK GND VDDI BANK_EN0 GND BANK_EN1 VDDI nMR/OE DIV_SELC DIV_SELD DIV_SELD nMR/OE BANK_EN0 BANK_EN1 48 47 46 45 44 43 42 41 40 39 38 37 1 36 2 35 3 34 4 33 5 32 6 31 7 30 8 29 9 28 10 27 11 26 12 25 13 14 15 16 17 18 19 20 21 22 23 24 Bank Enable Logic 48-Pin LQFP Y Package Top View 8701I www.icst.com/products/hiperclocks.html 1 REV. A MARCH 16, 2001 ICS8701I LOW SKEW ¸1, ¸2 Integrated Circuit Systems, Inc. CLOCK GENERATOR TABLE 1. PIN DESCRIPTIONS Number 2, 5, 11, 26, 32, 35, 41, 44 7, 9, 18, 21, 28, 30, 37, 39, 46, 48 16, 20 25, 27, 29, 31, 33 34, 36, 38, 40, 42 43, 45, 47, 1, 3 4, 6, 8, 10, 12 22 13 DIV_SELD Input 14 DIV_SELC Input 23 DIV_SELB Input 24 DIV_SELA Input 17, 19 BANK_EN1, BANK_EN0 Input Pullup Enables and disables outputs by banks. LVCMOS interface levels. 15 nMR/OE Input Pullup Master reset and output enable. Enables and disables all outputs. LVCMOS interface levels. 8701I Name Type Description VDDO Power Output power supply. Connect to 3.3V or 2.5V. GND Power Ground. Connect to ground. VDDI QA0, QA1, QA2, QA3, QA4 QB0, QB1, QB2, QB3, QB4 QC0, QC1, QC2, QC3, QC4 QD0, QD1, QD2, QD3, QD4 LVCMOS_CLK Power Input power supply. Connect to 3.3V. Output Bank A outputs. LVCMOS interface levels. 7W typical output impedance. Output Bank B outputs. LVCMOS interface levels. 7W typical output impedance. Output Bank C outputs. LVCMOS interface levels. 7W typical output impedance. Output Bank D outputs. LVCMOS interface levels 7W typical output impedance. Input Pulldown Clock input. LVCMOS interface levels. Controls frequency division for bank D outputs. Pullup LVCMOS interface levels. Controls frequency division for bank C outputs. Pullup LVCMOS interface levels. Controls frequency division for bank B outputs. Pullup LVCMOS interface levels. Controls frequency division for bank A outputs. Pullup LVCMOS interface levels. www.icst.com/products/hiperclocks.html 2 REV. A MARCH 16, 2001 ICS8701I LOW SKEW ¸1, ¸2 Integrated Circuit Systems, Inc. CLOCK GENERATOR TABLE 2. PIN CHARACTERISTICS Symbol Parameter Test Conditions Minimum Typical RPULLUP LVCMOS_CLK D IV_SELA, DIV_SELB, Input D I V_SELC, DIV_SELD, Capacitance BANK_EN0, NMR/OE, BANK_EN1, Input Pullup Resistor 51 RPULLDOWN Input Pulldown Resistor 51 CIN CPD Power Dissipation Capacitance (per output) ROUT Maximum Units pF KW KW VDDI, VDDO = 3.465V VDDI = 3.465V, VDDO = 2.625V pF pF Output Impedance W 7 TABLE 3. FUNCTION TABLE Inputs Outputs nMR/OE BANK_EN1 BANK_EN0 DIV_SELx QA0 - QA4 QB0 - QB4 QC0 - QC4 QD0 - QD4 0 1 1 1 1 1 1 1 1 X 0 1 0 1 0 1 0 1 X 0 0 1 1 0 0 1 1 X 0 0 0 0 1 1 1 1 Hi Z Active Active Active Active Active Active Active Active Hi Z Hi Z Active Active Active Hi Z Active Active Active Hi Z Hi Z Hi Z Active Active Hi Z Hi Z Active Active Hi Z Hi Z Hi Z Hi Z Active Hi Z Hi Z Hi Z Active 8701I www.icst.com/products/hiperclocks.html 3 Qx frequency zero fIN/2 fIN/2 fIN/2 fIN/2 fIN fIN fIN fIN REV. A MARCH 16, 2001 ICS8701I LOW SKEW ¸1, ¸2 Integrated Circuit Systems, Inc. CLOCK GENERATOR ABSOLUTE MAXIMUM RATINGS Supply Voltage 4.6V Inputs -0.5V to VDD + 0.5V Outputs -0.5V to VDDO + 0.5V Ambient Operating Temperature -40°C to 85°C Storage Temperature -65°C to 150°C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of product at these condition or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDDI=VDDO=3.3V±5%, TA=-40°C TO 85°C Symbol VDDI VDDO Parameter Input Power Supply Voltage Output Power Supply Voltage Test Conditions IDD Quiescent Power Supply Current Minimum 3.135 3.135 Typical 3.3 3.3 VDDI = VIH = 3.465V VIL = 0V Maximum 3.465 3.465 Units V V 100 mA Maximum Units TABLE 4B. LVCMOS DC CHARACTERISTICS, VDDI=VDDO=3.3V±5%, TA=-40°C TO 85°C Symbol VIH VIL IIH IIL Parameter Input High Voltage Input Low Voltage Input High Current Input Low Current DIV_SELA, DIV_SELB, DIV_SELC, DIV_SELD, BANK_EN0, BANK_EN1, nMR/OE LVCMOS_CLK DIV_SELA, DIV_SELB, DIV_SELC, DIV_SELD, BANK_EN0, BANK_EN1, nMR/OE LVCMOS_CLK DIV_SELA, DIV_SELB, DIV_SELC, DIV_SELD, BANK_EN0, BANK_EN1, nMR/OE LVCMOS_CLK DIV_SELA, DIV_SELB, DIV_SELC, DIV_SELD, BANK_EN0, BANK_EN1, nMR/OE LVCMOS_CLK VOH Output High Voltage VOL Output Low Voltage 8701I Test Conditions Minimum Typical VDDI = 3.465V 2 3.8 V VDDI = 3.465V 2 3.8 V VDDI = 3.465V -0.3 0.8 V VDDI = 3.465V -0.3 1.3 V VDDI = VIN = 3.465V 5 µA VDDI = VIN = 3.465V 150 µA VDDI = 3.465V, VIN = 0V -150 µA VDDI = 3.465V, VIN = 0V VDDI = VDDO = 3.135V IOH = -36mA VDDI = VDDO = 3.135V IOL = 36mA -5 µA 2.6 V www.icst.com/products/hiperclocks.html 4 0.5 V REV. A MARCH 16, 2001 ICS8701I LOW SKEW ¸1, ¸2 Integrated Circuit Systems, Inc. CLOCK GENERATOR TABLE 5A. AC CHARACTERISTICS, VDDI=VDDO=3.3V±5%, TA=-40°C TO 85°C Symbol Parameter fMAX Maximum Input Frequency Propagation Delay, Low-to-High Propagation Delay, High-to-Low Bank Skew; NOTE 2 tpLH tpHL tsk(b) tsk(o) Test Conditions Minimum Typical Maximum Units 250 MHz 0MHZ £ f £ 200MHz 2.2 3.6 ns 0MHZ £ f £ 200MHz 2.2 3.6 ns Measured on rising edge at VDDO/2 200 ps Measured on rising edge at VDDO/2 250 ps Measured on rising edge at VDDO/2 300 ps tsk(pp) Output Skew; NOTE 3 Multiple Frequency Skew; NOTE 4 Par t to Par t Skew; NOTE 5 600 ps tR Output Rise Time; NOTE 6 30% to 70% 200 900 ps tF Output Fall Time; NOTE 6 30% to 70% Output Pulse Width 900 tCYCLE/2 + 0.6 3.1 ps tPW 200 tCYCLE/2 - 0.6 1.9 tsk(w) Measured on rising edge at VDDO/2 0MHZ £ f £ 200MHz tCYCLE/2 f = 200MHz 2.5 Output Enable Time; f = 10MHz 6 tEN NOTE 6 Output Disable Time; tDIS f = 10MHz 6 NOTE 6 NOTE 1: All parameters measured at 200MHz unless noted otherwise. All outputs terminated with 50W to VDDO/2. NOTE 2: Defined as skew within a bank of outputs at the same supply voltages and with equal load conditions. NOTE 3: Defined as skew across banks of outputs at the same supply voltages and with equal load conditions. NOTE 4: Defined as skew across banks of outputs operating at different frequency with the same supply voltages and equal load conditions. NOTE 5: Defined as the skew at different outputs on different devices operating at the same supply voltages and with equal load conditions. NOTE 6: These parameters are guaranteed by characterization. Not tested in production. 8701I www.icst.com/products/hiperclocks.html 5 ns ns ns ns REV. A MARCH 16, 2001 ICS8701I LOW SKEW ¸1, ¸2 Integrated Circuit Systems, Inc. CLOCK GENERATOR TABLE 4C. POWER SUPPLY DC CHARACTERISTICS, VDDI=3.3V±5%, VDDO=2.5V±5%, TA=-40°C TO 85°C Symbol VDDI VDDO Parameter Input Power Supply Voltage Output Power Supply Voltage Test Conditions IDD Quiescent Power Supply Current Minimum 3.135 2.375 Typical 3.3 2.5 VDDI = VIH = 3.465V VIL = 0V Maximum 3.465 2.625 Units V V 100 mA Maximum Units TABLE 4B. LVCMOS DC CHARACTERISTICS, VDDI=3.3V±5%, VDDO=2.5V±5%, TA=-40°C TO 85°C Symbol VIH VIL IIH IIL Parameter Input High Voltage Input Low Voltage Input High Current Input Low Current DIV_SELA, DIV_SELB, DIV_SELC, DIV_SELD, BANK_EN0, BANK_EN1, nMR/OE LVCMOS_CLK DIV_SELA, DIV_SELB, DIV_SELC, DIV_SELD, BANK_EN0, BANK_EN1, nMR/OE LVCMOS_CLK DIV_SELA, DIV_SELB, DIV_SELC, DIV_SELD, BANK_EN0, BANK_EN1, nMR/OE LVCMOS_CLK DIV_SELA, DIV_SELB, DIV_SELC, DIV_SELD, BANK_EN0, BANK_EN1, nMR/OE LVCMOS_CLK VOH Output High Voltage VOL Output Low Voltage 8701I Test Conditions Minimum Typical VDDI = 3.465V 2 3.8 V VDDI = 3.465V 2 3.8 V VDDI = 3.465V -0.3 0.8 V VDDI = 3.465V -0.3 1.3 V VIN = 3.465V 5 µA VIN = 3.465V 150 µA VIN = 0V -150 µA VIN = 0V VDDI = 3.135V, VDDO = 2.375V IOH = -27mA VDDI = 3.135V, VDDO = 2.375V IOH = 27mA -5 µA 1.8 V www.icst.com/products/hiperclocks.html 6 0.5 V REV. A MARCH 16, 2001 ICS8701I LOW SKEW ¸1, ¸2 Integrated Circuit Systems, Inc. CLOCK GENERATOR TABLE 5B. AC CHARACTERISTICS, VDDI=3.3V±5%, VDDO=2.5V±5%, TA=-40°C TO 85°C Symbol Parameter fMAX Maximum Input Frequency Propagation Delay, Low-to-High Propagation Delay, High-to-Low Bank Skew; NOTE 2 tpLH tpHL tsk(b) Test Conditions Minimum Typical Maximum Units 250 MHz 0MHZ £ f £ 200MHz 2.4 3.7 ns 0MHZ £ f £ 200MHz 2.4 3.7 ns Measured on rising edge at VDDO/2 225 ps Measured on rising edge at VDDO/2 250 ps Measured on rising edge at VDDO/2 300 ps tsk(pp) Output Skew; NOTE 3 Multiple Frequency Skew; NOTE 4 Par t to Par t Skew; NOTE 5 Measured on rising edge at VDDO/2 650 ps tR Output Rise Time; NOTE 6 30% to 70% 200 900 ps tF Output Fall Time; NOTE 6 30% to 70% Output Pulse Width 900 tCYCLE/2 + 0.6 3.1 ps tPW 200 tCYCLE/2 - 0.6 1.9 tsk(o) tsk(w) 0MHZ £ f £ 200MHz tCYCLE/2 f = 200MHz 2.5 Output Enable Time; f = 10MHz 6 tEN NOTE 6 Output Disable Time; tDIS f = 10MHz 6 NOTE 6 NOTE 1: All parameters measured at 200MHz unless noted otherwise. All outputs terminated with 50W to VDDO/2. NOTE 2: Defined as skew within a bank of outputs at the same supply voltages and with equal load conditions. NOTE 3: Defined as skew across banks of outputs at the same supply voltages and with equal load conditions. NOTE 4: Defined as skew across banks of outputs operating at different frequency with the same supply voltages and equal load conditions. NOTE 5: Defined as the skew at different outputs on different devices operating at the same supply voltages and with equal load conditions. NOTE 6: These parameters are guaranteed by characterization. Not tested in production. 8701I www.icst.com/products/hiperclocks.html 7 ns ns ns ns REV. A MARCH 16, 2001 ICS8701I LOW SKEW ¸1, ¸2 Integrated Circuit Systems, Inc. CLOCK GENERATOR FIGURE 1A, 1B - TIMING DIAGRAMS CLK Qx, ÷1 Qx, ÷2 FIGURE 1A - ACTIVE, ÷1, ÷2 nMR/OE CLK Qx, ÷1 Qx, ÷2 High Impedance Active FIGURE 1B - RESET TO ACTIVE, ÷1, ÷2 8701I www.icst.com/products/hiperclocks.html 8 REV. A MARCH 16, 2001 ICS8701I LOW SKEW ¸1, ¸2 Integrated Circuit Systems, Inc. CLOCK GENERATOR FIGURE 2A, 2B - TIMING WAVEFORMS CLK tPHL tPLH Q VDDO/2 FIGURE 2A - PROPAGATION DELAYS fin = 200MHz, Vamp = 3.3V, tr = tf = 600ps nMR/OE, BANK_ENx 3.3V BANK_ENx 0V tPHZ Q tPZH VOH VOH - 300mV VDDO/2 tPLZ tPZL VDDO/2 VOL + 300mV Q VOL FIGURE 2B - DISABLE AND ENABLE TIMES fin = 10MHz, Vamp = 3.3V, tr = tf = 600ps 8701I www.icst.com/products/hiperclocks.html 9 REV. A MARCH 16, 2001 ICS8701I LOW SKEW ¸1, ¸2 Integrated Circuit Systems, Inc. CLOCK GENERATOR FIGURE 3A, 3B - SKEW DEFINITIONS & WAVEFORMS Bank Skew - Skew between outputs within a bank. Outputs operating at the same temperature, supply voltages and with equal load conditions. CLK VDDO/2 VDDO/2 ○ ○ ○ ○ ○ ○ ○ ○ Qx0 tsk(b) tsk(b) Qx4 VDDO/2 VDDO/2 FIGURE 3A - BANK SKEW fin = 200MHz, Vamp = 3.3V, tr = tf = 200ps Output Skew - Skew between outputs of any bank. Outputs operating at the same temperature, supply voltages and with equal load conditions. CLK QA0 - QA4 VDDO/2 VDDO/2 tsk(o) tsk(o) QB0 - QB4 QC0 - QC4 QD0 - QD4 VDDO/2 VDDO/2 FIGURE 3B - OUTPUT SKEW fin = 200MHz, Vamp = 3.3V, tr = tf = 200ps 8701I www.icst.com/products/hiperclocks.html 10 REV. A MARCH 16, 2001 ICS8701I LOW SKEW ¸1, ¸2 Integrated Circuit Systems, Inc. CLOCK GENERATOR FIGURE 3C, 3D - SKEW DEFINITIONS & WAVEFORMS Multiple Frequency Skew - Skew between banks of outputs operating at different frequencies. Outputs operating at the same temperature, supply voltages and with equal load conditions. CLK QA0 - QA4, QB0 - QB4, QC0 - QC4, or QD0 - QD4 VDDO/2 VDDO/2 in ÷1 tsk(w) tsk(w) VDDO/2 QA0 - QA4, QB0 - QB4, QC0 - QC4, or QD0 - QD4 in ÷2 VDDO/2 FIGURE 3C - MULTIPLE FREQUENCY SKEW fin = 200MHz, Vamp = 3.3V, tr = tf = 200ps Part to Part Skew - Skew between outputs of any bank on different parts. Outputs operating at the same temperature, supply voltages and with equal load conditions. CLK VDDO/2 PART 1 QA0 - QA4 QB0 - QB4 QC0 - QC4 QD0 - QD4 VDDO/2 tsk(p) tsk(p) VDDO/2 PART 2 QA0 - QA4 QB0 - QB4 QC0 - QC4 QD0 - QD4 8701I VDDO/2 FIGURE 3B - OUTPUT SKEW fin = 200MHz, Vamp = 3.3V, tr = tf = 200ps www.icst.com/products/hiperclocks.html 11 REV. A MARCH 16, 2001 ICS8701I LOW SKEW ¸1, ¸2 Integrated Circuit Systems, Inc. CLOCK GENERATOR PACKAGE OUTLINE - Y SUFFIX D D2 θ 48 37 36 1 2 3 L E1 E E2 N 12 13 24 25 e A D1 A2 -Cccc C A1 SEATING PLANE c b TABLE 6. PACKAGE DIMENSIONS JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS BCC SYMBOL MINIMUM NOMINAL MAXIMUM 48 N 1.60 A A1 0.05 0.15 A2 1.35 1.40 1.45 b 0.17 0.22 0.27 c 0.09 0.20 D 9.00 BASIC D1 7.00 BASIC D2 5.50 E 9.00 BASIC E1 7.00 BASIC E2 5.50 e 0.5 BASIC L 0.45 q 0° 0.60 0.75 7° 0.08 ccc Reference Document: JEDEC Publication 95, MS-026 8701I www.icst.com/products/hiperclocks.html 12 REV. A MARCH 16, 2001 ICS8701I LOW SKEW ¸1, ¸2 Integrated Circuit Systems, Inc. CLOCK GENERATOR TABLE 7. ORDERING INFORMATION Part/Order Number Marking Package Count Temperature ICS8701CYI ICS8701CYI 48 Lead LQFP 250 per tray -40°C to 85°C ICS8701CYIT ICS8701CYI 48 Lead LQFP on Tape and Reel 2000 -40°C to 85°C While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 8701I www.icst.com/products/hiperclocks.html 13 REV. A MARCH 16, 2001