TI1 OPA2810IDCNT Dual high-performance, low-power, wide supply range, rail-to-rail input/output fet-input operational amplifier Datasheet

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OPA2810
SBOS789 – AUGUST 2017
1 Features
3 Description
•
The OPA2810 is a dual-channel, FET-input, voltagefeedback operational amplifier (op amp) with
extremely low input bias current. The OPA2810 is
unity-gain stable with a small-signal unity-gain
bandwidth of 120 MHz, and offers both excellent DC
precision and dynamic AC performance at very low
quiescent power. The OPA2810 is fabricated on
Texas Instrument's proprietary, high-speed SiGe
BiCMOS
process
and
achieves
significant
performance improvements over comparable FETinput amplifiers at similar levels of quiescent power.
With a gain-bandwidth product (GBWP) of 70 MHz,
extremely high slew-rate (240 V/µs), and very lownoise (5.7 nV/√Hz) the OPA2810 is ideal in a wide
range of data acquisition and signal processing
applications. It achieves these benchmark levels of
performance while consuming a typical quiescent
current (IQ) of 3.6 mA /channel.
1
•
•
•
•
•
•
•
•
•
•
•
•
High Speed: 70-MHz Gain-Bandwidth Product
120 MHz Small-Signal Bandwidth
High Slew Rate: 180 V/µs
Wide Supply Range: 4.75 V to 27 V
Low Noise:
– Input Voltage Noise: 5.7 nV/√Hz (f = 100 kHz)
– Input Current Noise: 0.7 fA/√Hz (f = 100 kHz)
Rail-to-Rail FET Input:
– Low Input Bias Current: 2 pA
Rail-to-Rail Output:
– High Linear Output Current: 50 mA
Low Input Offset: ±500 µV (Max)
Low Offset Drift: ±2 µV/°C (Typ)
Low Distortion: –95/–95dBc HD2/3 at 2 VPP, 1
MHz
High Common-Mode Rejection Ratio (CMRR):
100 dB
Low Power: 3.6 mA/Channel
Small Packaging: 8-Pin SOT-23 and VSSOP
Extended Temperature Operation:
–40°C to +125°C
2 Applications
•
•
•
•
•
•
•
Wideband Photodiode Amplifiers
High-Z Front-Ends
Impedance Measurements
Active Filters
Power Analyzers
Level Shifting and Buffering
Optoelectronic Drivers
The OPA2810 is characterized to operate over a wide
supply range of 4.75 V to 27 V, and features rail-torail inputs and outputs. The wide supply-range and
excellent dynamic performance of the OPA2810
device makes it well suited for a wide range of
applications,
such
as
wideband
photodiode
transimpedance amplifiers, test and measurement
front end buffers, active filters, impedance
measurement systems, power analyzers, as well as
general purpose gain and level-shifting stages. The
OPA2810 amplifier is capable of delivering 50 mA of
linear output current, and is therefore suitable for
driving optoelectronics components and buffering
DAC outputs into heavy loads.
The OPA2810 is available in an 8-pin, SOT23-8 and
VSSOP-8 package and is rated to work over the
extended industrial temperature range of –40°C to
+125°C.
Small-Signal Frequency Response vs Gain
Device Information(1)
PART NUMBER
24
G=+1
G=+2
G=+5
G=+10
G=+1 CL=35pF
21
18
GAIN (dB)
15
OPA2810
PACKAGE
BODY SIZE (NOM)
SOT-23 (8)
2.90 mm × 1.60 mm
VSSOP (8)
3.00 mm × 3.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
12
9
6
3
0
-3
-6
0.1
1
10
FREQUENCY (Hz)
100
1000
D001
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. ADVANCE INFORMATION for pre-production products; subject to
change without notice.
ADVANCE INFORMATION
OPA2810 Dual High-Performance, Low-Power, Wide Supply Range,
Rail-to-Rail Input/Output FET-Input Operational Amplifier
OPA2810
SBOS789 – AUGUST 2017
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Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
6.1
6.2
6.3
6.4
6.5
6.6
6.7
7
7.4 Device Functional Modes........................................ 16
1
1
1
2
3
4
8
Application and Implementation ........................ 17
8.1 Application Information............................................ 17
8.2 Typical Application ................................................. 19
9 Power Supply Recommendations...................... 20
10 Layout................................................................... 21
10.1 Layout Guidelines ................................................. 21
10.2 Layout Example .................................................... 22
10.3 Thermal Considerations ........................................ 22
Absolute Maximum Ratings ...................................... 4
ESD Ratings ............................................................ 4
Recommended Operating Conditions....................... 4
Thermal Information ................................................. 4
Electrical Characteristics: ±5 V ................................. 5
Electrical Characteristics: ±12 V ............................... 8
Electrical Characteristics: 5 V ................................. 11
11 Device and Documentation Support ................. 23
11.1
11.2
11.3
11.4
11.5
Detailed Description ............................................ 14
7.1 Overview ................................................................. 14
7.2 Functional Block Diagram ....................................... 14
7.3 Feature Description................................................. 15
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
23
23
23
23
23
12 Mechanical, Packaging, and Orderable
Information ........................................................... 23
ADVANCE INFORMATION
4 Revision History
2
DATE
REVISION
NOTES
August 2017
*
Initial release.
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5 Pin Configuration and Functions
DCN and DGK Packages
8-Pin SOT-23 and VSSOP Surface-Mount
Top View
OUT1
1
8
VS+
IN1-
2
7
OUT2
IN1+
3
6
IN2-
VS-
4
5
IN2+
Not to scale
Pin Functions
I/O (1)
DESCRIPTION
NAME
SOT-23-8
VSSOP-8
OUT1
1
1
O
Output of amplifier 1
IN1-
2
2
I
Inverting input of amplifier 1
IN1+
3
3
I
Noninverting input of amplifier 1
VS-
4
4
P
Negative power supply
IN2+
5
5
I
Noninverting input of amplifier 2
IN2-
6
6
I
Inverting input of amplifier 2
OUT2
7
7
O
Output of amplifier 2
VS+
8
8
P
Positive power supply
(1)
ADVANCE INFORMATION
PIN
I = input, O = output, and P = power.
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
Supply voltage (total bipolar supplies)
Internal power dissipation
MAX
UNIT
±14
V
See Thermal Information
Differential input voltage
VS-
VS+
V
Input voltage
VS-
VS+
V
150
°C
125
°C
Junction temperature, TJ
Storage temperature, Tstg
(1)
–65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
ADVANCE INFORMATION
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±2000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
VS
Total supply voltage
4.75
TA
Ambient temperature
–40
NOM
MAX
UNIT
27
V
25
125
°C
6.4 Thermal Information
OPA2810
THERMAL METRIC (1)
DCN (SOT-23)
DGK (VSSOP)
8 PINS
8 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
123.3
171
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
81.3
58.5
°C/W
RθJB
Junction-to-board thermal resistance
40.6
92.6
°C/W
ψJT
Junction-to-top characterization parameter
25.1
7.4
°C/W
ψJB
Junction-to-board characterization parameter
40.7
91.1
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
—
—
°C/W
(1)
4
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.5 Electrical Characteristics: ±5 V
at TA = 25°C, VS+ = 5 V, VS– = –5 V, G = 2, VCM = 0 V, RF = 1 kΩ, RL = 1 kΩ, and CL = 5 pF (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
TEST
LEVEL
AC PERFORMANCE
G = 1, VO = 200 mVPP, CL = 35 pF
SSBW
Small-signal bandwidth
Large-signal bandwidth
GBWP
Gain-bandwidth product
Bandwidth for 0.1-dB flatness
SR
Slew rate (10%-90%)
50
50
G = 5, VO = 200 mVPP
14
C
C
MHz
C
7
C
G = 100, VO = 200 mVPP
0.7
C
G = 2, VO = 2 VPP
30
G = 2, VO = 4 VPP
20
G=1
C
MHz
C
MHz
C
G = –1, VO = 5-V step
180
G = 1, VO = -4V to +1V
150
VO = 1-V step
C
12
180
Fall time
MHz
70
G = 2, VO = 5-V step
VO = 1-V step
C
V/µs
C
C
8
ns
C
8
ns
C
G = 1, 2-V step
40
G = 1, VO = –4 V to 1 V
70
ns
C
C
G = 2, 5V-step
200
G = 1, VO = –4 V to 1 V
300
G = 1, VO = –4 V to 1 V
3%
C
G = –1, 5-V step
3%
C
Input overdrive recovery
G = 1, (VS– – 1 V) to (VS+ + 1 V) input
200
ns
C
Output overdrive recovery
G = 2, (VS– – 1 V) / 2 to (VS+ + 1 V) / 2
input
100
ns
C
f = 1 MHz, RL = 1 kΩ, VO = 2 VPP
–92
C
f = 1 MHz, RL = 500 Ω, VO = 2 VPP
–92
C
f = 1 MHz, RL = 1 kΩ, VO = 8 VPP
–75
C
f = 1 MHz, RL = 500 Ω, VO = 8 VPP
–75
C
f = 5 MHz, RL = 1 kΩ, VO = 2 VPP
–67
C
f = 5 MHz, RL = 500 Ω, VO = 2 VPP
–67
f = 5 MHz, RL = 1 kΩ, VO = 8 VPP
–42
Settling time to 0.001%
Overshoot, undershoot
HD2
C
G = 2, VO = 200 mVPP
Rise time
Settling time to 0.1%
C
G = –1, VO = 200 mVPP
G = 10, VO = 200 mVPP
LSBW
90
120
Second-order harmonic distortion
ns
dBc
C
C
C
C
f = 5 MHz, RL = 500 Ω, VO = 8 VPP
–42
C
f = 100 kHz, RL = 1 kΩ, VO = 2 VPP
–105
C
f = 100 kHz, RL = 500 Ω, VO = 2 VPP
–105
C
f = 100 kHz, RL = 1 kΩ, VO = 8 VPP
–92
C
f = 100 kHz, RL = 500 Ω, VO = 8 VPP
–92
C
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ADVANCE INFORMATION
G = 1, VO = 200 mVPP
5
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Electrical Characteristics: ±5 V (continued)
at TA = 25°C, VS+ = 5 V, VS– = –5 V, G = 2, VCM = 0 V, RF = 1 kΩ, RL = 1 kΩ, and CL = 5 pF (unless otherwise noted)
PARAMETER
HD3
Third-order harmonic distortion
TEST CONDITIONS
MIN
ADVANCE INFORMATION
Input-referred voltage noise
MAX
UNIT
TEST
LEVEL
f = 1 MHz, RL = 1 kΩ, VO = 2 VPP
–92
C
f = 1 MHz, RL = 500 Ω, VO = 2 VPP
–90
C
f = 1 MHz, RL = 1 kΩ, VO = 8 VPP
–90
C
f = 1 MHz, RL = 500 Ω, VO = 8 VPP
–85
C
f = 5 MHz, RL = 1 kΩ, VO = 2 VPP
–60
C
f = 5 MHz, RL = 500 Ω, VO = 2 VPP
–59
f = 5 MHz, RL = 1 kΩ, VO = 8 VPP
–35
f = 5 MHz, RL = 500 Ω, VO = 8 VPP
–35
C
f = 100 kHz, RL = 1 kΩ, VO = 2 VPP
–115
C
f = 100 kHz, RL = 500 Ω, VO = 2 VPP
–115
C
f = 100 kHz, RL = 1 kΩ, VO = 8 VPP
–100
C
f = 100 kHz, RL = 500 Ω, VO = 8 VPP
–100
f = 100 kHz
en
TYP
dBc
C
C
C
5.7
nV/√Hz
C
f = 0.1 Hz to 10 Hz integrated, rms
TBD
µVrms
C
f = 0.1 Hz to 10 Hz integrated, peak-topeak
TBD
µVPP
C
in
Input-referred current noise
f = 100 kHz
0.7
fA/√Hz
C
zO
Close-loop output impedance
f = 100 kHz
0.1
Ω
C
110
dB
A
DC PERFORMANCE
AOL
Open-loop voltage gain
Input offset voltage
f = dc, VO = ±2.5 V
100
TA = 25°C, VCM = mid-supply, for
OPA810/2810
0.1
0.5
TA = 25°C, VCM = mid-supply, for
OPA811
0.05
0.1
TMIN – 125°C, for OPA810/2810
TMIN – 125°C, for OPA811
Input offset voltage drift
For OPA810/2810
For OPA811
TA = 25°C
Input bias current
Input offset current
TMIN – 85°C
2
20
1
60
TMIN – 125°C
CMRR
B
2
2
TMIN – 85°C
B
15
TA = 25°C
A
2
2
TMIN – 125°C
mV
0.5
0.3
120
A
µV/°C
pA
nA
pA
B
B
A
B
B
A
B
1
nA
B
100
dBc
A
Common-mode input impedance
1000 ||
2.5
GΩ ||
pF
C
Differential input impedance
1000 ||
0.5
GΩ ||
pF
C
Most positive input voltage
(VS+) +
0.3
V
A
Most negative input voltage
(VS–) –
0.3
V
A
(VS+) –
2.5
V
A
Common-mode rejection ratio
f = dc, TA = 25°C, VCM = –3 V to 1 V
90
INPUT
(VS+) –
3
Most positive JFET input voltage
OUTPUT
6
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Electrical Characteristics: ±5 V (continued)
at TA = 25°C, VS+ = 5 V, VS– = –5 V, G = 2, VCM = 0 V, RF = 1 kΩ, RL = 1 kΩ, and CL = 5 pF (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA = 25°C
VOCRH
VOCRL
Output voltage range high
ISC
Output short-circuit current
CLOAD
Capacitive load drive
(VS+) –
0.2
(VS+) –
0.1
(VS+) –
0.5
TA = 25°C
(VS–) +
0.2
TA = –40°C to +125°C
Linear output drive
TYP
TA = –40°C to +125°C
Output voltage range low
IO_max
MIN
MAX
40
TA = –40°C to +125°C
30
80
G = 1, 30% overshoot
TEST
LEVEL
A
V
C
(VS–) +
0.1
A
V
(VS–) +
0.5
VCM = mid-supply, pulling current until
VOS = 20 mV (TBD)
UNIT
C
50
mA
A
B
100
mA
A
50
pF
C
V
A
VS
IQ
Operating voltage
Quiescent current per channel
PSRR
TA = 25°C
4.75
TA = 25°C
27
3.5
TA = –40°C to +125°C
3.2
VS = ±2 V, VCM = –1 V
85
3.8
100
mA
ADVANCE INFORMATION
POWER SUPPLY
A
B
dB
A
°C
C
THERMAL CHARACTERISTICS
Specified operating temperature
range
–40
125
CHANNEL MATCHING (FOR DUAL OPA2810 ONLY)
Channel-to-channel crosstalk
Input offset voltage match
f = 10 kHz
–120
f = 1 MHz
–90
TA = 25°C
0.2
dBc
1
mV
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C
A
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6.6 Electrical Characteristics: ±12 V
at TA = 25°C, VS+ = 12 V, VS– = –12 V, G = 2, VCM = 0 V, RF = 1 kΩ, RL = 1 kΩ, and CL = 5 pF (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
TEST
LEVEL
AC PERFORMANCE
G = 1, VO = 200 mVPP
G = 1, VO = 200 mVPP, CL = TBD
SSBW
Small-signal bandwidth
Large-signal bandwidth
GBWP
Gain-bandwidth product
Bandwidth for 0.1-dB flatness
ADVANCE INFORMATION
SR
Slew rate (10%-90%)
50
50
G = 5, VO = 200 mVPP
14
C
C
MHz
C
7
C
G = 100, VO = 200 mVPP
0.7
C
G = 2, VO = 2 VPP
30
G = 2, VO = 10 VPP
20
G=1
C
MHz
C
MHz
C
G = –1, VO = 10-V step
170
G = 1, VO = 10-V step
170
VO = 1-V step
C
12
170
Fall time
MHz
70
G = 2, VO = 10-V step
VO = 1-V step
C
V/µs
C
C
8
ns
C
8
ns
C
G = 1, 2-V step
40
G = 1, 10-V step
70
G = 2, 10-V step
200
G = 1, 10-V step
300
G = 1, 10-V step
3%
C
G = –1, 10-V step
3%
C
Input overdrive recovery
G = 1, (VS– – 1 V) to (VS+ + 1 V) input
200
ns
C
Output overdrive recovery
G = 2, (VS– – 1 V) / 2 to (VS+ + 1 V) / 2
input
100
ns
C
f = 1 MHz, RL = 1 kΩ, VO = 2 VPP
–95
dBc
C
f = 1 MHz, RL = 500 Ω, VO = 2 VPP
–95
dBc
C
f = 1 MHz, RL = 1 kΩ, VO = 10 VPP
–80
dBc
C
f = 1 MHz, RL = 500 Ω, VO = 10 VPP
–80
dBc
C
f = 5 MHz, RL = 1 kΩ, VO = 2 VPP
–74
dBc
C
f = 5 MHz, RL = 500 Ω, VO = 2 VPP
–71
dBc
C
f = 5 MHz, RL = 1 kΩ, VO = 10 VPP
–53
dBc
C
f = 5 MHz, RL = 500 Ω, Vo = 10 VPP
–53
dBc
C
f = 100 kHz, RL = 1 kΩ, VO = 2 VPP
–115
dBc
C
f = 100 kHz, RL = 500 Ω, VO = 2 VPP
–115
dBc
C
f = 100 kHz, RL = 1 kΩ, VO = 10 VPP
–97
dBc
C
f = 100 kHz, RL = 500 Ω, VO = 10 VPP
–97
dBc
C
Settling time to 0.001%
Overshoot, undershoot
8
C
G = 2, VO = 200 mVPP
Rise time
Settling time to 0.1%
HD2
C
G = –1, VO = 200 mVPP
G = 10, VO = 200 mVPP
LSBW
90
120
Second-order harmonic distortion
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ns
ns
C
C
C
C
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Electrical Characteristics: ±12 V (continued)
PARAMETER
HD3
Third-order harmonic distortion
TEST CONDITIONS
MIN
Input-referred voltage noise
MAX
UNIT
TEST
LEVEL
f = 1 MHz, RL = 1 kΩ, VO = 2 VPP
–95
dBc
C
f = 1 MHz, RL = 500 Ω, VO = 2 VPP
–92
dBc
C
f = 1 MHz, RL = 1 kΩ, VO = 10 VPP
–90
dBc
C
f = 1 MHz, RL = 500 Ω, VO = 10 VPP
–85
dBc
C
f = 5 MHz, RL = 1 kΩ, VO = 2 VPP
–60
dBc
C
f = 5 MHz, RL = 500 Ω, VO = 2 VPP
–59
dBc
C
f = 5 MHz, RL = 1 kΩ, VO = 10 VPP
–35
dBc
C
f = 5 MHz, RL = 500 Ω, VO = 10 VPP
–35
dBc
C
f = 100 kHz, RL = 1 kΩ, VO = 2 VPP
–115
dBc
C
f = 100 kHz, RL = 500 Ω, VO = 2 VPP
–115
dBc
C
f = 100 kHz, RL = 1 kΩ, VO = 10 VPP
–100
dBc
C
f = 100 kHz, RL = 500 Ω, VO = 10 VPP
–100
dBc
C
nV/√Hz
C
f = 100 kHz
en
TYP
5.7
f = 0.1 Hz to 10 Hz integrated, rms
TBD
µVrms
C
f = 0.1 Hz to 10 Hz integrated, peak-topeak
TBD
µVPP
C
in
Input-referred current noise
f = 100 kHz
0.7
fA/√Hz
C
zO
Closed-loop output impedance
f = 100 kHz
0.1
Ω
C
110
dB
A
ADVANCE INFORMATION
at TA = 25°C, VS+ = 12 V, VS– = –12 V, G = 2, VCM = 0 V, RF = 1 kΩ, RL = 1 kΩ, and CL = 5 pF (unless otherwise noted)
DC PERFORMANCE
AOL
Open-loop voltage gain
Input offset voltage
f = dc, VO = ±8 V
100
TA = 25°C, VCM = mid-supply, for
OPA810/2810
0.1
0.5
TA = 25°C, VCM = mid-supply, for
OPA811
0.05
0.1
TMIN – 125°C, for OPA810/2810
TMIN – 125°C, for OPA811
Input offset voltage drift
For OPA810/2810
For OPA811
TA = 25°C
Input bias current
Input offset current
TMIN – 85°C
2
20
1
60
TMIN – 125°C
CMRR
B
2
2
TMIN – 85°C
B
15
TA = 25°C
A
2
2
TMIN – 125°C
mV
0.5
0.3
120
A
µV/°C
pA
nA
pA
B
B
A
B
B
A
B
1
nA
B
100
dBc
A
Common-mode input impedance
1000 ||
2.5
GΩ ||
pF
C
Differential input impedance
1000 ||
0.5
GΩ ||
pF
C
Most positive input voltage
(VS+) +
0.3
V
A
Most negative input voltage
(VS–) –
0.3
V
A
(VS+) –
2.5
V
A
Common-mode rejection ratio
f = dc, TA = 25°C, VCM = ±5 V
90
INPUT
(VS+) –
3
Most positive JFET input voltage
OUTPUT
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Electrical Characteristics: ±12 V (continued)
at TA = 25°C, VS+ = 12 V, VS– = –12 V, G = 2, VCM = 0 V, RF = 1 kΩ, RL = 1 kΩ, and CL = 5 pF (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA = 25°C
VOCRH
VOCRL
Output voltage range high
ISC
Output short-circuit current
CLOAD
Capacitive load drive
(VS+) –
0.2
(VS+) –
0.1
(VS+) –
0.5
TA = 25°C
(VS–) +
0.2
TA = –40°C to +125°C
Linear output drive
TYP
TA = –40°C to +125°C
Output voltage range low
IO_max
MIN
MAX
40
TA = –40°C to +125°C
30
80
G = 1, 30% overshoot
TEST
LEVEL
A
V
C
(VS–) +
0.1
A
V
(VS–) +
0.5
VCM = mid-supply, pulling current until
VOS = 20 mV (TBD)
UNIT
C
50
mA
A
A
100
mA
A
50
pF
C
V
A
POWER SUPPLY
ADVANCE INFORMATION
VS
IQ
Operating voltage
Quiescent current per channel
PSRR
TA = 25°C
4.75
TA = 25°C
27
3.5
TA = –40°C to +125°C
3.2
VS = ±2 V
85
3.8
100
mA
A
B
dB
A
°C
C
THERMAL CHARACTERISTICS
Specified operating temperature
range
–40
125
CHANNEL MATCHING (FOR DUAL OPA2810 ONLY)
Channel-to-channel crosstalk
Input offset voltage match
10
f = 10 kHz
–120
f = 1 MHz
–90
TA = 25°C
0.5
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dBc
1.5
mV
C
C
A
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6.7 Electrical Characteristics: 5 V
at TA = 25°C, VS+ = 5 V, VS– = 0 V, G = 2, VCM = 1 V, RF = 1 kΩ, RL = 1 kΩ, CL = 5 pF (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
TEST
LEVEL
AC PERFORMANCE
SSBW
Small-signal bandwidth
90
C
G = 1, VO = 200 mVPP, CL = TBD
110
C
G = –1, VO = 200 mVPP, CL = TBD
50
G = 2, VO = 200 mVPP, CL = TBD
50
G = 5, VO = 200 mVPP
14
C
G = 10, VO = 200 mVPP
LSBW
Large-signal bandwidth
GBWP
Gain-bandwidth product
Bandwdith for 0.1dB flatness
SR
Slew rate (10%-90%)
C
7
C
G = 100, VO = 200 mVPP
0.7
C
G = 2, VO = 2 VPP
30
G = 2, VO = 2 VPP
25
G=1
MHz
C
C
70
MHz
C
20
MHz
C
G = 2, VO = 1 V to 3 V, VIN = 0.5 V to
1.5 V
120
G = –1, VO = 4-V step
170
G = 1, VO = 1 V to 2 V
90
C
V/µs
C
C
Rise time
VO = 1-V step
8
ns
C
Fall time
VO = 1-V step
8
ns
C
Settling time to 0.1%
G = 1, VO = 1 V to 2 V
40
G = 1, VO = 1 V to 2 V
40
ns
C
C
G = 2, VO = 1 V to 3 V, VIN = 0.5 V to
1.5 V
200
G = 1, VO = 1 V to 2 V
300
C
G = 1, VO = 1 V to 2 V
6%
C
G = –1, VO = 5-V step
6%
Input overdrive recovery
G = 1, (VS– – 1V) to (VS+ + 1 V) input
200
ns
C
Output overdrive recovery
G = 2, (VS– – 1V) / 2 to (VS+ + 1 V) / 2
input
100
ns
C
f = 1 MHz, RL = 1 kΩ, VCM = TBD, VO =
2 VPP
–72
C
f = 1MHz, RL = 500 Ω, VCM = TBD, VO
= 2 VPP
–72
C
f = 5 MHz, RL = 1 kΩ, VCM = TBD, VO =
2 VPP
–57
f = 5 MHz, RL = 500 Ω, VCM = TBD, VO
= 2 VPP
–57
C
f = 100 kHz, RL = 1 kΩ, VCM = TBD, VO
= 2 VPP
–92
C
f = 100 kHz, RL = 500 Ω, VCM = TBD,
VO = 2 VPP
–92
C
Settling time to 0.001%
Overshoot/undershoot
HD2
C
MHz
Second-order harmonic distortion
(VCM=1.25V)
ns
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dBc
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G = 1, VO = 200 mVPP
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Electrical Characteristics: 5 V (continued)
at TA = 25°C, VS+ = 5 V, VS– = 0 V, G = 2, VCM = 1 V, RF = 1 kΩ, RL = 1 kΩ, CL = 5 pF (unless otherwise noted)
PARAMETER
Third-order harmonic distortion
(VCM=1.25V)
HD3
TEST CONDITIONS
MIN
Input-referred voltage noise
MAX
UNIT
TEST
LEVEL
f = 1 MHz, RL = 1 kΩ, VCM = TBD, VO =
2 VPP
–92
C
f = 1 MHz, RL = 500 Ω, VCM = TBD, VO
= 2 VPP
–92
C
f = 5 MHz, RL = 1 kΩ, VCM = TBD, VO =
2 VPP
–65
f = 5 MHz, RL = 500 Ω, VCM = TBD, VO
= 2 VPP
–65
C
f = 100 kHz, RL = 1 kΩ, VCM = TBD, VO
= 2 VPP
–110
C
f = 100 kHz, RL = 500 Ω, VCM = TBD,
VO = 2 VPP
–110
C
C
dBc
f = 100 kHz
en
TYP
f = 0.1 Hz to 10 Hz integrated, rms
ADVANCE INFORMATION
f = 0.1 Hz to 10 Hz integrated, peak-topeak
5.7
nV/√Hz
C
0.45
µVrms
C
3
µVPP
C
in
Input-referred current noise
f = 100 kHz
0.7
fA/√Hz
C
zO
Close-loop output impedance
f = 100 kHz
0.1
Ω
C
110
dB
A
DC PERFORMANCE
AOL
Open-loop voltage gain
Input offset voltage
f = dc, VO = 1 V to 3 V
100
TA = 25°C, VCM = mid-supply, for
OPA810/2810
0.1
0.5
TA = 25°C, VCM = mid-supply, for
OPA811
0.05
0.1
TMIN – 125°C, for OPA810/2810
TMIN – 125°C, for OPA811
Input offset voltage drift
For OPA810/2810
2
For OPA811
TA = 25°C
Input bias current
TMIN – 85°C
TMIN – 125°C
TA = 25°C
Input offset current
CMRR
B
B
15
2
20
1
A
2
2
2
mV
0.5
0.3
120
A
µV/°C
pA
nA
pA
B
B
A
B
B
A
TMIN – 85°C
60
TMIN – 125°C
1
nA
B
100
dBc
A
Common-mode input impedance
1000 ||
2.5
GΩ ||
pF
C
Differential input impedance
1000 ||
0.5
GΩ ||
pF
C
Most positive input voltage
(VS+) +
0.3
V
A
Most negative input voltage
(VS–) –
0.3
V
A
(VS+) –
2.5
V
A
Common-mode rejection ratio
f = dc, TA = 25°C, VCM = 0.5 V to 1.5 V
90
B
INPUT
(VS+) –
3
Most positive JFET input voltage
OUTPUT
12
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Electrical Characteristics: 5 V (continued)
at TA = 25°C, VS+ = 5 V, VS– = 0 V, G = 2, VCM = 1 V, RF = 1 kΩ, RL = 1 kΩ, CL = 5 pF (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA = 25°C
VOCRH
VOCRL
Output voltage range high
ISC
Output short-circuit current
CLOAD
Capacitive load drive
(VS+) –
0.2
(VS+) –
0.1
(VS+) –
0.5
TA = 25°C
(VS–) +
0.2
TA = –40°C to +125°C
Linear output drive
TYP
TA = –40°C to +125°C
Output voltage range low
IO_max
MIN
MAX
40
TA = –40°C to +125°C
30
80
G = 1, 30% overshoot
TEST
LEVEL
A
V
C
(VS–) +
0.1
A
V
(VS–) +
0.5
VCM = 1 V, pulling current until VOS =
20 mV (TBD)
UNIT
C
50
mA
A
A
100
mA
A
50
pF
C
V
A
VS
IQ
Operating voltage
Quiescent current per channel
PSRR
TA = 25°C
4.75
TA = 25°C
27
3.5
TA = –40°C to +125°C
3.2
VS = ±0.5 V, VCM = 1 V
85
3.8
100
mA
ADVANCE INFORMATION
POWER SUPPLY
A
B
dB
A
°C
C
THERMAL CHARACTERISTICS
Specified operating temperature
range
–40
125
CHANNEL MATCHING (FOR DUAL OPA2810 ONLY)
Channel-to-channel crosstalk
Input offset voltage match
f = 10 kHz
–120
f = 1 MHz
–90
TA = 25°C
0.5
dBc
1.5
mV
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C
A
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7 Detailed Description
7.1 Overview
The OPA2810 is a dual-channel, FET-input, voltage-feedback operational amplifier with extremely low input bias
current. The OPA2810 is unity-gain stable with a small-signal unity-gain bandwidth of 120 MHz, and offers both
excellent DC precision and dynamic AC performance at very low quiescent power. The OPA2810 is fabricated on
Texas Instrument's proprietary, high-speed SiGe BiCMOS process and achieves significant performance
improvements over comparable FET-input amplifiers at similar levels of quiescent power. With a gain-bandwidth
product (GBWP) of 70MHz, extremely high slew-rate (240 V/µs), and very low-noise (5.7 nV/√Hz) the OPA2810
is ideal in a wide range of data acquisition and signal processing applications. It achieves these benchmark
levels of performance while consuming a typical quiescent current (IQ) of 3.6mA /channel.
The OPA2810 can source and sink large amounts of current without degrading its linearity performance. The
wide-bandwidth of the OPA2810 implies that it has very low output-impedance across a wide frequency range
thereby allowing the amplifier to drive capacitive loads up to 35 pF without the need for any output isolation.
7.2 Functional Block Diagram
ADVANCE INFORMATION
The OPA2810 is a classic voltage feedback op amp and each channel has two high-impedance inputs and a
low-impedance output. Standard application circuits are supported like the two basic options shown in Figure 1
and Figure 1. The DC operating point for each configuration is level-shifted by the reference voltage VREF which
is typically set to mid-supply in single-supply operation. VREF is often connected to ground in split-supply
applications.
VSIG
VS+
VREF
VIN
(1+RF/RG)VSIG
+
VOUT
VREF
±
RG
VS-
VREF
RF
Figure 1. Noninverting Amplifier
VS+
VREF
VSIG
VREF
-(RF/RG)VSIG
+
VOUT
VIN
RG
VREF
±
VSRF
Figure 2. Inverting Amplifier
14
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7.3 Feature Description
7.3.1 OPA2810 Comparison
Table 1 lists several members of the device family that includes the OPA2810.
Table 1. Related Operational Amplifier Products
VS± (V)
IQ / Channel
(mA)
GBWP
(MHz)
SLEW RATE
(V/μs)
VOLTAGE NOISE
(nV/√Hz)
OPA2810
±12
3.5
70
240
5.7
Unity-gain stable FET input (Dualchannel)
OPA810
±12
3.5
70
240
5.7
Unity-gain stable FET input (Single)
THS4631
±15
13
210
900
7
Unity-gain stable FET input
OPA656
±6
14
230
290
7
Unity-gain stable FET input
OPA657
±6
14
1600
700
4.8
Gain of 7 stable FET input
OPA659
±6
32
350
2550
8.9
Unity-gain stable FET input
DEVICE
AMPLIFIER DESCRIPTION
The OPA2810 is built using a very high-speed complementary bipolar process. The internal junction breakdown
voltages are relatively low for these very small geometry devices. These breakdowns are reflected in the
Absolute Maximum Ratings table. All device pins are protected with internal ESD protection diodes to the power
supplies as shown in Figure 3.
These diodes provide moderate protection to input overdrive voltages above the supplies as well. The protection
diodes can typically support 30-mA continuous current. Where higher currents are possible (for example, in
systems with ±12-V supply parts driving into the OPA2810), current limiting series resistors should be added into
the two inputs. Keep these resistor values as low as possible because high values degrade both noise
performance and frequency response.
VS+
Power Supply
ESD Cell
VIN(1,2)+
200 A
ICLAMP
+
±
VOUT(1,2)
VIN(1,2)-
VS-
Figure 3. Internal ESD Protection
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7.4 Device Functional Modes
7.4.1 Split-Supply Operation (±2.375 V to ±13.5 V)
To facilitate testing with common lab equipment, the OPA2810 may be configured to allow for split-supply
operation. This configuration eases lab testing because the mid-point between the power rails is ground, and
most signal generators, network analyzers, oscilloscopes, spectrum analyzers and other lab equipment reference
their inputs and outputs to ground. Figure 1 shows the OPA2810 configured as a noninverting amplifier while
Figure 1 shows the OPA2810 configured as an inverting amplifier. For split-supply operation referenced to
ground, the power supplies VS+ and VS- are symmetrical around ground and VREF = GND. Split-supply operation
is preferred in systems where the signals swing around ground because of its ease-of-use; however, it requires
the use of two supply rails.
7.4.2 Single-Supply Operation (4.75 V to 27 V)
ADVANCE INFORMATION
Many newer systems use a single power supply to improve efficiency and reduce the cost of the extra power
supply. The OPA2810 can be used with a single supply (negative supply set to ground) with no change in
performance, as long as the input and output are biased within the linear operation of the device. To change the
circuit from split supply to a balanced, single-supply configuration, level shift all the voltages by half the difference
between the power-supply rails. An additional advantage of configuring an amplifier for single-supply operation is
that the effects of PSRR are minimized because the low-supply rail has been grounded.
16
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
8.1.1 Noise Analysis and the Effect of Resistor Elements on Total Noise
The OPA2810 provides a very low input-referred broadband noise voltage density of 5.7 nV/√Hz while requiring a
low 7.2-mA quiescent supply current. To take full advantage of this low input noise, careful attention to the other
possible noise contributors is required. Figure 4 shows the operational amplifier noise analysis model with all the
noise terms included. In this model, all the noise terms are taken to be noise voltage or current density terms in
either nV/√Hz or pA/√Hz.
+
EO
IBN
RS
±
ERS
4kTR S
4kT
RF
RG
RG
4kTR F
IBI
4kT
1.6E 20 J
at 290q K
Figure 4. Operational Amplifier Noise Analysis Model
The total output spot noise voltage can be computed as the square root of the squared contributing terms to the
output noise voltage. This computation adds all the contributing noise powers at the output by superposition, then
calculates the square root to get back to a spot noise voltage. Figure 4 shows the general form for this output
noise voltage using the terms shown in Equation 1.
EO =
(E
2
NI
2
)
(
+ (IBNRS ) + 4kTRS NG2 + IBIRF
2
) + 4kTRFNG
(1)
Dividing this expression by the noise gain (NG = 1+RF/RG) gives the equivalent input referred spot noise voltage
at the noninverting input, see Equation 2.
2
4kTRF
æI R ö
2
EN = ENI2 + (IBNRS ) + 4kTRS + ç BI F ÷ +
NG
NG
è
ø
(2)
Substituting large resistor values into Equation 2 can quickly dominate the total equivalent input referred noise. A
source impedance on the noninverting input of 2 kΩadds a Johnson voltage noise term equal to just that of the
amplifier itself (5.7 nV/√Hz).
Table 2 compares the noise contributions from the various terms when the OPA2810 is configured in a
noninverting gain of 5V/V as shown in Figure 5. Two cases have been considered where the resistor values in
case 2 are 10x the resistor values in case 1. The total output noise In case 1 is 31.3 nV/√Hz while the noise is
case 2 is 49.7 nV/√Hz. The large value resistors in case 2 dilute the benefits of selecting a low noise amplifier
like the OPA2810. To minimize total system noise it is beneficial to reduce the size of the resistor values,
however this also increases the amplifiers output load and results in a degradation of its distortion performance.
The increased loading also increases the dynamic power consumption of the amplifier. The circuit designer
should make the appropriate tradeoffs to maximize the amplifiers overall performance to match the system
requirements.
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Application Information (continued)
VS+ = 5V
+
EO
Case1: 200
Case2: 2 k
RS
±
VS- = -5V
RG
Case1: 250
Case2: 2.5 k
RF
Case1: 1 k
Case2: 10 k
Figure 5. Comparing Noise Contributors for Two Cases With the Amplifier in a Noninverting Gain of 5
V/V
Table 2. Comparing Noise Contributions for the Circuit in Figure 5
Case1
Case2
ADVANCE INFORMATION
Noise
Source
Output
Noise
Equation
Source
resistor, RS
ERS
(1+RF/RG)
1.82
nV/√Hz
9.1
82.81
8.47
5.76
nV/√Hz
28.8
829.44
33.57
Gain resistor,
RG
ERG
(RF/RG)
2.04
nV/√Hz
8.16
66.59
6.81
6.44
nV/√Hz
25.76
663.58
26.86
Feedback
resistor, RF
ERF
4.07
nV/√Hz
4.07
16.57
1.69
12.87
nV/√Hz
12.87
165.64
6.70
Amplifier
voltage
noise, ENI
ENI
(1+RF/RG)
5.7
nV/√Hz
28.5
812.25
83.03
5.7
nV/√Hz
28.5
812.25
32.87
Inverting
current
noise, IBI
IBI
(RF||RG)
0.7
fA/√Hz
0.7E-3
-
-
0.7
fA/√Hz
7E-3
-
-
Noninverting
current
noise, IBN
IBNRS
(1+RF/RG)
0.7
fA/√Hz
0.14E-3
-
-
0.7
fA/√Hz
1.4E-3
-
18
Noise
Source
Value
Voltage
Noise Power
Noise
Contribution
Contribution
Contribution
(%)
2
(nV /Hz)
(nV/√Hz)
Noise
Source
Value
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Voltage
Noise Power
Noise
Contribution
Contribution
Contribution
(%)
2
(nV /Hz)
(nV/√Hz)
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8.2 Typical Application
The high GBP and low input voltage and current noise for the OPA2810 make it an ideal wideband
transimpedance amplifier for moderate to high transimpedance gains.
VBIAS
Supply Decoupling not
shown
+5 V
+
CPCB
0.3 pF
RS
50
Oscilloscope
with 50
Inputs
-5 V
RF
100 k
CF + CPCB
1.03 pF
Figure 6. Wideband, High-Sensitivity, Transimpedance Amplifier
8.2.1 Design Requirements
Design a high-bandwidth, high-gain transimpedance amplifier with the design requirements shown in Table 3.
Table 3. Design Requirements
TARGET BANDWIDTH (MHz)
TRANSIMPEDANCE GAIN (KΩ)
PHOTODIODE CAPACITANCE (pF)
>2
100
20
8.2.2 Detailed Design Procedure
Designs that require high bandwidth from a large area detector with relatively high transimpedance gain benefit
from the low input voltage noise of the OPA2810. This input voltage noise is peaked up over frequency by the
diode source capacitance, and can, in many cases, become the limiting factor to input sensitivity. The key
elements to the design are the expected diode capacitance (CD) with the reverse bias voltage (VBIAS) applied the
desired transimpedance gain, RF, and the GBP for the OPA2810 (70 MHz). Figure 6 shows a transimpedance
circuit with the parameters as described in Table 3. With these three variables set (and including the parasitic
input capacitance for the OPA2810 and the PCB added to CD), the feedback capacitor value (CF) may be set to
control the frequency response. To achieve a maximally-flat second-order Butterworth frequency response, set
the feedback pole to:
1
=
2pRFCF
GBP
4pRFCD
(3)
The input capacitance of the amplifier is the sum of its common-mode and differential capacitance (2.5+0.5) pF.
The parasitic capacitance from the photo-diode package and the PCB is approximately 0.3 pF. This results in a
total input capacitance, CD = 23.3 pF. From Equation 3, set the feedback pole at 1.55 MHz. Setting the pole at
1.55 MHz requires a total feedback capacitance of 1.03 pF
The approximate –3-dB bandwidth of the transimpedance amplifier circuit is given by:
f-3dB = GBP / (2pRFCD ) Hz
(4)
Equation 4 estimates a closed-loop bandwidth of 2.19 MHz.
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CD
20 pF
OPA2810
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If the total output noise of the TIA is band-limited to a frequency less than the feedback pole frequency, a very
simple expression for the equivalent output noise voltage can be derived as shown in Equation 5. The lowfrequency output noise of 45 nV/√Hz is dominated by the 100-kΩ feedback resistor and can be input-referred to
0.45 pA/√Hz. The transimpedance gain resistor is the dominant noise source at low frequencies. A JFET input
amplifier's current noise is negligible and can therefore be ignored. At the mid and high frequencies the
operational amplifiers voltage noise gets peaked up by the noise gain zero formed by RF and CD. The output
noise contribution at the mid and high frequencies is represented by the fourth term in Equation 5.
where
•
•
•
•
•
•
VOUTN = Equivalent output noise when band limited to F < 1 / (2 ΩRfCf)
IN = Input current noise for the operational amplifier inverting input
EN = Input voltage noise for the operational amplifier
CD = Diode capacitance including operational amplifier and PCB parasitic capacitance
F = Band-limiting frequency in Hz (usually a postfilter before further signal processing)
4 kT = 1.6 e – 20 J at T = 290°K
(5)
ADVANCE INFORMATION
9 Power Supply Recommendations
The OPA2810 is intended for operation on supplies ranging from 4.75-V to 27-V. The OPA2810 may be operated
on single-sided supplies, split and balanced bipolar supplies or unbalanced bipolar supplies. Operating from a
single supply can have numerous advantages. With the negative supply at ground, the DC errors due to the
–PSRR term can be minimized. Typically, AC performance improves slightly at 12-V operation with minimal
increase in supply current.
20
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10 Layout
Achieving optimum performance with a high-frequency amplifier like the OPA2810 requires careful attention to
board layout parasitics and external component types. Recommendations that optimize performance include:
1. Minimize parasitic capacitance to any AC ground for all of the signal I/O pins. Parasitic capacitance on the
output and inverting input pins can cause instability—on the noninverting input, it can react with the source
impedance to cause unintentional bandlimiting. To reduce unwanted capacitance, open a window around the
signal I/O pins in all of the ground and power planes around those pins. Otherwise, ground and power planes
must be unbroken elsewhere on the board.
2. Minimize the distance (< 0.25") from the power-supply pins to high-frequency 0.1-µF decoupling capacitors.
At the device pins, do not allow the ground and power plane layout to be in close proximity to the signal I/O
pins. Avoid narrow power and ground traces to minimize inductance between the pins and the decoupling
capacitors. The power-supply connections must always be decoupled with these capacitors. Larger (2.2-µF
to 6.8-µF) decoupling capacitors, effective at lower frequency, must also be used on the supply pins. These
can be placed somewhat farther from the device and shared among several devices in the same area of the
PC board.
3. Careful selection and placement of external components preserve the high frequency performance of
the OPA2810. Resistors must be a very low reactance type. Surface-mount resistors work best and allow a
tighter overall layout. Metal film and carbon composition axially leaded resistors can also provide good high
frequency performance. Again, keep their leads and PCB trace length as short as possible. Never use
wirewound type resistors in a high frequency application. Because the output pin and inverting input pin are
the most sensitive to parasitic capacitance, always position the feedback and series output resistor, if any, as
close as possible to the output pin. Other network components, such as noninverting input termination
resistors, must also be placed close to the package. Even with a low parasitic capacitance shunting the
external resistors, excessively high resistor values can create significant time constants that can degrade
performance. Good axial metal film or surface mount resistors have approximately 0.2 pF in shunt with the
resistor. For resistor values > 10 kΩ, this parasitic capacitance can add a pole or zero close to the
OPA2810s GBP of 70 MHz and subsequently affects circuit operation. Keep resistor values as low as
possible consistent with load driving considerations. Lowering the resistor values keep the resistor noise
terms low, and minimize the effect of its parasitic capacitance, however lower resistor values increase the
dynamic power consumption because RF and RG become part of the amplifiers output load network.
Transimpedance applications (see ) can use whatever feedback resistor is required by the application as
long as the feedback compensation capacitor is set considering all parasitic capacitance terms on the
inverting node.
4. Connections to other wideband devices on the board may be made with short direct traces or through
onboard transmission lines. For short connections, consider the trace and the input to the next device as a
lumped capacitive load. Relatively wide traces (50 mils to 100 mils) must be used, preferably with ground
and power planes opened up around them. Estimate the total capacitive load and set RS from the plot of
Recommended RS vs Capacitive Load. Low parasitic capacitive loads (< 35 pF) may not need an RS
because the OPA2810 is nominally compensated to operate with a 35-pF parasitic load. Higher parasitic
capacitive loads without an RS are allowed as the signal gain increases (increasing the unloaded phase
margin) If a long trace is required, and the 6-dB signal loss intrinsic to a doubly-terminated transmission line
is acceptable, implement a matched impedance transmission line using microstrip or stripline techniques
(consult an ECL design handbook for microstrip and stripline layout techniques). A 50-Ω environment is
normally not necessary onboard, and a higher impedance environment improves distortion. With a
characteristic board trace impedance defined based on board material and trace dimensions, a matching
series resistor into the trace from the output of the OPA2810 is used as well as a terminating shunt resistor
at the input of the destination device. Remember also that the terminating impedance is the parallel
combination of the shunt resistor and the input impedance of the destination device— this total effective
impedance must be set to match the trace impedance. If the 6-dB attenuation of a doubly-terminated
transmission line is unacceptable, a long trace can be series-terminated at the source end only. Treat the
trace as a capacitive load in this case and set the series resistor value as shown in the plot of
Recommended RS vs Capacitive Load. This does not preserve signal integrity as well as a doubly-terminated
line. If the input impedance of the destination device is low, the signal attenuates because of the voltage
divider formed by the series output into the terminating impedance.
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21
ADVANCE INFORMATION
10.1 Layout Guidelines
OPA2810
SBOS789 – AUGUST 2017
www.ti.com
Layout Guidelines (continued)
5. Socketing a high speed part like the OPA2810 is not recommended. The additional lead length and pinto-pin capacitance introduced by the socket can create an extremely troublesome parasitic network which
can make it almost impossible to achieve a smooth, stable frequency response. Best results are obtained by
soldering the OPA2810 onto the board.
10.2 Layout Example
VS+
Representative schematic of a
single channel
CBYP
RS
+
±
CBYP
VSRG
RF
Ground and power plane exist on
inner layers.
ADVANCE INFORMATION
Place series output resistors
close to output pin to minimize
parasitic capacitance
Ground and power plane removed
from inner layers. Ground fill on
outer layers also removed
CBYP
RS
1
8
2
7
3
6
RF
RS
RG
Place bypass capacitors
close to power pins
RF
RG
Place bypass capacitors
close to power pins
4
Place gain and feedback resistors
close to pins to minimize stray
capacitance
5
Remove GND and Power plane
under output and inverting pins to
minimize stray PCB capacitance
CBYP
Figure 7. Layout Recommendation
10.3 Thermal Considerations
The OPA2810 does not require heat sinking or airflow in most applications. Maximum allowed junction
temperature sets the maximum allowed internal power dissipation. Do not allow the maximum junction
temperature to exceed 150°C.
Operating junction temperature (TJ) is given by TA + PD × θJA. The total internal power dissipation (PD) is the sum
of quiescent power (PDQ) and additional power dissipated in the output stage (PDL) to deliver load power.
Quiescent power is simply the specified no-load supply current times the total supply voltage across the part. PDL
depends on the required output signal and load but would, for a grounded resistive load, be at a maximum when
the output is fixed at a voltage equal to 1/2 of either supply voltage (for equal bipolar supplies). Under this
condition PDL = VS 2/(4 × RL) where RL includes feedback network loading.
Note that it is the power in the output stage and not into the load that determines internal power dissipation.
As a worst-case example, compute the maximum TJ using an OPA2810-DGK (VSSOP package) configured as a
unity gain buffer, operating on ±12V supplies at an ambient temperature of +25°C and driving a grounded 200-Ω
load.
PD = 24 V × 7.2 mA + 122 /(4 × 200 Ω) = 353 mW
Maximum TJ = 25°C + (0.353 W × 171°C/W) = 85.4°C.
22
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OPA2810
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SBOS789 – AUGUST 2017
11 Device and Documentation Support
11.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
11.3 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
11.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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23
ADVANCE INFORMATION
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
PACKAGE OPTION ADDENDUM
www.ti.com
24-Jan-2018
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
OPA2810IDCNT
PREVIEW
SOT-23
DCN
8
250
TBD
Call TI
Call TI
-40 to 125
OPA2810IDGKR
PREVIEW
VSSOP
DGK
8
2500
TBD
Call TI
Call TI
-40 to 125
XOPA2810IDCNT
PREVIEW
SOT-23
DCN
8
250
TBD
Call TI
Call TI
-40 to 125
XOPA2810IDGKR
ACTIVE
VSSOP
DGK
8
2500
TBD
Call TI
Call TI
-40 to 125
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
24-Jan-2018
Addendum-Page 2
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