ALD ALD1722E Epadâ® low power cmos operational amplifier Datasheet

ADVANCED
LINEAR
DEVICES, INC.
TM
e
®
EPAD
D
LE
AB
EN
ALD1722E
EPAD® LOW POWER CMOS OPERATIONAL AMPLIFIER
KEY FEATURES
BENEFITS
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EPAD (Electrically Programmable Analog Device)
User programmable VOS trimmer
Computer-assisted trimming
Rail-to-rail input/output
Compatible with standard EPAD Programmer
High precision through in-system circuit precision trimming
Reduces or eliminates VOS, PSRR, CMRR and TCVOS errors
System level “calibration” capability
Application Specific Programming mode
In-System Programming mode
Electrically programmable to compensate for external
component tolerances
Achieves 0.01pA input bias current and 25µV input offset
voltage simultaneously
Compatible with industry standard pinout
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Eliminates manual system trimming
Drive up to 4000pF load capacitance
Remote controlled automated trimming
In-System Programming capable
Industry standard pinout
Rail-to-rail input/output
Input bias current of 0.01pA and
input offset voltage of 25µV
No external components
No internal chopper clocking noise
No chopper dynamic power dissipation
Simple and cost effective
Small package size
Low power
APPLICATIONS
GENERAL DESCRIPTION
The ALD1722E is a monolithic rail-to-rail precision CMOS operational
amplifier with integrated user programmable EPAD (Electrically Programmable Analog Device) based offset voltage adjustment. The ALD1722E
is a direct replacement of the ALD1712 operational amplifier, with the
added feature of user-programmable offset voltage trimming resulting in
significantly enhanced total system performance and user flexibility.
EPAD technology is an exclusive ALD design which has been refined for
analog applications where precision voltage trimming is necessary to
achieve a desired performance. It utilizes CMOS FETs as in-circuit
elements for trimming of offset voltage bias characteristics with the aid of
a personal computer under software control. Once programmed, the set
parameters are stored indefinitely within the device even after powerdown. EPAD offers the circuit designer a convenient and cost-effective
trimming solution for achieving the very highest amplifier/system performance.
The ALD1722E operational amplifier features rail-to-rail input and output
voltage ranges, tolerance to over-voltage input spikes of 300mV beyond
supply rails, high capacitive loading up to 4000pF, extremely low input
currents of 0.01pA typical, high open loop voltage gain, useful bandwidth
of 1.5MHz, slew rate of 2.1V/µs, and low supply current of 0.8mA.
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Sensor interface circuits
Unity gain buffer amplifier
Precision analog cable driver
Transducer biasing circuits
Capacitive and charge integration circuits
Biochemical probe interface
Signal conditioning
Portable instruments
High source impedance electrode
amplifiers
Precision Sample and Hold amplifiers
Precision current to voltage converter
Error correction circuits
Sensor compensation circuits
Precision gain amplifiers
Current sources
Periodic In-system calibration
System output level shifter
PIN CONFIGURATION
8
VE2
7
V+
3
6
OUT
4
5
N/C
VE1
1
-IN
2
+IN
V-
ORDERING INFORMATION (“L” suffix denotes lead-free (RoHS))
Operating Temperature Range
0°C to +70°C
0°C to +70°C
-55°C to +125°C
8-Pin
Small Outline
Package (SOIC)
8-Pin
Plastic Dip
Package
8-Pin
CERDIP
Package
ALD1722ESAL
ALD1722EPAL
ALD1722EDA
* Contact factory for leaded (non-RoHS) or high temperature versions.
2
TOP VIEW
SAL, PAL, DA PACKAGES
* N/C Pin is internally connected. Do not connect externally.
Rev 2.1 ©2011 Advanced Linear Devices, Inc. 415 Tasman Drive, Sunnyvale, CA 94089-1706 Tel: (408) 747-1155 Fax: (408) 747-1286
www.aldinc.com
FUNCTIONAL DESCRIPTION
USER PROGRAMMABLE VOS FEATURE
The ALD1722E uses EPADs as in-circuit elements for trimming of offset voltage bias characteristics. Each ALD1722E
has a pair of EPAD-based circuits connected such that one
circuit is used to adjust VOS in one direction and the other
circuit is used to adjust VOS in the other direction. While each
of the EPAD devices is a monotonically adjustable programmable device, the VOS of the ALD1722E can be adjusted
many times in both directions. Once programmed, the set
VOS levels are stored permanently, even when the device
power is removed.
Each ALD1722E has two pins named VE1 and VE2 which are
internally connected to an internal offset bias circuit. VE1/
VE2 have initial typical values of 1.6V. The voltage on these
pins can be programmed using the ALD E100 EPAD Programmer and the appropriate Adapter Module. The useful
programming range of VE1 and VE2 is 1.6V to 3.5V.
The ALD1722E is pre-programmed at the factory under
standard operating conditions for minimum equivalent input
offset voltage. It also has a guaranteed offset voltage
program range, which is ideal for applications that require
electrical offset voltage programming.
The ALD1722E is an operational amplifier that can be
trimmed with user application-specific programming or insystem programming conditions. User application-specific
circuit programming refers to the situation where the Total
Input Offset Voltage of the ALD1722E can be trimmed with
the actual intended operating conditions.
For example, an application circuit may have +6V and -2.5V
power supplies, and the operational amplifier input is biased
at +0.7V, and an average operating temperature at 55°C.
The circuit can be wired up to these conditions within an
environmental chamber with the ALD1722E inserted into a
test socket connected to this circuit while it is being electrically trimmed. Any error in VOS due to these bias conditions
can be automatically zeroed out. The Total VOS error is now
limited only by the adjustable range and the stability of VOS,
and the input noise voltage of the operational amplifier.
Therefore, this Total VOS error now includes VOS as VOS is
traditionally specified; plus the VOS error contributions from
PSRR, CMRR, TCVOS, and noise. Typically this total VOS
error term (VOST) is approximately ±25µV for the ALD1722E.
The VOS contribution due to PSRR, CMRR, TCVOS and
external components can be large for operational amplifiers
without trimming. Therefore the ALD1722E with EPAD trimming is able to provide much improved system performance
by reducing these other sources of error to provide significantly reduced VOST.
VE1 and VE2 pins are programming pins, used during
programming mode to inject charge into the internal EPADs.
Increasing voltage on VE1 decreases the offset voltage
whereas increasing voltage on VE2 increases the offset
voltage of the operational amplifier. The injected charge is
permanently stored and determines the offset voltage of the
operational amplifier. After programming, VE1 and VE2
terminals must be left open to settle on a voltage determined
by internal bias currents.
During programming, the voltages on VE1 or VE2 are increased incrementally to set the offset voltage of the operational amplifier to the desired Vos. Note that desired Vos can
be any value within the offset voltage programmable ranges,
and can be zero, a positive value or a negative value. This
VOS value can also be reprogrammed to a different value at
a later time, provided that the useful VE1 or VE2 programming voltage range has not been exceeded. VE1 or VE2 pins
can also serve as capacitively coupled input pins.
Internally, VE1 and VE2 are programmed and connected
differentially. Temperature drift effects between the two
internal offset bias circuits cancel each other and introduce
less net temperature drift coefficient change than offset
voltage trimming techniques such as offset adjustment with
an external trimmer potentiometer.
While programming, V+, VE1 and VE2 pins may be alternately pulsed with 12V (approximately) pulses generated by
the EPAD Programmer. In-system programming requires
the ALD1722E application circuit to accommodate these
programming pulses. This can be accomplished by adding
resistors at certain appropriate circuit nodes. For more
information, see Application Note AN1700.
In-System Programming refers to the condition where the
EPAD adjustment is made after the ALD1722E has been
inserted into a circuit board. In this case, the circuit design
must provide for the ALD1722E to operate in normal mode
and in programming mode. One of the benefits of in-system
programming is that not only is the ALD1722E offset voltage
from operating bias conditions accounted for, any residual
errors introduced by other circuit components, such as
resistor or sensor induced voltage errors, can also be corrected. In this way, the “in-system” circuit output can be
adjusted to a desired level, eliminating the need for another
trimming function.
ALD1722E
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2 of 13
ABSOLUTE MAXIMUM RATINGS
Supply voltage, V+
Differential input voltage range
Power dissipation
Operating temperature range SAL, PAL packages
DA package
Storage temperature range
Lead temperature, 10 seconds
CAUTION: ESD Sensitive Device. Use static control procedures in ESD controlled environment.
10.6V
-0.3V to V+ +0.3V
600 mW
0°C to +70°C
-55°C to +125°C
-65°C to +150°C
+260°C
OPERATING ELECTRICAL CHARACTERISTICS
TA = 25oC VS = ±2.5V unless otherwise specified
ALD1722E
Parameter
Symbol
Min
Supply Voltage
VS
V+
±2.0
4.0
1
Initial Input Offset Voltage
Offset Voltage Program Range
Programmed Input Offset
3
Voltage Error
Total Input Offset Voltage
Input Offset Current
Input Bias Current
4
5
5
Input Voltage Range
6
2
∆VOS
25
±5
±5.0
10.0
V
V
Single Supply
µV
RS ≤ 100KΩ
90
mV
50
µV
At user specified
target offset voltage
VOST
25
50
µV
At user specified
target offset voltage
IOS
0.01
10
280
pA
pA
TA = 25°C
0°C ≤ TA ≤ +70°C
IB
0.01
10
280
pA
pA
TA = 25°C
0°C ≤ TA ≤ +70°C
5.3
+2.8
V
V
V+ = +5V; notes 2,5
VS = ±2.5V
-0.3
-2.8
1014
Ω
µV/°C
RS ≤ 100KΩ
85
dB
RS ≤ 100KΩ
97
dB
RS ≤ 100KΩ
250
V/mV
500
V/mV
RL =10KΩ
RL ≥ 1MΩ
V
V
V
V
RL =1MΩ V+ = 5V
0°C ≤ TA ≤ +70°C
RL =10KΩ
0°C ≤ TA ≤ +70°C
5
PSRR i
Initial Common Mode
8
Rejection Ratio
CMRR i
Large Signal Voltage Gain
AV
Initial Power Supply
Test Conditions
±8
TCVOS
Rejection Ratio
Unit
25
RIN
7
Max
VOS
VIR
Input Resistance
Input Offset Voltage Drift
VOS i
Typ
8
Output Voltage Range
Output Short Circuit Current
VO low
VO high
VO low
VO high
50
4.99
2.35
ISC
0.002
4.998
-2.44
2.44
8
0.01
-2.35
mA
* NOTES 1 through 9, see "Definitions and Design Notes" on page 6.
ALD1722E
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OPERATING ELECTRICAL CHARACTERISTICS (cont'd)
TA = 25oC VS = ±2.5V unless otherwise specified
1722E
Parameter
Symbol
Supply Current
No Load
Min
Typ
Max
Unit
Test Conditions
IS
0.8
1.5
mA
VIN = 0V
Power Dissipation
PD
4.0
7.5
mW
VS = ±2.5V
Input Capacitance
CIN
Maximum Load Capacitance
1
pF
CL
400
4000
pF
pF
Gain = 1
Gain = 5
Input Noise Voltage
en
26
nV/√ Hz
f = 1KHz
Input Current Noise
in
0.6
fA/√ Hz
f =10Hz
Bandwidth
BW
1.0
1.5
MHz
Slew Rate
SR
1.4
2.1
V/µs
AV = +1
RL = 10KΩ
Rise time
tr
0.2
µs
RL = 10KΩ
10
%
RL = 10KΩ,
CL = 100pF
8.0
3.0
µs
µs
0.01%
0.1%
AV = -1, RL= 5KΩ
CL = 50pF
Unit
Test Conditions
Overshoot Factor
Settling Time
ts
TA = 25oC VS = ±2.5V unless otherwise specified
1722E
Parameter
Symbol
Average Long Term Input Offset
9
Voltage Stability
∆ VOS
∆ time
0.02
Initial VE Voltage
VE1 i
VE2 i
1.6
V
Programmable VE Range
∆VE1
∆VE2
2.0
V
VE Pin Leakage Current
ieb
-5
µA
ALD1722E
Min
1.5
Typ
Advanced Linear Devices
Max
µV/
1000 hrs
4 of 13
OPERATING ELECTRICAL CHARACTERISTICS (cont'd)
VS = ±2.5V -55°C ≤ TA ≤ +125°C unless otherwise specified
1722E
Parameter
Symbol
Min
Typ
Max
Initial Input Offset Voltage
VOS i
Input Offset Current
IOS
2.0
nA
Input Bias Current
IB
2.0
nA
Initial Power Supply
8
Rejection Ratio
PSRR i
85
dB
RS ≤ 100KΩ
Initial Common Mode
8
RejectionRatio
CMRR i
97
dB
RS ≤ 100KΩ
Large Signal Voltage Gain
AV
10
25
V/mV
RL ≤ 10KΩ
Output Voltage Range
VO low
VO high
-2.4
2.4
-2.3
V
V
RL ≤ 10KΩ
2.3
Max
Unit
Test Conditions
0.5
Unit
Test Conditions
mV
RS ≤ 100KΩ
TA = 25oC VS = ±5.0V unless otherwise specified
1722E
Parameter
Symbol
Min
Typ
Initial Power Supply
8
Rejection Ratio
PSRR i
85
dB
RS ≤ 100KΩ
Initial Common Mode
8
Rejection Ratio
CMRRi
97
dB
RS ≤ 100KΩ
Large Signal Voltage Gain
AV
V/mV
RL = 10KΩ
Output Voltage Range
VO low
VO high
V
RL = 10KΩ
250
4.80
-4.90
4.93
-4.80
Bandwidth
BW
1.7
MHz
Slew Rate
SR
2.8
V/µs
ALD1722E
Advanced Linear Devices
AV = +1,
CL = 50pF
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DEFINITIONS AND DESIGN NOTES:
ADDITIONAL DESIGN NOTES:
1. Initial Input Offset Voltage is the initial offset voltage of the
ALD1722E operational amplifier when shipped from the factory.
The device has been pre-programmed and tested for programmability.
A. The ALD1722E is internally compensated for unity gain
stability using a novel scheme which produces a single pole role
off in the gain characteristics while providing more than 70
degrees of phase margin at unity gain frequency. A unity gain
buffer using the ALD1722E will typically drive 400pF of external
load capacitance; in the inverting unity gain configuration, it can
drive up to 800pF of load capacitance. At a gain of 5, the
ALD1722E can drive up to 4000pF load capacitance, and is
ideally suited for high precision analog signal transmitted across
a cable or a wiring harness applications.
2. Offset Voltage Program Range is the range of adjustment of
user specified target offset voltage. This is typically an adjustment in either the positive or the negative direction of the input
offset voltage from an initial input offset voltage. The input offset
programming pins, VE1 or VE2, change the input offset voltage
in the negative or positive direction, respectively. User specified
target offset voltage can be any offset voltage within this programming range.
3. Programmed Input Offset Voltage Error is the final offset
voltage error after programming when the Input Offset Voltage
is at target Offset Voltage. This parameter is sample tested.
4. Total Input Offset Voltage is the same as Programmed Input
Offset Voltage, corrected for system offset voltage error. Usually this is an all inclusive system offset voltage, which also
includes offset voltage contributions from input offset voltage,
PSRR, CMRR, TCVOS and noise. It can also include errors
introduced by external components, at a system level. Programmed Input Offset Voltage and Total Input Offset Voltage is
not necessarily zero offset voltage, but an offset voltage set to
compensate for other system errors as well. This parameter is
sample tested.
5. The Input Offset and Bias Currents are essentially input
protection diode reverse bias leakage currents. This low input
bias current assures that the analog signal from the source will
not be distorted by it. For applications where source impedance
is very high, it may be necessary to limit noise and hum pickup
through proper shielding.
6. Input Voltage Range is determined by two parallel complementary input stages that are summed internally, each stage
having a separate input offset voltage. While Total Input Offset
Voltage can be trimmed to a desired target value, it is essential
to note that this trimming occurs at only one user selected input
bias voltage. Depending on the selected input bias voltage
relative to the power supply voltages, offset voltage trimming
may affect one or both input stages. For the ALD1722E, the
switching point between the two stages occurs at approximately
1.5V above negative supply voltage.
7. Input Offset Voltage Drift is the average change in Total Input
Offset Voltage as a function of ambient temperature. This
parameter is sample tested.
8. Initial PSRR and initial CMRR specifications are provided as
reference information. After programming, error contribution to
the offset voltage from PSRR and CMRR is set to zero under the
specific power supply and common mode conditions, and becomes part of the Programmed Input Offset Voltage Error.
9. Average Long Term Input Offset Voltage Stability is based on
input offset voltage shift through operating life test at 125°C
extrapolated to TA = 25°C, assuming activation energy of 1.0eV.
This parameter is sample tested.
ALD1722E
B. The ALD1722E has complementary p-channel and n-channel input differential stages connected in parallel to accomplish
rail to rail input common mode voltage range. The switching
point between the two differential stages is 1.5V above negative
supply voltage. For applications such as inverting amplifiers or
non-inverting amplifiers with a gain larger than 2.5 (5V operation), the common mode voltage does not make excursions
below this switching point.
C. The output stage consists of class AB complementary output
drivers. The oscillation resistant feature, combined with the railto-rail input and output feature, makes the ALD1722E an effective analog signal buffer for high source impedance sensors,
transducers, and other circuit networks.
D. The ALD1722E has static discharge protection. However,
care must be exercised when handling the device to avoid strong
static fields that may degrade a diode junction, causing increased input leakage currents. The user is advised to power up
the circuit before, or simultaneously with, any input voltages
applied and to limit input voltages not to exceed 0.3V of the
power supply voltage levels.
E. VE1 and VE2 are high impedance terminals, as the internal
bias currents are set very low to a few microamperes to conserve
power. For some applications, these terminals may need to be
shielded from external noise coupling sources. For example,
digital signals running nearby may cause unwanted offset voltage fluctuations. Care during the printed circuit board layout, to
place ground traces around these pins and to isolate them from
digital lines, will generally eliminate such coupling effects. In
addition, optional decoupling capacitors of 1000pF or greater
value can be added to VE1 and VE2 terminals.
F. The ALD1722E is designed for use in low voltage, low power
circuits. The maximum operating voltage during normal operation should remain below 10V at all times. Care should be taken
to insure that the application in which the device is used does not
experience any positive or negative transient voltages that
cause any of the terminal voltages to exceed this limit.
G. All inputs or unused pins except VE1 and VE2 pins should be
connected to a supply voltage such as Ground so that they do
not become floating pins, since input impedance at these pins is
very high. If any of these pins are left undefined, they may cause
unwanted oscillation or intermittent excessive current drain. As
these devices are built with CMOS technology, normal operating
and storage temperature limits, ESD and latchup handling
precautions pertaining to CMOS device handling should be
observed.
Advanced Linear Devices
6 of 13
TYPICAL PERFORMANCE CHARACTERISTICS
OPEN LOOP VOLTAGE GAIN AS A FUNCTION
OF SUPPLY VOLTAGE AND TEMPERATURE
COMMON MODE INPUT VOLTAGE RANGE
AS A FUNCTION OF SUPPLY VOLTAGE
1000
TA = 25°C
±6
OPEN LOOP VOLTAGE
GAIN (V/mV)
COMMON MODE INPUT
VOLTAGE RANGE (V)
±7
±5
±4
±3
±2
±1
} -55°C
} +25°C
100
} +125°C
10
RL= 10KΩ
RL= 5KΩ
0
±1
0
±2
±3
±4
±5
±6
1
±7
±2
0
SUPPLY VOLTAGE (V)
±4
±8
±6
SUPPLY VOLTAGE (V)
INPUT BIAS CURRENT AS A FUNCTION
OF AMBIENT TEMPERATURE
SUPPLY CURRENT AS A FUNCTION
OF SUPPLY VOLTAGE
2.5
VS = ±2.5V
100
SUPPLY CURRENT (mA)
INPUT BIAS CURRENT (pA)
1000
10
1.0
0.1
INPUTS GROUNDED
OUTPUT UNLOADED
2.0
1.5
1.0
TA = -55ºC
-25°C
0.5
+25°C
+80°C
+125°C
0
0.01
-50
-25
0
25
50
75
100
±1
0
125
±4
±5
±6
120
5
4
OPEN LOOP VOLTAGE
GAIN (dB)
VE2
3
2
1
0
-1
-2
-3
-4
VE1
-5
0
0.5
1.0
1.5
2.0
2.5
100
VS = ±2.5V
TA = 25°C
80
60
0
40
45
20
90
0
135
-20
180
3.0
1
10
100
1K
10K
100K
1M
PHASE SHIFT IN DEGREES
CHANGE IN INPUT OFFSET
VOLTAGE ∆VOS (mV)
±3
OPEN LOOP VOLTAGE AS A
FUNCTION OF FREQUENCY
ADJUSTMENT IN INPUT OFFSET VOLTAGE AS
A FUNCTION OF CHANGE IN VE1 AND VE2
10M
FREQUENCY (Hz)
CHANGE IN VE1 AND VE2 (V)
ALD1722E
±2
SUPPLY VOLTAGE (V)
AMBIENT TEMPERATURE (°C)
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TYPICAL PERFORMANCE CHARACTERISTICS (cont'd)
±7
OUTPUT VOLTAGE SWING (V)
LARGE - SIGNAL TRANSIENT
RESPONSE
OUTPUT VOLTAGE SWING AS A
FUNCTION OF SUPPLY VOLTAGE
5V/div
-55°C ≤ TA ≤ 125°C
±6
VS = ±2.5V
TA = 25°C
RL = 10KΩ
CL = 50pF
RL = 10KΩ
RL = 10KΩ
±5
±4
RL = 2KΩ
±3
2µs/div
1V/div
±2
0
±1
±2
±4
±3
±5
±6
±7
SUPPLY VOLTAGE (V)
OPEN LOOP VOLTAGE GAIN AS A
FUNCTION OF LOAD RESISTANCE
SMALL - SIGNAL TRANSIENT
RESPONSE
1000
VS = ±2.5V
TA = 25°C
RL = 10KΩ
CL = 50pF
OPEN LOOP VOLTAGE
GAIN (V/mV)
100mV/div
100
VS = ±2.5V
TA = 25°C
10
20mV/div
1
1K
10K
100K
2µs/div
1000K
LOAD RESISTANCE (Ω)
DISTRIBUTION OF TOTAL INPUT OFFSET VOLTAGE
BEFORE AND AFTER EPAD PROGRAMMING
PERCENTAGE OF UNITS (%)
100
80
EXAMPLE A:
VOST AFTER EPAD
PROGRAMMING
VOST TARGET = 0.0µV
EXAMPLE B:
VOST AFTER EPAD
PROGRAMMING
VOST TARGET = -750µV
60
VOST BEFORE EPAD
PROGRAMMING
40
20
0
-2500
-2000
-1500
-1000
-500
0
500
1000
1500
2000
2500
TOTAL INPUT OFFSET VOLTAGE (µV)
ALD1722E
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EQUIVALENT INPUT OFFSET VOLTAGE DUE TO
CHANGE IN SUPPLY VOLTAGE (µV)
TYPICAL PERFORMANCE CHARACTERISTICS (cont'd)
TWO EXAMPLES OF EQUIVALENT INPUT OFFSET VOLTAGE DUE TO
CHANGE IN SUPPLY VOLTAGE vs. SUPPLY VOLTAGE
500
PSRR = 80 dB
400
EXAMPLE A:
VOS EPAD PROGRAMMED
AT VSUPPLY = +5V
300
EXAMPLE B:
VOS EPAD
PROGRAMMED
AT VSUPPLY = +8V
200
100
0
1
0
2
3
4
6
5
7
8
9
10
EQUIVALENT INPUT OFFSET VOLTAGE DUE TO
CHANGE IN COMMON MODE VOLTAGE (µV)
SUPPLY VOLTAGE (V)
THREE EXAMPLES OF EQUIVALENT INPUT OFFSET VOLTAGE DUE TO
CHANGE IN COMMON MODE VOLTAGE vs. COMMON MODE VOLTAGE
500
VSUPPLY = ±5V
CMRR = 80dB
400
300
EXAMPLE B:
VOS EPAD
PROGRAMMED
AT VIN = -4.3V
200
EXAMPLE A:
VOS EPAD PROGRAMMED
AT VIN = 0V
100
EXAMPLE C:
VOS EPAD PROGRAMMED
AT VIN = +5V
0
-5
-4
-3
-2
-1
1
0
2
3
4
5
EQUIVALENT INPUT OFFSET VOLTAGE DUE TO
CHANGE IN COMMON MODE VOLTAGE (µV)
COMMON MODE VOLTAGE (V)
EXAMPLE OF MINIMIZING EQUIVALENT INPUT OFFSET VOLTAGE
FOR A COMMON MODE VOLTAGE RANGE OF 0.5V
50
COMMON MODE VOLTAGE RANGE OF 0.5V
40
30
VOS EPAD
PROGRAMMED
AT COMMON MODE
VOLTAGE OF 0.25V
20
CMRR = 80dB
10
0
-0.5
-0.4
-0.3
-0.2
-0.1
0.0
0.1
0.2
0.3
0.4
0.5
COMMON MODE VOLTAGE (V)
ALD1722E
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TYPICAL PERFORMANCE CHARACTERISTICS (cont'd)
APPLICATION SPECIFIC / IN-SYSTEM PROGRAMMING
2500
2500
2000
2000
1500
1500
1000
TOTAL INPUT OFFSET VOLTAGE (µV)
TOTAL INPUT OFFSET VOLTAGE (µV)
Examples of applications where accumulated total input offset voltage from various
contributing sources is minimized under different sets of user-specified operating conditions
VOS BUDGET AFTER
EPAD PROGRAMMING
500
0
-500
+
X
-1000
-1500
-2000
VOS BUDGET BEFORE
EPAD PROGRAMMING
1000
VOS BUDGET AFTER
EPAD PROGRAMMING
500
+
0
X
-500
-1000
-1500
VOS BUDGET BEFORE
EPAD PROGRAMMING
-2000
-2500
-2500
EXAMPLE B
2500
2500
2000
2000
1500
1500
1000
TOTAL INPUT OFFSET VOLTAGE (µV)
TOTAL INPUT OFFSET VOLGAGE (µV)
EXAMPLE A
VOS BUDGET BEFORE
EPAD PROGRAMMING
500
0
-500
-1000
+
X
-1500
-2000
-2500
VOS BUDGET AFTER
EPAD PROGRAMMING
1000
VOS BUDGET AFTER
EPAD PROGRAMMING
500
0
+
X
-500
-1000
-1500
-2000
VOS BUDGET BEFORE
EPAD PROGRAMMING
-2500
EXAMPLE C
EXAMPLE D
Device input VOS
PSRR equivalent VOS
+
Total Input VOS
after EPAD
Programming
CMRR equivalent VOS
TA equivalent VOS
X
Noise equivalent VOS
External Error equivalent VOS
ALD1722E
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SOIC-8 PACKAGE DRAWING
8 Pin Plastic SOIC Package
E
Millimeters
Dim
S (45°)
D
A
Min
1.35
Max
1.75
Min
0.053
Max
0.069
A1
0.10
0.25
0.004
0.010
b
0.35
0.45
0.014
0.018
C
0.18
0.25
0.007
0.010
D-8
4.69
5.00
0.185
0.196
E
3.50
4.05
0.140
0.160
1.27 BSC
e
A
A1
e
Inches
0.050 BSC
H
5.70
6.30
0.224
0.248
L
0.60
0.937
0.024
0.037
ø
0°
8°
0°
8°
S
0.25
0.50
0.010
0.020
b
S (45°)
H
L
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C
ø
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PDIP-8 PACKAGE DRAWING
8 Pin Plastic DIP Package
E
E1
Millimeters
D
S
A2
A1
e
b
b1
A
L
Inches
Dim
Min
Max
Min
Max
A
3.81
5.08
0.105
0.200
A1
0.38
1.27
0.015
0.050
A2
1.27
2.03
0.050
0.080
b
0.89
1.65
0.035
0.065
b1
0.38
0.51
0.015
0.020
c
0.20
0.30
0.008
0.012
D-8
9.40
11.68
0.370
0.460
E
5.59
7.11
0.220
0.280
E1
7.62
8.26
0.300
0.325
e
2.29
2.79
0.090
0.110
e1
L
7.37
7.87
0.290
0.310
2.79
3.81
0.110
0.150
S-8
1.02
2.03
0.040
0.080
0°
15°
0°
15°
ø
c
e1
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CERDIP-8 PACKAGE DRAWING
8 Pin CERDIP Package
E E1
Millimeters
D
A1
s
A
L
L2
b
b1
e
L1
Min
Inches
Dim
A
3.55
Max
5.08
Min
0.140
Max
0.200
A1
1.27
2.16
0.050
0.085
b
0.97
1.65
0.038
0.065
b1
0.36
0.58
0.014
0.023
C
0.20
0.38
0.008
0.015
D-8
--
10.29
--
0.405
E
5.59
7.87
0.220
0.310
E1
7.73
8.26
0.290
0.325
e
2.54 BSC
0.100 BSC
e1
7.62 BSC
0.300 BSC
L
3.81
5.08
0.150
0.200
L1
3.18
--
0.125
--
L2
0.38
1.78
0.015
0.070
S
--
2.49
--
0.098
Ø
0°
15°
0°
15°
C
e1
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ø
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