MC74AC125, MC74ACT125 Quad Buffer with 3−State Outputs Features • Outputs Source/Sink • ′ACT125 Has TTL Compatible Inputs • Pb−Free Packages are Available http://onsemi.com VCC A2 B2 O2 A3 B3 O3 14 13 12 11 10 9 8 PDIP−14 N SUFFIX CASE 646 14 1 SOIC−14 D SUFFIX CASE 751A 14 1 2 3 4 5 6 7 A0 B0 O0 A1 B1 O1 GND 1 Figure 1. Pinout: 14−Lead Packages Conductors (Top View) 14 1 TSSOP−14 DT SUFFIX CASE 948G PIN ASSIGNMENT PIN FUNCTION An, Bn Inputs On Outputs 14 1 SOEIAJ−14 M SUFFIX CASE 965 FUNCTION TABLE Inputs An Output Bn L L L H H X NOTE: H = High Voltage Level; L = Low Voltage Level; Z = High Impedance; X = Immaterial © Semiconductor Components Industries, LLC, 2006 October, 2006 − Rev. 7 ORDERING INFORMATION On See detailed ordering and shipping information in the package dimensions section on page 5 of this data sheet. L H Z DEVICE MARKING INFORMATION See general marking information in the device marking section on page 5 of this data sheet. 1 Publication Order Number: MC74AC125/D MC74AC125, MC74ACT125 MAXIMUM RATINGS Symbol Parameter Value Unit VCC DC Supply Voltage (Referenced to GND) −0.5 to +7.0 V Vin DC Input Voltage (Referenced to GND) −0.5 to VCC + 0.5 V Vout DC Output Voltage (Referenced to GND) −0.5 to VCC + 0.5 V Iin DC Input Current, per Pin ± 20 mA Iout DC Output Sink/Source Current, per Pin ± 50 mA ICC DC VCC or GND Current per Output Pin ± 50 mA Tstg Storage Temperature −65 to +150 °C Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. RECOMMENDED OPERATING CONDITIONS Symbol VCC Vin, Vout tr, tf Parameter Supply Voltage Min Typ Max ′AC 2.0 5.0 6.0 ′ACT 4.5 5.0 5.5 0 − VCC VCC @ 3.0 V − 150 − VCC @ 4.5 V − 40 − VCC @ 5.5 V − 25 − − − 140 °C −40 25 85 °C DC Input Voltage, Output Voltage (Ref. to GND) Input Rise and Fall Time (Note 1) ′AC Devices except Schmitt Inputs Unit V V ns/V TJ Junction Temperature (PDIP) TA Operating Ambient Temperature Range IOH Output Current − HIGH − − −24 mA IOL Output Current − LOW − − 24 mA 1. Vin from 30% to 70% VCC; see individual Data Sheets for devices that differ from the typical input rise and fall times. 2. Vin from 0.8 V to 2.0 V; see individual Data Sheets for devices that differ from the typical input rise and fall times. http://onsemi.com 2 MC74AC125, MC74ACT125 DC CHARACTERISTICS Symbol Parameter VIH Minimum High Level Input Voltage VIL Maximum Low Level Input Voltage VOH Minimum High Level Output Voltage VOL Minimum Low Level Output Voltage IIN Maximum Input Leakage Current IOZ VI (OE) = VIL, VIH VI = VCC, GND VO = VCC , GND †Minimum Dynamic Output Current IOLD IOHD ICC Maximum Quiescent Supply Current 74AC 74AC VCC (V) TA = +25°C TA = −40°C to +85°C 3.0 4.5 5.5 3.0 4.5 5.5 3.0 4.5 5.5 Typ 1.5 2.25 2.75 1.5 2.25 2.75 2.99 4.46 5.49 Guaranteed Limits 2.1 2.1 3.15 3.15 3.85 3.85 0.9 0.9 1.35 1.35 1.65 1.65 2.9 2.9 4.4 4.4 5.4 5.4 3.0 4.5 5.5 3.0 4.5 5.5 − − − 0.002 0.001 0.001 2.56 3.86 4.86 0.1 0.1 0.1 2.46 3.76 4.76 0.1 0.1 0.1 3.0 4.5 5.5 − − − 0.36 0.36 0.36 0.44 0.44 0.44 5.5 − ±0.1 ±1.0 mA 5.5 − ±0.5 ±5.0 mA 5.5 5.5 − − − − 75 −75 mA mA 5.5 − 8.0 80 mA Unit Conditions V VOUT = 0.1 V or VCC − 0.1 V V VOUT = 0.1 V or VCC − 0.1 V V V V V IOUT = − 50 mA *VIN = VIL or VIH −12 mA IOH − 24 mA − 24 mA IOUT = 50 mA *VIN = VIL or VIH 12 mA IOL 24 mA 24 mA VI = VCC, GND VI (OE) = VIL, VIH VI = VCC, GND VO = VCC, GND VOLD = 1.65 V Max VOHD = 3.85 V Min VIN = VCC or GND *All outputs loaded; thresholds on input associated with output under test. †Maximum test duration 2.0 ms, one input loaded at a time. NOTE: IIN and ICC @ 3.0 V are guaranteed to be less than or equal to the respective limit @ 5.5 V. AC CHARACTERISTICS Symbol VCC* (V) Parameter tPLH Propagation Delay Data to Output tPHL Propagation Delay Data to Output tPZH Output Enable Time tPZL Output Enable Time tPHZ Output Disable Time 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 Output Disable Time *Voltage Range 3.3 V is 3.3 V ±0.3 V. Voltage Range 5.0 V is 5.0 V ±0.5 V. tPLZ http://onsemi.com 3 74AC 74AC TA = +25°C CL = 50 pF TA = −40°C to +85°C CL = 50 pF Min 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 Min 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 Max 9.0 7.0 9.0 7.0 10.5 7.0 10 8.0 10 9.0 10.5 9.0 Max 10 7.5 10 7.5 11 8.0 11 8.5 10.5 9.5 11.5 9.5 Unit ns ns ns ns ns ns MC74AC125, MC74ACT125 DC CHARACTERISTICS Symbol Parameter 74ACT 74ACT VCC (V) TA = +25°C TA = −40°C to +85°C Typ 1.5 1.5 1.5 1.5 4.49 5.49 Guaranteed Limits 2.2 2.0 2.0 2.0 0.8 0.8 0.8 0.8 4.4 4.4 5.4 5.4 Unit VIH Minimum High Level Input Voltage VIL Maximum Low Level Input Voltage VOH Minimum High Level Output Voltage 4.5 5.5 4.5 5.5 4.5 5.5 − − 0.001 0.001 3.86 4.86 0.1 0.1 3.76 4.76 0.1 0.1 V Minimum Low Level Output Voltage 4.5 5.5 4.5 5.5 4.5 5.5 − − 0.36 0.36 0.44 0.44 V VOL V V V V Conditions VOUT = 0.1 V or VCC − 0.1 V VOUT = 0.1 V or VCC − 0.1 V IOUT = − 50 mA *VIN = VIL or VIH − 24 mA IOH − 24 mA IOUT = − 50 mA *VIN = VIL or VIH IOH − 24 mA − 24 mA VI = VCC, GND IIN Maximum Input Leakage Current 5.5 − ±0.1 ±1.0 mA IOZ VI (OE) = VIL, VIH VI = VCC, GND VO = VCC , GND 5.5 − ±0.5 ±5.0 mA VI (OE) = VIL, VIH VI = VCC, GND VO = VCC, GND DICCT Additional Max. ICC/Input 5.5 0.6 − 1.5 mA VI = VCC − 2.1 V IOLD †Minimum Dynamic Output Current 5.5 − − 75 mA VOLD = 1.65 V Max 5.5 − − −75 mA VOHD = 3.85 V Min 8.0 80 mA VIN = VCC or GND IOHD ICC Maximum Quiescent Supply Current 5.5 − *All outputs loaded; thresholds on input associated with output under test. †Maximum test duration 2.0 ms, one input loaded at a time. AC CHARACTERISTICS Symbol VCC* (V) Parameter 74ACT 74ACT TA = +25°C CL = 50 pF TA = −40°C to +85°C CL = 50 pF Unit Min Max Min Max 5.0 1.0 9.0 1.0 10 ns Propagation Delay Data to Output 5.0 1.0 9.0 1.0 10 ns tPZH Output Enable Time 5.0 1.0 8.5 1.0 9.5 ns tPZL Output Enable Time 5.0 1.0 9.5 1.0 10.5 ns tPHZ Output Disable Time 5.0 1.0 9.5 1.0 10.5 ns 5.0 1.0 10 1.0 10.5 ns tPLH Propagation Delay Data to Output tPHL Output Disable Time *Voltage Range 5.0 V is 5.0 V ±0.5 V. tPLZ CAPACITANCE Symbol Parameter Value Typ Unit Test Conditions CIN Input Capacitance 4.5 pF VCC = 5.0 V CPD Power Dissipation Capacitance 45 pF VCC = 5.0 V http://onsemi.com 4 MC74AC125, MC74ACT125 ORDERING INFORMATION Device Shipping † Package MC74AC125N PDIP−14 MC74AC125NG PDIP−14 (Pb−Free) MC74AC125D SOIC−14 MC74AC125DG SOIC−14 (Pb−Free) MC74AC125DR2 SOIC−14 MC74AC125DR2G SOIC−14 (Pb−Free) MC74AC125DTR2 TSSOP−14* MC74AC125DTR2G TSSOP−14* MC74AC125M SOEIAJ−14 MC74AC125MG SOEIAJ−14 (Pb−Free) MC74AC125MEL SOEIAJ−14 MC74AC125MELG SOEIAJ−14 (Pb−Free) MC74ACT125DR2 SOIC−14 MC74ACT125DR2G SOIC−14 (Pb−Free) MC74ACT125DTR2 TSSOP−14* MC74ACT125DTR2G TSSOP−14* MC74ACT125MEL SOEIAJ−14 MC74ACT125MELG SOEIAJ−14 (Pb−Free) MC74ACT125N PDIP−14 MC74ACT125NG PDIP−14 (Pb−Free) 25 Units / Rail 55 Units / Rail 2500 / Tape & Reel 50 Units / Rail 2000 / Tape & Reel 2500 / Tape & Reel 2000 / Tape & Reel 25 Units / Rail †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *This package is inherently Pb−Free. MARKING DIAGRAMS PDIP−14 SOIC−14 14 14 14 AC125G AWLYWW MC74AC125N AWLYYWWG 1 TSSOP−14 1 1 14 14 ACT125G AWLYWW 1 1 AC 125 ALYW 5 74AC125 ALYWG 1 14 ACT 125 ALYW A = Assembly Location L, WL = Wafer Lot Y, YY = Year W, WW = Work Week G or = Pb−Free Package (Note: Microdot may be in either location) http://onsemi.com SOEIAJ−14 14 74ACT125 ALYWG 1 MC74AC125, MC74ACT125 PACKAGE DIMENSIONS PDIP−14 CASE 646−06 ISSUE P 14 8 1 7 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. B A F L N C −T− SEATING PLANE H G D 14 PL J K 0.13 (0.005) M M http://onsemi.com 6 DIM A B C D F G H J K L M N INCHES MIN MAX 0.715 0.770 0.240 0.260 0.145 0.185 0.015 0.021 0.040 0.070 0.100 BSC 0.052 0.095 0.008 0.015 0.115 0.135 0.290 0.310 −−− 10 0.015 0.039 MILLIMETERS MIN MAX 18.16 19.56 6.10 6.60 3.69 4.69 0.38 0.53 1.02 1.78 2.54 BSC 1.32 2.41 0.20 0.38 2.92 3.43 7.37 7.87 −−− 10 0.38 1.01 MC74AC125, MC74ACT125 PACKAGE DIMENSIONS SOIC−14 CASE 751A−03 ISSUE H NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. −A− 14 8 −B− P 7 PL 0.25 (0.010) M 7 1 G −T− D 14 PL 0.25 (0.010) T B S A DIM A B C D F G J K M P R J M K M F R X 45 C SEATING PLANE B M S SOLDERING FOOTPRINT* 7X 7.04 14X 1.52 1 14X 0.58 1.27 PITCH DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 7 MILLIMETERS MIN MAX 8.55 8.75 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0 7 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.337 0.344 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0 7 0.228 0.244 0.010 0.019 MC74AC125, MC74ACT125 PACKAGE DIMENSIONS TSSOP−14 CASE 948G−01 ISSUE B 14X K REF 0.10 (0.004) 0.15 (0.006) T U M T U V S S N 2X 14 L/2 0.25 (0.010) 8 M B −U− L PIN 1 IDENT. N F 7 1 0.15 (0.006) T U NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE −W−. S S DETAIL E ÇÇÇ ÉÉÉ ÇÇÇ ÉÉÉ ÇÇÇ K A −V− K1 J J1 DIM A B C D F G H J J1 K K1 L M SECTION N−N −W− C 0.10 (0.004) −T− SEATING PLANE D H G DETAIL E SOLDERING FOOTPRINT* 7.06 1 0.65 PITCH 14X 0.36 14X 1.26 DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 8 MILLIMETERS MIN MAX 4.90 5.10 4.30 4.50 −−− 1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.50 0.60 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0 8 INCHES MIN MAX 0.193 0.200 0.169 0.177 −−− 0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.020 0.024 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0 8 MC74AC125, MC74ACT125 PACKAGE DIMENSIONS SOEIAJ−14 CASE 965−01 ISSUE A 14 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS AND ARE MEASURED AT THE PARTING LINE. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 5. THE LEAD WIDTH DIMENSION (b) DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE LEAD WIDTH DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSIONS AND ADJACENT LEAD TO BE 0.46 ( 0.018). LE 8 Q1 E HE M L 7 1 DETAIL P Z D VIEW P A e A1 b 0.13 (0.005) c M 0.10 (0.004) DIM A A1 b c D E e HE 0.50 LE M Q1 Z MILLIMETERS MIN MAX −−− 2.05 0.05 0.20 0.35 0.50 0.10 0.20 9.90 10.50 5.10 5.45 1.27 BSC 7.40 8.20 0.50 0.85 1.10 1.50 10 0 0.70 0.90 −−− 1.42 INCHES MIN MAX −−− 0.081 0.002 0.008 0.014 0.020 0.004 0.008 0.390 0.413 0.201 0.215 0.050 BSC 0.291 0.323 0.020 0.033 0.043 0.059 10 0 0.028 0.035 −−− 0.056 ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). 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