ON NCP51530AMNTWG High frequency high and low side driver Datasheet

NCP51530
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High Frequency, 700 V- 2 A
High and Low Side Driver
NCP51530 is a 700 V high side and low side driver with 2 A current
drive capability for AC−DC power supplies and inverters. NCP51530
offers best in class propagation delay, low quiescent current and low
switching current at high frequencies of operation. This device is
tailored for highly efficient power supplies operating at high
frequencies. NCP51530 is offered in two versions, NCP51530A/B.
NCP51530A has a typical 60 ns propagation delay, while NCP51530B
has a typical propagation delay of 25 ns. NCP51530 comes in SOIC8
and DFN10 packages.
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MARKING
DIAGRAMS
8
1
SOIC−8
D SUFFIX
CASE 751−07
NCP51530x
ALYW
G
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
High voltage range: Up to 700 V
NCP51530A: Typical 60 ns Propagation Delay
NCP51530B: Typical 25 ns Propagation Delay
Low Quiescent and Operating Currents
15 ns Rise and Fall Time
2.2 A/1.7 A Source/sink Currents
Under−voltage Lockout for Both Channels
3.3 V and 5 V Input Logic Compatible
High dv/dt Immunity up to 50 V/ns
Pin to Pin Compatible with Industry Standard Half−bridge ICs.
Matched Propagation Delay (7 ns Max)
High Negative Transient Immunity on Bridge Pin
DFN10 Package Offers Both Improved Creepage and Exposed Pad
1
51530x
ALYWG
G
DFN10
MN SUFFIX
CASE 506DJ
NCP5106
x
A
WL
YY
WW
G
= Specific Device Code
= A or B version
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
PINOUT INFORMATION
Applications
•
•
•
•
•
1
HIN
LIN
GND
LO
High−density SMPS for Servers, Telecom and Industrial
Half/Full−bridge & LLC Converters
Active Clamp Flyback/Forward Converters
Solar Inverters & Motor Controls
Electric Power Steering
VB
HO
HB
VCC
1
8 Pin Package
(Top View)
This document contains information on a product under development. ON Semiconductor
reserves the right to change or discontinue this product without notice.
VCC
HIN
LIN
GND
GND
1
VB
HO
HB
NC
LO
10 Pin DFN Package
(Top View)
ORDERING INFORMATION
See detailed ordering and shipping information on page 23 of
this data sheet.
© Semiconductor Components Industries, LLC, 2018
March, 2018 − Rev. P0
1
Publication Order Number:
NCP51530/D
NCP51530
HIN
VB
LIN
HO
GND
HB
LO
VCC
VCC
VB
HIN
HO
LIN
HB
GND
NC
GND
LO
SOIC8
(Top View)
DFN10
(Top View)
Table 1. PIN DESCRIPTION SOIC 8 PACKAGE
Pin Out
Name
Function
1
HIN
High side input
2
LIN
Low side input
3
GND
4
LO
5
VCC
6
HB
High side supply return
7
HO
High side output
8
VB
High side voltage supply
Ground reference
Low side output
Low side and logic supply
Table 2. PIN DESCRIPTION DFN10 PACKAGE
Pin Out
Name
Function
1
VCC
Low side and logic supply
2
HIN
High side input
3
LIN
Low side input
4
GND
Ground reference
5
GND
Ground reference
6
LO
Low side output
7
NC
No Connect
8
HB
High side supply return
9
HO
High side output
10
VB
High side voltage supply
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2
NCP51530
VHV
ADRV
LDRV
PWM CONTROLLER
COMP
HIN
VB
LIN
HO
NCP51530
GND
HB
LO
VCC
Figure 1. Simplified Applications Schematic for a Half−Bridge Converter (SOIC8)
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NCP51530
VHV
VCC
VB
HIN
HO
LIN
HB
GND
NC
GND
LO
VCC
HIN
LIN
GND
GND
VB
HO
HB
NC
LO
LIN 1
HIN 1
LIN 2
Micro Controller
Digital Isolator
HIN 2
Figure 2. Simplified Applications Schematic for a Full Bridge Converter (DFN 10)
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NCP51530
VCC
VB
UV
Detect
Pulse
Trigg er
HIN
Level
Shifter
S
Q
R
Q
HO
r
UV
DETECT
HB
VCC
LO
DELAY
LIN
r
GND
Figure 3. Internal Block Diagram for NCP51530
Table 3. ABSOLUTE MAXIMUM RATINGS All voltages are referenced to GND pin.
Rating
Symbol
Value
Unit
VCC
−0.3 to 19
V
High side boot pin voltage
VB
−0.3 to 720
V
High side floating voltage
VB−VHB
−0.3 to 20
V
VHO
VHB – 0.3 to VB + 0.3
V
Input voltage range
High side drive output voltage
Low side drive output voltage
Allowable hb slew rate
Drive input voltage
Junction temperature
Storage temperature range
ESD Capability (Note 1)
Human Body Model per JEDEC Standard JESD22−A114E.
Charge Device Model per JEDEC Standard JESD22−C101E.
VLO
−0.3 to VCC + 0.3
V
dVHB/dt
50
V/ns
VLIN,
VHIN
−5 to VCC + 0.3
V
TJ(MAX)
150°
C
TSTG
−55° to 150°
C
4000
1000
Lead Temperature Soldering
Reflow (SMD Styles ONLY), Pb−Free Versions (Note 2)
260
V
°C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. This device series incorporates ESD protection and is tested by the following methods. ESD Human Body Model tested per
AEC−Q100−002(EIA/JESD22−A114)
ESD Charged Device Model tested per AEC−Q100−11(EIA/JESD22−C101E)
Latchup Current Maximum Rating: ≤150 mA per JEDEC standard: JESD78
2. For information, please refer to our Soldering and Mounting Techniques Reference Manual, SOLDERRM/D
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NCP51530
Table 4. THERMAL CHARACTERSTICS
Rating
Symbol
Value
Unit
Thermal Characteristics, SOIC8 (Note 3)
Thermal Resistance, Junction to Air (Note 4)
RqJA
130
145
°C/W
Thermal Characteristics, DFN10
Thermal Resistance, Junction to Air
RqJA
45
72
°C/W
3. Refer to ELECTRICAL CHARACTERSTICS and APPLICATION INFORMATION for Safe Operating Area.
4. Values based on copper area of 645 mm2 (or 1 in2) of 1 oz thickness and FR4 PCB substrate.
Table 5. RECOMMENDED OPERATING CONDITIONS
Rating
Input Voltage Range
High Side Floating Voltage
Symbol
Min
Max
Unit
VCC
10
17
V
VB−VHB
10
17
V
High Side Bridge pin Voltage
VHB
−1
700
V
High Side Output Voltage
VHO
VHB
VB
V
High Side Output Voltage
VLO
GND
VCC
V
Input Voltage on LIN and HIN pins
VLIN,
VHIN
GND
VCC−2
V
TJ
−40
125
°C
Operating Junction Temperature Range
Table 6. ELECTRICAL CHARACTERISTICS
(−40°C <TJ < 125°C, VCC =VB =12V, VHB = GND, outputs are not loaded, all voltages are referenced to GND; unless otherwise noted,
Typical values are at TJ = 25°C.)
Parameters
Test Conditions
Symbol
Min
Typ
Max
Unit
SUPPLY SECTION
VCC quiescent current
VLIN=VHIN=0
ICCQ
0.15
0.25
mA
VCC operating current
f = 500 kHz, CLOAD = 0
ICCO
2
2.5
mA
Boot voltage quiescent current
VLIN = VHIN = 0 V
IBQ
0.1
0.15
mA
Boot voltage operating current
f = 500 kHz, CLOAD = 0
IBO
2
2.5
mA
HB to GND quiescent current
VHS = VHB = 700 V
IHBQ
6
11
mA
INPUT SECTION
Input rising threshold
VHIT
2.3
2.7
3.1
V
Input falling threshold
VLIT
1
1.4
1.8
V
Input voltage Hysteresis
Input pulldown resistance
VIHYS
1.3
V
VXIN= 5 V
RIN
100
175
250
kW
VCC Rising
VCCon
8.6
9.1
9.6
V
UNDER VOLTAGE LOCKOUT (UVLO)
VCC ON
VCC hysteresis
VB ON
VCChys
VB Rising
VBon
VB hysteresis
VBhyst
High Side Startup Time
Time between VB > UVLO &
HO Pulse
Low level output voltage
1st
0.5
8
8.5
V
9
0.5
V
V
Tstartup
10
ms
ILO = 100 mA
VLOL
0.250
V
High level output voltage
ILO = −100 mA, VLOH = VCC
−VLO
VLOH
0.270
V
Peak source current
VLO = 0 V
ILOpullup
2.2
A
Peak sink current
VLO = 12 V
ILOpulldown
1.7
A
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NCP51530
Table 6. ELECTRICAL CHARACTERISTICS
(−40°C <TJ < 125°C, VCC =VB =12V, VHB = GND, outputs are not loaded, all voltages are referenced to GND; unless otherwise noted,
Typical values are at TJ = 25°C.)
Parameters
Test Conditions
Symbol
Min
Typ
Max
Unit
HO GATE DRIVER
Low level output voltage
IHO = 100 mA
VHOL
0.250
V
High level output voltage
IHO = −100 mA, VHOH = VHB
–VHO
VHOH
0.270
V
Peak source current
VHO = 0 V
IHOpullup
2.2
A
Peak sink current
VHO = 12 V
IHOpulldown
1.7
A
OUTPUT RISE AND FALL TIME
Rise Time LO, HO
Cload = 1000 pF
TR
8
15
ns
Fall Time LO, HO
Cload = 1000 pF
TF
8
15
ns
DELAY MATCHING
LI ON, HI OFF
Pulse width = 1 ms
TMON
7
ns
LI OFF, HI ON
Pulse width = 1 ms
TMOFF
7
ns
TIMING
VXIN = 5 V , Input pulse width
above which output change occurs.
TFT
VLI falling to VLO falling
Cload = 0, Minimum On/Off−time
to register as a valid change =
50 ns
TDLFF
60
100
ns
VHI falling to VHO falling
Cload = 0, Minimum On/Off−time
to register as a valid change =
50 ns
TDHFF
60
100
ns
VLI rising to VLO rising
Cload = 0, Minimum On/Off−time
to register as a valid change =
50 ns
TDLRR
60
100
ns
VHI rising to VHO rising
Cload = 0, Minimum On/Off−time
to register as a valid change =
50 ns
TDHRR
60
100
ns
VLI falling to VLO falling
Cload = 0, Minimum On/Off−time
to register as a valid change =
50 ns
TDLFF
25
40
ns
VHI falling to VHO falling
Cload = 0, Minimum On/Off−time
to register as a valid change =
50 ns
TDHFF
25
40
ns
VLI rising to VLO rising
Cload = 0, Minimum On/Off−time
to register as a valid change =
50 ns
TDLRR
25
40
ns
VHI rising to VHO rising
Cload = 0, Minimum On/Off−time
to register as a valid change =
50 ns
TDHRR
25
40
ns
Minimum Input Filter (NCP51530A)
30
40
ns
PROPAGATION DELAY
NCP51530A
PROPAGATION DELAY
NCP51530B
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NCP51530
Figure 4. Propagation Delay, Rise and Fall Times
Figure 5. Delay Matching
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NCP51530
Figure 6. NCP51530 Operating Currents (No Load, VCC = 12V)
Figure 7. NCP51530 Operating Currents (1nF load, VCC = 12V)
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NCP51530
9.7
9.6
9.5
9.3
VCCOFF (V)
VCCON (V)
9.4
9.2
9.1
9
8.9
8.8
8.7
8.6
8.5
−40.0 −20.0 0.0
20.0 40.0 60.0 80.0 100.0 120.0 140.0
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 9. VCCOFF vs Temperature
1
9.2
9.1
9
0.8
8.9
8.8
0.7
VBON (V)
0.6
0.5
0.4
0.3
8.7
8.6
8.5
8.4
8.3
0.2
8.2
8.1
0.1
0
−40.0 −20.0 0.0
8
−40.0 −20.0 0.0
20.0 40.0 60.0 80.0 100.0 120.0 140.0
TEMPERATURE (°C)
Figure 11. VBON vs Temperature
1
0.9
0.8
0.7
VBHyst (V)
8.8
8.7
8.6
8.5
8.4
8.3
8.2
8.1
8
7.9
7.8
7.7
7.6
7.5
7.4
−40.0 −20.0 0.0
20.0 40.0 60.0 80.0 100.0 120.0 140.0
TEMPERATURE (°C)
Figure 10. VCCHyst vs Temperature
VBOFF (V)
20.0 40.0 60.0 80.0 100.0 120.0 140.0
Figure 8. VCCON vs Temperature
0.9
VHystON (V)
9.2
9.1
9
8.9
8.8
8.7
8.6
8.5
8.4
8.3
8.2
8.1
8
7.9
7.8
−40.0 −20.0 0.0
0.6
0.5
0.4
0.3
0.2
0.1
0
−40.0 −20.0 0.0 20.0 40.0 60.0 80.0 100.0 120.0 140.0
TEMPERATURE (°C)
20.0 40.0 60.0 80.0 100.0 120.0 140.0
TEMPERATURE (°C)
Figure 12. VBOff vs Temperature
Figure 13. VbHyst vs Temperature
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300
280
260
240
220
200
180
160
140
120
100
80
60
40
20
0
−40.0 −20.0 0.0 20.0 40.0 60.0 80.0 100.0 120.0 140.0
200
180
160
140
IBQ (mA)
ICCQ (mA)
NCP51530
80
40
20
0
−40.0 −20.0 0.0 20.0 40.0 60.0 80.0 100.0 120.0 140.0
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 14. ICCQ vs Temperature
Figure 15. IBQ vs Temperature
100
90
12
80
70
10
TDLFF (ns)
IHB_LEAK (mA)
100
60
14
8
6
60
50
40
30
4
20
2
10
0
−40.0 −20.0 0.0 20.0 40.0 60.0 80.0 100.0 120.0 140.0
0
−40.0 −20.0 0.0 20.0 40.0 60.0 80.0 100.0 120.0 140.0
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 16. IHB_Leakage vs Temperature
Figure 17. Low Side Turn on Propagation
Delay vs Temperature
100
100
90
90
80
80
70
70
60
TDHFF (ns)
TDLRR (ns)
120
50
40
30
60
50
40
30
20
20
10
0
−40.0 −20.0 0.0
10
0
−40.0 −20.0 0.0
20.0 40.0 60.0 80.0 100.0 120.0 140.0
20.0 40.0 60.0 80.0 100.0 120.0 140.0
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 18. Low Side Turn on Propagation
Delay vs Temperature
Figure 19. High Side Turn off Propagation
Delay vs Temperature
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NCP51530
100
14
80
12
70
10
60
Tr_LO (ns)
TDHRR (ns)
90
50
40
30
8
6
4
20
2
10
0
−40.0 −20.0 0.0
0
−40.0 −20.0 0.0
20.0 40.0 60.0 80.0 100.0 120.0 140.0
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 21. Low Side Rise Time vs Temperature
14
14
12
12
10
10
Tf_LO
Tr_HO
Figure 20. High Side Turn off Propagation
Delay vs Temperature
8
6
8
6
4
4
2
2
0
−40.0 −20.0 0.0
20.0 40.0 60.0 80.0 100.0 120.0 140.0
0
−40.0 −20.0 0.0
20.0 40.0 60.0 80.0 100.0 120.0 140.0
20.0 40.0 60.0 80.0 100.0 120.0 140.0
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 22. High Side Rise Time vs
Temperature
Figure 23. Low Side Fall Time vs Temperature
0
NEGATIVE PULSE AMPLITUDE
14
12
Tr_HO
10
8
6
4
2
0
−40.0 −20.0 0.0
−20
−40
−60
−80
−100
−120
0
20.0 40.0 60.0 80.0 100.0 120.0 140.0
100
200
300
400
500
TEMPERATURE (°C)
NEGATIVE PULSE WIDTH (ns)
Figure 24. High Side Fall Time vs Temperature
Figure 25. Typical Safe Operating Area with
Negative Transient Voltage on HB Pin
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600
NCP51530
GENERAL DESCRIPTION
For popular topologies like LLC, half bridge converters,
full bridge converters, two switch forward converter etc.
low−side high−side drivers are needed which perform the
function of both buffer and level shifter. These devices can
drive the gate of the topside MOSFETs whose source node
is a dynamically changing node. The bias for the high side
driver in these devices is usually provided through a
bootstrap circuit.
In a bid to make modern power supplies more compact
and efficient, power supply designers are increasingly
opting for high frequency operations. High frequency
operation causes higher losses in the drivers, hence reducing
the efficiency of the power supply.
NCP51530 is a 700 V high side−low side driver for
AC−DC power supplies and inverters. NCP51530 offers
best in class propagation delay, low quiescent current and
low switching current at high frequencies of operation. This
device thus enables highly efficient power supplies
operating at high frequencies.
NCP51530 is offered in two versions, NCP51530A/B.
NCP51530A has a typical 60 ns propagation delay, while
NCP51530B has propagation delay of 25 ns.
NCP51530 comes in SOIC8 and DFN10 packages.
SOIC8 package of the device is pin to pin compatible with
industry standard solutions.
NCP51530 has two independent input pins HI and LI
allowing it to be used in a variety of applications. This device
also includes features wherein, in case of floating input, the
logic is still defined. Driver inputs are compatible with both
CMOS and TTL logic hence it provides easy interface with
analog and digital controllers. NCP51530 has under voltage
lock out feature for both high and low side drivers which
ensures operation at correct VCC and VB voltage levels. The
output stage of NCP51530 has 2.2 A/1.7 A current
source/sink capability which can effectively charge and
discharge a 1 nF load in 15 ns.
FEATURES
INPUT STAGES
NCP51530 has two independent input pins HIN and LIN
allowing it to be used in a variety of applications. The input
stages of NCP51530 are TTL and CMOS compatible. This
ensures that the inputs of NCP51530 can be driven with
3.3 V or 5 V logic signals from analog or digital PWM
controllers or logic gates.
The input pins have Schmitt triggers to avoid noise
induced logic errors. The hysteresis on the input pins is
typically 1.3 V. This high value ensures good noise
immunity.
NCP51530 comes with an important feature wherein
outputs (HO, LO) stays low in case any of the input pin is
floating. At both the input pins there is an internal pull down
resistor to define its logic value in case the pin is left open
or NCP51530 is driven by open drain signal. The input logic
is explained in the Table 7 below.
NCP51530 input pins are also tolerant to negative voltage
below the GND pin level as long as it is within the ratings
defined in the datasheet. This tolerance allows the use of
transformer as an isolation barrier for input pulses.
NCP51530A features a noise rejection function to ensure
that any pulse glitch shorter than 30 ns will not produce any
output. These features are well illustrated in the Figure 28
below.
NCP51530B has no such filters in the input stages. The
timing diagram NCP51530B is Figure 29 below.
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NCP51530
Table 7. INPUT TABLE
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NCP51530
50ns
80ns
30ns
40ns
10ns
LIN/HIN
80ns
60ns
60ns
100ns
LO /HO
Figure 26. Input Filter (NCP51530A)
50ns
80ns
30ns
10ns
LIN/HIN
25ns
30ns
25ns
40ns
80ns
25ns
50ns
10ns
Figure 27. No Input Filter (NCP51530B)
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NCP51530
VCCON
VCCOFF
VCC
LIN
LO
VBON
VB − VHB
HIN
HO
Figure 28. UVLO Timing Diagram
UNDER VOLTAGE LOCK−OUT
If the VCC is below the VCC UVLO voltage, the low side
driver output (LO) and high side driver output (HO) both
remain low.
If VB is below VB UVLO voltage the high side driver
output (HO) remains low. However if the VCC is above VCC
UVLO voltage level, the low side driver output (LO) can
still turn on and off based on the low side driver input (LI)
NCP51530 has under voltage lockout protection on both
the high side and the low side driver. The function of the
UVLO circuits is to ensure that there is enough supply
voltages (VCC and VB) to correctly bias high side and low
side circuits. This also ensures that the gate of external
MOSFETs are driven at an optimum voltage.
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NCP51530
ensures continuous operation in case of a small drop in the
bias voltage. This drop in the bias can happen when device
starts switching MOSFET and the operating current of the
device increases. The UVLO feature of the device is
explained in the Figure 30.
and is not affected by the VB status. This ensures proper
charging of the bootstrap capacitor to bring the high side bias
supply VB above UVLO voltage.
Both the VCC and VB UVLO circuits are provided with
hysteresis feature. This hysteresis feature avoids errors due
to ground noise in the power supply. The hysteresis also
Figure 29. NCP51530 Turn ON−OFF Paths
OUTPUT STAGES
side external MOSFETs respectively. When a logic high is
received from input stage, Qsource turns on and VCC/VB
starts charging Cgs through Rg. Once the Cgs is charged to
the drive voltage level the external power MOSFET turns on
the external MOSFET to discharge to GND/HB level.
When a logic low signal is received from the input stage,
Qsource turns off and Qsink turns on providing a path for
gate terminal of
As seen in the figure, there are parasitic inductances in
charging and discharging path of the Cgs. This can result in
a little dip in the bias voltages VCC/VB. If the VCC/VB drops
below UVLO the power supply can shut down the device.
The NCP51530 is equipped with two independent drivers.
The output stage of NCP51530 has 1.7 A/2.2 A current
source/sink capability which can effectively charge and
discharge a 1 nF load in 15 ns.
The outputs of NCP51530 can be turned on at the same
time and there is no internal dead−time built between them.
This allows NCP51530 to be used in topologies like two
switch forward converter.
The figure below show the output stage structure and the
charging and discharging path of the external power
MOSFET. The bias supply VCC or VB supply the energy to
charge the gate capacitance Cgs of the low side or the top
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NCP51530
Figure 30. Low Side Turn−ON Propagation Delay (NCP51530A)
FAST PROPAGATION DELAY
Since NCP51530B doesn t have the input filter included,
the propagation delay are even faster. NCP51530B offers
30 ns propagation delay between input and output.
NCP51530 boasts of industry best propagation delay
between input and output. NCP51530A has a typical of
60 ns propagation delay. The best in class propagation delay
in NCP51530 makes it suitable for high frequency
operation.
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NCP51530
Figure 31. Low Side Turn−Off Propagation Delay (NCP51530A)
Figure 32. High Side Turn−Off Propagation Delay (NCP51530B)
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NCP51530
Figure 33. High Side Turn−Off Propagation Delay (NCP51530B)
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NCP51530
Figure 34. Bootstrap Circuit
COMPONENT SELECTION
It is recommended to use a larger value so as to cover any
variations in the gate charge and voltage with temperature.
CBOOT CAPACITOR VALUE CALCULATION
NCP51530 has two independent drivers for driving high
side and low side external MOSFETs. The bias for the high
side driver is usually provided through a bootstrap circuit. A
typical bootstrap circuit is shown in the figure 8 below.
The high side driver is biased by the Cboot (bootstrap
capacitor). As can be seen in the circuit, Cboot will charge
only when HB goes to GND level. Low value of Cboot can
result in a little dip in the bias voltages VB. If the VB drops
below UVLO the power supply can shut down the high side
driver. Therefore choosing the right value of Cboot is very
important for a robust design.
An example design for Cboot is given below.
Q g + 30 nC, V CC + 15 V
Rboot RESISTOR VALUE CALCULATION
Rboot resistor value is very important to ensure proper
function of the device. A high value of Rboot would slow
down the charging of the Cboot while too low a value would
push very high charging currents for Cboot. For NCP51530
a value between 2 W and 10 W is recommended for Rboot.
For example Rboot = 5 W
I boot(pk) +
C boot +
Q tot
V ripple
+
30.4 nC
150 mV
+ 203 nF
R boot
+
15 V * 1 V
5W
+ 2.8 A
(eq. 5)
Where VD is the bootstrap diode forward drop.
Thus, Rboot value of 5 W keeps the peak current below 2.8 A.
(eq. 1)
HIN AND LIN INPUT FILTER
Q b + I BQ * t discharge + 81 mC * 5 mS + 405 pC (eq. 2)
Q tot + Q g ) Q b + 30 nC ) 405p + 30.4 pC
V CC * V D
For PWM connection on the LIN and HIN pin of the
NCP51530, a RC is recommended to filter high frequency
input noise.
This filter is particularly important in case of NCP51530B
where no internal filter is included.
The recommended value for RLIN/RHIN and CHIN/CLIN
are as below.
(eq. 3)
(eq. 4)
Qg is equivalent gate charge of the FET
IBQ is the boot quiescent current
tdishcharge is the discharge time for bootstrap capacitor
Vripple is the allowed ripple voltage in the bootstrap
capacitor
RLIN/RHIN = 100 W
CHIN/CLIN = 120 pF
www.onsemi.com
21
NCP51530
VCC CAPACITOR SELECTION
P operating + V boot * I BO ) V CC * I CCO
VCC capacitor value should be selected at least ten times
the value of Cboot. In this case thus CVCC > 2 mF.
+ 14 V * 0.4 mA ) 15 V * 0.4 mA + 11.6 mW
IBO is the operating current for the high side driver
ICCO is the operating current for the low side driver
2. Power loss of driving external FET (Hard
Switching)
Rgate SELECTION
Rgate are selected to limit the peak gate current during
charging and discharging of the gate capacitance. This
resistance also helps to damp the ringing due to the parasitic
inductances.
For example for a Rgate value of 5 W, the peak source and
sink currents would be limited to the following values.
R gate + 5W
I LO_Source +
I LO_Sink +
R Lgate ) R LOH
V CC
R Lgate ) R LOL
I HO_Source +
I HO_Sink +
V CC
+
V CC * V Dboot
R Lgate ) R HOH
V CC * V Dboot
R Lgate ) R HOL
+
+
6.7 W
15 V
6.8 W
+
P drivers +
Qg is total gate charge of the MOSFET
3. Power loss of driving external FET (Soft
Switching)
+ 2.23 A (eq. 7)
6.7 W
ǒǒQgs * VbootǓ ) ǒQgs * VCCǓǓ * f
(eq. 13)
4. Level shifting losses
(eq. 8)
P levelshifting + ǒV r ) V bǓ * Q * f
(eq. 14)
+ 415 V * 1 nC * 100 kHz + 41.5 mW
+ 2.09 A (eq. 9)
15 V * 1 V
6.8 W
P drivers +
+ ǒǒ4 nC * 14 VǓ ) ǒ4 nC * 15 VǓǓ * 100 kHz + 11 mW
+ 2.20 A
14 V
ǒǒQg * VboostǓ ) ǒQg * VCCǓǓf
(eq. 12)
+ ǒǒ30 nC * 14 VǓ ) ǒ30 nC * 15 VǓǓ * 100 kHz + 87 mW
(eq. 6)
15 V
(eq. 11)
Vr is the rail voltage
Q is the substrate charge on the level shifter
5. Total Power Loss (Hard Switching)
(eq. 10)
+ 2.06 A
P total + P driver ) P operating ) P levelshifting
(eq. 15)
+ 11.6 mW ) 87 mW ) 40 mW + 138.6 mW
TOTAL POWER DISSIPATION
Total power dissipation of NCP51530 can be calculated as
follows.
1. Static power loss of device (excluding drivers)
while switching at an appropriate frequency.
6. Junction temperature increase
t J + R qJA * P total + 183 * 0.14 + 25° C
www.onsemi.com
22
(eq. 16)
NCP51530
LAYOUT RECOMMENDATIONS
NCP51530 is a high speed and high current high side and
low side driver. To avoid any device malfunction during
device operation, it is very important that there is very low
parasitic inductance in the current switching path. It is very
important that the best layout practices are followed for the
PCB layout of the NCP51530. An example layout is shown
in the figure below. Some of the layout rules to be followed
are listed below.
• Keep the low side drive path LO−Q1−GND as small as
possible. This reduces the parasitic inductance in the
path and hence eliminates ringing on the gate terminal
of the low side MOSFET Q1.
• Keep the high side drive loop HO−Q2−HB as small as
possible. This reduces the parasitic inductance in the
•
•
•
path and hence eliminates ringing on the gate terminal
of the low side MOSFET Q1.
Keep CVCC as near to the VCC pin as possible and the
VCC−CVCC−GND loop as small as possible.
Keep CVB as near to VB pin as possible and
VB−CVB−HB loop as small as possible.
Keep the HB−GND−Q1 loop as small as possible. This
loop has the potential to produce a negative voltage
spike on the HB pin. This negative voltage spike can
cause damage to the driver. This negative spike can
increase the boot capacitor voltage above the maximum
rating and hence cause damage to the driver.
Figure 35. Example Layout
ORDERING INFORMATION17
Propagation Delay
(ns)
Input filter
Package
Shipping†
NCP51530ADR2G
60
Yes
SOIC−8
(Pb−Free)
2500 / Tape & Reel
NCP51530BDR2G
25
No
SOIC−8
(Pb−Free)
2500 / Tape & Reel
NCP51530AMNTWG
60
Yes
DFN10 4x4
(Pb−Free)
4000 / Tape & Reel
NCP51530BMNTWG
25
No
DFN10 4x4
(Pb−Free)
4000 / Tape & Reel
Device
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specification Brochure, BRD8011/D.
www.onsemi.com
23
NCP51530
PACKAGE DIMENSIONS
SOIC−8 NB
CASE 751−07
ISSUE AK
−X−
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
A
8
5
S
B
0.25 (0.010)
M
Y
M
1
4
−Y−
K
G
C
N
DIM
A
B
C
D
G
H
J
K
M
N
S
X 45 _
SEATING
PLANE
−Z−
0.10 (0.004)
H
D
0.25 (0.010)
M
Z Y
S
X
S
M
J
SOLDERING FOOTPRINT*
1.52
0.060
7.0
0.275
4.0
0.155
0.6
0.024
1.270
0.050
SCALE 6:1
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
www.onsemi.com
24
MILLIMETERS
MIN
MAX
4.80
5.00
3.80
4.00
1.35
1.75
0.33
0.51
1.27 BSC
0.10
0.25
0.19
0.25
0.40
1.27
0_
8_
0.25
0.50
5.80
6.20
INCHES
MIN
MAX
0.189
0.197
0.150
0.157
0.053
0.069
0.013
0.020
0.050 BSC
0.004
0.010
0.007
0.010
0.016
0.050
0 _
8 _
0.010
0.020
0.228
0.244
NCP51530
PACKAGE DIMENSIONS
DFN10 4x4, 0.8P
CASE 506DJ
ISSUE O
B
A
D
L
PIN ONE
REFERENCE
2X
ÇÇÇÇ
ÇÇÇÇ
ÇÇÇÇ
ÇÇÇÇ
0.10 C
L1
ALTERNATE TERMINAL
CONSTRUCTIONS
ÉÉ
ÉÉ
ÇÇ
A1
A
DETAIL B
ALTERNATE A−2
DETAIL A
E
TOP VIEW
0.10 C
L
ALTERNATE A−1
0.10 C
2X
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS
MEASURED BETWEEN 0.25 AND 0.30 MM FROM THE
TERMINAL TIP.
4. COPLANARITY APPLIES TO THE EXPOSED PAD AS
WELL AS THE TERMINALS.
5. FOR DEVICE OPN CONTAINING W OPTION, DETAIL A
ALTERNATE CONSTRUCTION A−2 AND DETAIL B ALTERNATE CONSTRUCTION B−2 ARE NOT APPLICABLE.
A3
ÉÉÉ
ÇÇÇ
ÇÇÇ
EXPOSED Cu
ALTERNATE B−1
MOLD CMPD
ALTERNATE B−2
DETAIL B
ALTERNATE
CONSTRUCTIONS
10X
0.08 C
NOTE 4
SIDE VIEW
A3
A1
C
SEATING
PLANE
0.10 C A B
DETAIL A
1
D2
10X
MILLIMETERS
MIN
MAX
0.80
1.00
0.00
0.05
0.20 REF
0.25
0.35
4.00 BSC
2.90
3.10
4.00 BSC
1.85
2.05
0.375 BSC
0.80 BSC
0.90
−−−
0.35
0.45
0.00
0.15
RECOMMENDED
MOUNTING FOOTPRINT*
L
5
3.20
PACKAGE
OUTLINE
0.10 C A B
E3
DIM
A
A1
A3
b
D
D2
E
E2
E3
e
K
L
L1
10X
0.60
E2
2.15
0.75
K
10
6
e
BOTTOM VIEW
10X
1
b
0.10 C A B
0.05 C
4.30
0.80
PITCH
NOTE 3
10X
0.42
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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NCP51530/D
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