MPQ8632 High Efficiency 18V Synchronous Step-down Converter Family for 4A to 20A FEATURES Part Number Current Rating (A) Input Voltage OVP Mode MPQ8632GLE-4 4 2.5V to 18V Non-Latch MPQ8632GLE-6 6 2.5V to 18V Non-Latch MPQ8632GLE-8 8 2.5V to 18V Non-Latch MPQ8632HGLE-10 10 2.5V to 18V Non-Latch MPQ8632GLE-10 10 2.5V to 18V Latch-Off MPQ8632GLE-12 12 2.5V to 18V Non-Latch MPQ8632GVE-15 15 2.5V to 18V Non-Latch MPQ8632GVE-20 20 2.5V to 18V Non-Latch DESCRIPTION The MPQ8632 is a fully integrated high frequency synchronous rectified step-down switch mode converter. It offers a very compact solution to achieve 4A/6A/8A/10A/12A/15A/20A output current over a wide input supply range with excellent load and line regulation. The MPQ8632 uses Constant-On-Time (COT) control mode to provide fast transient response and ease loop stabilization. An external resistor programs the operating frequency from 200kHz to 1MHz and the frequency keeps nearly constant as input supply varies with the feedforward compensation. The default under voltage lockout threshold is internally set at 4.1V, but a resistor network on the enable pin can increase this threshold. The soft start pin controls the output voltage startup ramp. An open drain power good signal indicates that the output is within nominal voltage range. It has fully integrated protection features that include over-current protection, over-voltage protection and thermal shutdown. The MPQ8632 requires a minimal number of readily available standard external components and is available in a 16-Pin QFN 3mm×4mm or a 29-Pin QFN 5mm×4mm package. Low Input Voltage Range from 2.5V: -- 2.5V to 18V with External 5V Bias -- 4.5V to 18V with Internal Bias Scalable Family of Products for 4A to 20A Output Current Applications -- 4A/6A/8A/10A/12A Share the Same Footprint --15A/20A Share the Same Footprint, with Slight Change on Power Stage Section from 4A/6A/8A/10A/12A Optimal Low RDS(ON) Internal Power MOSFETs Per Device Proprietary Switching Loss Reduction Technique Adaptive COT for Ultrafast Transient Response 0.5% Reference Voltage Over 0C to 70C Junction Temperature Range Programmable Soft Start Time Pre-Bias Start up Programmable Switching Frequency from 200kHz to 1MHz Non-latch OCP, OVP and Thermal Shutdown Protection Output Adjustable from 0.611V to 13V APPLICATIONS Telecom and Networking Systems Base Stations Servers Personal Video Recorders Flat Panel Television and Monitors Distributed Power Systems All MPS parts are lead-free and adhere to the RoHS directive. For MPS green status, please visit MPS website under Products, Quality Assurance page. “MPS” and “The Future of Analog IC Technology” are registered trademarks of Monolithic Power Systems, Inc. MPQ8632 Rev.1.24 www.MonolithicPower.com 8/28/2013 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. 1 MPQ8632 HIGH EFFICIENCY 18V SYNCHRONOUS STEP-DOWN CONVERTER FAMILY FOR 4A TO 20A TYPICAL APPLICATION VIN BST IN C1 C3 RFREQ FREQ EN ON/OFF VOUT R4 C4 R1 MPQ8632 C2 FB VCC C5 L1 SW R2 R3 SS C6 PG PGND AGND MPQ8632 Rev.1.24 www.MonolithicPower.com 8/28/2013 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. 2 MPQ8632 HIGH EFFICIENCY 18V SYNCHRONOUS STEP-DOWN CONVERTER FAMILY FOR 4A TO 20A ORDERING INFORMATION Part Number Package MPQ8632GLE-4* QFN(3X4mm) MPQ8632GLE-6 QFN(3X4mm) MPQ8632GLE-8 QFN(3X4mm) MPQ8632GLE-10 QFN(3X4mm) MPQ8632HGLE-10 QFN(3X4mm) MPQ8632GLE-12 QFN(3X4mm) MPQ8632GVE-15 QFN(5X4mm) MPQ8632GVE-20 QFN(5X4mm) Top Marking MP8632 E4 MP8632 E6 MP8632 E8 MP8632 E10 MP8632H E10 MP8632 E12 MP8632 E15 MP8632 E20 * For Tape & Reel, add suffix –Z (e.g. MPQ8632GLE–4–Z) PACKAGE REFERENCE TOP VIEW PG 6 PG 6 VCC 7 VCC 7 BST 8 BST 8 PGND 12 PGND 14 VIN PGND VIN 11 5 PGND AGND 16 5 SW AGND PGND 10 4 13 VIN SS 15 4 11 SS PGND 10 FB 3 9 FB 3 SW PGND 12 2 9 PGND 13 FREQ 16 1 SW VIN 2 14 FREQ EN 15 1 SW EN TOP VIEW Part Number* Package Part Number* Package MPQ8632GLE-4 Junction Temperature QFN (3x4mm) Top Marking MPQ8632GLE-6 Junction Temperature QFN (3x4mm) Top Marking –40C to +125C MP8632 E4 –40C to +125C MP8632 E6 * For Tape & Reel, add suffix –Z (eg. MPQ8632GLE-4–Z) * For Tape & Reel, add suffix –Z (eg. MPQ8632GLE-6–Z) MPQ8632 Rev.1.24 www.MonolithicPower.com 8/28/2013 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. 3 MPQ8632 HIGH EFFICIENCY 18V SYNCHRONOUS STEP-DOWN CONVERTER FAMILY FOR 4A TO 20A TOP VIEW AGND 5 PG 6 PG 6 VCC 7 VCC 7 BST 8 BST 8 PGND 12 PGND 14 VIN PGND PGND 10 9 VIN 11 5 PGND AGND 16 4 SW SS PGND 10 4 13 VIN SS 15 FB 3 11 FB 3 SW PGND 12 2 9 PGND 13 FREQ 16 1 SW VIN 2 14 FREQ EN 15 1 SW EN TOP VIEW Part Number* Package Part Number* Package MPQ8632GLE-8 Junction Temperature QFN (3x4mm) MPQ8632GLE-10 Junction Temperature QFN (3x4mm) –40C to +125C MP8632 E8 –40C to +125C MP8632 E10 Top Marking * For Tape & Reel, add suffix –Z (eg. MPQ8632GLE-8–Z) * For Tape & Reel, add suffix –Z (eg. MPQ8632GLE-10–Z) TOP VIEW PG 6 PG 6 VCC 7 VCC 7 BST 8 BST 8 PGND 12 PGND 14 VIN PGND VIN 11 5 PGND AGND 16 5 SW AGND PGND 10 4 13 VIN SS 15 4 11 SS PGND 10 FB 3 9 FB 3 SW PGND 12 2 9 PGND 13 FREQ 16 1 SW VIN 2 14 FREQ EN 15 1 TOP VIEW SW EN Top Marking Part Number* Package Part Number* Package MPQ8632HGLE-10 Junction Temperature QFN (3x4mm) Top Marking MPQ8632GLE-12 Junction Temperature QFN (3x4mm) Top Marking –40C to +125C MP8632H E10 –40C to +125C MP8632 E12 * For Tape & Reel, add suffix –Z (eg. MPQ8632HGLE-10–Z) * For Tape & Reel, add suffix –Z (eg. MPQ8632GLE-12–Z) MPQ8632 Rev.1.24 www.MonolithicPower.com 8/28/2013 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. 4 MPQ8632 HIGH EFFICIENCY 18V SYNCHRONOUS STEP-DOWN CONVERTER FAMILY FOR 4A TO 20A PGND 22 21 PGND PGND 23 26 27 28 29 SW SW SW SW 8 12 BST PGND 13 PGND 11 8 PGND BST 10 7 18 SW PGND VCC 12 14 PGND PGND 7 11 VCC PGND 15 SW 10 6 PGND PG 9 IN 14 PGND 16 SW IN 24 15 SW 29 6 SW PG 28 16 SW AGND 5 SW AGND 5 27 17 SW SW 4 26 SS 17 SW SW FB 3 25 18 SW 4 SS 19 PGND 25 FREQ 2 20 PGND SW 19 PGND SW FB 3 EN 1 9 PGND 22 FREQ 2 20 PGND IN PGND 23 TOP VIEW 21 PGND IN EN 1 24 TOP VIEW 13 PGND Part Number* Package Part Number* Package MPQ8632GVE-15 Junction Temperature QFN (5x4mm) Top Marking MPQ8632GVE-20 Junction Temperature QFN (5x4mm) Top Marking –40C to +125C MP8632 E15 –40C to +125C MP8632 E20 * For Tape & Reel, add suffix –Z (eg. MPQ8632GVE-15–Z) * For Tape & Reel, add suffix –Z (eg. MPQ8632GVE-20–Z) MPQ8632 Rev.1.24 www.MonolithicPower.com 8/28/2013 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. 5 MPQ8632 HIGH EFFICIENCY 18V SYNCHRONOUS STEP-DOWN CONVERTER FAMILY FOR 4A TO 20A ABSOLUTE MAXIMUM RATINGS (1) Supply Voltage VIN .......................................21V VSW ....................................... -0.3V to VIN + 0.3V VSW (30ns) ..................................-3V to VIN + 3V VBST .....................................................VSW + 6V VBST (30ns) ........................................VSW + 6.5V Enable Current IEN(2)................................ 2.5mA All Other Pins ................................ –0.3V to +6V (3) Continuous Power Dissipation (TA=+25) QFN3X4……………………….…..…………2.7W QFN5X4……………………….…..…………3.3W Junction Temperature .............................. 150C Lead Temperature ................................... 260C Storage Temperature ............... -65C to +150C Recommended Operating Conditions Thermal Resistance (5) θJA θJC QFN (3x4mm) ........................ 46 ....... 9 .... C/W QFN (5x4mm) ........................ 38 ....... 6 .... C/W Notes: 1) Exceeding these ratings may damage the device. 2) Refer to the section “Configuring the EN Control”. 3) The maximum allowable power dissipation is a function of the maximum junction temperature TJ(MAX), the junction-toambient thermal resistance θJA, and the ambient temperature TA. The maximum allowable continuous power dissipation at any ambient temperature is calculated by PD(MAX)=(TJ(MAX)TA)/θJA. Exceeding the maximum allowable power dissipation will cause excessive die temperature, and the regulator will go into thermal shutdown. Internal thermal shutdown circuitry protects the device from permanent damage. 4) The device is not guaranteed to function outside of its operating conditions. 5) Measured on JESD51-7, 4-layer PCB. (4) Supply Voltage VIN .......................... 4.5V to 18V Output Voltage VOUT.................... 0.611V to 13V Enable Current IEN...................................... 1mA Operating Junction Temp. (TJ).-40°C to +125°C MPQ8632 Rev.1.24 www.MonolithicPower.com 8/28/2013 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. 6 MPQ8632 HIGH EFFICIENCY 18V SYNCHRONOUS STEP-DOWN CONVERTER FAMILY FOR 4A TO 20A ELECTRICAL CHARACTERISTICS VIN = 12V, TJ = -40C to +125C, unless otherwise noted. Parameters Symbol Condition Min Typ Max Units 700 0 860 1 1000 μA μA Supply Current Supply Current (Shutdown) Supply Current (Quiescent) IIN IIN VEN = 0V VEN = 2V, VFB = 1V MOSFET High-side Switch On Resistance Low-side Switch On Resistance Switch Leakage HSRDS-ON LSRDS-ON SW LKG MPQ8632GLE-4,6,8, TJ =25C MPQ8632GLE-10,12, MPQ8632HGLE-10, TJ =25C MPQ8632GVE-15,20, TJ =25C 28 mΩ 19.6 mΩ 9.9 mΩ MPQ8632GLE-4, TJ =25C 16.4 MPQ8632GLE-6, TJ =25C 15.8 MPQ8632GLE-8, TJ =25C 15.3 MPQ8632GLE-10, MPQ8632HGLE-10, TJ =25C 5.7 MPQ8632GLE-12, TJ =25C 5.2 MPQ8632GVE-15, TJ =25C 3 MPQ8632GVE-20, TJ =25C 2.4 VEN = 0V, VSW = 0V or 12V mΩ 0 10 μA A Current Limit High-side Peak Current Limit Low-side Valley Current Limit Low-side Negative Current (6) Limit ILIMIT_PEAK (6) ILIMIT_VALLEY MPQ8632GLE-10 13 17.3 21.6 MPQ8632GLE-4 4 5 6 MPQ8632GLE-6 6.5 7.5 8.5 MPQ8632GLE-8 8 10 12 MPQ8632GLE-10 9.5 11 12.5 MPQ8632HGLE-10 10 13 16 MPQ8632GLE-12 12 15 18 MPQ8632GVE-15 15 20 25 MPQ8632GVE-20 20 25 30 MPQ8632GVE-15 -6.6 -5.6 -4.6 -4 -2.5 -1 ILIMIT_NEGATIVE A A All other parts MPQ8632 Rev.1.24 www.MonolithicPower.com 8/28/2013 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. 7 MPQ8632 HIGH EFFICIENCY 18V SYNCHRONOUS STEP-DOWN CONVERTER FAMILY FOR 4A TO 20A ELECTRICAL CHARACTERISTICS (continued) VIN = 12V, TJ = -40C to +125C, unless otherwise noted. Parameters Symbol Condition Min Typ Max Units Timer One-Shot On Time TON Minimum On Time (6) TON_MIN Minimum Off Time (6) TOFF_MIN Over-voltage and Under-voltage Protection (6) OVP Latch Threshold VOVP_LATCH OVP Non-latch Threshold RFREQ=453kΩ, VOUT=1.2V 250 ns 20 30 40 ns MPQ8632GLE-10 Other parts 50 200 100 360 150 420 ns MPQ8632GLE-10 127% 130% 133% VFB 117% 120% 123% VFB VOVP_NONLATCH OVP Delay (6) UVP Threshold Reference And Soft Start Reference Voltage Feedback Current Soft Start Charging Current TOVP VUVP VREF IFB ISS μs 2 TJ = 0°C to +70°C TJ = 0°C to +125°C TJ = -40°C to +125°C VFB = 611mV VSS=0V 47% 50% 53% VFB 608 605 602 611 611 611 50 20 614 617 620 100 25 mV mV mV nA μA 1.3 250 0 0 1.5 V mV 16 Enable And UVLO Enable Input Low Voltage Enable Hysteresis Enable Input Current VILEN VEN-HYS IEN 1.1 VEN = 2V VEN = 0V μA VCC Regulator VCC Under Voltage Lockout Threshold Rising VCC Under Voltage Lockout Threshold Hysteresis VCC Regulator VCCVth 3.8 V VCCHYS 500 mV VCC 4.8 V 0.5 % VCC Load Regulation Power Good Power Good Rising Threshold Power Good Falling Threshold Power Good Lower to High Delay Power Good Sink Current Capability Power Good Leakage Current Icc=5mA PGVth-Hi PGVth-Lo PGTd 87% IOL VOL=600mV IPG_LEAK VPG = 3.3V 91% 80% 2.5 10 MPQ8632 Rev.1.24 www.MonolithicPower.com 8/28/2013 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. 94% VFB VFB ms 12 mA nA 8 MPQ8632 HIGH EFFICIENCY 18V SYNCHRONOUS STEP-DOWN CONVERTER FAMILY FOR 4A TO 20A ELECTRICAL CHARACTERISTICS (continued) VIN = 12V, TJ = -40C to +125C, unless otherwise noted. Parameters Thermal Protection Symbol Condition Min Typ Max Units (6) Thermal Shutdown Thermal Shutdown Hysteresis TSD 150 25 °C °C Note: 6) Guaranteed by design. MPQ8632 Rev.1.24 www.MonolithicPower.com 8/28/2013 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. 9 MPQ8632 HIGH EFFICIENCY 18V SYNCHRONOUS STEP-DOWN CONVERTER FAMILY FOR 4A TO 20A PIN FUNCTIONS MPQ8632GLE-4, MPQ8632GLE-6, MPQ8632HGLE-10, MPQ8632GLE-12 MPQ8632GLE-8, MPQ8632GLE-10, PIN # Name 1 EN 2 FREQ 3 FB 4 SS 5 AGND 6 PG 7 VCC 8 BST 9, 14 IN 10-13 PGND System Ground. Reference ground of the regulated output voltage. PCB layout requires extra care. Connect using wide PCB traces. SW Switch Output. Connect to the inductor and bootstrap capacitor. The high-side switch drives the pin up to the VIN during the PWM duty cycle’s ON time. The inductor current drives the SW pin negative during the OFF-time. The low-side switch’s ON-resistance and the internal Schottky diode clamp the negative voltage. Connect using wide PCB traces. 15, 16 Description Enable. Digital input that turns the regulator on or off. Drive EN high to turn on the regulator, drive it low to turn it off. Connect EN to IN through a pull-up resistor or a resistive voltage divider for automatic startup. Do not float this pin. Frequency Set. Require a resistor connected between FREQ and IN to set the switching frequency. The input voltage and the resistor connected to the FREQ pin determine the ON time. The connection to the IN pin provides line feed-forward and stabilizes the frequency during input voltage’s variation. Feedback. Connect to the tap of an external resistor divider from the output to GND to set the output voltage. FB is also configured to realize over-voltage protection (OVP) by monitoring output voltage. MPQ8632 and MPQ8632H provide different OVP mode. Please refer to the section “Over-Voltage-Protection (OVP)”. Place the resistor divider as close to FB pin as possible. Avoid using vias on the FB traces. Soft Start. Connect an external capacitor to program the soft start time for the switch mode regulator. Analog ground. The control circuit reference. Power Good. The output is an open drain signal. Require a pull-up resistor to a DC voltage to indicate high if the output voltage exceeds 91% of the nominal voltage. There is a delay from FB ≥ 91% to PG goes high. Internal 4.8V LDO Output. Power the driver and control circuits. 5V external bias can disable the internal LDO. Decouple with a ≥ 1µF ceramic capacitor as close to the pin as possible. For best results, use X7R or X5R dielectric ceramic capacitors for their stable temperature characteristics. Bootstrap. Require a capacitor connected between SW and BST pins to form a floating supply across the high-side switch driver. Supply Voltage. Supply power to the internal MOSFET and regulator. The MPQ8632 operates from a +2.5V to +18V input rail with 5V external bias and a +4.5V to +18V input rail with internal bias. Require an input decoupling capacitor. Connect using wide PCB traces and multiple vias. MPQ8632 Rev.1.24 www.MonolithicPower.com 8/28/2013 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. 10 MPQ8632 HIGH EFFICIENCY 18V SYNCHRONOUS STEP-DOWN CONVERTER FAMILY FOR 4A TO 20A MPQ8632GVE-15, MPQ8632GVE-20 PIN # Name 1 EN 2 FREQ 3 FB 4 SS 5 AGND 6 PG 7 VCC 8 BST 15-18, 25-29 SW 10-14, 19-23 PGND 9, 24 IN Description Enable. Digital input that turns the regulator on or off. Drive EN high to turn on the regulator; drive it low to turn it off. Connect EN to IN through a pull-up resistor or a resistive voltage divider for automatic startup. Do not float this pin. Frequency Set. Require a resistor connected between FREQ and IN to set the switching frequency. The input voltage and the resistor connected to the FREQ pin determine the ON time. The connection to the IN pin provides line feed-forward and stabilizes the frequency during input voltage’s variation. Feedback. Connect to the tap of an external resistor divider from the output to GND to set the output voltage. Place the resistor divider as close to FB pin as possible. Avoid using vias on the FB traces. Soft-Start. Connect an external capacitor to program the soft start time for the switch mode regulator. Analog Ground. The control circuit reference. Power-Good. The output is an open drain signal. Requires a pull-up resistor to a DC voltage to indicate HIGH if the output voltage exceeds 91% of the nominal voltage. There is a delay from FB ≥ 91% to when PG goes high. Internal 4.8V LDO Output. Powers the driver and control circuits. 5V external bias can disable the internal LDO. Decouple with a ≥1µF ceramic capacitor as close to the pin as possible. For best results, use X7R or X5R dielectric ceramic capacitors for their stable temperature characteristics. Bootstrap. Require a capacitor connected between SW and BST pins to form a floating supply across the high-side switch driver. Switch Output. Connect to the inductor and bootstrap capacitor. The high-side switch drives these pins up to VIN during the PWM duty cycle’s ON time. The inductor current drives the SW pin negative during the OFF-time. The low-side switch’s ONresistance and the internal Schottky diode holds the negative voltage. Connect all SW pins using wide PCB traces. System Ground. Reference ground of the regulated output voltage. PCB layout requires extra care. Connect using wide PCB traces. Supply Voltage. Supplies power to the internal MOSFET and regulator. The MPQ8632GVE operate from a 4.5V-to-18V input rail. If 5V external bias is tied to VCC pin, the input voltage can be low as 2.5V. Requires an input decoupling capacitor. Connect using wide PCB traces and multiple vias. MPQ8632 Rev.1.24 www.MonolithicPower.com 8/28/2013 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. 11 MPQ8632 HIGH EFFICIENCY 18V SYNCHRONOUS STEP-DOWN CONVERTER FAMILY FOR 4A TO 20A TYPICAL CHARACTERISTICS MPQ8632GLE-10, VIN = 12V, VOUT = 1V, L = 1µH, TA = 25ºC, unless otherwise noted. MPQ8632 Rev.1.24 www.MonolithicPower.com 8/28/2013 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. 12 MPQ8632 HIGH EFFICIENCY 18V SYNCHRONOUS STEP-DOWN CONVERTER FAMILY FOR 4A TO 20A TYPICAL CHARACTERISTICS (continued) MPQ8632GLE-10, VIN = 12V, VOUT = 1V, L = 1µH, TA = 25ºC, unless otherwise noted. MPQ8632 Rev.1.24 www.MonolithicPower.com 8/28/2013 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. 13 MPQ8632 HIGH EFFICIENCY 18V SYNCHRONOUS STEP-DOWN CONVERTER FAMILY FOR 4A TO 20A TYPICAL PERFORMANCE CHARACTERISTICS (continued) MPQ8632GLE-10, VIN = 12V, VOUT = 1V, L = 1µH, TA = 25ºC, unless otherwise noted. MPQ8632 Rev.1.24 www.MonolithicPower.com 8/28/2013 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. 14 MPQ8632 HIGH EFFICIENCY 18V SYNCHRONOUS STEP-DOWN CONVERTER FAMILY FOR 4A TO 20A TYPICAL PERFORMANCE CHARACTERISTICS (continued) MPQ8632GLE-10, VIN=12V, VOUT =1V, L=1µH, TA=+25°C, unless otherwise noted. MPQ8632 Rev.1.24 www.MonolithicPower.com 8/28/2013 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. 15 MPQ8632 HIGH EFFICIENCY 18V SYNCHRONOUS STEP-DOWN CONVERTER FAMILY FOR 4A TO 20A TYPICAL PERFORMANCE CHARACTERISTICS (continued) MPQ8632GLE-10, VIN=12V, VOUT =1V, L=1µH, TA=+25°C, unless otherwise noted. MPQ8632 Rev.1.24 www.MonolithicPower.com 8/28/2013 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. 16 MPQ8632 HIGH EFFICIENCY 18V SYNCHRONOUS STEP-DOWN CONVERTER FAMILY FOR 4A TO 20A TYPICAL PERFORMANCE CHARACTERISTICS (continued) MPQ8632GLE-10, VIN=12V, VOUT =1V, L=1µH, TA=+25°C, unless otherwise noted. MPQ8632 Rev.1.24 www.MonolithicPower.com 8/28/2013 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. 17 MPQ8632 HIGH EFFICIENCY 18V SYNCHRONOUS STEP-DOWN CONVERTER FAMILY FOR 4A TO 20A BLOCK DIAGRAM IN FREQ VCC VCC EN LDO BST BIAS Minimum OFF Timer REFERENCE ON Timer BST HS Driver HS-FET LOGIC SS SW SOFT START VCC FB LS Driver FB Comparator PG UV PGOOD Comparator UV Detect Comparator OV LS-FET ZCD Current Modulator GND LS Current Limit AGND OV Detect Comparator Figure 1—Functional Block Diagram MPQ8632 Rev.1.24 www.MonolithicPower.com 8/28/2013 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. 18 MPQ8632 HIGH EFFICIENCY 18V SYNCHRONOUS STEP-DOWN CONVERTER FAMILY FOR 4A TO 20A OPERATION PWM Operation The MPQ8632 is a fully integrated synchronous rectified step-down switch mode converter. It uses Constant-on-time (COT) control to provide a fast transient response and ease loop stabilization. At the beginning of each cycle, the high-side MOSFET (HS-FET) turns ON when the feedback voltage (VFB) drops below the reference voltage (VREF), which indicates an insufficient output voltage. The input voltage and the frequency-set resistor determine the ON period as follows: TON (ns) 6.1 RFREQ (k) VIN (V) 0.4 (1) After the ON period elapses, the HS-FET turns off. It turns ON again when VFB drops below VREF. By repeating this operation, the converter regulates the output voltage. The integrated lowside MOSFET (LS-FET) turns on when the HSFET is OFF to minimize the conduction loss. There is a dead short (or shoot-through) between input and GND if both HS-FET and LSFET turn on at the same time. A dead-time (DT) internally generated between HS-FET OFF and LS-FETON, or LS-FET OFF and HS-FET ON avoids shoot-through. Heavy-Load Operation interval determined by the one- shot on-timer as per equation 1. When the HS-FET turns off, the LS-FET turns on until the next period. In CCM operation, the switching frequency is fairly constant and is also called PWM mode. Light-Load Operation As the load decreases, the inductor current decreases too. When the inductor current touches zero, the operation is transited from continuous-conduction-mode (CCM) to discontinuous-conduction-mode (DCM). Figure 3 shows the light load operation. When VFB drops below VREF, HS-FET turns on for a fixed interval determined by the one- shot ontimer as per equation 1. When the HS-FET turns off, the LS-FET turns on until the inductor current reaches zero. In DCM operation, the VFB does not reach VREF when the inductor current is approaching zero. The LS-FET driver turns into tri-state (high Z) whenever the inductor current reaches zero. A current modulator takes over the control of LS-FET and limits the inductor current less than -1mA. Hence, the output capacitors discharge slowly to GND through LS-FET. As a result, this mode improves greatly the light load efficiency. At light load condition, the HS-FET does not turns ON as frequently as at heavy load condition. This is called skip mode. At light load or no load condition, the output drops very slowly and the MPQ8632 reduces the switching frequency naturally and then achieves high efficiency at light load. Figure 2—Heavy Load Operation Figure 3—Light Load Operation When the output current is high and the inductor current is always above zero amps, it is called continuous-conduction-mode (CCM). Figure 2 shows the CCM operation. When VFB is below VREF, HS-FET turns on for a fixed MPQ8632 Rev.1.24 www.MonolithicPower.com 8/28/2013 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. 19 MPQ8632 HIGH EFFICIENCY 18V SYNCHRONOUS STEP-DOWN CONVERTER FAMILY FOR 4A TO 20A As the output current increases from the light load condition, the current modulator regulates the operating period that becomes shorter. The HS-FET turns ON more frequently. Hence, the switching frequency increases correspondingly. The output current reaches the critical level when the current modulator time decreases to zero. Determine the critical output current level as follows: IOUT ( VIN VOUT ) VOUT 2 L FSW VIN (2) Where FSW is the switching frequency. high switching frequencies allow for physically smaller LC filter components to reduce the PCB footprint. Jitter and FB Ramp Slope Figure 4 and Figure 5 show jitter occurring in both PWM mode and skip mode. When there is noise on the VFB descending slope, the HS-FET ON time deviates from its intended point and produces jitter and influences system stability. The VFB ripple’s slope steepness dominates the noise immunity though its magnitude has no direct effect. The IC turns into PWM mode once the output current exceeds the critical level. After that, the switching frequency stays fairly constant over the output current range. Switching Frequency Selecting the switching frequency requires trading off between efficiency and component size. Low frequency operation increases efficiency by reducing MOSFET switching losses, but requires larger inductor and capacitor values to minimize the output voltage ripple. Figure 4—Jitter in PWM Mode For MPQ8632，set the on time using the FREQ pin to set the frequency for steady state operation at CCM. The MPQ8632 uses adaptive constant-on-time (COT) control, though the IC lacks a dedicated oscillator. Connect the FREQ pin to the IN pin through the resistor (RFREQ) so that the input voltage is feed-forwarded to the one-shot on-time timer. When operating in steady state at CCM, the duty ratio stays at VOUT/VIN, so the switching frequency is fairly constant over the input voltage range. Set the switching frequency as follows: FSW (kHz) 106 6.1 RFREQ (k) VIN (V) TDELAY (ns) VIN (V) 0.4 VOUT (V) (3) Figure 5—Jitter in Skip Mode Ramp with a Large ESR Capacitor Using POSCAPs or other large-ESR capacitors as the output capacitor results in the ESR ripple dominating the output ripple. The ESR also significantly influences the VFB slope. Figure 6 shows the simplified equivalent circuit in PWM mode with the HS-FET off and without an external ramp circuit. Where TDELAY is the comparator delay of about 5ns. Typically, the MPQ8632 is set to 200kHz to 1MHz applications. It is optimized to operate at high switching frequencies at high efficiency: MPQ8632 Rev.1.24 www.MonolithicPower.com 8/28/2013 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. 20 MPQ8632 HIGH EFFICIENCY 18V SYNCHRONOUS STEP-DOWN CONVERTER FAMILY FOR 4A TO 20A Where: SW L VOUT FB IR4 IC4 IFB IC4 ESR R1 (6) Then estimate the ramp on VFB as: VRAMP POSCAP R2 VIN VOUT R1// R2 TON R4 C4 R1// R2 R9 (7) The VFB ripple’s descending slope then follows: Figure 6—Simplified Circuit in PWM Mode without External Ramp Compensation To realize the stability without an external ramp, usually select the ESR value as follows: TSW T ON 0 . 7 2 RESR COUT (4) VSLOPE1 L SW R4 VOUT C4 IR4 IC4 R9 (8) Equation 8 shows that if there is instability in PWM mode, reduce either R4 or C4. If C4 is irreducible due to equation 5 limitations, then reduce R4. For a stable PWM operation, design Vslope1 based on equation 9. Where TSW is the switching period. Ramp with a Small ESR Capacitor Use an external ramp when using ceramic output capacitors, because the ESR ripple is not high enough to stabilize the system. VOUT VRAMP TOFF R4 C4 VSLOPE1 TSW T ON RESR COUT I 103 0.7 2 VOUT OUT 2 L COUT TSW TON (9) Where IOUT is the load current. In skip mode, The VFB ripple’s descending slope is almost same whether the external ramp is used or not. Figure 8 shows the simplified circuit in skip mode when both the HS-FET and LS-FET are off. R1 VOUT IFB Ceramic FB FB R2 R1 COUT ROUT R2 Figure 7—Simplified Circuit in PWM Mode with External Ramp Compensation Figure 7 shows the simplified circuit in PWM mode with the HS-FET OFF and an external ramp compensation circuit (R4, C4). Design the external ramp based on the inductor ripple current. Select C4, R9, R1 and R2 to meet the following condition: 1 R1 R2 R9 2 FSW C4 5 R1 R2 1 (5) Figure 8—Simplified Circuit in skip Mode Determine the VFB ripple’s descending slope in skip mode as follows: VSLOPE2 VREF [(R1 R2) // ROUT ] COUT (10) Where ROUT is the equivalent load resistor. Figure 5 shows that VSLOPE2 in skip mode is lower than that is in PWM mode, so it is MPQ8632 Rev.1.24 www.MonolithicPower.com 8/28/2013 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. 21 MPQ8632 HIGH EFFICIENCY 18V SYNCHRONOUS STEP-DOWN CONVERTER FAMILY FOR 4A TO 20A reasonable that the jitter in skip mode is larger To achieve less jitter during ultra light load condition, reduce R1 and R2, but that will decrease the light load efficiency. Configuring the EN Control The regulator turns on when En goes high; conversely it turns off when EN goes low. Do not float the pin. For automatic start-up, pull the EN pin up to input voltage through a resistive voltage divider. Choose the values of the pull-up resistor (RUP from the IN pin to the EN pin) and the pull-down resistor (RDOWN from the EN pin to GND) to determine the automatic start-up voltage: VINSTART 1.5 (RUP RDOWN ) (V) RDOWN (11) For example, for RUP=100kΩ and RDOWN=51kΩ, the VIN-START is set at 4.44V. To reduce noise, add a 10nF ceramic capacitor from EN to GND. An internal zener diode on the EN pin clamps the EN pin voltage to prevent run away. The maximum pull up current assuming the worst case 6V for the internal zener clamp should be less than 1mA. Therefore, when driving EN with an external logic signal, use an EN voltage less than 6V. When connecting EN to IN through a pull-up resistor or a resistive voltage divider, select a resistance that ensures a maximum pull-up current less than 1mA. If using a resistive voltage divider and VIN exceeds 6V, then the minimum resistance for the pull-up resistor RUP should meet: VIN 6V 6V 1mA R UP R DOWN (12) With only RUP (the pull-down resistor, RDOWN, is not connected), then the VCC UVLO threshold determines VIN-START, so the minimum resistor value is: R UP VIN 6V () 1mA A typical pull-up resistor is 100kΩ. External VCC bias An external 5V VCC bias can disable the internal LDO, in this case, Vin can be as low as 2.5V. Soft Start The MPQ8632 employs a soft start (SS) mechanism to ensure a smooth output during power-up. When the EN pin goes high, an internal current source (20μA) charges the SS capacitor. The SS capacitor voltage takes over the REF voltage to the PWM comparator. The output voltage smoothly ramps up with the SS voltage. Once the SS voltage reaches the REF voltage, it continues ramping up while VREF takes over the PWM comparator. At this point, soft start finishes and the device enters steady state operation. Determine the SS capacitor value as follows: CSS nF TSS ms ISS A VREF V (14) If the output capacitors are large, then avoid setting a short SS time or risk hitting the current limit during SS. Use a minimum value of 4.7nF if the output capacitance value exceeds 330μF. Pre-Bias Startup The MPQ8632 has been designed for monotonic startup into pre-biased loads. If the output is prebiased to a certain voltage during startup, the IC will disable switching for both high-side and lowside switches until the voltage on the soft-start capacitor exceeds the sensed output voltage at the FB pin. Power Good (PG) The MPQ8632 has a power-good (PG) output. The PG pin is the open drain of a MOSFET. Connect it to VCC or some other voltage source that measures less than 5.5V through a pull-up resistor (typically 100kΩ). After applying the input voltage, the MOSFET turns on so that the PG pin is pulled to GND before the SS is ready. After the FB voltage reaches 91% of the REF voltage, the PG pin is pulled high after a 2.5ms delay. (13) MPQ8632 Rev.1.24 www.MonolithicPower.com 8/28/2013 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. 22 MPQ8632 HIGH EFFICIENCY 18V SYNCHRONOUS STEP-DOWN CONVERTER FAMILY FOR 4A TO 20A When the FB voltage drops to 80% of the REF voltage or exceeds 120% of the nominal REF voltage, the PG pin is pulled low. If the input supply fails to power the MPQ8632, the PG pin is also pulled low even though this pin is tied to an external DC source through a pull-up resistor (typically 100kΩ). Over-Current Protection (OCP) The MPQ8632 features three current limit levels for over-current conditions: high-side peak current limit, low-side valley current limit and lowside negative current limit. However, the OCP operation mechanism of MPQ8632GL-10 is different from other parts in this family. For MPQ8632GLE-10: High-Side Peak Current Limit: The part has a cycle-by-cycle over-current limiting function. The device monitors the inductor current during the HS-FET ON state. When the sensed inductor current hits the peak current limit, the output over-current comparator goes high, the device enters OCP mode immediately and turns off the HS-FET and turns on the LS-FET. Low-Side Valley Current Limit: The device also monitors the inductor current during the LS-FET ON state. When ILIM=1 and at the end of the OFF time, the LS-FET sourcing current is compared to the internal positive-valley–current limit. If the valley current limit is less than the LSFET sourcing current, the HS-FET remains OFF and the LS-FET remains ON for the next ON time. When the LS-FET sourcing current drops below the valley current limit, the HS-FET turns on again. For other parts except MPQ8632GLE-10: These parts enter OCP mode if only the LS-FET sourcing valley current exceeds the valley current limit. Once the OCP is triggered, the LS-FET keeps ON state until the LS-FET sourcing valley current is less than the valley current limit. And then the LS-FET turns off, the HS-FET turns on for a fixed time determined by frequency-set resistor RFREQ and input voltage. soft-start capacitor and then automatically retries soft-start. If the over-current condition still holds after soft-start ends, the device repeats this operation cycle until the over-current conditions disappear and then output rises back to regulation level. OCP offers non-latch protection. Low-Side Negative Current Limit: If the sensed LS-FET negative current exceeds the negative current limit, the LS-FET turns off immediately and stays OFF for the remainder of the OFF period. In this situation, both MOSFETs are OFF until the end of a fixed interval. The HS-FET body diode conducts the inductor current for the fixed time. Over -Voltage Protection (OVP) The MPQ8632 monitors the output voltage using the FB pin connected to the tap of a resistor divider to detect over-voltage. MPQ8632 and MPQ8632H provide non-latch and latch off OVP mode as showed in Table 1. Table 1—OVP Mode OVP Mode Part # Non-Latch Mode Latch-Off Mode MPQ8632-4 MPQ8632-6 MPQ8632-8 MPQ8632H-10 MPQ8632-12 MPQ8632-15 MPQ8632-20 MPQ8632-10 For MPQ8632GLE-10: If the FB voltage exceeds the nominal REF voltage but remains lower than 120% of the REF voltage (0.611V), both MOSFETs are off. If the FB voltage exceeds 120% of the REF voltage but remains below 130%, the LS-FET turns on while the HS-FET remains off. The LSFET remains on until the FB voltage drops below 110% of the REF voltage or the low-side negative current limit is hit. If the FB voltage exceeds 130% of the REF voltage, then the device is latched off. Need cycle the input power supply or EN to restart. During OCP, the device tries to recover from the over-current fault with hiccup mode: the chip disables the output power stage, discharges the MPQ8632 Rev.1.24 www.MonolithicPower.com 8/28/2013 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. 23 MPQ8632 HIGH EFFICIENCY 18V SYNCHRONOUS STEP-DOWN CONVERTER FAMILY FOR 4A TO 20A For other parts except MPQ8632GLE-10: Even the FB voltage exceeds 130% of the REF voltage, these parts enter a non-latch off mode. Once the FB voltage comes back to the reasonable value, they will exit this OVP mode and operate normally again. UVLO protection Thermal Shutdown The MPQ8632 has thermal shutdown. The IC internally monitors the junction temperature. If the junction temperature exceeds the threshold value (minimum 150ºC), the converter shuts off. This is a non-latch protection. There is about 25ºC hysteresis. Once the junction temperature drops to about 125ºC, it initiates a soft startup. The MPQ8632 has under-voltage lock-out protection (UVLO). When the VCC voltage exceeds the UVLO rising threshold voltage, the MPQ8632 powers up. It shuts off when the VCC voltage falls below the UVLO falling threshold voltage. This is non-latch protection. The MPQ8632 is disabled when the VCC voltage falls below 3.3 V. If an application requires a higher UVLO threshold, use the two external resistors connected to the EN pin as shown in Figure 9 to adjust the startup input voltage. For best results, use the enable resistors to set the input voltage falling threshold (VSTOP) above 3.6 V. Set the rising threshold (VSTART) to provide enough hysteresis to account for any input supply variations. IN RUP R DOWN EN Comparator EN Figure 9—Adjustable UVLO Threshold MPQ8632 Rev.1.24 www.MonolithicPower.com 8/28/2013 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. 24 MPQ8632 HIGH EFFICIENCY 18V SYNCHRONOUS STEP-DOWN CONVERTER FAMILY FOR 4A TO 20A APPLICATION INFORMATION Setting the Capacitors Output Voltage-Large ESR For applications that electrolytic capacitor or POS capacitor with a large ESR is set as output capacitors. The feedback resistors—R1 and R2 as shown in Figure 10—set the output voltage. SW L VOUT FB ESR R1 R1 Figure10—Simplified POSCAP Circuit First, choose a value for R2 that balances between high quiescent current loss (low R2) and high noise sensitivity on FB (high R2). A typical value falls within 5kΩ to 50kΩ, using a comparatively larger R2 when VOUT is low, and a smaller R2 when VOUT is high. Then calculate R1 as follows, which considers the output ripple: (15) Where VOUT is the output ripple determined by equation 24. Setting the Capacitors Output SW FB Voltage-Small L R4 ESR VOUT C4 R2 VFB( AVG) VOUT VFB( AVG) POSCAP R2 1 VOUT VOUT VREF 2 R1 R2 VREF to the FB pin consisting of R4 and C4.The ramp voltage, VRAMP, and the resistor divider influence the output voltage as shown in Figure 11. Calculate VRAMP as shown in equation 7. Select R2 to balance between high quiescent current loss and FB noise sensitivity. Choose R2 within 5kΩ to 50kΩ, using a larger R2 when VOUT is low, and a smaller R2 when VOUT is high. Determine the value of R1 as follows: R1 R9 Ceramic R2 (16) R2 R4 R9 Where VFB(AVG) is the average FB voltage. VFB(AVG) varies with the VIN, VOUT, and load condition, where the load regulation is strictly related to the VFB(AVG). Also the line regulation is related to the VFB(AVG); improving the load or line regulation involves a lower VRAMP that meets equation 9. For PWM operation, estimate VFB(AVG) from equation 17. VFB( AVG) VREF 1 R1// R2 VRAMP 2 R1// R2 R9 (17) Usually, R9 is 0Ω, though it can also be set following equation 18 for better noise immunity. It should also be less than 20% of R1//R2 to minimize its influence on VRAMP. 1 R1 R2 (18) R9 5 R1 R2 Using equations 16 and 17 to calculate the output voltage can be complicated. To simplify the R1 calculation in equation 16, add a DCblocking capacitor, CDC, to filter the DC influence from R4 and R9. Figure 12 shows a simplified circuit with external ramp compensation and a DC-blocking capacitor. The addition of this capacitor, simplifies the R1 calculation as per equation 19 for PWM mode operation. Figure11—Simplified Ceramic Capacitor Circuit When using a low ESR ceramic capacitor on the output, add an external voltage ramp MPQ8632 Rev.1.24 www.MonolithicPower.com 8/28/2013 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. 25 MPQ8632 HIGH EFFICIENCY 18V SYNCHRONOUS STEP-DOWN CONVERTER FAMILY FOR 4A TO 20A R1 1 VRAMP 2 R2 1 VRAMP 2 VOUT VREF VREF (19) For best results, select a CDC Value at least 10× C4 for better DC blocking performance, but smaller than 0.47µF account for start-up performance. To use a larger CDC for better FB noise immunity, reduce R1 and R2 to limit effects on system start-up. Note that even with Cdc, the load and line regulation are still related to VRAMP. SW FB L VOUT R4 C4 Ceramic R2 Figure12—Simplified Ceramic Capacitor Circuit with DC Blocking Capacitor Input Capacitor The input current to the step-down converter is discontinuous, and therefore, requires a capacitor to supply the AC current to the stepdown converter while maintaining the DC input voltage. Use ceramic capacitors for best performance. During layout, Place the input capacitors as close to the IN pin as possible. The capacitance can vary significantly with temperature. Use capacitors with X5R and X7R ceramic dielectrics because they are fairly stable over a wide temperature range. The capacitors must also have a ripple current rating that exceeds the converter’s maximum input ripple current. Estimate the input ripple current as follows: ICIN IOUT VOUT V (1 OUT ) VIN VIN For simplification, choose an input capacitor with an RMS current rating that exceeds half the maximum load current. The input capacitance value determines the converter input voltage ripple. Select a capacitor value that meets any input voltage ripple requirements. Estimate the input voltage ripple as follows: IOUT V V (22) VIN OUT (1 OUT ) FSW CIN VIN VIN R1 C DC The worst-case condition occurs at VIN = 2VOUT, where: I ICIN OUT (21) 2 (20) The worst-case condition occurs at VIN = 2VOUT, where: IOUT 1 (23) VIN 4 FSW CIN Output Capacitor The output capacitor maintains the DC output voltage. Use ceramic capacitors or POSCAPs. Estimate the output voltage ripple as: VOUT VOUT V 1 (1 OUT ) (RESR ) FSW L VIN 8 FSW COUT (24) When using ceramic capacitors, the capacitance dominates the impedance at the switching frequency. The capacitance also dominates the output voltage ripple. For simplification, estimate the output voltage ripple as: VOUT VOUT 8 FSW L COUT 2 (1 VOUT ) VIN (25) The ESR only contributes minimally to the output voltage ripple, thus requiring an external ramp to stabilize the system. Design the external ramp with R4 and C4 as per equation 5, 8 and 9. MPQ8632 Rev.1.24 www.MonolithicPower.com 8/28/2013 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. 26 MPQ8632 HIGH EFFICIENCY 18V SYNCHRONOUS STEP-DOWN CONVERTER FAMILY FOR 4A TO 20A The ESR dominates the switching-frequency impedance for POSCAPs,. The ESR ramp voltage is high enough to stabilize the system. thus eliminating the need for an external ramp. Select a minimum ESR value around 12mΩ to ensure stable operation. For simplification, the output ripple can be approximated as: VOUT VOUT V (1 OUT ) RESR FSW L VIN (26) Inductor The inductor supplies constant current to the output load while being driven by the switching input voltage. A larger value inductor results in less ripple current and lower output ripple voltage, but is larger physical size, has a higher series resistance, and/or lower saturation current. Generally, select an inductor value that allows the inductor peak-to-peak ripple current to 30% to 40% of the maximum switch current limit. Also, design for a peak inductor current that is below the maximum switch current limit. Calculate the inductance value as: L VOUT V (1 OUT ) FSW IL VIN (27) Where ΔIL is the peak-to-peak inductor ripple current. Choose an inductor that will not saturate under the maximum inductor peak current. The peak inductor current can be calculated as: ILP IOUT VOUT V (1 OUT ) 2 FSW L VIN (28) Table 2 lists a few highly-recommended highefficiency inductors. Table 2—Inductor Selection Guide Part Number Manufacturer Inductance (µH) DCR (mΩ) Current Rating (A) Dimensions 3 L x W x H (mm ) 744325072 FDU1250C-1R0M FDA1055-1R5M 744325180 FDA1055-2R2M FDA1055-3R3M HC7-3R9-R Wurth TOKO TOKO Wurth TOKO TOKO Cooper 0.72 1 1.5 1.8 2.2 3.3 3.9 1.35 1.72 2.8 3.5 3.94 5.92 7.9 35 31.3 24 18 20.6 15.6 10.6 10.2 x 10.5 x 4.7 13.3 x 12.1 x 5 11.6 x 10.8 x 5.5 10.2 x 10.5 x 4.7 11.6 x 10.8 x 5.5 11.6 x 10.8 x 5.5 13.8 x 13 x 5.5 Typical Design Parameter Tables The following tables include recommended component values for typical output voltages (1V, 2.5V, 3.3V) and switching frequency (500kHz). Refer to Tables 3-9 for design cases without external ramp compensation. And Tables 10-16 are for design cases with external ramp compensation. An external ramp is not needed when using high-ESR output capacitors, such as electrolytic or POSCAPs. Use an external ramp when using low-ESR capacitors, such as ceramic capacitors. For cases not listed in this datasheet, an excel spreadsheet provided by local sales representatives can assist with the calculations. Switching Frequency (kHz) 500 500 500 500 500 500 500 Table 3—MPQ8632-4, FSW=500kHz, VIN=12V VOUT (V) 1 L (μH) 1.8 R1 (kΩ) 13.3 R2 (kΩ) 20 R7 (kΩ) 357 2.5 3.3 3.3 3.9 63.4 91 20 20 887 1200 Table 4—MPQ8632-6, FSW=500kHz, VIN=12V VOUT (V) 1 2.5 3.3 L (μH) 1 2.2 3.3 R1 (kΩ) 13.3 63.4 91 R2 (kΩ) 20 20 20 MPQ8632 Rev.1.24 www.MonolithicPower.com 8/28/2013 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. R7 (kΩ) 357 887 1200 27 MPQ8632 HIGH EFFICIENCY 18V SYNCHRONOUS STEP-DOWN CONVERTER FAMILY FOR 4A TO 20A Table 5—MPQ8632-8, FSW=500kHz, VIN=12V Table 11—MPQ8632-6, FSW=500kHz, VIN=12V VOUT (V) 1 L (μH) 0.72 R1 (kΩ) 13.3 R2 (kΩ) 20 R7 (kΩ) 357 VOUT (V) 1 L (μH) 1 R1 (kΩ) 13.7 R2 (kΩ) 20 R4 (kΩ) 750 C4 (pF) 220 R7 (kΩ) 357 2.5 3.3 1.8 2.2 63.4 91 20 20 887 1200 2.5 3.3 2.2 3.3 66.5 95.3 20 20 1000 1200 220 220 887 1200 Table 6—MPQ8632-10, MPQ8632H-10, FSW=500kHz, VIN=12V VOUT (V) 1 2.5 3.3 L (μH) 0.72 1.5 1.8 R1 (kΩ) 13.3 63.4 91 R2 (kΩ) 20 20 20 R7 (kΩ) 357 887 1200 Table 7—MPQ8632-12, FSW=500kHz, VIN=12V VOUT (V) 1 2.5 3.3 L (μH) 0.72 1.5 1.8 R1 (kΩ) 13.3 63.4 91 R2 (kΩ) 20 20 20 R7 (kΩ) 357 887 1200 Table 8—MPQ8632GVE-15, FSW=500kHz, VIN=12V VOUT (V) 1 2.5 3.3 L (μH) 0.72 0.72 1 R1 (kΩ) 13.3 63.4 91 R2 (kΩ) 20 20 20 R7 (kΩ) 357 887 1200 Table 9— MPQ8632GVE-20, FSW=500kHz, VIN=12V VOUT (V) 1 2.5 L (μH) 0.72 0.72 R1 (kΩ) 13.3 63.4 R2 (kΩ) 20 20 R7 (kΩ) 357 887 3.3 0.72 91 20 1200 Table 10—MPQ8632-4, FSW=500kHz, VIN=12V Table 12—MPQ8632-8, FSW=500kHz, VIN=12V VOUT (V) 1 2.5 3.3 L (μH) 0.72 1.8 2.2 R1 (kΩ) 13.7 66.5 95.3 R2 (kΩ) 20 20 20 R4 (kΩ) 750 1000 1200 C4 (pF) 220 220 220 R7 (kΩ) 357 887 1200 Table 13—MPQ8632-10, MPQ8632H-10, FSW=500kHz, VIN=12V VOUT (V) 1 2.5 3.3 L (μH) 0.72 1.5 1.8 R1 (kΩ) 13.7 66.5 95.3 R2 (kΩ) 20 20 20 R4 (kΩ) 750 1000 1200 C4 (pF) 220 220 220 R7 (kΩ) 357 887 1200 Table 14—MPQ8632-12, FSW=500kHz, VIN=12V VOUT (V) 1 2.5 L (μH) 0.72 1.5 R1 (kΩ) 13.7 66.5 R2 (kΩ) 20 20 R4 (kΩ) 750 1000 C4 (pF) 220 220 R7 (kΩ) 357 887 3.3 1.8 95.3 20 1200 220 1200 Table 15—MPQ8632GVE-15, FSW=500kHz, VIN=12V VOUT (V) 1 2.5 3.3 L (μH) 0.72 0.72 1 R1 (kΩ) 13.7 68 95.3 R2 (kΩ) 20 20 20 R4 (kΩ) 750 1000 1200 C4 (pF) 220 220 220 R7 (kΩ) 357 887 1200 Table 16—MPQ8632GVE-20, FSW=500kHz, VIN=12V VOUT (V) 1 L (μH) 1.8 R1 (kΩ) 13.7 R2 (kΩ) 20 R4 (kΩ) 750 C4 (pF) 220 R7 (kΩ) 357 VOUT (V) 1 L (μH) 0.72 R1 (kΩ) 13.7 R2 (kΩ) 20 R4 (kΩ) 750 C4 (pF) 220 R7 (kΩ) 357 2.5 3.3 3.3 3.9 66.5 95.3 20 20 1000 1200 220 220 887 1200 2.5 3.3 0.72 0.72 68 95.3 20 20 1000 1200 220 220 887 1200 MPQ8632 Rev.1.24 www.MonolithicPower.com 8/28/2013 MPS Proprietary Information. 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All Rights Reserved. 28 MPQ8632 HIGH EFFICIENCY 18V SYNCHRONOUS STEP-DOWN CONVERTER FAMILY FOR 4A TO 20A TYPICAL APPLICATION (7) R3 V IN BST IN C1A 10uF C1B 10uF C1C C1D 0 R7 C3 0.1uF L1 1uH, TOKO FDU1250C-1R0M R5 0.1uF 0.1uF 357K 100K SW FREQ VOUT R1 + 13.7K EN R6 1uF 100K C2B 0.1uF MPQ8632 FB VCC C5 C2A 220uF/20mΩ R2 SS 20K C6 33nF PG PGND AGND Figure 13 — Typical Application Circuit with No External Ramp MPQ8632-10, VIN=12V, VOUT=1V, IOUT=10A, FSW=500kHz R3 V IN BST IN C1A 10uF C1B 10uF C1C C1D 0.1uF 0.1uF R7 0 R5 357K 100K C3 0.1uF L1 1uH, TOKO FDU1250C-1R0M SW FREQ VOUT R4 330K EN MPQ8632 FB VCC C5 R6 1uF 100K C4 220pF R9 100 R1 13.7K C2A C2B C2C 47uF 47uF 47uF 0.1uF C2D C2E 0.1uF R2 SS 20K C6 33nF PG PGND AGND Figure 14 — Typical Application Circuit with Low ESR Ceramic Capacitor MPQ8632-10, VIN=12V, VOUT=1V, IOUT=10A, FSW=500kHz V IN BST IN C1A 10uF C1B 10uF C1C C1D 0.1uF 0.1uF R7 R5 357K 100K 0 C3 0.1uF L1 1uH, TOKO FDU1250C-1R0M SW VOUT FREQ R4 330K EN MPQ8632 FB VCC C5 R6 1uF 100K C4 220pF CDC 10nF R1 13.7K C2A C2B C2C 47uF 47uF 47uF 0.1uF C2D C2E 0.1uF R2 SS C6 33nF PG PGND 20K AGND Figure 15 — Typical Application Circuit with Low ESR Ceramic Capacitor and DC-Blocking Capacitor. MPQ8632-10, VIN=12V, VOUT=1V, IOUT=10A, FSW=500kHz MPQ8632 Rev.1.24 www.MonolithicPower.com 8/28/2013 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. 29 MPQ8632 HIGH EFFICIENCY 18V SYNCHRONOUS STEP-DOWN CONVERTER FAMILY FOR 4A TO 20A Figure 16 — Efficiency Curve MPQ8632-10, VOUT=1V, IOUT=0.01A-10A, FSW=500kHz R3 V IN BST IN C1A C1B 10uF 10uF C1C C1D 0.1uF 0.1uF R7 R5 604K 100K 0 C3 0.1uF L1 1uH, TOKO FDU1250C-1R0M SW FREQ VOUT R4 270K EN MPQ8632 FB VCC C5 R6 1uF 100K C4 390pF R9 100 R1 13.7K C2A C2B C2C 47uF 47uF 47uF 0.1uF C2D C2E 0.1uF R2 SS C6 33nF PG PGND 20K AGND Figure 17 — Typical Application Circuit with Low ESR Ceramic Capacitor MPQ8632-10, VIN=12V, VOUT=1V, IOUT=10A, FSW=300kHz Figure 18 — Efficiency Curve MPQ8632-10, VOUT=1V, IOUT=0.01A-10A, FSW=300kHz MPQ8632 Rev.1.24 www.MonolithicPower.com 8/28/2013 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. 30 MPQ8632 HIGH EFFICIENCY 18V SYNCHRONOUS STEP-DOWN CONVERTER FAMILY FOR 4A TO 20A R3 V IN BST IN C1A 10uF C1B 10uF C1C C1D 0.1uF 0.1uF R7 0 R5 220K 100K C3 0.1uF L1 1uH, TOKO FDU1250C-1R0M SW FREQ VOUT R4 301K EN MPQ8632 FB VCC C5 R6 1uF 100K C4 220pF R9 100 R1 28K C2A C2B C2C 47uF 47uF 47uF 0.1uF C2D C2E 0.1uF R2 SS 40.2K C6 33nF PG PGND AGND Figure 19 — Typical Application Circuit with Low ESR Ceramic Capacitor MPQ8632-10, VIN=12V, VOUT=1V, IOUT=10A, FSW=800kHz Figure 20 — Efficiency Curve MPQ8632-10, VOUT=1V, IOUT=0.01A-10A, FSW=800kHz R3 V IN BST IN C1A 10uF C1B 10uF C1C C1D 0.1uF 0.1uF R7 R5 475K 100K 0 C3 0.1uF L1 1uH, TOKO FDU1250C-1R0M SW FREQ VOUT R4 330K EN MPQ8632 FB VCC C5 R6 1uF 100K C4 330pF R9 100 R1 12.7K C2A C2B C2C 47uF 47uF 47uF 0.1uF C2D C2E 0.1uF R2 SS C6 33nF PG PGND 40.2K AGND Figure 21 — Typical Application Circuit with Low ESR Ceramic Capacitor MPQ8632-10, VIN=12V, VOUT=0.8V, IOUT=10A, FSW=300kHz MPQ8632 Rev.1.24 www.MonolithicPower.com 8/28/2013 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. 31 MPQ8632 HIGH EFFICIENCY 18V SYNCHRONOUS STEP-DOWN CONVERTER FAMILY FOR 4A TO 20A Figure 22 — Efficiency Curve MPQ8632-10, VOUT=0.8V, IOUT=0.01A-10A, FSW=300kHz R3 V IN BST IN C1A 10uF C1B 10uF C1C C1D 0.1uF 0.1uF R7 R5 287K 100K 0 C3 0.1uF L1 1uH, TOKO FDU1250C-1R0M SW FREQ VOUT R4 330K EN MPQ8632 FB VCC C5 R6 1uF 100K C4 220pF R9 100 R1 12.7K C2A C2B C2C 47uF 47uF 47uF 0.1uF C2D C2E 0.1uF R2 SS C6 33nF PG PGND 40.2K AGND Figure 23 — Typical Application Circuit with Low ESR Ceramic Capacitor MPQ8632-10, VIN=12V, VOUT=0.8V, IOUT=10A, FSW=500kHz Figure 24 — Efficiency Curve MPQ8632-10, VOUT=0.8V, IOUT=0.01A-10A, FSW=500kHz MPQ8632 Rev.1.24 www.MonolithicPower.com 8/28/2013 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. 32 MPQ8632 HIGH EFFICIENCY 18V SYNCHRONOUS STEP-DOWN CONVERTER FAMILY FOR 4A TO 20A R3 V IN BST IN C1A 10uF C1B 10uF C1C C1D 0.1uF 0.1uF R7 0 R5 715K 100K C3 0.1uF L1 2.2uH, TOKO FDA1254-2R2M SW FREQ VOUT R4 330K EN MPQ8632 FB VCC C5 R6 1uF 100K C4 330pF R9 100 R1 20.5K C2A C2B C2C 47uF 47uF 47uF 0.1uF C2D C2E 0.1uF R2 SS 20K C6 33nF PG PGND AGND Figure 25 — Typical Application Circuit with Low ESR Ceramic Capacitor MPQ8632-10, VIN=12V, VOUT=1.2V, IOUT=10A, FSW=300kHz Figure 26 — Efficiency Curve MPQ8632-10, VOUT=1.2V, IOUT=0.01A-10A, FSW=300kHz R3 V IN BST IN C1A 10uF C1B 10uF C1C C1D 0.1uF 0.1uF R7 R5 432K 100K 0 C3 0.1uF L1 1uH, TOKO FDU1250C-1R0M SW FREQ VOUT R4 220K EN MPQ8632 FB VCC C5 R6 1uF 100K C4 330pF R9 100 R1 10K C2A C2B C2C 47uF 47uF 47uF 0.1uF C2D C2E 0.1uF R2 SS C6 33nF PG PGND 10K AGND Figure 27 — Typical Application Circuit with Low ESR Ceramic Capacitor MPQ8632-10, VIN=12V, VOUT=1.2V, IOUT=10A, FSW=500kHz MPQ8632 Rev.1.24 www.MonolithicPower.com 8/28/2013 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. 33 MPQ8632 HIGH EFFICIENCY 18V SYNCHRONOUS STEP-DOWN CONVERTER FAMILY FOR 4A TO 20A Figure 28 — Efficiency Curve MPQ8632-10, VOUT=1.2V, IOUT=0.01A-10A, FSW=500kHz R3 V IN BST IN C1A 10uF C1B 10uF C1C C1D 0.1uF 0.1uF R7 R5 270K 100K 0 C3 0.1uF L1 1uH, TOKO FDU1250C-1R0M SW FREQ VOUT R4 220K EN MPQ8632 FB VCC C5 R6 1uF 100K C4 220pF R9 100 R1 10K C2A C2B C2C 47uF 47uF 47uF 0.1uF C2D C2E 0.1uF R2 SS C6 33nF PG PGND 10K AGND Figure 29 — Typical Application Circuit with Low ESR Ceramic Capacitor MPQ8632-10, VIN=12V, VOUT=1.2V, IOUT=10A, FSW=800kHz Figure 30 — Efficiency Curve MPQ8632-10, VOUT=1.2V, IOUT=0.01A-10A, FSW=800kHz MPQ8632 Rev.1.24 www.MonolithicPower.com 8/28/2013 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. 34 MPQ8632 HIGH EFFICIENCY 18V SYNCHRONOUS STEP-DOWN CONVERTER FAMILY FOR 4A TO 20A R3 V IN BST IN C1A 10uF C1B 10uF C1C C1D 0.1uF 0.1uF R7 0 R5 887K 100K C3 0.1uF L1 2.2uH, TOKO FDA1254-2R2M SW FREQ VOUT R4 470K EN MPQ8632 FB VCC C5 R6 1uF 100K C4 470pF R9 100 R1 15K C2A C2B C2C 47uF 47uF 47uF 0.1uF C2D C2E 0.1uF R2 SS 10K C6 33nF PG PGND AGND Figure 31 — Typical Application Circuit with Low ESR Ceramic Capacitor MPQ8632-10, VIN=12V, VOUT=1.5 V, IOUT=10A, FSW=300kHz Figure 32 — Efficiency Curve MPQ8632-10, VOUT=1.5V, IOUT=0.01A-10A, FSW=300kHz R3 V IN BST IN C1A 10uF C1B 10uF C1C C1D 0.1uF 0.1uF R7 R5 536K 100K 0 C3 0.1uF L1 1.2uH, TOKO FDA1254-1R2M SW FREQ VOUT R4 470K EN MPQ8632 FB VCC C5 R6 1uF 100K C4 330pF R9 100 R1 15.4K C2A C2B C2C 47uF 47uF 47uF 0.1uF C2D C2E 0.1uF R2 SS C6 33nF PG PGND 10K AGND Figure 33 — Typical Application Circuit with Low ESR Ceramic Capacitor MPQ8632-10, VIN=12V, VOUT=1.5 V, IOUT=10A, FSW=500kHz MPQ8632 Rev.1.24 www.MonolithicPower.com 8/28/2013 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. 35 MPQ8632 HIGH EFFICIENCY 18V SYNCHRONOUS STEP-DOWN CONVERTER FAMILY FOR 4A TO 20A Figure 34 — Efficiency Curve MPQ8632-10, VOUT=1.5V, IOUT=0.01A-10A, FSW=500kHz R3 V IN BST IN C1A C1B 10uF 10uF C1C C1D 0.1uF 0.1uF R7 R5 332K 100K 0 C3 0.1uF L1 1.2uH, TOKO FDA1254-1R2M SW FREQ VOUT R4 470K EN MPQ8632 FB VCC C5 R6 1uF 100K C4 220pF R9 100 R1 15.4K C2A C2B C2C 47uF 47uF 47uF 0.1uF C2D C2E 0.1uF R2 SS C6 33nF PG PGND 10K AGND Figure 35 — Typical Application Circuit with Low ESR Ceramic Capacitor MPQ8632-10, VIN=12V, VOUT=1.5 V, IOUT=10A, FSW=800kHz Figure 36 — Efficiency Curve MPQ8632-10, VOUT=1.5V, IOUT=0.01A-10A, FSW=800kHz MPQ8632 Rev.1.24 www.MonolithicPower.com 8/28/2013 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. 36 MPQ8632 HIGH EFFICIENCY 18V SYNCHRONOUS STEP-DOWN CONVERTER FAMILY FOR 4A TO 20A R3 V IN BST IN C1A 10uF C1B 10uF C1C C1D 0.1uF 0.1uF R7 0 R5 1.1M 100K C3 0.1uF L1 2.2uH, TOKO FDA1254-2R2M SW FREQ VOUT R4 470K EN MPQ8632 FB VCC C5 R6 1uF 100K C4 220pF R9 100 R1 19.6K C2A C2B C2C 47uF 47uF 47uF 0.1uF C2D C2E 0.1uF R2 SS 10K C6 33nF PG PGND AGND Figure 37 — Typical Application Circuit with Low ESR Ceramic Capacitor MPQ8632-10, VIN=12V, VOUT=1.8 V, IOUT=10A, FSW=300kHz Figure 38 — Efficiency Curve MPQ8632-10, VOUT=1.8V, IOUT=0.01A-10A, FSW=300kHz R3 V IN BST IN C1A 10uF C1B 10uF C1C C1D 0.1uF 0.1uF R7 R5 634K 100K 0 C3 0.1uF L1 2.2uH, TOKO FDA1254-2R2M SW FREQ VOUT R4 470K EN MPQ8632 FB VCC C5 R6 1uF 100K C4 220pF R9 100 R1 21K C2A C2B C2C 47uF 47uF 47uF 0.1uF C2D C2E 0.1uF R2 SS C6 33nF PG PGND 10K AGND Figure 39 — Typical Application Circuit with Low ESR Ceramic Capacitor MPQ8632-10, VIN=12V, VOUT=1.8 V, IOUT=10A, FSW=500kHz MPQ8632 Rev.1.24 www.MonolithicPower.com 8/28/2013 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. 37 MPQ8632 HIGH EFFICIENCY 18V SYNCHRONOUS STEP-DOWN CONVERTER FAMILY FOR 4A TO 20A Figure 40 — Efficiency Curve MPQ8632-10, VOUT=1.8V, IOUT=0.01A-10A, FSW=500kHz V IN BST IN C1A C1B RFREQ C1C C3 L1 SW VOUT FREQ R5 R4 C4 R1 EN MPQ8632 FB VCC C5 C2 R3 SS R2 C6 PG PGND AGND Figure 41 — Typical Application Circuit with Low ESR Ceramic Capacitor MPQ8632-10, VIN=12V, VOUT=1.8 V, IOUT=10A, FSW=800kHz Figure 42 — Efficiency Curve MPQ8632-10, VOUT=1.8V, IOUT=0.01A-10A, FSW=800kHz MPQ8632 Rev.1.24 www.MonolithicPower.com 8/28/2013 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. 38 MPQ8632 HIGH EFFICIENCY 18V SYNCHRONOUS STEP-DOWN CONVERTER FAMILY FOR 4A TO 20A R3 V IN BST IN C1A 10uF C1B 10uF C1C C1D 0.1uF 0.1uF R7 0 R5 2M 100K C3 0.1uF L1 2.2uH, TOKO FDA1254-2R2M SW FREQ VOUT R4 470K EN MPQ8632 FB VCC C5 R6 1uF 100K C4 220pF R9 100 R1 48.7K C2A C2B C2C 47uF 47uF 47uF 0.1uF C2D C2E 0.1uF R2 SS 10K C6 33nF PG PGND AGND Figure 43 — Typical Application Circuit with Low ESR Ceramic Capacitor MPQ8632-10, VIN=12V, VOUT=3.3 V, IOUT=10A, FSW=300kHz Figure 44 — Efficiency Curve MPQ8632-10, VOUT=3.3V, IOUT=0.01A-10A, FSW=300kHz R3 V IN BST IN C1A 10uF C1B 10uF C1C C1D 0.1uF 0.1uF R7 R5 1.2M 100K 0 C3 0.1uF L1 2.2uH, TOKO FDA1254-2R2M SW FREQ VOUT R4 470K EN MPQ8632 FB VCC C5 R6 1uF 100K C4 220pF R9 100 R1 48.7K C2A C2B C2C 47uF 47uF 47uF 0.1uF C2D C2E 0.1uF R2 SS C6 33nF PG PGND 10K AGND Figure 45 — Typical Application Circuit with Low ESR Ceramic Capacitor MPQ8632-10, VIN=12V, VOUT=3.3 V, IOUT=10A, FSW=500kHz MPQ8632 Rev.1.24 www.MonolithicPower.com 8/28/2013 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. 39 MPQ8632 HIGH EFFICIENCY 18V SYNCHRONOUS STEP-DOWN CONVERTER FAMILY FOR 4A TO 20A Figure 46 — Efficiency Curve MPQ8632-10, VOUT=3.3V, IOUT=0.01A-10A, FSW=500kHz R3 V IN BST IN C1A 10uF C1B 10uF C1C C1D 0.1uF 0.1uF R7 R5 715K 100K 0 C3 0.1uF L1 2.2uH, TOKO FDA1254-2R2M SW FREQ VOUT R4 470K EN MPQ8632 FB VCC C5 R6 1uF 100K C4 220pF R9 100 R1 48.7K C2A C2B C2C 47uF 47uF 47uF 0.1uF C2D C2E 0.1uF R2 SS C6 33nF PG PGND 10K AGND Figure 47 — Typical Application Circuit with Low ESR Ceramic Capacitor MPQ8632-10, VIN=12V, VOUT=3.3 V, IOUT=10A, FSW=800kHz Figure 48 — Efficiency Curve MPQ8632-10, VOUT=3.3V, IOUT=0.01A-10A, FSW=800kHz MPQ8632 Rev.1.24 www.MonolithicPower.com 8/28/2013 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. 40 MPQ8632 HIGH EFFICIENCY 18V SYNCHRONOUS STEP-DOWN CONVERTER FAMILY FOR 4A TO 20A R3 V IN BST IN C1A 10uF C1B 10uF C1C C1D 0.1uF 0.1uF R7 0 R5 2.7M 100K C3 0.1uF L1 3.3uH, TOKO FDA1254-3R3M SW FREQ VOUT R4 470K EN MPQ8632 FB VCC C5 R6 1uF 100K C4 330pF R9 100 R1 82.5K C2A C2B C2C 47uF 47uF 47uF 0.1uF C2D C2E 0.1uF R2 SS 10K C6 33nF PG PGND AGND Figure 49 — Typical Application Circuit with Low ESR Ceramic Capacitor MPQ8632-10, VIN=12V, VOUT=5 V, IOUT=10A, FSW=300kHz Figure 50 — Efficiency Curve MPQ8632-10, VOUT=5V, IOUT=0.01A-10A, FSW=300kHz R3 V IN BST IN C1A 10uF C1B 10uF C1C C1D 0.1uF 0.1uF R7 R5 1.8M 100K 0 C3 0.1uF L1 3.3uH, TOKO FDA1254-3R3M SW FREQ VOUT R4 470K EN MPQ8632 FB VCC C5 R6 1uF 100K C4 330pF R9 100 R1 84.5K C2A C2B C2C 47uF 47uF 47uF 0.1uF C2D C2E 0.1uF R2 SS C6 33nF PG PGND 10K AGND Figure 51 — Typical Application Circuit with Low ESR Ceramic Capacitor MPQ8632-10, VIN=12V, VOUT=5 V, IOUT=10A, FSW=500kHz MPQ8632 Rev.1.24 www.MonolithicPower.com 8/28/2013 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. 41 MPQ8632 HIGH EFFICIENCY 18V SYNCHRONOUS STEP-DOWN CONVERTER FAMILY FOR 4A TO 20A Figure 52 — Efficiency Curve MPQ8632-10, VOUT=5V, IOUT=0.01A-10A, FSW=500kHz R3 V IN BST IN C1A 10uF C1B 10uF C1C C1D 0.1uF 0.1uF R7 R5 1.1M 100K 0 C3 0.1uF L1 1uH, TOKO FDU1250C-1R0M SW FREQ VOUT R4 330K EN MPQ8632 FB VCC C5 R6 1uF 100K C4 220pF R9 100 R1 82K C2A C2B C2C 47uF 47uF 47uF 0.1uF C2D C2E 0.1uF R2 SS C6 33nF PG PGND 10K AGND Figure 53 — Typical Application Circuit with Low ESR Ceramic Capacitor MPQ8632-10, VIN=12V, VOUT=5 V, IOUT=10A, FSW=800kHz Figure 54 — Efficiency Curve MPQ8632-10, VOUT=5V, IOUT=0.01A-10A, FSW=800kHz NOTE: 7) The all application circuits’ steady states are OK, but other performances are not tested. MPQ8632 Rev.1.24 www.MonolithicPower.com 8/28/2013 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. 42 MPQ8632 HIGH EFFICIENCY 18V SYNCHRONOUS STEP-DOWN CONVERTER FAMILY FOR 4A TO 20A LAYOUT RECOMMENDATION GND C1E IN PGND PGND PGND VCC SW SW SW R3 C6 SW SW AGND SW PG SW R3 R4 SW SS IN PGND PGND EN R3 R1 PGND FB FREQ R3 C4 SW PGND PGND R3 R3 BST PGND R3 R2 C1A R3 R5 C1B R3 RFREQ R3 RFREQ C1C C1D C1E PGND C2 R3 GND VOUT VIN Top Layer GND Inner1 Layer BST IN C1A C1B R3 C3 C1D R3 C5 VIN C1E L1 1. Place high current paths (GND, IN, and SW) very close to the device with short, direct and wide traces. 2. Two-layer IN copper layers are required to achieve better performance. Place at least one 0.1uF-1uF 0603 or 0402 decoupling input capacitor on each side of the IC. The input capacitors should be placed as close to the IN and GND pins as possible (maximum 2mm edge-to-edge distance is allowed). Multiple vias with 18mil diameter and 8mil hole-size are required to be placed under the device and near input capacitors. These vias can help to reduce the parasitic inductance and optimize the thermal dissipation. 3. Put a decoupling capacitor as close to the VCC and AGND pins as possible. 4. Keep the switching node (SW) plane as small as possible and far away from the feedback network. 5. Place the external feedback resistors next to the FB pin. Make sure that there are no vias on the FB trace. The feedback resistors should refer to AGND instead of PGND. 6. Keep the BST voltage path (BST, C3, and SW) as short as possible. 7. Recommend strongly a four-layer layout to improve thermal performance. C3 L1 SW VOUT FREQ R5 R4 C4 R1 MPQ8632 MPQ8632H EN VCC C5 R3 C2 FB SS R2 C6 PG AGND PGND EN 5 FREQ 6 SS AGND 7 FB VCC 8 PG BST Figure 55—Schematic for PCB Layout Guideline 4 3 2 1 VIN VIN SW CIN GND CIN CIN CIN PGND PGND SW PGND PGND To Inductor Inner2 Layer Figure 56—Recommend Input Capacitor Placement for 16-Pin QFN 3mmx4mm Package Part, including MPQ8632-4/6/8/10/12 and MPQ8632H-10. MPQ8632 Rev.1.24 www.MonolithicPower.com 8/28/2013 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. 43 MPQ8632 HIGH EFFICIENCY 18V SYNCHRONOUS STEP-DOWN CONVERTER FAMILY FOR 4A TO 20A Design Example Below is a design example following the application guidelines for the specifications: Table 13—Design Example VIN 4.5-18V VOUT 1V FSW 500kHz C1C GND VIN The detailed application schematic is shown in Figure 14. The typical performance and circuit waveforms have been shown in the Typical Performance Characteristics section. For more device applications, please refer to the related Evaluation Board Datasheets. Bottom Layer Figure 57—PCB Layout Guideline For 29-Pin QFN 5mmx4mm Package Part, Including MPQ8632-15 and MPQ8632-20. MPQ8632 Rev.1.24 www.MonolithicPower.com 8/28/2013 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. 44 MPQ8632 HIGH EFFICIENCY 18V SYNCHRONOUS STEP-DOWN CONVERTER FAMILY FOR 4A TO 20A PACKAGE PACKAGE INFORMATION OUTLINE DRAWING FOR 16L FCQFN (3X4MM) MF-PO-D-0170 revision 0.0 QFN(3X4mm) PIN 1 ID 0.125x45° TYP. PIN 1 ID MARKING PIN 1 ID INDEX AREA BOTTOM VIEW TOP VIEW SIDE VIEW NOTE: 0.125x45° 1) ALL DIMENSIONS ARE IN MILLIMETERS. 2) EXPOSED PADDLE SIZE DOES NOT INCLUDE MOLD FLASH. 3) LEAD COPLANARITY SHALL BE 0.10 MILLIMETERS MAX. 4) JEDEC REFERENCE IS MO-220. 5) DRAWING IS NOT TO SCALE. RECOMMENDED LAND PATTERN MPQ8632 Rev.1.24 www.MonolithicPower.com 8/28/2013 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. 45 MPQ8632 HIGH EFFICIENCY 18V SYNCHRONOUS STEP-DOWN CONVERTER FAMILY FOR 4A TO 20A QFN(5X4mm) PIN 1 ID 0.125x45° TYP. PIN 1 ID MARKING PIN 1 ID INDEX AREA BOTTOM VIEW TOP VIEW SIDE VIEW NOTE: 0.125x45° 1) ALL DIMENSIONS ARE IN MILLIMETERS. 2) EXPOSED PADDLE SIZE DOES NOT INCLUDE MOLD FLASH. 3) LEAD COPLANARITY SHALL BE 0.10 MILLIMETERS MAX. 4) JEDEC REFERENCE IS MO-220. 5) DRAWING IS NOT TO SCALE. RECOMMENDED LAND PATTERN NOTICE: The information in this document is subject to change without notice. Users should warrant and guarantee that third party Intellectual Property rights are not infringed upon when integrating MPS products into any application. MPS will not assume any legal responsibility for any said applications. MPQ8632 Rev.1.24 www.MonolithicPower.com 8/28/2013 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. 46