TI1 ISO7710F Iso7710 high speed, robust emc reinforced single-channel digital isolator Datasheet

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ISO7710
SLLSER9A – NOVEMBER 2016 – REVISED DECEMBER 2016
ISO7710 High Speed, Robust EMC Reinforced Single-Channel Digital Isolator
1 Features
3 Description
•
•
•
•
•
•
The ISO7710 device is a high-performance, singlechannel digital isolator with 5000 VRMS (DW package)
and 3000 VRMS (D package) isolation ratings per UL
1577. This device is also certified by VDE, TUV,
CSA, and CQC.
1
•
•
•
•
•
•
Signaling Rate: Up to 100 Mbps
Wide Supply Range: 2.25 V to 5.5 V
2.25 V to 5.5 V Level Translation
Default Output High and Low Options
Wide Temperature Range: –55°C to 125°C
Low Power Consumption, Typical 1.7 mA at
1 Mbps
Low Propagation Delay: 11 ns Typical
(5-V Supplies)
High CMTI: ±100 kV/μs Typical
Robust Electromagnetic Compatibility (EMC)
– System-Level ESD, EFT, and Surge Immunity
– Low Emissions
Isolation Barrier Life: > 40 Years
Wide-SOIC (DW-16) and Narrow-SOIC (D-8)
Package Options
Safety and Regulatory Approvals:
– VDE Reinforced Insulation per DIN V VDE
V 0884-10 (VDE V 0884-10):2006-12
– UL 1577 Component Recognition Program
– CSA Component Acceptance Notice
5A, IEC 60950-1 and IEC 60601-1 End
Equipment Standards
– CQC Certification per GB4943.1-2011
– TUV Certification according to EN 60950-1 and
EN 61010-1
– VDE, UL, CSA, and TUV Certifications for DW16 Package Complete; All Other Certifications
Planned
The ISO7710 device provides high electromagnetic
immunity and low emissions at low power
consumption, while isolating CMOS or LVCMOS
digital I/Os. The isolation channel has a logic input
and output buffer separated by a silicon dioxide
(SiO2) insulation barrier. In the event of input power
or signal loss, default output is high for a device
without suffix F and low for a device with suffix F. See
the Device Functional Modes section for further
details.
Used in conjunction with isolated power supplies, the
device helps prevent noise currents on a data bus or
other circuits from entering the local ground and
interfering with or damaging sensitive circuitry.
Through innovative chip design and layout
techniques, the electromagnetic compatibility of the
ISO7710 device has been significantly enhanced to
ease system-level ESD, EFT, surge, and emissions
compliance. The ISO7710 device is available in 16pin SOIC wide-body (DW) and 8-pin SOIC narrowbody (D) packages.
Device Information(1)
PART NUMBER
ISO7710
PACKAGE
BODY SIZE (NOM)
SOIC (D)
4.90 mm × 3.91 mm
SOIC (DW)
10.30 mm × 7.50 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Schematic
2 Applications
•
•
•
•
•
•
Industrial Automation
Hybrid Electric Vehicles
Motor Control
Power Supplies
Solar Inverters
Medical Equipment
VCC1
Isolation
Capacitor
VCC2
IN
OUT
GND1
GND2
Copyright © 2016, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
ISO7710
SLLSER9A – NOVEMBER 2016 – REVISED DECEMBER 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
6.10
6.11
6.12
6.13
6.14
6.15
6.16
6.17
6.18
1
1
1
2
3
4
Absolute Maximum Ratings ..................................... 4
ESD Ratings.............................................................. 4
Recommended Operating Conditions....................... 4
Thermal Information .................................................. 5
Power Rating............................................................. 5
Insulation Specifications .......................................... 6
Regulatory Information.............................................. 7
Safety Limiting Values .............................................. 8
Electrical Characteristics—5-V Supply ..................... 9
Supply Current Characteristics—5-V Supply .......... 9
Electrical Characteristics—3.3-V Supply .............. 10
Supply Current Characteristics—3.3-V Supply ..... 10
Electrical Characteristics—2.5-V Supply .............. 11
Supply Current Characteristics—2.5-V Supply ..... 11
Switching Characteristics—5-V Supply................. 12
Switching Characteristics—3.3-V Supply.............. 12
Switching Characteristics—2.5-V Supply.............. 12
Safety and Insulation Characteristics Curves ....... 13
6.19 Typical Characteristics .......................................... 14
7
8
Parameter Measurement Information ................ 15
Detailed Description ............................................ 16
8.1
8.2
8.3
8.4
9
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
16
16
17
18
Applications and Implementation ...................... 19
9.1 Application Information............................................ 19
9.2 Typical Application .................................................. 19
10 Power Supply Recommendations ..................... 21
11 Layout................................................................... 22
11.1 Layout Guidelines ................................................. 22
11.2 Layout Example .................................................... 22
12 Device and Documentation Support ................. 23
12.1
12.2
12.3
12.4
12.5
12.6
12.7
Documentation Support ........................................
Related Links ........................................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
23
23
23
23
23
23
23
13 Mechanical, Packaging, and Orderable
Information ........................................................... 23
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (November 2016) to Revision A
Page
•
Changed Feature From: IEC 60950-1, IEC 60601-1 and IEC 61010-1 End Equipment Standards To: IEC 60950-1
and IEC 60601-1 End Equipment Standards ......................................................................................................................... 1
•
Added Climatic category to the Insulation Specifications ...................................................................................................... 6
•
Changed the CSA column of Regulatory Information ........................................................................................................... 7
•
Changed DW package) To: (DW-16) in the TUV column of Regulatory Information ............................................................ 7
•
Changed the tie TYP value From: 1.5 To 1 in Switching Characteristics—5-V Supply ........................................................ 12
•
Changed the tie TYP value From: 1.5 To 1 in Switching Characteristics—3.3-V Supply ..................................................... 12
•
Changed the tie TYP value From: 1.5 To 1 in Switching Characteristics—2.5-V Supply ..................................................... 12
2
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5 Pin Configuration and Functions
DW Package
16-Pin SOIC
Top View
16 GND2
1
IN
2
3
NC
2
15
VCC1
3
14 VCC2
VCC1
IN
4
13 OUT
GND1 4
NC
5
NC
ISOLATION
NC
VCC1
12
NC
6
11
NC
GND1 7
10
NC
NC
8
8 VCC2
ISOLATION
GND1 1
D Package
8-Pin SOIC
Top View
7
NC
6 OUT
5 GND2
9 GND2
Pin Functions
PIN
NAME
NO.
I/O
DESCRIPTION
DW
D
VCC1
3
1, 3
—
Power supply, VCC1
VCC2
14
8
—
Power supply, VCC2
GND1
1, 7
4
—
Ground connection for VCC1
GND2
9, 16
5
—
Ground connection for VCC2
IN
4
2
I
Input channel
OUT
13
6
O
Output channel
2, 5, 6, 8, 10 ,11,
12, 15
7
—
Not connect pin; it has no internal connection
NC
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6 Specifications
6.1 Absolute Maximum Ratings
See
(1)
VCC1, VCC2
Supply voltage (2)
MIN
MAX
–0.5
6
V
Voltage at IN, OUT
–0.5
IO
Output Current
–15
TJ
Junction temperature
Tstg
Storage temperature
(1)
(2)
(3)
VCC + 0.5
–65
UNIT
V
(3)
V
15
mA
150
°C
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values except differential I/O bus voltages are with respect to the local ground terminal (GND1 or GND2) and are peak
voltage values.
Maximum voltage must not exceed 6 V.
6.2 ESD Ratings
VESD
(1)
(2)
Electrostatic discharge
VALUE
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all
pins (1)
±6000
V
Charged device model (CDM), per JEDEC specification
JESD22-C101, all pins (2)
±1500
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
MIN
TYP
2.25
MAX
UNIT
VCC1, VCC2
Supply voltage
VCC(UVLO+)
UVLO threshold when supply voltage is rising
VCC(UVLO-)
UVLO threshold when supply voltage is falling
1.7
1.8
V
VHYS(UVLO)
Supply voltage UVLO hysteresis
100
200
mV
IOH
High-level output current
2
VCC2 = 5 V
–4
VCC2 = 3.3 V
–2
VCC2 = 2.5 V
–1
5.5
V
2.25
V
mA
VCC2 = 5 V
4
VCC2 = 3.3 V
2
IOL
Low-level output current
VIH
High-level input voltage
0.7 × VCC1
VCC1
V
VIL
Low-level input voltage
0
0.3 × VCC1
V
DR
Signaling rate
TA
Ambient temperature
VCC2 = 2.5 V
4
1
0
–55
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mA
25
100
Mbps
125
°C
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6.4 Thermal Information
ISO7710
THERMAL METRIC (1)
DW (SOIC)
D (SOIC)
(16-Pin)
(8-Pin)
UNIT
RθJA
Junction-to-ambient thermal resistance
94.4
146.1
°C/W
RθJC(top)
Junction-to-case(top) thermal resistance
57.3
63.1
°C/W
RθJB
Junction-to-board thermal resistance
57.1
80.0
°C/W
ψJT
Junction-to-top characterization parameter
40.0
9.6
°C/W
ψJB
Junction-to-board characterization parameter
56.8
79.0
°C/W
RθJC(bottom)
Junction-to-case(bottom) thermal resistance
n/a
n/a
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Power Rating
PARAMETER
PD
Maximum power dissipation
PD1
Maximum power dissipation by side-1
PD2
Maximum power dissipation by side-2
TEST CONDITIONS
VCC1 = VCC2 = 5.5 V, TJ = 150°C, CL = 15 pF,
input a 50 MHz 50% duty cycle square wave
VALUE
UNIT
50
mW
12.5
mW
37.5
mW
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6.6 Insulation Specifications
PARAMETER
CLR
External clearance
VALUE
TEST CONDITIONS
8
4
mm
(1)
Shortest terminal-to-terminal distance across the
package surface
8
4
mm
21
21
μm
> 600
> 600
V
DTI
Distance through the insulation
Minimum internal gap (internal clearance)
Comparative tracking index
DIN EN 60112 (VDE 0303-11); IEC 60112; UL
746A
Material group
According to IEC 60664-1
Overvoltage category per IEC 60664-1
DIN V VDE V 0884-10 (VDE V 0884-10):2006-12
VIORM
Maximum repetitive peak isolation
voltage
VIOWM
Maximum working isolation voltage
VIOTM
Maximum transient isolation voltage
VIOSM
Maximum surge isolation voltage
Apparent charge
(3)
(4)
Barrier capacitance, input to output (5)
CIO
Isolation resistance (5)
RIO
UNIT
Shortest terminal-to-terminal distance through air
External creepage
qpd
D-8
(1)
CPG
CTI
DW-16
I
I
Rated mains voltage ≤ 150 VRMS
I–IV
I–IV
Rated mains voltage ≤ 300 VRMS
I–IV
I–III
Rated mains voltage ≤ 600 VRMS
I–IV
n/a
Rated mains voltage ≤ 1000 VRMS
I–III
n/a
AC voltage (bipolar)
1414
637
VPK
AC voltage; Time dependent dielectric breakdown
(TDDB) test
1000
450
VRMS
DC voltage
1414
637
VDC
VTEST = VIOTM
t = 60 s (qualification)
t= 1 s (100% production)
8000
4242
VPK
Test method per IEC 60065, 1.2/50 µs waveform,
VTEST = 1.6 × VIOSM (qualification)
8000
5000
VPK
Method a, After Input/Output safety test subgroup
2/3,
Vini = VIOTM, tini = 60 s; Vpd(m) = 1.2 × VIORM, tm =
10 s
≤5
≤5
Method a, After environmental tests subgroup 1,
Vini = VIOTM, tini = 60 s; Vpd(m) = 1.6 × VIORM, tm =
10 s
≤5
≤5
Method b1; At routine test (100% production) and
preconditioning (type test)
Vini = VIOTM, tini = 1 s; Vpd(m) = 1.875 × VIORM, tm =
1s
≤5
≤5
~0.4
~0.4
(2)
VIO = 0.4 × sin (2πft), f = 1 MHz
12
>10
VIO = 500 V, 100°C ≤ TA ≤ 125°C
>1011
>1011
9
>109
>10
pF
12
VIO = 500 V, TA = 25°C
VIO = 500 V at TS = 150°C
pC
>10
Pollution degree
2
2
Climatic category
55/125/21
55/125/21
5000
3000
Ω
UL 1577
VISO
(1)
(2)
(3)
(4)
(5)
6
Withstanding isolation voltage
VTEST = VISO, t = 60 s (qualification);
VTEST = 1.2 × VISO, t = 1 s (100% production)
VRMS
Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application. Care
should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on
the printed-circuit board do not reduce this distance. Creepage and clearance on a printed-circuit board become equal in certain cases.
Techniques such as inserting grooves and/or ribs on a printed circuit board are used to help increase these specifications.
This coupler is suitable for safe electrical insulation only within the safety ratings. Compliance with the safety ratings shall be ensured by
means of suitable protective circuits.
Testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier.
Apparent charge is electrical discharge caused by a partial discharge (pd).
All pins on each side of the barrier tied together creating a two-terminal device.
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6.7 Regulatory Information
VDE, CSA, UL and TUV certifications for DW-16 package are complete; All other certifications are planned.
VDE
Certified according to
DIN V VDE V 0884-10
(VDE V 0884-10):200612
Maximum transient
isolation voltage, 8000
VPK (DW-16) and 4242
VPK (D-8);
Maximum repetitive peak
isolation voltage, 1414
VPK (DW-16) and 637
VPK (D-8);
Maximum surge isolation
voltage, 8000 VPK (DW16) and 5000 VPK (D-8)
Certificate number:
40040142
CSA
UL
Certified under CSA
Component Acceptance
Notice 5A, IEC 60950-1,
and IEC 60601-1
Reinforced insulation per
CSA 60950-1-07+A1+A2
and IEC 60950-1 2nd Ed.,
800 VRMS (DW-16) and 400
VRMS (D-8) max working
voltage (pollution degree 2,
material group I);
2 MOPP (Means of Patient
Protection) per CSA 606011:14 and IEC 60601-1 Ed.
3.1, 250 VRMS (DW-16) max
working voltage
Master contract number:
220991
CQC
TUV
Certified according to UL
1577 Component
Recognition Program
Certified according to EN
61010-1:2010 (3rd Ed)
Plan to certify according to
and EN 60950GB4943.1-2011
1:2006/A11:2009/A1:2010/
A12:2011/A2:2013
DW-16: Single
protection, 5000 VRMS ;
D-8: Single protection,
3000 VRMS
DW-16: Reinforced
Insulation, Altitude ≤ 5000
m, Tropical Climate, 400
VRMS maximum working
voltage;
D-8: Basic Insulation,
Altitude ≤ 5000 m, Tropical
Climate, 250 VRMS
maximum working voltage
File number: E181974
Certification Planned
5000 VRMS Reinforced
insulation per EN 610101:2010 (3rd Ed) up to
working voltage of 600
VRMS (DW-16)
5000 VRMS Reinforced
insulation per EN 609501:2006/A11:2009/A1:2010/
A12:2011/A2:2013 up to
working voltage of 800
VRMS (DW-16)
Client ID number: 77311
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6.8 Safety Limiting Values
Safety limiting intends to minimize potential damage to the isolation barrier upon failure of input or output circuitry. A failure of
the I/O can allow low resistance to ground or the supply and, without current limiting, dissipate sufficient power to overheat
the die and damage the isolation barrier potentially leading to secondary system failures.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DW-16 Package
IS
Safety input, output, or supply
current
PS
Safety input, output, or total
power
TS
Maximum safety temperature
RθJA = 94.4 °C/W, VI = 5.5 V, TJ = 150°C, TA = 25°C,
see Figure 1
241
RθJA = 94.4 °C/W, VI = 3.6 V, TJ = 150°C, TA = 25°C,
see Figure 1
368
RθJA = 94.4 °C/W, VI = 2.75 V, TJ = 150°C, TA = 25°C,
see Figure 1
482
RθJA = 94.4 °C/W, TJ = 150°C, TA = 25°C, see Figure 2
1324
mW
150
°C
mA
D-8 Package
IS
Safety input, output, or supply
current
PS
Safety input, output, or total
power
TS
Maximum safety temperature
RθJA = 146.1 °C/W, VI = 5.5 V, TJ = 150°C, TA = 25°C,
see Figure 3
156
RθJA = 146.1 °C/W, VI = 3.6 V, TJ = 150°C, TA = 25°C,
see Figure 3
238
RθJA = 146.1 °C/W, VI = 2.75 V, TJ = 150°C, TA = 25°C,
see Figure 3
311
RθJA = 146.1 °C/W, TJ = 150°C, TA = 25°C, see Figure 4
856
mW
150
°C
mA
The maximum safety temperature is the maximum junction temperature specified for the device. The power
dissipation and junction-to-air thermal impedance of the device installed in the application hardware determines
the junction temperature. The assumed junction-to-air thermal resistance in the Thermal Information table is that
of a device installed on a High-K test board for leaded surface mount packages. The power is the recommended
maximum input voltage times the current. The junction temperature is then the ambient temperature plus the
power times the junction-to-air thermal resistance.
8
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6.9 Electrical Characteristics—5-V Supply
VCC1 = VCC2 = 5 V ± 10% (over recommended operating conditions unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
VCC2 – 0.4
4.8
VOH
High-level output voltage
IOH = –4 mA; see Figure 11
VOL
Low-level output voltage
IOL = 4 mA; see Figure 11
VIT+(IN)
Rising input threshold voltage
VIT-(IN)
Falling input threshold voltage
0.3 x VCC1
0.4 x VCC1
VI(HYS)
Input threshold voltage hysteresis
0.1 × VCC1
0.2 × VCC1
IIH
High-level input current
VIH = VCC1 at IN
IIL
Low-level input current
VIL = 0 V at IN
CMTI
Common-mode transient immunity
VI = VCC1 or 0 V, VCM = 1200 V; see Figure 13
CI
Input Capacitance (1)
VI = VCC/ 2 + 0.4×sin(2πft), f = 1 MHz, VCC = 5 V
(1)
MAX
V
0.2
0.4
V
0.6 x VCC1
0.7 x VCC1
V
V
V
10
–10
40
UNIT
μA
μA
100
kV/μs
2
pF
Measured from input pin to ground.
6.10 Supply Current Characteristics—5-V Supply
VCC1 = VCC2 = 5 V ± 10% (over recommended operating conditions unless otherwise noted)
PARAMETER
SUPPLY
CURRENT
TEST CONDITIONS
VI = VCC1 (ISO7710), VI = 0 V (ISO7710 with F suffix)
Supply current - DC signal
VI = 0 V (ISO7710), VI = VCC1 (ISO7710 with F suffix)
1 Mbps
Supply current - AC signal
All channels switching with square
wave clock input; CL = 15 pF
10 Mbps
100 Mbps
MIN
TYP
MAX
ICC1
0.5
0.8
ICC2
0.6
1
ICC1
1.6
2.5
ICC2
0.6
1
ICC1
1.1
1.5
ICC2
0.6
1.1
ICC1
1.1
1.6
ICC2
1.1
1.6
ICC1
1.4
2
ICC2
5.9
7
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UNIT
mA
9
ISO7710
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6.11 Electrical Characteristics—3.3-V Supply
VCC1 = VCC2 = 3.3 V ± 10% (over recommended operating conditions unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
VCC2 – 0.3
3.2
VOH
High-level output voltage
IOH = –2 mA; see Figure 11
VOL
Low-level output voltage
IOL = 2 mA; see Figure 11
VIT+(IN)
Rising input voltage threshold
VIT-(IN)
Falling input voltage threshold
0.3 x VCC1
0.4 x VCC1
VI(HYS)
Input threshold voltage hysteresis
0.1 × VCC1
0.2 × VCC1
IIH
High-level input current
VIH = VCC1 at IN
IIL
Low-level input current
VIL = 0 V at IN
CMTI
Common-mode transient immunity
VI = VCC1 or 0 V, VCM = 1200 V; see Figure 13
MAX
UNIT
V
0.1
0.3
V
0.6 x VCC1
0.7 x VCC1
V
V
V
10
–10
μA
μA
40
100
kV/μs
6.12 Supply Current Characteristics—3.3-V Supply
VCC1 = VCC2 = 3.3 V ± 10% (over recommended operating conditions unless otherwise noted)
PARAMETER
SUPPLY
CURRENT
TEST CONDITIONS
VI = VCC1 (ISO7710), VI = 0 V (ISO7710 with F suffix)
Supply current - DC signal
VI = 0 V (ISO7710), VI = VCC1 (ISO7710 with F suffix)
1 Mbps
Supply current - AC signal
All channels switching with square
wave clock input; CL = 15 pF
10 Mbps
100 Mbps
10
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MIN
TYP
MAX
ICC1
0.5
0.8
ICC2
0.6
1
ICC1
1.6
2.5
ICC2
0.6
1
ICC1
1.1
1.5
ICC2
0.6
1
ICC1
1
1.6
ICC2
1.1
1.4
ICC1
1.3
1.8
ICC2
4.3
5.3
UNIT
mA
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6.13 Electrical Characteristics—2.5-V Supply
VCC1 = VCC2 = 2.5 V ± 10% (over recommended operating conditions unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
VCC2 – 0.2
2.45
VOH
High-level output voltage
IOH = –1 mA; see Figure 11
VOL
Low-level output voltage
IOL = 1 mA; see Figure 11
VIT+(IN)
Rising input voltage threshold
VIT-(IN)
Falling input voltage threshold
0.3 x VCC1
0.4 x VCC1
VI(HYS)
Input threshold voltage hysteresis
0.1 × VCC1
0.2 × VCC1
IIH
High-level input current
VIH = VCC1 at IN
IIL
Low-level input current
VIL = 0 V at IN
CMTI
Common-mode transient
immunity
VI = VCC1 or 0 V, VCM = 1200 V; see Figure 13
MAX
UNIT
V
0.05
0.2
V
0.6 x VCC1
0.7 x VCC1
V
V
V
10
–10
μA
μA
40
100
kV/μs
6.14 Supply Current Characteristics—2.5-V Supply
VCC1 = VCC2 = 2.5 V ± 10% (over recommended operating conditions unless otherwise noted)
PARAMETER
SUPPLY
CURRENT
TEST CONDITIONS
VI = VCC1 (ISO7710), VI = 0 V (ISO7710 with F suffix)
Supply current - DC signal
VI = 0 V (ISO7710), VI = VCC1 (ISO7710 with F suffix)
1 Mbps
Supply current - AC signal
All channels switching with square
wave clock input; CL = 15 pF
10 Mbps
100 Mbps
MIN
TYP
MAX
ICC1
0.5
0.8
ICC2
0.6
1
ICC1
1.6
2.5
ICC2
0.6
1
ICC1
1.1
1.5
ICC2
0.6
1
ICC1
1.1
1.5
ICC2
0.9
1.4
ICC1
1.2
1.6
ICC2
3.4
4.4
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mA
11
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6.15 Switching Characteristics—5-V Supply
VCC1 = VCC2 = 5 V ± 10% (over recommended operating conditions unless otherwise noted)
PARAMETER
tPLH, tPHL
Propagation delay time
PWD
Pulse width distortion (1) |tPHL – tPLH|
tsk(pp)
Part-to-part skew time (2)
tr
Output signal rise time
tf
Output signal fall time
TEST CONDITIONS
TYP
MAX
6
11
16
ns
0.6
4.9
ns
4.5
ns
1.8
3.9
ns
1.9
3.9
ns
0.1
0.3
μs
See Figure 11
See Figure 11
tDO
Default output delay time from input power loss
Measured from the time VCC1 goes below 1.7 V.
See Figure 12
tie
Time interval error
216 – 1 PRBS data at 100 Mbps
(1)
(2)
MIN
1
UNIT
ns
Also known as pulse skew.
tsk(pp) is the magnitude of the difference in propagation delay times between terminals of different devices switching in the same
direction while operating at identical supply voltages, temperature, input signals and loads.
6.16 Switching Characteristics—3.3-V Supply
VCC1 = VCC2 = 3.3 V ± 10% (over recommended operating conditions unless otherwise noted)
PARAMETER
tPLH, tPHL
Propagation delay time
PWD
Pulse width distortion (1) |tPHL – tPLH|
tsk(pp)
Part-to-part skew time (2)
tr
Output signal rise time
tf
Output signal fall time
TEST CONDITIONS
See Figure 11
TYP
MAX
6
11
16
ns
0.1
5
ns
4.5
ns
0.7
3
ns
0.7
3
ns
0.1
0.3
μs
See Figure 11
tDO
Default output delay time from input power loss
Measured from the time VCC1 goes below 1.7 V.
See Figure 12
tie
Time interval error
216 – 1 PRBS data at 100 Mbps
(1)
(2)
MIN
1
UNIT
ns
Also known as pulse skew.
tsk(pp) is the magnitude of the difference in propagation delay times between terminals of different devices switching in the same
direction while operating at identical supply voltages, temperature, input signals and loads.
6.17 Switching Characteristics—2.5-V Supply
VCC1 = VCC2 = 2.5 V ± 10% (over recommended operating conditions unless otherwise noted)
PARAMETER
tPLH, tPHL
Propagation delay time
PWD
Pulse width distortion (1) |tPHL – tPLH|
tsk(pp)
Part-to-part skew time (2)
tr
Output signal rise time
tf
Output signal fall time
tDO
tie
(1)
(2)
12
Default output delay time from input power loss
Time interval error
TEST CONDITIONS
See Figure 11
See Figure 11
Measured from the time VCC1 goes below 1.7 V.
See Figure 12
16
2
– 1 PRBS data at 100 Mbps
MIN
TYP
MAX
UNIT
7.5
12
18.5
ns
0.2
5.1
ns
4.6
ns
1
3.5
ns
1
3.5
ns
0.1
0.3
μs
1
ns
Also known as pulse skew.
tsk(pp) is the magnitude of the difference in propagation delay times between terminals of different devices switching in the same
direction while operating at identical supply voltages, temperature, input signals and loads.
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6.18 Safety and Insulation Characteristics Curves
1400
VCC1 = VCC2 = 2.75 V
VCC1 = VCC2 = 3.6 V
VCC1 = VCC2 = 5.5 V
500
1200
Safety Limiting Power (mW)
Safety Limiting Current (mA)
600
400
300
200
100
800
600
400
200
0
0
0
50
100
150
Ambient Temperature (qC)
0
200
50
D001
Figure 1. Thermal Derating Curve for Safety Limiting
Current for DW-16 Package
100
150
Ambient Temperature (qC)
200
D002
Figure 2. Thermal Derating Curve for Safety Limiting Power
for DW-16 Package
350
900
VCC1 = VCC2 = 2.75 V
VCC1 = VCC2 = 3.6 V
VCC1 = VCC2 = 5.5 V
800
Safety Limiting Power (mW)
300
Safety Limiting Current (mA)
1000
250
200
150
100
50
700
600
500
400
300
200
100
0
0
0
20
40
60
80
100
120
Ambient Temperature (qC)
140
160
0
D003
Figure 3. Thermal Derating Curve for Safety Limiting
Current for D-8 Package
50
100
150
Ambient Temperature (qC)
200
D004
Figure 4. Thermal Derating Curve for Safety Limiting Power
for D-8 Package
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6.19 Typical Characteristics
2.5
7
ICC1 at 2.5 V
ICC2 at 2.5 V
ICC1 at 3.3 V
6
ICC2 at 3.3 V
ICC1 at 5 V
ICC2 at 5 V
2
Supply Current (mA)
5
Supply Current (mA)
ICC1 at 2.5 V
ICC2 at 2.5 V
ICC1 at 3.3 V
4
3
2
ICC2 at 3.3 V
ICC1 at 5 V
ICC2 at 5 V
1.5
1
0.5
1
0
0
0
25
TA = 25°C
50
Data Rate (Mbps)
75
0
100
25
D005
CL = 15 pF
TA = 25°C
Figure 5. ISO7710 Supply Current vs Data Rate
(With 15 pF Load)
50
Data Rate (Mbps)
75
100
D006
CL = No Load
Figure 6. ISO7710 Supply Current vs Data Rate
(With No Load)
6
0.9
Low-Level Output Voltage (V)
High-Level Output Voltage (V)
0.8
5
4
3
2
VCC at 2.5 V
VCC at 3.3 V
VCC at 5 V
1
0
-15
0.7
0.6
0.5
0.4
0.3
0.2
0
-10
-5
High-Level Output Current (mA)
0
0
15
D012
TA = 25°C
TA = 25°C
Figure 7. High-Level Output Voltage vs High-level
Output Current
Figure 8. Low-Level Output Voltage vs Low-Level
Output Current
14
2.05
Propagation Delay Time (ns)
Power Supply UVLO Threshold (V)
5
10
Low-Level Output Current (mA)
D011
2.10
2.00
1.95
1.90
1.85
1.80
1.75
VCC1 Rising
VCC1 Falling
VCC2 Rising
VCC2 Falling
1.70
1.65
1.60
-55 -40 -25 -10
5 20 35 50 65 80
Free-Air Temperature (qC)
95 110 125
13
12
11
10
tPLH at 2.5 V
tPHL at 2.5 V
tPLH at 3.3 V
9
8
-55
D009
Figure 9. Power Supply Undervoltage Threshold vs
Free-Air Temperature
14
VCC at 2.5 V
VCC at 3.3 V
VCC at 5 V
0.1
-25
5
35
65
Free Air Temperature (qC)
tPHL at 3.3 V
tPLH at 5 V
tPHL at 5 V
95
125
D010
Figure 10. Propagation Delay Time vs Free-Air Temperature
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Isolation Barrier
7 Parameter Measurement Information
IN
Input
Generator
Note A
VI
50 W
VCC1
VI
OUT
50%
50%
0V
tPLH
VO
CL
Note B
tPHL
90%
10%
50%
VO
50%
VOH
VOL
tr
tf
Copyright © 2016, Texas Instruments Incorporated
A.
The input pulse is supplied by a generator having the following characteristics: PRR ≤ 50 kHz, 50% duty cycle, tr ≤ 3
ns, tf ≤ 3ns, ZO = 50 Ω. At the input, 50 Ω resistor is required to terminate Input Generator signal. It is not needed in
actual application.
B.
CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 11. Switching Characteristics Test Circuit and Voltage Waveforms
VI See Note B
VCC
VCC
Isolation Barrier
IN = 0 V (Devices without suffix F)
IN = VCC (Devices with suffix F)
VI
IN
1.7 V
0V
OUT
VO
tDO
CL
See Note A
default high
VOH
50%
VO
VOL
default low
Copyright © 2016, Texas Instruments Incorporated
A.
CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
B.
Power Supply Ramp Rate = 10 mV/ns
Figure 12. Default Output Delay Time Test Circuit and Voltage Waveforms
VCC1
VCC1
Isolation Barrier
C = 0.1 µF ±1%
IN
S1
C = 0.1 µF ±1%
Pass-fail criteria:
The output must
remain stable.
OUT
+
EN
CL
See Note A
GND1
+
VCM ±
VOH or VOL
±
GND2
Copyright © 2016, Texas Instruments Incorporated
A.
CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 13. Common-Mode Transient Immunity Test Circuit
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8 Detailed Description
8.1 Overview
The ISO7710 device has an ON-OFF keying (OOK) modulation scheme to transmit the digital data across a
silicon dioxide based isolation barrier. The transmitter sends a high frequency carrier across the barrier to
represent one digital state and sends no signal to represent the other digital state. The receiver demodulates the
signal after advanced signal conditioning and produces the output through a buffer stage. The device also
incorporates advanced circuit techniques to maximize the CMTI performance and minimize the radiated
emissions due the high frequency carrier and IO buffer switching. The conceptual block diagram of a digital
capacitive isolator, Figure 14, shows a functional block diagram of a typical channel.
8.2 Functional Block Diagram
Receiver
Transmitter
TX IN
OOK
Modulation
TX Signal
Conditioning
Oscillator
SiO2 based
Capacitive
Isolation
Barrier
RX Signal
Conditioning
Envelope
Detection
RX OUT
Emissions
Reduction
Techniques
Copyright © 2016, Texas Instruments Incorporated
Figure 14. Conceptual Block Diagram of a Digital Capacitive Isolator
Figure 15 shows a conceptual detail of how the ON/OFF keying scheme works.
TX IN
Carrier signal through
isolation barrier
RX OUT
Figure 15. On-Off Keying (OOK) Based Modulation Scheme
16
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8.3 Feature Description
The ISO7710 device is available in two default output state options to enable a variety of application uses.
Table 1 lists the device features.
Table 1. Device Features
PART NUMBER
MAXIMUM DATA
RATE
CHANNEL
DIRECTION
DEFAULT OUTPUT
STATE
ISO7710
100 Mbps
1 Forward, 0 Reverse
High
ISO7710F
100 Mbps
1 Forward, 0 Reverse
Low
(1)
PACKAGE
RATED ISOLATION (1)
DW-16
5000 VRMS / 8000 VPK
D-8
3000 VRMS / 4242 VPK
DW-16
5000 VRMS / 8000 VPK
D-8
3000 VRMS / 4242 VPK
See the Regulatory Information section for detailed isolation ratings.
8.3.1 Electromagnetic Compatibility (EMC) Considerations
Many applications in harsh industrial environment are sensitive to disturbances such as electrostatic discharge
(ESD), electrical fast transient (EFT), surge and electromagnetic emissions. These electromagnetic disturbances
are regulated by international standards such as IEC 61000-4-x and CISPR 22. Although system-level
performance and reliability depends, to a large extent, on the application board design and layout, the ISO7710
device incorporates many chip-level design improvements for overall system robustness. Some of these
improvements include:
• Robust ESD protection cells for input and output signal pins and inter-chip bond pads.
• Low-resistance connectivity of ESD cells to supply and ground pins.
• Enhanced performance of high voltage isolation capacitor for better tolerance of ESD, EFT and surge events.
• Bigger on-chip decoupling capacitors to bypass undesirable high energy signals through a low impedance
path.
• PMOS and NMOS devices isolated from each other by using guard rings to avoid triggering of parasitic
SCRs.
• Reduced common mode currents across the isolation barrier by ensuring purely differential internal operation.
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8.4 Device Functional Modes
Table 2 lists the functional modes of ISO7710 device.
Table 2. Function Table (1)
VCC1
VCC2
PU
(1)
(2)
(3)
INPUT
(IN) (2)
OUTPUT
(OUT)
H
H
L
L
Open
Default
Default mode: When IN is open, the corresponding channel output goes to its
default logic state. Default is High for ISO7710 and Low for ISO7710F.
Default mode: When VCC1 is unpowered, a channel output assumes the logic
state based on the selected default option. Default is High for ISO7710 and
Low for ISO7710F.
When VCC1 transitions from unpowered to powered-up, a channel output
assumes the logic state of its input.
When VCC1 transitions from powered-up to unpowered, channel output
assumes the selected default state.
PU
COMMENTS
Normal Operation:
A channel output assumes the logic state of its input.
PD
PU
X
Default
X
PD
X
Undetermined
When VCC2 is unpowered, a channel output is undetermined (3).
When VCC2 transitions from unpowered to powered-up, a channel output
assumes the logic state of its input
PU = Powered up (VCC ≥ 2.25 V); PD = Powered down (VCC ≤ 1.7 V); X = Irrelevant; H = High level; L = Low level
A strongly driven input signal can weakly power the floating VCC via an internal protection diode and cause undetermined output.
The outputs are in undetermined state when 1.7 V < VCC1, VCC2 < 2.25 V.
8.4.1 Device I/O Schematics
Input (Devices without F suffix)
VCC1
VCC1
VCC1
Input (Devices with F suffix)
VCC1
VCC1
VCC1
VCC1
1.5 M
985
985
IN
IN
1.5 M
Output
VCC2
~20
OUT
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Figure 16. Device I/O Schematics
18
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9 Applications and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The ISO7710 device is a high-performance, single-channel digital isolator. The device uses single-ended CMOSlogic switching technology. The supply voltage range is from 2.25 V to 5.5 V for both supplies, VCC1 and VCC2.
When designing with digital isolators, keep in mind that because of the single-ended design structure, digital
isolators do not conform to any specific interface standard and are only intended for isolating single-ended
CMOS or TTL digital signal lines. The isolator is typically placed between the data controller (that is, μC or
UART), and a data converter or a line transceiver, regardless of the interface type or standard.
9.2 Typical Application
The ISO7710 device can be used with Texas Instruments' mixed signal microcontroller, CAN transceiver,
transformer driver, and low-dropout voltage regulator to create an Isolated CAN Interface as shown below.
VS
3.3 V
10 F
2
Vcc
D2
1:1.33
3
MBR0520L
1
10 F 0.1 F
D1
4
OUT
ISO 3.3V
5
TPS76333
SN6501
GND
IN
3
1
EN
GND
10 F
2
MBR0520L
GND
5
ISO Barrier
0.1 F
5
4
GND2
0.1 F
6
8
29,57
VDDIO
IN
VCC1
0.1 F
VCC2
0.1 F
3
2
1,3
25
4
1
26
CANRXA
TMS320F28035PAG
CANTXA
VSS
GND1
ISO7710
OUT
1,3
2
6,28
4
0.1 F
0.1 F
VCC1
VCC2
IN
VCC
RS 8
R
CANH
SN65HVD231
D
CANL
GND
2
8
10
(optional)
10
(optional)
7
6
Vref 5
SM712
ISO7710 OUT 6
GND2
GND1
5
4.7 nF /
2 kV
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Figure 17. Isolated CAN Interface
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Typical Application (continued)
9.2.1 Design Requirements
To design with this device, use the parameters listed in Table 3.
Table 3. Design Parameters
PARAMETER
VALUE
Supply voltage, VCC1 and VCC2
2.25 V to 5.5 V
Decoupling capacitor between VCC1 and GND1
0.1 µF
Decoupling capacitor from VCC2 and GND2
0.1 µF
9.2.2 Detailed Design Procedure
Unlike optocouplers, which need require components to improve performance, provide bias, or limit current, the
ISO7710 device only requires two external bypass capacitors to operate.
VCC1
VCC1
0.1 µF
2 mm
maximum
from
VCC1
1
2
INPUT
3
4
GND1
8
2 mm
maximum
from
VCC2
0.1 µF
7
IN
OUT
6
OUTPUT
5
GND2
Copyright © 2016, Texas Instruments Incorporated
Figure 18. Typical ISO7710 Circuit Hook-up
20
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9.2.3 Application Curve
1 V/ div
The following typical eye diagram of the ISO7710 device indicates low jitter and wide open eye at the maximum
data rate of 100 Mbps.
Time = 3.5 ns / div
Figure 19. ISO7710 Eye Diagram at 100 Mbps PRBS, 5 V Supplies and 25°C
10 Power Supply Recommendations
To help ensure reliable operation at data rates and supply voltages, a 0.1-μF bypass capacitor is recommended
at the input and output supply pins (VCC1 and VCC2). The capacitors should be placed as close to the supply pins
as possible. If only a single primary-side power supply is available in an application, isolated power can be
generated for the secondary-side with the help of a transformer driver such as Texas Instruments' SN6501 or
SN6505A. For such applications, detailed power supply design and transformer selection recommendations are
available in the SN6501 data sheet (SLLSEA0) or SN6505A data sheet (SLLSEP9).
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11 Layout
11.1 Layout Guidelines
A minimum of four layers is required to accomplish a low EMI PCB design (see Figure 20). Layer stacking should
be in the following order (top-to-bottom): high-speed signal layer, ground plane, power plane and low-frequency
signal layer.
• Routing the high-speed traces on the top layer avoids the use of vias (and the introduction of their
inductances) and allows for clean interconnects between the isolator and the transmitter and receiver circuits
of the data link.
• Placing a solid ground plane next to the high-speed signal layer establishes controlled impedance for
transmission line interconnects and provides an excellent low-inductance path for the return current flow.
• Placing the power plane next to the ground plane creates additional high-frequency bypass capacitance of
approximately 100 pF/in2.
• Routing the slower speed control signals on the bottom layer allows for greater flexibility as these signal links
usually have margin to tolerate discontinuities such as vias.
If an additional supply voltage plane or signal layer is needed, add a second power or ground plane system to
the stack to keep it symmetrical. This makes the stack mechanically stable and prevents it from warping. Also the
power and ground plane of each power system can be placed closer together, thus increasing the high-frequency
bypass capacitance significantly.
For detailed layout recommendations, see the application note, Digital Isolator Design Guide (SLLA284).
11.1.1 PCB Material
For digital circuit boards operating below 150 Mbps, (or rise and fall times higher than 1 ns), and trace lengths of
up to 10 inches, use standard FR-4 UL94V-0 printed circuit boards. This PCB is preferred over cheaper
alternatives due to its lower dielectric losses at high frequencies, less moisture absorption, greater strength and
stiffness, and self-extinguishing flammability-characteristics.
11.2 Layout Example
High-speed traces
10 mils
Ground plane
40 mils
Keep this
space free
from planes,
traces, pads,
and vias
FR-4
0r ~ 4.5
Power plane
10 mils
Low-speed traces
Figure 20. Layout Example
22
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12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation, see the following:
• Isolation Glossary, SLLA353
• SN6501 Transformer Driver for Isolated Power Supplies, SLLSEA0
• SN65HVD23x 3.3-V CAN Bus Transceivers, SLOS346
• TMS320F28035 Piccolo™ Microcontrollers, SPRS584
• TPS76333 Low-Power 150-mA Low-Dropout Linear Regulators, SLVS181
12.2 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 4. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
ISO7710
Click here
Click here
Click here
Click here
Click here
12.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.4 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.5 Trademarks
Piccolo, E2E are trademarks of Texas Instruments.
12.6 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OUTLINE
D0008B
SOIC - 1.75 mm max height
SCALE 2.800
SOIC
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
A
.004 [0.1] C
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.150
[3.81]
.189-.197
[4.81-5.00]
NOTE 3
4
5
B
8X .012-.020
[0.31-0.51]
.150-.157
[3.81-3.98]
NOTE 4
.010 [0.25]
C A
B
.069 MAX
[1.75]
.005-.010 TYP
[0.13-0.25]
SEE DETAIL A
.010
[0.25]
.004-.010
[ 0.11 -0.25]
0 -8
.016-.050
[0.41-1.27]
DETAIL A
.041
[1.04]
TYPICAL
4221445/B 04/2014
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15], per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
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ISO7710
www.ti.com
SLLSER9A – NOVEMBER 2016 – REVISED DECEMBER 2016
EXAMPLE BOARD LAYOUT
D0008B
SOIC - 1.75 mm max height
SOIC
8X (.061 )
[1.55]
SEE
DETAILS
SYMM
8X (.055)
[1.4]
SEE
DETAILS
SYMM
1
1
8
8X (.024)
[0.6]
8
SYMM
8X (.024)
[0.6]
5
4
6X (.050 )
[1.27]
SYMM
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
(.217)
[5.5]
HV / ISOLATION OPTION
.162 [4.1] CLEARANCE / CREEPAGE
IPC-7351 NOMINAL
.150 [3.85] CLEARANCE / CREEPAGE
LAND PATTERN EXAMPLE
SCALE:6X
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
.0028 MAX
[0.07]
ALL AROUND
METAL
.0028 MIN
[0.07]
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4221445/B 04/2014
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
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25
ISO7710
SLLSER9A – NOVEMBER 2016 – REVISED DECEMBER 2016
www.ti.com
EXAMPLE STENCIL DESIGN
D0008B
SOIC - 1.75 mm max height
SOIC
8X (.061 )
[1.55]
8X (.055)
[1.4]
SYMM
SYMM
1
1
8
8X (.024)
[0.6]
6X (.050 )
[1.27]
8
SYMM
8X (.024)
[0.6]
5
4
6X (.050 )
[1.27]
SYMM
5
4
(.217)
[5.5]
(.213)
[5.4]
HV / ISOLATION OPTION
.162 [4.1] CLEARANCE / CREEPAGE
IPC-7351 NOMINAL
.150 [3.85] CLEARANCE / CREEPAGE
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.127 MM] THICK STENCIL
SCALE:6X
4221445/B 04/2014
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
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ISO7710
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SLLSER9A – NOVEMBER 2016 – REVISED DECEMBER 2016
PACKAGE OUTLINE
DW0016B
SOIC - 2.65 mm max height
SCALE 1.500
SOIC
C
10.63
TYP
9.97
SEATING PLANE
PIN 1 ID
AREA
A
0.1 C
14X 1.27
16
1
2X
8.89
10.5
10.1
NOTE 3
8
9
0.51
0.31
0.25
C A
16X
7.6
7.4
NOTE 4
B
2.65 MAX
B
0.33
TYP
0.10
SEE DETAIL A
0.25
GAGE PLANE
0.3
0.1
0 -8
1.27
0.40
DETAIL A
(1.4)
TYPICAL
4221009/B 07/2016
NOTES:
1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm, per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm, per side.
5. Reference JEDEC registration MS-013.
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ISO7710
SLLSER9A – NOVEMBER 2016 – REVISED DECEMBER 2016
www.ti.com
EXAMPLE BOARD LAYOUT
DW0016B
SOIC - 2.65 mm max height
SOIC
SYMM
SYMM
16X (2)
16X (1.65)
SEE
DETAILS
1
SEE
DETAILS
1
16
16
16X (0.6)
16X (0.6)
SYMM
SYMM
14X (1.27)
14X (1.27)
9
8
9
8
R0.05 TYP
R0.05 TYP
(9.75)
(9.3)
HV / ISOLATION OPTION
8.1 mm CLEARANCE/CREEPAGE
IPC-7351 NOMINAL
7.3 mm CLEARANCE/CREEPAGE
LAND PATTERN EXAMPLE
SCALE:4X
METAL
SOLDER MASK
OPENING
SOLDER MASK
OPENING
0.07 MAX
ALL AROUND
METAL
0.07 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4221009/B 07/2016
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
28
Submit Documentation Feedback
Copyright © 2016, Texas Instruments Incorporated
Product Folder Links: ISO7710
ISO7710
www.ti.com
SLLSER9A – NOVEMBER 2016 – REVISED DECEMBER 2016
EXAMPLE STENCIL DESIGN
DW0016B
SOIC - 2.65 mm max height
SOIC
SYMM
SYMM
16X (1.65)
16X (2)
1
1
16
16
16X (0.6)
16X (0.6)
SYMM
SYMM
14X (1.27)
14X (1.27)
9
8
9
8
R0.05 TYP
R0.05 TYP
(9.3)
(9.75)
IPC-7351 NOMINAL
7.3 mm CLEARANCE/CREEPAGE
HV / ISOLATION OPTION
8.1 mm CLEARANCE/CREEPAGE
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:4X
4221009/B 07/2016
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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Copyright © 2016, Texas Instruments Incorporated
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29
PACKAGE OPTION ADDENDUM
www.ti.com
30-Nov-2016
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
ISO7710D
PREVIEW
SOIC
D
8
75
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Green (RoHS
& no Sb/Br)
Call TI
Level-2-260C-1 YEAR
-55 to 125
Device Marking
(4/5)
7710
ISO7710DR
PREVIEW
SOIC
D
8
2500
TBD
Call TI
Call TI
-55 to 125
ISO7710DW
PREVIEW
SOIC
DW
16
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-55 to 125
ISO7710
ISO7710DWR
PREVIEW
SOIC
DW
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-55 to 125
ISO7710
ISO7710FD
PREVIEW
SOIC
D
8
75
TBD
Call TI
Call TI
-55 to 125
ISO7710FDR
PREVIEW
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
Call TI
Level-2-260C-1 YEAR
-55 to 125
7710F
ISO7710FDW
PREVIEW
SOIC
DW
16
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-55 to 125
ISO7710F
ISO7710FDWR
PREVIEW
SOIC
DW
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-55 to 125
ISO7710F
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
30-Nov-2016
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
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