Fujitsu MB89PV190 8-bit proprietary microcontroller Datasheet

FUJITSU SEMICONDUCTOR
DATA SHEET
DS07-12538-1E
8-bit Proprietary Microcontroller
CMOS
F2MC-8L MB89990 Series
MB89997
■ OUTLINE
The MB89990 series microcontrollers contain various resources such as timers, external interrupts, and remotecontrol functions, as well as an F2MC*-8L CPU core for low-voltage and high-speed operations. These singlechip microcontrollers are suitable for small devices such as remote controllers incorporating compact packages.
*: F2MC stands for FUJITSU Flexible Microcontroller.
■ FEATURES
• Minimum execution time: 0.95 µs at 4.2 MHz (VCC = 2.7 V)
• F2MC-8L family CPU core
• Two timers
8/16-bit timer/counter
20-bit timebase counter
(Continued)
■ PACKAGE
28-pin Plastic SOP
28-pin Plastic SH-DIP
48-pin Ceramic MQFP
(FPT-28P-M17)
(DIP-28P-M03)
(MQP-48C-P01)
MB89990 Series
(Continued)
• External interrupts
Edge detection (Edge selection enabled): 3 channels
Low-level interrupt (Wake-up function): 8 channels
• Internal remote-control transmission frequency generator
• Low-power consumption modes
Stop mode (Almost no current consumption occurs because oscillation stops.)
Sleep mode (The current consumption is about 1/3 of that during normal operation because the CPU stops.)
• Packages
SOP-28 and SH-DIP-28
■ PRODUCT LINEUP
Part number
MB89997
MB89P195*1
Mass-produced products
(mask ROM products)
One-time PROM product
MB89PV190*2
Item
Classification
ROM size
32 K × 8 bits
(internal mask ROM)
For development and
evaluation
16 K × 8 bits
(internal PROM, to be
programmed with generalpurpose EPROM
programmer)
32 K × 8 bits
(external ROM)
RAM size
128 × 8 bits
256 × 8 bits
CPU functions
The number of basic instructions:
Instruction bit length:
Instruction length:
Data bit length:
Minimum execution time:
Interrupt processing time:
136
8 bits
1 to 3 bytes
1, 8, and 16 bits
0.95 µs at 4.2 MHz
8.57 µs at 4.2 MHz
Ports
I/O port (N channel open drain):
I/O port (CMOS):
Total:
6
16 (13 serves as resources)
22
8/16-bit timer/
counter
2 channels for 8-bit timer counter or for 16-bit event counter (operation clock: 1.9 µs, 30.4
µs, and 487.6 µs at 4.2 MHz, and external clock)
External interrupt 1
3 independent channels (edge selection, interrupt vector, and interrupt source flag)
Rising edge/falling edge/both edge selectability
Used for wake-up from stop/sleep mode. (Edge detection is also permitted in stop mode.)
External interrupt 2
(Wake-up function)
Remote-control
transmission
frequency
generation
8 channels (low-level interrupt only)
The pulse width and cycle are software-programmable.
(Continued)
2
MB89990 Series
(Continued)
Part number
MB89997
MB89P195*1
MB89PV190*2
Item
Low-power
consumption
(standby mode)
Sleep mode and stop mode
Process
CMOS
Power supply
voltage*3
2.2 V to 6.0 V
2.7 V to 6.0 V
EPROM for use
MBM27C256A-20TVM
*1 : The MB89P195 microtroller is the one-time product for the MB89190 series which can be also be used for the
MB89990 series.
*2 : The MB89PV190 microtroller is the evaluation and development product for the MB89190 series which can
be also be used for the MB89990 series.
*3 : Varies with conditions such as operating frequencies (see “■ Electrical Characteristics.”)
■ PACKAGE AND CORRESPONDING PRODUCTS
Package
MB89997
DIP-28P-M03
MB89P195
MB89PV190
×
×
×
FPT-28P-M17
MQP-48C-P01
: Available
×
×
*
× : Not available
* : A socket (manufacturer: Sun Hayato Co., Ltd.) for pin pitch conversion is available.
480F-28SOP-8L: (MQP-48C-P01) → for conversion to FPT-28P-M02
Inquiry: Sun Hayato Co., Ltd.: TEL: (81)-3-3986-0403
FAX: (81)-3-5396-9106
Note: For more information on each package, see “■ Package Dimensions.”
3
MB89990 Series
■ DIFFERENCES AMONG PRODUCTS
1. Memory Size
Before evaluating using the piggyback model, verify its difference from the model that will actually be used.
Take particular care on the following points:
• On the MB89997, addresses 0140H to 0180H cannot be used for register banks.
• The stack area, etc., is set in the upper limit of the RAM.
2. Current Consumption
• In the case of MB89PV190, add the current consumed by the EPROM which is connected to the top socket.
• When operated at low speed, a model with an OTPROM (EPROM) will consume more current than a model
with a mask ROM.
However, current consumption in the sleep/stop mode in the same. (For more information, see “■ Electrical
Characteristics.”)
3. Mask Options
Functions that can be selected as options and how to designate these options vary by model.
Before using options check “■ Mask Options.”
Take particular care on the following points:
• The power-on reset option is fixed as “enabled” for MB89P195.
• Options are fixed on the MB89PV190.
4
MB89990 Series
■ PIN ASSIGNMENT
(Top view)
P04/INT24
1
28
VCC
P05/INT25
2
27
P03/INT23
P06/INT26
3
26
P02/INT22
P07/INT27
4
25
P01/INT21
TEST
5
24
P00/INT20
RST
6
23
P45
X0
7
22
P44
X1
8
21
P43
VSS
9
20
P42
P37/RCO
10
19
P41
P36/INT12
11
18
P40
P35/INT11
12
17
P30
P34/TO/INT10
13
16
P31
P33/EC
14
15
P32
(FPT-28P-M17)
(DIP-28P-M03)
5
MB89990 Series
P35/INT11
N. C.
N. C.
N. C.
N. C.
N. C.
V SS
N. C.
N. C.
N. C.
N. C.
N. C.
48
47
46
45
44
43
42
41
40
39
38
37
68
67
66
65
64
63
62
61
(Top view)
P34/TO/INT10
1
P33/EC
2
P32/(SI)
3
69
P31/(SO)
4
70
P30/(SCK)
5
71
Each pin inside the dashed line
is for MB89PV190/PV190A
units only.
36
N. C.
35
N. C.
60
34
P36/INT12
59
33
P37/(BZ)/RCO
58
32
X1
57
31
X0
56
30
RST
74
55
29
TEST
P43/(AN3)
9
75
54
28
P07/INT27
P44/(AV SS)
10
76
53
27
P06/INT26
P45/(AVR)
11
26
P05/INT25
P00/INT20/(AN4)
12
25
P04/INT24
13
14
15
16
17
18
19
20
21
22
23
24
P01/INT21/(AN5)
N. C.
N. C.
N. C.
N. C.
V CC
N. C.
N. C.
N. C.
N. C.
P02/INT22/(AN6)
P03/INT23/(AN7)
52
8
51
P42/(AN2)
50
73
49
7
80
P41/(AN1)
79
72
78
6
77
P40/(AN0)
(MQP-48C-P01)
• Pin assignment on the package top (MB89PV190/PV190A only)
Pin no.
Pin name
Pin no.
Pin name
Pin no.
Pin name
Pin no.
Pin name
49
VPP
57
N.C.
65
O4
73
OE
50
A12
58
A2
66
O5
74
N.C.
51
A7
59
A1
67
O6
75
A11
52
A6
60
A0
68
O7
76
A9
53
A5
61
O1
69
O8
77
A8
54
A4
62
O2
70
CE
78
A13
55
A3
63
O3
71
A10
79
A14
56
N.C.
64
VSS
72
N.C.
80
VCC
N.C.: Internally connected. Do not use.
Note: Parenthesized pin function is only for the MB89PV190A.
6
MB89990 Series
■ PIN DESCRIPTION
Pin no.
Pin name
SOP*1,
SH-DIP*2
MQFP*3
7
31
X0
8
32
X1
5
29
6
Circuit type
Function
A
Clock oscillation pins
TEST
B
Test input pin
This pin is connected directly to VSS.
30
RST
C
Reset I/O pin
This pin consists of an N-ch open-drain output with
a pull-up resistor and hysteresis input.
A low level is output from this pin by internal source.
The internal circuit is initialized at the input of a low
level.
24,
25,
26,
27
12,
13,
23,
24
P00/INT20,
P01/INT21,
P02/INT22,
P03/INT23
G
General-purpose I/O ports
Also serve as external interrupt input pins.
External interrupt input is hysteresis input type.
1 to 4
25 to 28
P04/INT24 to
P07/INT27
D
General-purpose I/O ports
Also serve as external interrupt input.
External interrupt input is hysteresis input type.
17
5
P30
D
General-purpose I/O port
Also serves as a serial I/O clock I/O.
The serial I/O clock input is hysteresis input type
with a built-in noise filter.
16
4
P31
E
General-purpose I/O port
Also serves as a serial I/O data output pin.
15
3
P32
D
General-purpose I/O port
Also serves as a serial I/O data input pin.
The serial I/O data input is hysteresis input type
with a built-in noise filter.
14
2
P33/EC
D
General-purpose I/O port
Also serves as an external clock input pin for the 8bit timer/counter.
External clock input of the 8-bit timer/counter is
hysteresis input type with a built-in noise filter.
13
1
P34/TO/INT10
D
General-purpose I/O port
Also serves as the overflow output and external
interrupt input for the 8-bit timer/counter.
External interrupt input is hysteresis input type with
a built-in noise filter.
12,
11
48,
34
P35/INT11,
P36/INT12
D
General-purpose I/O port
Also serve as external interrupt input pins.
External interrupt input is hysteresis input type with
a built-in noise filter.
*1: FPT-28P-M17
*2: DIP-28P-M03
*3: MQP-48C-P01
(Continued)
7
MB89990 Series
(Continued)
Pin no.
Circuit type
Function
MQFP*3
10
33
P37//RCO
E
General-purpose I/O port
Also serves as remote-control output pin.
18 to 21
6 to 9
P40 to P43
F
N-ch open-drain I/O ports
23
11
P45
F
N-ch open-drain type I/O port
22
10
P44
F
N-ch open-drain type I/O port
28
18
VCC
—
Power supply pin
9
42
VSS
—
Power supply (GND) pin
*1: FPT-28P-M17
*2: DIP-28P-M03
*3: MQP-48C-P01
8
Pin name
SOP*1,
SH-DIP*2
MB89990 Series
• External EPROM pins (MB89PV190 only)
Pin no.
Pin name
I/O
Function
49
VPP
O
“H” level output pin
79
78
50
75
71
76
77
51
52
53
54
55
58
59
60
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
O
Address output pins
61
62
63
65
66
67
68
69
O1
O2
O3
O4
O5
O6
O7
O8
I
Data input pins
70
CE
O
ROM chip enable pin
Outputs “H” during standby.
73
OE
O
ROM output enable pin
Outputs “L” at all times.
80
VCC
O
EPROM power pin
64
VSS
O
Power supply (GND) pin
9
MB89990 Series
■ I/O CIRCUIT TYPE
Type
A
Circuit
Remarks
• At an oscillation feedback registor of approximately
1 MΩ at 5.0 V
X1
X0
Standby control signal
• When crystal and ceramic oscillators are selected
optionally
Standby control signal
• When CR oscillation is selected optionally
X1
X0
B
C
• Output pull-up resistor (P-ch): About 50 kΩ at 5.0 V
• Hysteresis input
R
P-ch
N-ch
• Pull-up resistor optional
D
• CMOS output
• CMOS input
• Hysteresis input (resource input)
R
P-ch
P-ch
N-ch
• Pull-up resistor optional
(Continued)
10
MB89990 Series
(Continued)
Type
Circuit
Remarks
E
• CMOS output
• CMOS input
R
P-ch
P-ch
N-ch
• Pull-up resistor optional
F
• N-ch open-drain output
• Analog input
R
P-ch
P-ch
N-ch
Analog input
G
• Pull-up resistor optional (MB89990 series only)
•
•
•
•
R
P-ch
CMOS output
CMOS input
Hysteresis input (resource input)
Analog input
P-ch
N-ch
Analog input
• Pull-up resistor optional (MB89990 series only)
11
MB89990 Series
■ HANDLING DEVICES
1. Preventing Latch-up
Latchup may occur on CMOS ICs if voltage higher than VCC or lower than VSS is applied to input or output pins
other than medium-to high-voltage pins or if higher than the voltage which shows on “ 1. Absolute Maximum
Ratings” in “■ Electrical Characteristics” is applied between VCC to VSS.
When latchup occurs, power supply current increases rapidly and might thermally damage elements. When
using, take great care not to exceed the absolute maximum ratings.
2. Treatment of Unused Input Pins
Leaving unused input pins open could cause malfunctions. They should be connected to pull-up or pull-down
resistor.
3. Treatment of N.C. Pins
Be sure to leave (internally connected) N.C. pins open.
4. Power Supply Voltage Fluctuations
Although VCC power supply voltage is assured to operate within the rated range, a rapid fluctuation of the voltage
could cause malfunctions, even if it occurs within the rated range. Stabilizing voltage supplied to the IC is
therefore important. As stabilization guidelines, it is recommended to control power so that VCC ripple fluctuations
(P-P value) will be less than 10% of the standard VCC value at the commercial frequency (50 to 60 Hz) and the
transient fluctuation rate will be less than 0.1 V/ms at the time of a momentary fluctuation such as when power
is switched.
5. Precautions when Using an External Clock
When an external clock is used, oscillation stabilization time is required even for power-on reset (option selection)
and release from stop mode.
12
MB89990 Series
■ PROGRAMMING TO PROM ON THE MB89P195
The MB89P195 can program data in the internal PROM using a dedicated conversion adaptor and specified
general-purpose EPROM programmer.
1. Memory Space
Address in normal operation mode
EPROM mode
(Corresponding addresses on the EPROM programmer)
0000 H
I/O
0080 H
RAM
0180 H
8000 H
Not available
0000 H
Free area
(Read value FF H)
C000 H
4000 H
PROM
16 KB
FFFF H
EPROM
16 KB
7FFF H
2. Specified ROM Programmer Manufacturer, Model Name, and Programming in ROM
• Recommended ROM programmer
Manufacturer
Model
ADVANTEST
R4945
• Programming procedure
(1) Load program data into the ROM programmer at addresses 4000H to 7FFFH. (Addresses 0C000H to 0FFFFH
in the operation mode assign to 4000H to 7FFFH in ROM programmer. See the illustration above.)
(2) Set the data at addresses 0000H to 3FFFH of the programmer ROM in the ROM programmer, to FFH.
(3) To set up the successive-address write mode of the ROM programmer, press the DEVICE, PROG, SET,
SELECT, E and SET keys in this order.
Note: Program must be started at the address 0000H.
For details, contact our Sales Division.
13
MB89990 Series
3. Recommended Screening Conditions
High-temperature aging is recommended as the pre-assembly screening procedure for a product with a blanked
OTPROM microcontroller program.
Program, verify
Aging
+150°C for 48 Hrs.
Data verification
Assembly
4. Programming Yield
All bits cannot be programmed at Fujitsu shipping test to a blanked OTPROM microcomputer, due to its nature
(one time PROM). For this reason, a programming yield of 100% cannot be assured at all times.
5. EPROM Programmer Socket Adapter and Recommended Programmer Manufacturer
Part no.
MB89P195PF
Package
SOP-28
Compatible socket adapter
Sun Hayato Co., Ltd.
Minato
Electronics Inc.
Recommended
programmer
manufacturer and
programmer name
ROM-28SOP-28DP-8L
MODEL 1890A
(ver. 2.2)
+
OU-910 (ver. 4.1)
UNISITE
(ver. 5.0 or later)
Data I/O Co., Ltd.
3900
(ver. 2.8 or later)
2900
(ver. 3.8 or later)
Inquiry: Sun Hayato Co., Ltd. : TEL: (81)-3-3986-0403
FAX: (81)-3-5396-9106
Minato Electronics Inc. : TEL: USA (1)-916-348-6066
JAPAN (81)-45-591-5611
Data I/O Co., Ltd. : TEL: USA/ASIA (1)-206-881-6444
EUROPE (49)-8-985-8580
14
Recommended
Recommended
MB89990 Series
■ PROGRAMMING TO THE EPROM WITH PIGGYBACK/EVALUATION DEVICE
1. EPROM for Use
MBM27C256A-20TVM
2. Programming Socket Adapter
To program to the EPROM using an EPROM programmer, use the socket adapter (manufacturer: Sun Hayato
Co., Ltd.) below.
Package
Adapter socket part number
LCC-32 (Rectangle)
ROM-32LC-28DP-S
Inquiry: Sun Hayato Co., Ltd.: TEL: (81)-3-3986-0403
FAX: (81)-3-5396-9106
3. Memory Space
Address in normal operation mode
Address when writing to EPROM
(Corresponding addresses on the EPROM programmer)
0000 H
I/O
0080 H
RAM
0180 H
Not available
8000 H
0000 H
EPROM
32 KB
PROM
32 KB
FFFF H
7FFF H
4. Programming to the EPROM
(1) Set the EPROM programmer to MBM27C256A.
(2) Load program data into the EPROM programmer at 0006H to 7FFFH.
(3) Program to 0000H to 7FFFH with the EPROM programmer.
15
MB89990 Series
■ BLOCK DIAGRAM
Clock control
RST
Remote-control
carrier frequency
Main oscillator
circuit
Reset circuit
(WDT)
P34/TO/INT10
P33/EC
8-bit timer/counter
Port 3
X1
Internal data bus
X0
P30 to P32
8-bit timer/counter
P35/INT11
External interrupt
P36/INT12
Timebase timer
CMOS I/O port
P37/RCO
RAM
(128 × 8 bits)
F2MC-8L
CPU
External interrupt
(wake-up function)
Port 0
CMOS I/O port
8
P00/INT20 to
P07/INT27
Port 4
ROM
(32K × 8 bits)
The other pins
6
TEST, VCC, VSS
N-ch open drain I/O port
16
P40 to P45
MB89990 Series
■ CPU CORE
1. Memory Space
The microcontrollers of MB89990 series offer 64 Kbytes of memory for storing all of I/O, data, and program
areas. The I/O area is located at the lowest address. The data area is provide immediately above the I/O area.
The data area can be divided into register, stack, and direct areas according to the application. The program
area is located at exactly the opposite end of I/O area, that is, near the highest address. Provide the tables of
interrupt reset vectors, and vector call instructions toward the highest address within the program area. The
memory space of the MB89990 series is structured below:
• Memory Space
MB89997
0000H
0080H
00C0H
I/O
Reserved
MB89P195
0000H
0080H
I/O
RAM
MB89PV190
0000H
RAM
256 B
RAM
128 B
0100H Register
0100H
0140H
0200H
Register
I/O
0080H
256 B
0100H
Register
0200H
0280H
Not available
0280H
Not available
Not available
C000H
8000H
8000H
ROM
ROM
32 KB
ROM
32 KB
16 KB
FFFFH
17
MB89990 Series
2. Registers
The F2MC-8L family has two types of registers; dedicated registers in the CPU and general-purpose registers
in the memory. The following dedicated registers are provided:
Program counter (PC):
A 16-bit-long register for indicating the instruction storage positions
Accumulator (A):
A 16-bit-long temporary register for storing arithmetic operations, etc. When the
instruction is an 8-bit data processing instruction, the lower byte is used.
Temporary accumulator (T):
A 16-bit-long register which performs arithmetic operations with the accumulator.
When the instruction is an 18-bit data processing instruction, the lower byte is
used.
Index register (IX):
A 16-bit-long register for index modification
Extra pointer (EP) :
A 16-bit-long pointer for indicating a memory address
Stack pointer (SP) :
A 16-bit-long register for indicating a stack area
Program status (PS) :
A 16-bit-long register for storing a register pointer, a condition code
Initial value
16 bits
FFFDH
: Program counter
PC
A
: Accumulator
T
: Temporary accumulator Indeterminate
IX
: Index register
Indeterminate
EP
: Extra pointer
Indeterminate
SP
: Stack pointer
Indeterminate
PS
: Program status
Indeterminate
I-flag = 0, IL1, 0 = 11
The other bit values are indeterminate.
The PS can further be divided into higher 8 bits for use as a register bank pointer (RP) and the lower 8 bits for
use as a condition code register (CCR) (see the diagram below).
• Structure of the Program Status Register
15
PS
14
13
12
RP
10
9
8
Vacancy Vacancy Vacancy
RP
18
11
7
6
H
I
5
4
IL1, 0
3
2
1
0
N
Z
V
C
CCR
MB89990 Series
The RP indicates the address of the register bank currently in use. The relationship between the pointer contents
and the actual address is based on the conversion rule illustrated below.
• Rule for Conversion of Actual Addresses of the General-purpose Register Area
RP
Lower OP codes
“0” “0” “0” “0” “0” “0” “0” “1” R4 R3 R2 R1 R0 b2
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
b1
b0
↓
↓
Generated addresses A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
The CCR consists of bits indicating the results of arithmetic operations and the contents of transfer data and
bits for control of CPU operations at the time of an interrupt.
H-flag: Set to ‘1’ when a carry or a borrow from bit 3 to bit 4 occurs as a result of an arithmetic operation.
Cleared to ‘0’ otherwise. This flag is for decimal adjustment instructions.
I-flag:
Interrupt is enabled when this flag is set to ‘1’. Interrupt is disabled when the flag is cleared to ‘0’.
Cleared to ‘0’ at the rest.
IL1, 0:
Indicates the level of the interrupt currently allowed. Processes an interrupt only if its request level is
higher than the value indicated by this bit.
IL1
IL0
Interrupt level
0
0
0
1
1
0
2
1
1
3
1
High-low
High
Low
N-flag: Set to ‘1’ if the MSB becomes 1 as the result of an arithmetic operation. Cleared to ‘0’ when the bit is
cleared to ‘0’.
Z-flag:
Set to ‘1’ when an arithmetic operation results in 0. Cleared otherwise.
V-flag:
Set to ‘1’ if the complement on 2 overflows as a result of an arithmetic operation. Cleared to ‘0’ if the
overflow does not occur.
C-flag: Set to ‘1’ when a carry or a borrow from bit 7 occurs as a result of an arithmetic operation. Cleared to
‘0’ otherwise.
Set the shift-out value in the case of a shift instruction.
19
MB89990 Series
The following general-purpose registers are provided:
General-purpose registers: An 8-bit-long register for storing data
The general-purpose registers are 8 bits and located in register banks of the memory. One bank contains eight
registers and up to a total of 16 banks can be used on the MB89957 (RAM 128 × 8 bits). The bank currently in
use is indicated by the register bank pointer. (RP)
Note: The number of register banks that can be used varies with the RAM size.
• Register Bank Configuraiton
This address = 0100 H + 8 × (RP)
R0
R1
R2
R3
R4
R5
R6
R7
16 banks
(8 banks for the MB89957)
Memory area
20
MB89990 Series
■ I/O MAP
Address
Read/write
Register name
00H
(R/W)
PDR0
Port 0 data register
01H
(W)
DDR0
Port 0 data direction register
02H to 07H
Register description
Vacancy
08H
(R/W)
STBC
Standby control register
09H
(R/W)
WDTC
Watchdog timer control register
0AH
(R/W)
TBTC
Timebase timer control register
0BH
Vacancy
0CH
(R/W)
PDR3
Port 3 data register
0DH
(W)
DDR3
Port 3 data direction register
0EH
(R/W)
PDR4
Port 4 data register
0FH to 13H
Vacancy
14H
(R/W)
RCR1
Remote-control register 1
15H
(R/W)
RCR2
Remote-control register 2
16H
Vacancy
17H
Vacancy
18H
(R/W)
T2CR
Timer 2 control register
19H
(R/W)
T1CR
Timer 1 control register
1AH
(R/W)
T2DR
Timer 2 data register
1BH
(R/W)
T1DR
Timer 1 data register
1CH to 22H
Vacancy
23H
(R/W)
EIC1
External interrupt control register 1
24H
(R/W)
EIC2
External interrupt control register 2
25H to 31H
Vacancy
32H
(R/W)
EIE2
External interrupt 2 enable register
33H
(R/W)
EIF2
External interrupt 2 flag register
34H to 7BH
Vacancy
7CH
(W)
ILR1
Interrupt level register 1
7DH
(W)
ILR2
Interrupt level register 2
7EH
(W)
ILR3
Interrupt level register 3
7FH
Vacancy
Note: Do not use vacancies.
21
MB89990 Series
■ ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Rating
(VSS = 0.0 V)
Parameter
Symbol
Value
Min.
Max.
Unit
Remarks
Power supply voltage
VCC
VSS – 0.3
VSS + 7.0
V
EPROM program voltage
VPP
VSS – 0.3
VSS + 13.0
V
Input voltage
VI
VSS – 0.3
VCC + 0.3
V
Output voltage
VO
VSS – 0.3
VCC + 0.3
V
“L” level maximum output
current
IOL1

10
mA
Except P33 and P34
IOL2

20
mA
P33, P34
IOLAV1

4
mA
Except P33 and P34
Average value (operating
current × operation rate)
IOLAV2

8
mA
P33 and P34
Average value (operating
current × operation rate)
“L” level total average output
current
ΣIOLAV

20
mA
Average value (operating
current × operation rate)
“L” level maximum total output
current
ΣIOL

–100
mA
“H” level maximum output
current
IOH1

–10
mA
Except P33, P34, and P37
IOH2

–20
mA
P33, P34, P37
IOHAV1

–2
mA
Except P33, P34, and P37
Average value (operating
current × operation rate)
IOHAV2

–4
mA
Except P33, P34, and P37
Average value (operating
current × operation rate)
“H” level total average output
current
ΣIOHAV

–10
mA
Average value (operating
current × operation rate)
“H” level total maximum output
current
ΣIOH

–30
mA
Power consumption
PD

200
mW
Operating temperature
TA
–40
+85
°C
Storage temperature
Tstg
–55
+150
°C
“L” level average output current
“H” level average output
current
Applicable to TEST pin of
MB89P195.
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
22
MB89990 Series
2. Recommended Operating Conditions
(VSS = 0.0 V)
Symbol
Parameter
Power supply voltage
VCC
Operating temperature
TA
Value
Unit
Remarks
Min.
Max.
2.2*
6.0*
V
Normal operation assurance range*
MB89997
2.7*
6.0*
V
Normal operation assurance range*
MB89P195
1.5
6.0
V
Retains the RAM state in stop mode
–40
+85
°C
* : The guaranteed normal operation range varies depending on the operation frequency and the guaranteed analog
operation range. See Figure 1.
• Figure 1 Operating Voltage vs. Main Clock Operating Frequency
Operating voltage (V)
6
5
Operation assurance range
4
3
2
1
1
2
3
4
Main clock operation frequency (at an instruction cycle of 4/Fc) (MHz)
4.0
2.0
0.95 (µs)
Minimum execution time (instruction cycle) (µs)
Note: The shaded area is assured only for the MB89997.
Figure 1 indicates the operating frequency of the external oscillator at an instruction cycle of 4/FC.
WARNING: Recommended operating conditions are normal operating ranges for the semiconductor device. All the
device’s electrical characteristics are warranted when operated within these ranges.
Always use semiconductor devices within the recommended operating conditions. Operation outside
these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representative beforehand.
23
MB89990 Series
3. DC Characteristics
Parameter
Symbol
Pin name
Condition
(VCC = +5.0 V, VSS = 0.0 V, TA = –40°C to +85°C)
Value
Unit Remarks
Min.
Typ.
Max.
VIH
P00 to P07,
P30 to P37,
TEST
—
0.7 VCC
—
VCC + 0.3
V
VIHS
RST,
INT10 to INT12,
EC,
INT20 to INT27
—
0.8 VCC
—
VCC + 0.3
V
VIL
P00 to P03,
P33 to P36,
TEST
—
VSS − 0.3
—
0.3 VCC
V
VILS
RST,
INT10 to INT12,
EC,
INT 20 to INT27
—
VSS − 0.3
—
0.2 VCC
V
VD
P40 to P44
—
VSS − 0.3
—
VSS + 0.3
V
VOH1
P00 to P07,
P30 to P32,
P35, P36
IOH = –2.0 mA
4.0
—
—
V
VOH2
P33, P34
IOH = –4.0 mA
4.0
—
—
V
VOH3
P37
IOH = –4.0 mA
4.0
—
—
V
VOL1
P00 to P07,
P30 to P32,
P35 to P37
IOL = 4.0 mA
—
—
0.4
V
VOL2
RST
IOL = 4.0 mA
—
—
0.4
V
VOL3
P33, P34
IOL = 12 mA
—
—
0.4
V
VOL4
P40 to P45
IOL = 8 mA
—
—
0.4
V
ILI1
P00 to P07,
P30 to P37,
TEST
0.45 V < VI <
VCC
—
—
±5
µA
Without
pull-up
resistor
Open-drain
output leakage
ILD1
current (Off state)
P40 to P45
0.45 V < VI <
VCC
—
—
±5
µA
Without
pull-up
resistor
Pull-up
resistance
P00 to P07,
P30 to P37,
P40 to P45,
RST
VI = 0.0 V
25
50
100
kΩ
“H” level
input voltage
“L” level
input voltage
Open-drain
output pin
application
voltage
“H” level
output voltage
“L” level
output voltage
Input leakage
current
(Hi-z output
leakage current)
RPULL
(Continued)
24
MB89990 Series
(Continued)
Parameter
Pin name
Symbol
ICC
Power supply
voltage*
ICCS
—
5
10
mA MB89997
—
7
12
mA MB89P195
FC = 4.2 MHz
—
3
7
mA Sleep mode
TA = +25 °C
—
—
1
µA
—
10
—
pF
FC = 4.2 MHz
VCC
ICCH
Input capacitance CIN
Condition
(VCC = 5.0 V, VSS = 0.0 V, TA = –40°C to +85°C)
Value
Unit Remarks
Min.
Typ.
Max.
Except AVR,
f = 1 MHz
AVSS, VCC, and VSS
Stop mode
* : For the MB89PV190, the current consumption of a connected EPROM and ICE is not included.
The mesurement condition of the power supply current are set as VCC = 5.0 V with an external clock.
4. AC Characteristics
(1) Reset Timing
Parameter
RST “L” pulse width
Symbol
(VCC = +5.0 V±10%, VSS = 0.0 V, TA = –40°C to +85°C)
Value
Condition
Unit
Remarks
Min.
Max.
tZLZH
—
16 tHCYL
—
ns
Note: tXCYL is the oscillation period (1/FC) input to the X0 pin.
t ZLZH
RST
0.2 VCC
0.2 VCC
25
MB89990 Series
(2) Power-on Reset
(VSS = 0.0 V, TA = –40°C to +85°C)
Parameter
Symbol
Power supply rising time
tR
Power supply cut-off time
tOFF
Condition
—
Value
Unit
Min.
Max.
—
50
ms
1
—
ms
Remarks
Due to repeated operations
Note: Make sure that power supply rises within the selected oscillation stabilization time.
If power supply voltage needs to be varied in the course of operation, a smooth voltage rise is recommended.
tR
t OFF
2.0 V
VCC
26
0.2 V
0.2 V
0.2 V
MB89990 Series
(3) Clock Timing
(VSS = 0.0 V, TA = –40°C to +85°C)
Symbol
Parameter
Pin
name
Value
Condition
Min.
Max.
Unit
Remarks
Clock frequency
FC
X0, X1
—
1
4.2
MHz
Clock cycle time
tXCYL
X0, X1
—
238
1000
ns
Input clock pulse width
PWH
PWL
X0
—
20
—
ns
External clock
Input clock pulse
risilng/falling time
tCR
tCF
X0
—
—
10
ns
External clock
• Timings Conditions
t XCYL
PWL
PWH
t CR
t CF
0.8 VCC
0.8 VCC
X0
0.2 VCC
0.2 VCC
0.2 VCC
• Clock Configurations
When a crystal or ceramic resonator is used
X0
X1
When an external clock is used
X0
X1
Open
(4) Instruction Cycle
(VSS = 0.0 V, TA = –40°C to +85°C)
Parameter
Instruction cycle
(minimum execution time)
Symbol
tinst
Value (typical)
Unit
4/FC
µs
Remarks
tinst = 0.95 µs when operating at
FC = 4.2 MHz
27
MB89990 Series
(5) Peripheral Input Timing
(VCC = 5.0 V±10%, VSS = 0.0 V, TA = –40°C to +85°C)
Value
Pin name
Unit Remarks
Min.
Max.
Symbol
Parameter
Peripheral input “H” pulse width 1
tILIH1
Peripheral input “L” pulse width 1
tIHIL1
EC, INT10 to INT12,
INT20 to INT27
2 tinst*
—
µs
2 tinst*
—
µs
* : For information on tinst, see “(4) Instruction Cycles.”
• Peripheral Input Timing Diagram
t IHIL
t ILIH
EC
INT10 to INTR
INT20 to INT27
0.8 VCC
0.2 VCC
0.8 VCC
0.2 VCC
(VCC = 5.0 V±10%, VSS = 0.0 V, TA = –40°C to +85°C)
Parameter
Symbol
Value
Pin name
Min.
Typ.
Max.
Peripheral input “H” noise
limit width
tIHNC
EC,
INT10 to INT12
7
15
23
ns
Peripheral input “L” noise
limit width
tILNC
EC, INT10 to INT12,
INT20 to INT27
7
15
23
ns
• Peripheral Input Timing Diagram
t ILNC
EC
INT10 to INT12
t IHNC
0.8 VCC
0.2 VCC
28
Unit
0.2 VCC
0.8 VCC
Remarks
MB89990 Series
■ EXAMPLE CHARACTERISTICS
(1) “L” Level Output Voltage
VOL1 vs. IOL
VCC = 2.5 V
VCC = 3.0 V
VCC = 2.0 V
VOL (V)
0.30
VCC = 4.0 V
TA = +25°C
0.25
VCC = 5.0 V
VCC = 6.0 V
0.20
0.4
0.10
0.2
0.05
0.1
1
2
3
4
5
IOL (mA)
VCC = 5.0 V
VCC = 6.0 V
0.5
0.3
0
VCC = 4.0 V
TA = +25°C
0.15
0.00
VOL2 vs. IOL
VCC = 2.5 V
VCC = 3.0 V
VCC = 2.0 V
VOL (V)
0.6
0.0
0
1
2
3
4
5
6
7
8
9
10
IOL (mA)
VOL3 vs. IOL
VOL (V)
1.2
VCC = 2.0 V
VCC = 2.5 V
TA = +25°C
1.0
0.8
VCC = 3.0 V
0.6
VCC = 4.0 V
VCC = 5.0 V
VCC = 6.0 V
0.4
0.2
0.0
0
2
4
6
8
10 12
14 16
18 20
IOL (mA)
29
MB89990 Series
(2) “H” Level Output Voltage
VOH1 vs. IOH
VCC = 4.0 V
VCC = 2.5 V
VCC = 2.0 V
VCC = 3.0 V
VCC - VOH (V)
0.6
TA = +25°C
0.5
VOH2 vs. IOH
VCC = 5.0 V
VCC = 6.0 V
VCC - VOH (V)
VCC = 3.0 V
3.0
TA = +25°C
VCC = 2.5 V
2.5
0.4
2.0
0.3
1.5
0.2
1.0
0.1
0.5
0.0
0
–1
–2
–3
–4
–5
IOH (mA)
0.0
VCC = 2.0 V
VCC = 4.0 V
VCC = 5.0 V
VCC = 6.0 V
0
–4
–8
– 12
– 16
– 20
IOH (mA)
VOH3 vs. IOH
VCC - VOH (V)
VCC = 2.0 V
1.2
TA = + 25°C
VCC = 2.5 V
VCC = 3.0 V
1.0
0.8
VCC = 4.0 V
0.6
VCC = 5.0 V
VCC = 6.0 V
0.4
0.2
0.0
0
–2
–4
–6
–8
– 10
IOH (mA)
(3) “H” Level Input Voltage/“L” Level
Input Voltage (CMOS Input)
(4) “H” Level Input Voltage/“L” Level
Input Voltage (Hysteresis Input)
VIN vs. VCC
VIN (V)
5.0
4.5
3.5
3.0
3.5
2.5
3.0
2.0
2.5
1.5
2.0
1.0
1.5
0.5
1.0
0.0
30
VIHS
VILS
0
0.5
0
TA = +25°C
4.0
TA= +25°C
4.0
0.0
VIN vs. VCC
VIN (V)
5.0
4.5
1
2
3
4
5
6
7
VCC (V)
1
2
3
4
5
6
7
VCC (V)
VIHS: Threshold when input voltage in hysteresis
characteristics is set to “H” level
VILS: Threshold when input voltage in hysteresis
characteristics is set to “L” level
MB89990 Series
(5) Power Supply Current (External Clock)
ICC vs. VCC
ICC (mA)
6
ICCS vs. VCC
ICCS (mA)
1.50
TA = +25°C
TA = +25°C
5
Fc = 4.2 MHz
1.25
Fc = 4.2 MHz
4
1.00
Fc = 3.0 MHz
3
Fc = 3.0 MHz
0.75
2
0.50
Fc = 1.0 MHz
1
Fc = 1.0 MHz
0.25
0
0.00
1
2
3
4
5
6
7
2
1
3
4
5
6
7
VCC (V)
5
6
7
AVR (V)
VCC (V)
ICCH vs. VCC
ICCH (µA)
2.0
IR vs. AVR
IR (µA)
150
TA = +25°C
1.8
TA = +25°C
1.6
125
1.4
100
1.2
1.0
75
0.8
50
0.6
0.4
25
0.2
0
0
1
2
3
4
5
6
7
1
2
3
VCC (V)
4
(3) Pull-up Resistance
RPULL vs. VCC
RPULL (kΩ)
1000
TA = +25°C
100
10
1
2
3
4
5
6
VCC (V)
31
MB89990 Series
■ INSTRUCTIONS
Execution instructions can be divided into the following four groups:
•
•
•
•
Transfer
Arithmetic operation
Branch
Others
Table 1 lists symbols used for notation for instructions.
Table 1
Instruction Symbols
Symbol
Meaning
dir
Direct address (8 bits)
off
Offset (8 bits)
ext
Extended address (16 bits)
#vct
Vector table number (3 bits)
#d8
Immediate data (8 bits)
#d16
Immediate data (16 bits)
dir: b
Bit direct address (8:3 bits)
rel
Branch relative address (8 bits)
@
Register indirect (Example: @A, @IX, @EP)
A
Accumulator A (Whether its length is 8 or 16 bits is determined by the instruction in use.)
AH
Upper 8 bits of accumulator A (8 bits)
AL
Lower 8 bits of accumulator A (8 bits)
T
Temporary accumulator T (Whether its length is 8 or 16 bits is determined by the
instruction in use.)
TH
Upper 8 bits of temporary accumulator T (8 bits)
TL
Lower 8 bits of temporary accumulator T (8 bits)
IX
Index register IX (16 bits)
(Continued)
32
MB89990 Series
(Continued)
Symbol
Meaning
EP
Extra pointer EP (16 bits)
PC
Program counter PC (16 bits)
SP
Stack pointer SP (16 bits)
PS
Program status PS (16 bits)
dr
Accumulator A or index register IX (16 bits)
CCR
Condition code register CCR (8 bits)
RP
Register bank pointer RP (5 bits)
Ri
General-purpose register Ri (8 bits, i = 0 to 7)
×
Indicates that the very × is the immediate data.
(Whether its length is 8 or 16 bits is determined by the instruction in use.)
(×)
Indicates that the contents of × is the target of accessing.
(Whether its length is 8 or 16 bits is determined by the instruction in use.)
(( × ))
The address indicated by the contents of × is the target of accessing.
(Whether its length is 8 or 16 bits is determined by the instruction in use.)
Columns indicate the following:
Mnemonic:
Assembler notation of an instruction
~:
The number of instructions
#:
The number of bytes
Operation:
Operation of an instruction
TL, TH, AH:
A content change when each of the TL, TH, and AH instructions is executed. Symbols in
the column indicate the following:
• “-” indicates no change.
• dH is the 8 upper bits of operation description data.
• AL and AH must become the contents of AL and AH prior to the instruction executed.
• 00 becomes 00.
N, Z, V, C:
An instruction of which the corresponding flag will change. If + is written in this column,
the relevant instruction will change its corresponding flag.
OP code:
Code of an instruction. If an instruction is more than one code, it is written according to
the following rule:
Example: 48 to 4F ← This indicates 48, 49, ... 4F.
33
MB89990 Series
Table 2
Transfer Instructions (48 instructions)
Mnemonic
~
#
Operation
TL
TH
AH
NZVC
OP code
MOV dir,A
MOV @IX +off,A
MOV ext,A
MOV @EP,A
MOV Ri,A
MOV A,#d8
MOV A,dir
MOV A,@IX +off
MOV A,ext
MOV A,@A
MOV A,@EP
MOV A,Ri
MOV dir,#d8
MOV @IX +off,#d8
MOV @EP,#d8
MOV Ri,#d8
MOVW dir,A
MOVW @IX +off,A
3
4
4
3
3
2
3
4
4
3
3
3
4
5
4
4
4
5
2
2
3
1
1
2
2
2
3
1
1
1
3
3
2
2
2
2
–
–
–
–
–
AL
AL
AL
AL
AL
AL
AL
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
––––
––––
––––
––––
––––
++––
++––
++––
++––
++––
++––
++––
––––
––––
––––
––––
––––
––––
45
46
61
47
48 to 4F
04
05
06
60
92
07
08 to 0F
85
86
87
88 to 8F
D5
D6
MOVW ext,A
MOVW @EP,A
MOVW EP,A
MOVW A,#d16
MOVW A,dir
MOVW A,@IX +off
5
4
2
3
4
5
3
1
1
3
2
2
–
–
–
AL
AL
AL
–
–
–
AH
AH
AH
–
–
–
dH
dH
dH
––––
––––
––––
++––
++––
++––
D4
D7
E3
E4
C5
C6
MOVW A,ext
MOVW A,@A
MOVW A,@EP
MOVW A,EP
MOVW EP,#d16
MOVW IX,A
MOVW A,IX
MOVW SP,A
MOVW A,SP
MOV @A,T
MOVW @A,T
MOVW IX,#d16
MOVW A,PS
MOVW PS,A
MOVW SP,#d16
SWAP
SETB dir: b
CLRB dir: b
XCH A,T
XCHW A,T
XCHW A,EP
XCHW A,IX
XCHW A,SP
MOVW A,PC
5
4
4
2
3
2
2
2
2
3
4
3
2
2
3
2
4
4
2
3
3
3
3
2
3
1
1
1
3
1
1
1
1
1
1
3
1
1
3
1
2
2
1
1
1
1
1
1
(dir) ← (A)
( (IX) +off ) ← (A)
(ext) ← (A)
( (EP) ) ← (A)
(Ri) ← (A)
(A) ← d8
(A) ← (dir)
(A) ← ( (IX) +off)
(A) ← (ext)
(A) ← ( (A) )
(A) ← ( (EP) )
(A) ← (Ri)
(dir) ← d8
( (IX) +off ) ← d8
( (EP) ) ← d8
(Ri) ← d8
(dir) ← (AH),(dir + 1) ← (AL)
( (IX) +off) ← (AH),
( (IX) +off + 1) ← (AL)
(ext) ← (AH), (ext + 1) ← (AL)
((EP)) ← (AH),( (EP) + 1) ← (AL)
(EP) ← (A)
(A) ← d16
(AH) ← (dir), (AL) ← (dir + 1)
(AH) ← ((IX) +off),
(AL) ← ( (IX) +off + 1)
(AH) ← (ext), (AL) ← (ext + 1)
(AH) ← ( (A) ), (AL) ← ( (A) ) + 1)
AL
AL
AL
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
AL
AL
–
–
–
–
AH
AH
AH
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
AH
–
–
–
–
dH
dH
dH
dH
–
–
dH
–
dH
–
–
–
dH
–
–
AL
–
–
–
dH
dH
dH
dH
dH
++––
++––
++––
––––
––––
––––
––––
––––
––––
––––
––––
––––
––––
++++
––––
––––
––––
––––
––––
––––
––––
––––
––––
––––
C4
93
C7
F3
E7
E2
F2
E1
F1
82
83
E6
70
71
E5
10
A8 to AF
A0 to A7
42
43
F7
F6
F5
F0
(AH) ← ( (EP) ), (AL) ← ( (EP) + 1)
(A) ← (EP)
(EP) ← d16
(IX) ← (A)
(A) ← (IX)
(SP) ← (A)
(A) ← (SP)
( (A) ) ← (T)
( (A) ) ← (TH),( (A) + 1) ← (TL)
(IX) ← d16
(A) ← (PS)
(PS) ← (A)
(SP) ← d16
(AH) ↔ (AL)
(dir): b ← 1
(dir): b ← 0
(AL) ↔ (TL)
(A) ↔ (T)
(A) ↔ (EP)
(A) ↔ (IX)
(A) ↔ (SP)
(A) ← (PC)
Notes: • During byte transfer to A, T ← A is restricted to low bytes.
• Operands in more than one operand instruction must be stored in the order in which their mnemonics
are written. (Reverse arrangement of F2MC-8 family)
34
MB89990 Series
Table 3
Arithmetic Operation Instructions (62 instructions)
Mnemonic
~
#
Operation
TL
TH
AH
NZVC
OP code
ADDC A,Ri
ADDC A,#d8
ADDC A,dir
ADDC A,@IX +off
ADDC A,@EP
ADDCW A
ADDC A
SUBC A,Ri
SUBC A,#d8
SUBC A,dir
SUBC A,@IX +off
SUBC A,@EP
SUBCW A
SUBC A
INC Ri
INCW EP
INCW IX
INCW A
DEC Ri
DECW EP
DECW IX
DECW A
MULU A
DIVU A
ANDW A
ORW A
XORW A
CMP A
CMPW A
RORC A
3
2
3
4
3
3
2
3
2
3
4
3
3
2
4
3
3
3
4
3
3
3
19
21
3
3
3
2
3
2
1
2
2
2
1
1
1
1
2
2
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
(A) ← (A) + (Ri) + C
(A) ← (A) + d8 + C
(A) ← (A) + (dir) + C
(A) ← (A) + ( (IX) +off) + C
(A) ← (A) + ( (EP) ) + C
(A) ← (A) + (T) + C
(AL) ← (AL) + (TL) + C
(A) ← (A) − (Ri) − C
(A) ← (A) − d8 − C
(A) ← (A) − (dir) − C
(A) ← (A) − ( (IX) +off) − C
(A) ← (A) − ( (EP) ) − C
(A) ← (T) − (A) − C
(AL) ← (TL) − (AL) − C
(Ri) ← (Ri) + 1
(EP) ← (EP) + 1
(IX) ← (IX) + 1
(A) ← (A) + 1
(Ri) ← (Ri) − 1
(EP) ← (EP) − 1
(IX) ← (IX) − 1
(A) ← (A) − 1
(A) ← (AL) × (TL)
(A) ← (T) / (AL),MOD → (T)
(A) ← (A) ∧ (T)
(A) ← (A) ∨ (T)
(A) ← (A) ∀ (T)
(TL) − (AL)
(T) − (A)
→C →A
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
dL
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
00
–
–
–
–
–
–
–
–
–
–
–
dH
–
–
–
–
–
–
dH
–
–
–
–
dH
–
–
–
dH
dH
00
dH
dH
dH
–
–
–
++++
++++
++++
++++
++++
++++
++++
++++
++++
++++
++++
++++
++++
++++
+++–
––––
––––
++––
+++–
––––
––––
++––
––––
––––
++R–
++R–
++R–
++++
++++
++–+
28 to 2F
24
25
26
27
23
22
38 to 3F
34
35
36
37
33
32
C8 to CF
C3
C2
C0
D8 toDF
D3
D2
D0
01
11
63
73
53
12
13
03
ROLC A
2
1
C←A←
–
–
–
++–+
02
CMP A,#d8
CMP A,dir
CMP A,@EP
CMP A,@IX +off
CMP A,Ri
DAA
DAS
XOR A
XOR A,#d8
XOR A,dir
XOR A,@EP
XOR A,@IX +off
XOR A,Ri
AND A
AND A,#d8
AND A,dir
2
3
3
4
3
2
2
2
2
3
3
4
3
2
2
3
2
2
1
2
1
1
1
1
2
2
1
2
1
1
2
2
(A) −d8
(A) − (dir)
(A) − ( (EP) )
(A) − ( (IX) +off)
(A) − (Ri)
Decimal adjust for addition
Decimal adjust for subtraction
(A) ← (AL) ∀ (TL)
(A) ← (AL) ∀ d8
(A) ← (AL) ∀ (dir)
(A) ← (AL) ∀ ( (EP) )
(A) ← (AL) ∀ ( (IX) +off)
(A) ← (AL) ∀ (Ri)
(A) ← (AL) ∧ (TL)
(A) ← (AL) ∧ d8
(A) ← (AL) ∧ (dir)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
++++
++++
++++
++++
++++
++++
++++
++R–
++R–
++R–
++R–
++R–
++R–
++R–
++R–
++R–
14
15
17
16
18 to 1F
84
94
52
54
55
57
56
58 to 5F
62
64
65
(Continued)
35
MB89990 Series
(Continued)
Mnemonic
~
#
AND A,@EP
AND A,@IX +off
AND A,Ri
OR A
OR A,#d8
OR A,dir
OR A,@EP
OR A,@IX +off
OR A,Ri
CMP dir,#d8
CMP @EP,#d8
CMP @IX +off,#d8
CMP Ri,#d8
INCW SP
DECW SP
3
4
3
2
2
3
3
4
3
5
4
5
4
3
3
1
2
1
1
2
2
1
2
1
3
2
3
2
1
1
Operation
(A) ← (AL) ∧ ( (EP) )
(A) ← (AL) ∧ ( (IX) +off)
(A) ← (AL) ∧ (Ri)
(A) ← (AL) ∨ (TL)
(A) ← (AL) ∨ d8
(A) ← (AL) ∨ (dir)
(A) ← (AL) ∨ ( (EP) )
(A) ← (AL) ∨ ( (IX) +off)
(A) ← (AL) ∨ (Ri)
(dir) – d8
( (EP) ) – d8
( (IX) +off) – d8
(Ri) – d8
(SP) ← (SP) + 1
(SP) ← (SP) – 1
Table 4
Mnemonic
BZ/BEQ rel
BNZ/BNE rel
BC/BLO rel
BNC/BHS rel
BN rel
BP rel
BLT rel
BGE rel
BBC dir: b,rel
BBS dir: b,rel
JMP @A
JMP ext
CALLV #vct
CALL ext
XCHW A,PC
RET
RETI
PUSHW A
POPW A
PUSHW IX
POPW IX
NOP
CLRC
SETC
CLRI
SETI
36
TH
AH
NZVC
OP code
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
++R–
++R–
++R–
++R–
++R–
++R–
++R–
++R–
++R–
++++
++++
++++
++++
––––
––––
67
66
68 to 6F
72
74
75
77
76
78 to 7F
95
97
96
98 to 9F
C1
D1
Branch Instructions (17 instructions)
~
#
Operation
TL
TH
AH
NZVC
OP code
3
3
3
3
3
3
3
3
5
5
2
3
6
6
3
4
6
2
2
2
2
2
2
2
2
3
3
1
3
1
3
1
1
1
If Z = 1 then PC ← PC + rel
If Z = 0 then PC ← PC + rel
If C = 1 then PC ← PC + rel
If C = 0 then PC ← PC + rel
If N = 1 then PC ← PC + rel
If N = 0 then PC ← PC + rel
If V ∀ N= 1 then PC ← PC + rel
If V ∀ N= 0 then PC ← PC + reI
If (dir: b)= 0 then PC ← PC + rel
If (dir: b)= 1 then PC ← PC + rel
(PC) ← (A)
(PC) ← ext
Vector call
Subroutine call
(PC) ← (A),(A) ← (PC) + 1
Return from subrountine
Return form interrupt
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
dH
–
–
––––
––––
––––
––––
––––
––––
––––
––––
–+––
–+––
––––
––––
––––
––––
––––
––––
Restore
FD
FC
F9
F8
FB
FA
FF
FE
B0 to B7
B8 to BF
E0
21
E8 to EF
31
F4
20
30
Table 5
Mnemonic
TL
~
#
4
4
4
4
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Other Instructions (9 instructions)
Operation
TL
TH
AH
NZVC
OP code
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
dH
–
–
–
–
–
–
–
––––
––––
––––
––––
––––
–––R
–––S
––––
––––
40
50
41
51
00
81
91
80
90
L
D
E
F
CMP
ADDC
ADDC
A
SUBC
SUBC
A
MOV
A
XOR
AND
OR
CLRB
BBC
INCW
DECW MOVW MOVW
dir: 1 dir: 1,rel
SP
SP
SP,A
A,SP
MOV
CMP
DAS
MOV
CMP
ADDC SUBC MOV
XOR
AND
OR
MOV
CMP
SETB
BBS
INC
DEC
CALLV BNC
A,R0
A,R0
A,R0
A,R0
R0,A
A,R0
A,R0
A,R0 R0,#d8 R0,#d8
dir: 0 dir: 0,rel
R0
R0
#0
rel
MOV
CMP
ADDC SUBC MOV
XOR
AND
OR
MOV
CMP
SETB
BBS
INC
DEC
CALLV BC
A,R1
A,R1
A,R1
A,R1
R1,A
A,R1
A,R1
A,R1 R1,#d8 R1,#d8
dir: 1 dir: 1,rel
R1
R1
#1
MOV
CMP
ADDC SUBC MOV
XOR
AND
OR
MOV
CMP
SETB
BBS
INC
DEC
CALLV BP
A,R2
A,R2
A,R2
A,R2
R2,A
A,R2
A,R2
A,R2 R2,#d8 R2,#d8
dir: 2 dir: 2,rel
R2
R2
#2
MOV
CMP
ADDC SUBC MOV
XOR
AND
OR
MOV
CMP
SETB
BBS
INC
DEC
CALLV BN
A,R3
A,R3
A,R3
A,R3
R3,A
A,R3
A,R3
A,R3 R3,#d8 R3,#d8
dir: 3 dir: 3,rel
R3
R3
#3
MOV
CMP
ADDC SUBC MOV
XOR
AND
OR
MOV
CMP
SETB
BBS
INC
DEC
CALLV BNZ
A,R4
A,R4
A,R4
A,R4
R4,A
A,R4
A,R4
A,R4 R4,#d8 R4,#d8
dir: 4 dir: 4,rel
R4
R4
#4
rel
MOV
CMP
ADDC SUBC MOV
XOR
AND
OR
MOV
CMP
SETB
BBS
INC
DEC
CALLV BZ
A,R5
A,R5
A,R5
A,R5
R5,A
A,R5
A,R5
A,R5 R5,#d8 R5,#d8
dir: 5 dir: 5,rel
R5
R5
#5
MOV
CMP
ADDC SUBC MOV
XOR
AND
OR
MOV
CMP
SETB
BBS
INC
DEC
CALLV BGE
A,R6
A,R6
A,R6
A,R6
R6,A
A,R6
A,R6
A,R6 R6,#d8 R6,#d8
dir: 6 dir: 6,rel
R6
R6
#6
rel
MOV
CMP
ADDC SUBC MOV
XOR
AND
OR
MOV
CMP
SETB
BBS
INC
DEC
CALLV BLT
A,R7
A,R7
A,R7
A,R7
R7,A
A,R7
A,R7
A,R7 R7,#d8 R7,#d8
dir: 7 dir: 7,rel
R7
R7
#7
rel
8
9
A
B
C
D
E
F
rel
rel
rel
rel
MOV
CMP
ADDC SUBC MOV
XOR
AND
OR
MOV
CMP
CLRB
BBC
MOVW MOVW MOVW XCHW
A,@EP A,@EP A,@EP A,@EP @EP,A A,@EP A,@EP A,@EP @EP,#d8 @EP,#d8
dir: 7 dir: 7,rel A,@EP @EP,A EP,#d16
A,EP
CLRB
BBC
MOVW MOVW MOVW XCHW
dir: 6 dir: 6,rel A,@IX +d @IX +d,A IX,#d16
A,IX
CLRB
BBC
MOVW MOVW MOVW XCHW
dir: 4 dir: 4,rel
A,ext
ext,A A,#d16
A,PC
MOV
MOV
CLRB
BBC
INCW
DECW MOVW MOVW
@A,T
A,@A
dir: 2 dir: 2,rel
IX
IX
IX,A
A,IX
XOR
AND
OR
DAA
A,#d8
A,#d8
A,#d8
XCH
XOR
AND
OR
A, T
A
A
A,@IX +d A,@IX +d A,@IX +d A,@IX +d @IX +d,A A@,IX +d A,@IX +d A,@IX +d @IX +d,#d8 @IX +d,#d8
MOV
A
SETC
7
6
CMP
JMP
CALL
PUSHW POPW MOV
MOVW CLRC
addr16 addr16
IX
IX
ext,A
PS,A
MOV
CMP
ADDC SUBC MOV
XOR
AND
OR
MOV
CMP
CLRB
BBC
MOVW MOVW MOVW XCHW
A,dir
A,dir
A,dir
A,dir
dir,A
A,dir
A,dir
A,dir dir,#d8 dir,#d8
dir: 5 dir: 5,rel
A,dir
dir,A SP,#d16
A,SP
C
5
B
CLRB
BBC
INCW
DECW JMP
MOVW
dir: 0 dir: 0,rel
A
A
@A
A,PC
A
MOV
CMP
ADDC SUBC
A,#d8
A,#d8
A,#d8
A,#d8
A
DIVU
SETI
9
4
8
RORC CMPW ADDCW SUBCW XCHW XORW ANDW ORW
MOVW MOVW CLRB
BBC
INCW
DECW MOVW MOVW
A
A
A
A
A, T
A
A
A
@A,T
A,@A
dir: 3 dir: 3,rel
EP
EP
EP,A
A,EP
7
3
6
ROLC
A
5
PUSHW POPW MOV
MOVW CLRI
A
A
A,ext
A,PS
4
2
A
RETI
3
MULU
RET
2
1
SWAP
1
NOP
0
0
H
MB89990 Series
■ INSTRUCTION MAP
37
MB89990 Series
■ MASK OPTION LIST
No.
Part number
MB89997
Specifying procedure
Specify when
ordering masking
–101*2
Specify when
ordering masking
–201*2
Fixed
Selectable by pin
None
Selectable by pin
None
Not
available
Selectable
Enabled
Enabled
Enabled
Enabled
Selectable
Fixed to
216/FC
Selectable
Fixed to
216/FC
Fixed to
216/FC
P00 to P07
P30 to P37
P40 to P45
1
Port pull-up
resistors
2
Power-on reset selection
Power-on reset provided
No power-on reset
3
Selection of oscillation
stabilization wait time
(at 4.2 MHz)*1
218/FC (Approx. 62.4 ms)
216/FC (Approx. 15.6 ms)
212/FC (Approx. 0.98 ms)
22/FC (Approx. 0 ms)
MB89P195
MB89PV190
4
Reset pin output
Reset output provided
No reset output
Selectable
Enabled
Selectable
Enabled
Output
enabled
5
Oscillation type of clock
1 Crystal and ceramic
oscillators
2 CR
Selectable
“1” only
Selectable
“1” only
“1” only
*1: The oscillation stabilization delay time is generated by dividing the original clock oscillation. The time described
in this item should be used as a guideline since the oscillation cycle is unstable immediately after oscillation
starts. “FC” indicates the original oscillation frequency.
*2: –101 is provided respectively for the MB89P195 OTP versions as the standard product.
38
MB89990 Series
■ ORDERING INFORMATION
Part number
MB89997PF
MB89P195PF-101
Package
Remarks
28-pin Plastic SOP
(FPT-28P-M17)
MB89997P-SH
28-pin Plastic SH-DIP
(DIP-28C-M03)
MB89PV190CF
48-pin Ceramic MQFP
(MQP-48C-P01)
39
MB89990 Series
■ PACKAGE DIMENSIONS
28-pin Plastic SOP
(FPT-28P-M17)
+0.25
17.75 –0.20
+.010
.699 –.008
28
15
Details of "B" part
Details of "A" part
0.15(.006)
0.35(.014)
11.80±0.30
(.465±.012)
8.60±0.20
(.339±.008)
INDEX
0.20(.008)
0.20(.008)
"A"
0.18(.007)
MAX
0.68(.027)
MAX
1
0.18(.007)
MAX
0.68(.027)
MAX
14
1.27(.050)
TYP
0.45±0.10
(.018±.004)
0.13(.005)
M
2.80(.110)MAX
(Mounting height)
0.15±0.05
(.006±.002)
"B"
0.10(.004)
16.51(.650)
REF
C
0.80±0.20
(.031±.008)
10.20±0.30
(.402±.012)
1994 FUJITSU LIMITED F28048S-1C-1
28-pin Plastic SH-DIP
(DIP-28P-M03)
0(0)MIN
(STAND OFF)
Dimensions in mm (inches)
+0.20
26.00 –0.30
+.008
1.024 –.012
INDEX-1
9.10±0.25
(.358±.010)
INDEX-2
4.85(.191)MAX
0.51(.020)MIN
0.25±0.05
(.010±.002)
3.00(.118)MIN
0.45±0.10
(.018±.004)
+0.50
1.00 –0
+.020
.039 –0
1.778±0.18
(.070±.007)
1.778(.070)
MAX
C
40
1994 FUJITSU LIMITED D28012S-3C-3
10.16(.400)
TYP
15°MAX
23.114(.910)REF
Dimensions in mm (inches)
MB89990 Series
48-pin Ceramic MQFP
(MQP-48C-P01)
17.20(.677)TYP
PIN No.1 INDEX
15.00±0.25
(.591±.010)
14.82±0.35
(.583±.014)
1.50(.059)TYP
8.80(.346)REF
1.00(.040)TYP
0.80±0.22
(.0315±.0087)
PIN No.1 INDEX
1.02±0.13
(.040±.005)
+0.13
10.92 –0.0
+.005
.430 –0
7.14(.281) 8.71(.343)
TYP
TYP
PAD No.1 INDEX
0.30(.012)TYP
+0.45
4.50(.177)TYP
1.10 –0.25
+.018
.043 –.010
0.40±0.08
(.016±.003)
0.60(.024)TYP
8.50(.335)MAX
0.15±0.05
(.006±.002)
C
1994 FUJITSU LIMITED M48001SC-4-2
Dimensions in mm (inches)
41
MB89990 Series
FUJITSU LIMITED
All Rights Reserved.
The contents of this document are subject to change without notice.
Customers are advised to consult with FUJITSU sales
representatives before ordering.
The information and circuit diagrams in this document are
presented as examples of semiconductor device applications, and
are not intended to be incorporated in devices for actual use. Also,
FUJITSU is unable to assume responsibility for infringement of
any patent rights or other rights of third parties arising from the use
of this information or circuit diagrams.
The products described in this document are designed, developed
and manufactured as contemplated for general use, including
without limitation, ordinary industrial use, general office use,
personal use, and household use, but are not designed, developed
and manufactured as contemplated (1) for use accompanying fatal
risks or dangers that, unless extremely high safety is secured, could
have a serious effect to the public, and could lead directly to death,
personal injury, severe physical damage or other loss (i.e., nuclear
reaction control in nuclear facility, aircraft flight control, air traffic
control, mass transport control, medical life support system, missile
launch control in weapon system), or (2) for use requiring
extremely high reliability (i.e., submersible repeater and artificial
satellite).
Please note that Fujitsu will not be liable against you and/or any
third party for any claims or damages arising in connection with
above-mentioned uses of the products.
Any semiconductor devices have an inherent chance of failure. You
must protect against injury, damage or loss from such failures by
incorporating safety design measures into your facility and
equipment such as redundancy, fire protection, and prevention of
over-current levels and other abnormal operating conditions.
If any products described in this document represent goods or
technologies subject to certain restrictions on export under the
Foreign Exchange and Foreign Trade Law of Japan, the prior
authorization by Japanese government will be required for export
of those products from Japan.
F9710
 FUJITSU LIMITED Printed in Japan