Single-Channel, 128-/64-/32-Position, Up/Down, ±8% Resistor Tolerance, Nonvolatile Digital Potentiometer Data Sheet AD5111/AD5113/AD5115 FEATURES FUNCTIONAL BLOCK DIAGRAM VDD AD5111/ AD5113/ AD5115 POWER-ON RESET A W CLK DATA EN CS EEPROM UP/DOWN CONTROL LOGIC B RDAC REGISTER DATA U/D 09654-001 Single-channel, 128-/64-/32-position resolution 5 kΩ, 10 kΩ, 80 kΩ nominal resistance Maximum ±8% nominal resistor tolerance error Low wiper resistance ±6 mA maximum wiper current density Rheostat mode temperature coefficient: 35 ppm/°C Potentiometer mode temperature coefficient: 5 ppm/°C 2.3 V to 5.5 V single-supply operation Power-on EEPROM refresh time < 50 μs Simple up/down manual or digital configurable control Chip select enable multiple device operation 50-year typical data retention at 125°C 1 million write cycles Wide operating temperature: −40°C to +125°C Thin, 2 mm × 2 mm × 0.55 mm 8-lead LFCSP package GND Figure 1. APPLICATIONS Mechanical potentiometer replacement Portable electronics level adjustment Audio volume control Low resolution DAC LCD panel brightness and contrast control Programmable voltage to current conversion Programmable filters, delays, time constants Feedback resistor programmable power supply Sensor calibration GENERAL DESCRIPTION The AD5111/AD5113/AD5115 provide a nonvolatile solution for 128-/64-/32-position adjustment applications, offering guaranteed low resistor tolerance errors of ±8% and up to ±6 mA current density in the A, B, and W pins. The low resistor tolerance, low nominal temperature coefficient, and high bandwidth simplify open-loop applications, as well as tolerance matching applications. The new low wiper resistance feature minimizes the wiper resistance in the extremes of the resistor array to only 45 Ω, typical. A simple 3-wire up/down interface allows manual switching or high speed digital control with clock rates up to 50 MHz. The AD5111/AD5113/AD5115 are available in a 2 mm × 2 mm LFCSP package. The parts are guaranteed to operate over the extended industrial temperature range of −40°C to +125°C. Table 1. ±8% Resistance Tolerance Family Model AD5110 AD5111 AD5112 AD5113 AD5116 AD5114 AD5115 Resistance (kΩ) 10, 80 10, 80 5, 10, 80 5, 10, 80 5, 10, 80 10, 80 10, 80 Position 128 128 64 64 64 32 32 Interface I2C Up/down I2C Up/down Push-button I2C Up/down Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2011 Analog Devices, Inc. All rights reserved. AD5111/AD5113/AD5115 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Test Circuits..................................................................................... 17 Applications ....................................................................................... 1 Theory of Operation ...................................................................... 18 Functional Block Diagram .............................................................. 1 RDAC Register and EEPROM .................................................. 18 General Description ......................................................................... 1 Basic Operation .......................................................................... 18 Revision History ............................................................................... 2 Low Wiper Resistance Feature ................................................. 18 Specifications..................................................................................... 3 Shutdown Mode ......................................................................... 18 Electrical Characteristics—AD5111 .......................................... 3 EEPROM Write Operation ....................................................... 18 Electrical Characteristics—AD5113 .......................................... 5 RDAC Architecture .................................................................... 19 Electrical Characteristics—AD5115 .......................................... 7 Programming the Variable Resistor ......................................... 19 Interface Timing Specifications .................................................. 9 Programming the Potentiometer Divider ............................... 20 Timing Diagram ........................................................................... 9 Terminal Voltage Operating Range ......................................... 20 Absolute Maximum Ratings .......................................................... 10 Power-Up Sequence ................................................................... 21 Thermal Resistance .................................................................... 10 Layout and Power Supply Biasing ............................................ 21 ESD Caution ................................................................................ 10 Outline Dimensions ....................................................................... 22 Pin Configuration and Function Descriptions ........................... 11 Ordering Guide .......................................................................... 22 Typical Performance Characteristics ........................................... 12 REVISION HISTORY 10/11—Revision 0: Initial Version Rev. 0 | Page 2 of 24 Data Sheet AD5111/AD5113/AD5115 SPECIFICATIONS ELECTRICAL CHARACTERISTICS—AD5111 10 kΩ and 80 kΩ versions: VDD = 2.3 V to 5.5 V, VA = VDD, VB = 0 V, −40°C < TA < +125°C, unless otherwise noted. Table 2. Parameter DC CHARACTERISTICS—RHEOSTAT MODE Resolution Resistor Integral Nonlinearity2 Resistor Differential Nonlinearity2 Nominal Resistor Tolerance Resistance Temperature Coefficient3 Wiper Resistance DC CHARACTERISTICS—POTENTIOMETER DIVIDER MODE Integral Nonlinearity4 Differential Nonlinearity4 Full-Scale Error Zero-Scale Error Voltage Divider Temperature Coefficient3 RESISTOR TERMINALS Maximum Continuous IA, IB, and IW Current3 Symbol N R-INL R-DNL ΔRAB/RAB (ΔRAB/RAB)/ΔT × 106 RW RBS RTS INL DNL VWFSE VWZSE (ΔVW/VW)/ΔT × 106 RAB = 10 kΩ, VDD = 2.3 V to 2.7 V RAB = 10 kΩ, VDD = 2.7 V to 5.5 V RAB = 80 kΩ CA, CB Capacitance W3, 6 CW Min Typ1 Max 7 −2.5 −1 −0.5 −1 −8 ±0.5 ±0.25 ±0.1 ±0.25 +2.5 +1 +0.5 +1 +8 Code = zero scale Code = bottom scale Code = top scale RAB = 10 kΩ RAB = 80 kΩ RAB = 10 kΩ RAB = 80 kΩ Code = half scale RAB = 10 kΩ RAB = 80 kΩ Terminal Voltage Range5 Capacitance A, Capacitance B3, 6 Common-Mode Leakage Current3 DIGITAL INPUTS Input Logic3 High Low Input Current3 Input Capacitance3 POWER SUPPLIES Single-Supply Power Range Positive Supply Current EEMEM Store Current3, 7 EEMEM Read Current3, 8 Power Dissipation9 Power Supply Rejection3 Test Conditions/Comments f = 1 MHz, measured to GND, code = half scale f = 1 MHz, measured to GND, code = half scale VA = VW = VB VINH VINL IN CIN −0.5 −0.5 −2.5 −1.5 35 70 45 70 140 80 140 ±0.15 ±0.15 +0.5 +0.5 1.5 0.5 ±10 −6 −1.5 GND −500 +6 +1.5 VDD 35 pF ±15 +500 nA 0.8 ±1 V V μA pF 5 VIH = VDD or VIL = GND ∆VDD/∆VSS = 5 V ± 10% RAB = 10 kΩ RAB = 80 kΩ Rev. 0 | Page 3 of 24 LSB LSB LSB LSB LSB LSB ppm/°C 20 2 VIH = VDD or VIL = GND, VDD = 5 V Bits LSB LSB LSB LSB % ppm/°C Ω Ω Ω mA mA V pF 2.3 IDD IDD_NVM_STORE IDD_NVM_READ PDISS PSR Unit 750 2 320 5 5.5 V nA mA μA μW −50 −64 dB dB AD5111/AD5113/AD5115 Parameter DYNAMIC CHARACTERISTICS3, 10 Bandwidth Total Harmonic Distortion VW Settling Time Resistor Noise Density FLASH/EE MEMORY RELIABILITY3 Endurance11 Data Sheet Symbol Test Conditions/Comments BW Code = half scale, −3 dB RAB = 10 kΩ RAB = 80 kΩ VA = VDD/2 + 1 V rms, VB = VDD/ 2, f = 1 kHz, code = half scale RAB = 10 kΩ RAB = 80 kΩ VA = 5 V, VB = 0 V, ±0.5 LSB error band RAB = 10 kΩ RAB = 80 kΩ Code = half scale, TA = 25°C, f = 100 kHz RAB = 10 kΩ RAB = 80 kΩ THD ts eN_WB Min TA = 25°C Typ1 MHz kHz −80 −85 dB dB 3 12 μs μs 9 20 nV/√Hz nV/√Hz 1 MCycles kCycles Years 50 1 Unit 2 200 100 Data Retention12 Max Typical values represent average readings at 25°C, VDD = 5 V, VSS = 0 V, and VLOGIC = 5 V. R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. R-DNL measures the relative step change from ideal between successive tap positions. The maximum wiper current is limited to 0.8 × VDD/RAB. 3 Guaranteed by design and characterization; not subject to production test. 4 INL and DNL are measured at VWB with the RDAC configured as a potentiometer divider similar to a voltage output DAC. VA = VDD and VB = 0 V. DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions. 5 Resistor Terminal A, Resistor Terminal B, and Resistor Terminal W have no limitations on current direction with respect to each other. 6 CA is measured with VW = VA = 2.5 V, CB is measured with VW = VB = 2.5 V, and CW is measured with VA = VB = 2.5 V. 7 Different from operating current; supply current for NVM program lasts approximately 30 ms. 8 Different from operating current; supply current for NVM read lasts approximately 20 μs. 9 PDISS is calculated from (IDD × VDD). 10 All dynamic characteristics use VDD = 5.5 V and VLOGIC = 5 V. 11 Endurance is qualified at 100,000 cycles per JEDEC Standard 22, Method A117 and measured at 150°C. 12 Retention lifetime equivalent at junction temperature (TJ) is 125°C per JEDEC Standard 22, Method A117. Retention lifetime based on an activation energy of 1 eV derates with junction temperature in the Flash/EE memory. 2 Rev. 0 | Page 4 of 24 Data Sheet AD5111/AD5113/AD5115 ELECTRICAL CHARACTERISTICS—AD5113 5 kΩ, 10 kΩ, and 80 kΩ versions: VDD = 2.3 V to 5.5 V, VA = VDD, VB = 0 V, −40°C < TA < +125°C, unless otherwise noted. Table 3. Parameter DC CHARACTERISTICS—RHEOSTAT MODE Resolution Resistor Integral Nonlinearity2 Resistor Differential Nonlinearity2 Nominal Resistor Tolerance Resistance Temperature Coefficient3 Wiper Resistance DC CHARACTERISTICS—POTENTIOMETER DIVIDER MODE Integral Nonlinearity4 Differential Nonlinearity4 Full-Scale Error Zero-Scale Error Voltage Divider Temperature Coefficient3 RESISTOR TERMINALS Maximum Continuous IA, IB, and IW Current3 Symbol N R-INL R-DNL ΔRAB/RAB (ΔRAB/RAB)/ΔT × 106 RW RBS RTS INL DNL VWFSE VWZSE (ΔVW/VW)/ΔT × 106 RAB = 5 kΩ, VDD = 2.3 V to 2.7 V RAB = 5 kΩ, VDD = 2.7 V to 5.5 V RAB = 10 kΩ RAB = 80 kΩ CA, CB Capacitance W3, 6 CW Min Typ1 Max 6 −2.5 −1 −1 −0.25 −1 −8 ±0.5 ±0.25 ±0.25 ±0.1 ±0.25 +2.5 +1 +1 +0.25 +1 +8 Code = zero scale Code = bottom scale Code = top scale RAB = 5 kΩ RAB =10 kΩ RAB = 80 kΩ RAB = 5 kΩ RAB =10 kΩ RAB = 80 kΩ Code = half scale RAB = 5 kΩ, 10 kΩ RAB = 80 kΩ Terminal Voltage Range5 Capacitance A, Capacitance B3, 6 Common-Mode Leakage Current3 DIGITAL INPUTS Input Logic3 High Low Input Current3 Input Capacitance3 POWER SUPPLIES Single-Supply Power Range Positive Supply Current EEMEM Store Current3, 7 EEMEM Read Current3, 8 Power Dissipation9 Power Supply Rejection3 Test Conditions/Comments f = 1 MHz, measured to GND, code = half scale f = 1 MHz, measured to GND, code = half scale VA = VW = VB VINH VINL IN CIN −0.5 −0.5 −2.5 −1.5 −1 35 70 45 70 140 80 140 ±0.15 ±0.15 +0.5 +0.5 1.5 1 0.25 ±10 −6 −1.5 GND −500 +6 +1.5 VDD 35 pF ±15 +500 nA 0.8 ±1 V V μA pF 5 VIH = VDD or VIL = GND ∆VDD/∆VSS = 5 V ± 10% RAB = 5 kΩ RAB =10 kΩ RAB = 80 kΩ Rev. 0 | Page 5 of 24 LSB LSB LSB LSB LSB LSB LSB LSB ppm/°C 20 2 VIH = VDD or VIL = GND, VDD = 5 V Bits LSB LSB LSB LSB LSB % ppm/°C Ω Ω Ω mA mA V pF 2.3 IDD IDD_NVM_STORE IDD_NVM_READ PDISS PSR Unit 750 2 320 5 5.5 V nA mA μA μW −43 −50 −64 dB dB dB AD5111/AD5113/AD5115 Parameter DYNAMIC CHARACTERISTICS3, 10 Bandwidth Total Harmonic Distortion VW Settling Time Resistor Noise Density FLASH/EE MEMORY RELIABILITY3 Endurance11 Data Sheet Symbol Test Conditions/Comments BW Code = half scale, −3 dB RAB = 5 kΩ RAB = 10 kΩ RAB = 80 kΩ VA = VDD/2 + 1 V rms, VB = VDD/2, f = 1 kHz, code = half scale RAB = 5 kΩ RAB = 10 kΩ RAB = 80 kΩ VA = 5 V, VB = 0 V, ±0.5 LSB error band RAB = 5 kΩ RAB = 10 kΩ RAB = 80 kΩ Code = half scale, TA = 25°C, f = 100 kHz RAB = 5 kΩ RAB = 10 kΩ RAB = 80 kΩ THD ts eN_WB Min TA = 25°C Typ1 MHz MHz kHz −75 −80 −85 dB dB dB 2.5 3 10 μs μs μs 7 9 20 nV/√Hz nV/√Hz nV/√Hz 1 MCycles kCycles Years 50 1 Unit 4 2 200 100 Data Retention12 Max Typical values represent average readings at 25°C, VDD = 5 V, VSS = 0 V, and VLOGIC = 5 V. R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. R-DNL measures the relative step change from ideal between successive tap positions. The maximum wiper current is limited to 0.8 × VDD/RAB. 3 Guaranteed by design and characterization; not subject to production test. 4 INL and DNL are measured at VWB with the RDAC configured as a potentiometer divider similar to a voltage output DAC. VA = VDD and VB = 0 V. DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions. 5 Resistor Terminal A, Resistor Terminal B, and Resistor Terminal W have no limitations on current direction with respect to each other. 6 CA is measured with VW = VA = 2.5 V, CB is measured with VW = VB = 2.5 V, and CW is measured with VA = VB = 2.5 V. 7 Different from operating current; supply current for NVM program lasts approximately 30 ms. 8 Different from operating current; supply current for NVM read lasts approximately 20 μs. 9 PDISS is calculated from (IDD × VDD). 10 All dynamic characteristics use VDD = 5.5 V and VLOGIC = 5 V. 11 Endurance is qualified at 100,000 cycles per JEDEC Standard 22, Method A117 and measured at 150°C. 12 Retention lifetime equivalent at junction temperature (TJ) is 125°C per JEDEC Standard 22, Method A117. Retention lifetime based on an activation energy of 1 eV derates with junction temperature in the Flash/EE memory. 2 Rev. 0 | Page 6 of 24 Data Sheet AD5111/AD5113/AD5115 ELECTRICAL CHARACTERISTICS—AD5115 10 kΩ and 80 kΩ versions: VDD = 2.3 V to 5.5 V, VA = VDD, VB = 0 V, −40°C < TA < +125°C, unless otherwise noted. Table 4. Parameter DC CHARACTERISTICS—RHEOSTAT MODE Resolution Resistor Integral Nonlinearity2 Resistor Differential Nonlinearity2 Nominal Resistor Tolerance Resistance Temperature Coefficient3 Wiper Resistance DC CHARACTERISTICS—POTENTIOMETER DIVIDER MODE Integral Nonlinearity4 Differential Nonlinearity4 Full-Scale Error Zero-Scale Error Voltage Divider Temperature Coefficient3 RESISTOR TERMINALS Maximum Continuous IA, IB, and IW Current3 Symbol N R-INL R-DNL ΔRAB/RAB (ΔRAB/RAB)/ΔT × 106 RW RBS RTS INL DNL VWFSE VWZSE (ΔVW/VW)/ΔT × 106 CA, CB Capacitance W3, 6 CW Min Typ1 5 −0.5 −0.25 −8 RAB = 10 kΩ RAB = 80 kΩ RAB = 10 kΩ RAB = 80 kΩ Code = half scale f = 1 MHz, measured to GND, code = half scale f = 1 MHz, measured to GND, code = half scale VA = VW = VB VINH VINL IN CIN −0.25 −0.25 −1 −0.5 140 80 140 +0.25 +0.25 1 0.25 ±10 −6 −1.5 GND −500 +6 +1.5 VDD Rev. 0 | Page 7 of 24 LSB LSB LSB LSB LSB LSB ppm/°C 35 pF ±15 +500 nA 0.8 ±1 V V μA pF 5 VIH = VDD or VIL = GND ∆VDD/∆VSS = 5 V ± 10% RAB = 10 kΩ RAB = 80 kΩ Bits LSB LSB % ppm/°C Ω Ω Ω 20 2 VIH = VDD or VIL = GND, VDD = 5 V Unit mA mA V pF 2.3 IDD IDD_NVM_STORE IDD_NVM_READ PDISS PSR Max +0.5 +0.25 +8 35 70 45 70 Code = zero scale Code = bottom scale Code = top scale RAB = 10 kΩ RAB = 80 kΩ Terminal Voltage Range5 Capacitance A, Capacitance B3, 6 Common-Mode Leakage Current3 DIGITAL INPUTS Input Logic3 High Low Input Current3 Input Capacitance3 POWER SUPPLIES Single-Supply Power Range Positive Supply Current EEMEM Store Current3, 7 EEMEM Read Current3, 8 Power Dissipation9 Power Supply Rejection3 Test Conditions/Comments 750 2 320 5 5.5 V nA mA μA μW −50 −64 dB dB AD5111/AD5113/AD5115 Parameter DYNAMIC CHARACTERISTICS3, 10 Bandwidth Total Harmonic Distortion VW Settling Time Resistor Noise Density FLASH/EE MEMORY RELIABILITY3 Endurance11 Data Sheet Symbol Test Conditions/Comments BW Code = half scale, −3 dB RAB = 10 kΩ RAB = 80 kΩ VA = VDD/2 + 1 V rms, VB = VDD/2, f = 1 kHz, code = half scale RAB = 10 kΩ RAB = 80 kΩ VA = 5 V, VB = 0 V, ±0.5 LSB error band RAB = 10 kΩ RAB = 80 kΩ Code = half scale, TA = 25°C, f = 100 kHz RAB = 10 kΩ RAB = 80 kΩ THD ts eN_WB Min TA = 25°C Typ1 MHz kHz −80 −85 dB dB 2.7 9.5 μs μs 9 20 nV/√Hz V 1 MCycles kCycles Years 50 1 Unit 2 200 100 Data Retention12 Max Typical values represent average readings at 25°C, VDD = 5 V, VSS = 0 V, and VLOGIC = 5 V. R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. R-DNL measures the relative step change from ideal between successive tap positions. The maximum wiper current is limited to 0.8 × VDD/RAB. 3 Guaranteed by design and characterization; not subject to production test. 4 INL and DNL are measured at VWB with the RDAC configured as a potentiometer divider similar to a voltage output DAC. VA = VDD and VB = 0 V. DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions. 5 Resistor Terminal A, Resistor Terminal B, and Resistor Terminal W have no limitations on current direction with respect to each other. 6 CA is measured with VW = VA = 2.5 V, CB is measured with VW = VB = 2.5 V, and CW is measured with VA = VB = 2.5 V. 7 Different from operating current; supply current for NVM program lasts approximately 30 ms. 8 Different from operating current; supply current for NVM read lasts approximately 20 μs. 9 PDISS is calculated from (IDD × VDD). 10 All dynamic characteristics use VDD = 5.5 V and VLOGIC = 5 V. 11 Endurance is qualified at 100,000 cycles per JEDEC Standard 22, Method A117 and measured at 150°C. 12 Retention lifetime equivalent at junction temperature (TJ) is 125°C per JEDEC Standard 22, Method A117. Retention lifetime based on an activation energy of 1 eV derates with junction temperature in the Flash/EE memory. 2 Rev. 0 | Page 8 of 24 Data Sheet AD5111/AD5113/AD5115 INTERFACE TIMING SPECIFICATIONS VDD = 2.3 V to 5.5 V; all specifications TMIN to TMAX, unless otherwise noted. Table 5. Parameter fCLK Test Conditions/Comments VDD ≥ 2.7 V VDD < 2.7 V t1 t2 t4 t5 t6 VDD ≥ 2.7 V VDD < 2.7 V t7 t8 VDD ≥ 2.7 V VDD < 2.7 V t9 t10 tEEPROM_PROGRAM 1 tPOWER_UP 1 2 Typ Max 50 25 Description Clock frequency 50 Unit MHz MHz ns ns ns ns ns ns ns ns ns ns ns ns ns µs ms 50 µs Power-on EEPROM restore time 25 10 20 10 20 15 6 20 40 15 12 24 12 1 VDD ≥ 2.7 V VDD < 2.7 V VDD ≥ 2.7 V VDD < 2.7 V t3 Min 15 2 CS setup time CLK low time CLK high time U/D setup time U/D hold time CS rise to CLK hold time CS rising edge to next CLK ignored U/D minimum pulse time U/D rise to CLK falling edge Minimum CS time Memory program time EEPROM program time depends on the temperature and EEPROM write cycles. Higher timing is expected at a lower temperature and higher write cycles. Maximum time after VDD is equal to 2.3 V. TIMING DIAGRAMS t3 t2 t1 t10 t6 t1 CS t9 t6 CS t7 CLK CLK t5 09654-004 t4 09654-002 U/D RWB Figure 4. Shutdown Mode Timing Figure 2. Increment/Decrement Mode Timing t1 t8 t6 CS CLK tEEPROM_PROGRAM DATA NEW DATA 09654-003 U/D EEPROM U/D Figure 3. Storage Mode Timing Rev. 0 | Page 9 of 24 AD5111/AD5113/AD5115 Data Sheet ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 6. Parameter VDD to GND VLOGIC to GND VA, VW, VB to GND IA, IW, IB Pulsed1 Frequency > 10 kHz RAW = 5 kΩ and 10 kΩ RAW = 80 kΩ Frequency ≤ 10 kHz RAW = 5 kΩ and 10 kΩ RAW = 80 kΩ Continuous RAW = 5 kΩ and 10 kΩ RAW = 80 kΩ Digital Inputs U/D, CLK, and CS 3 Operating Temperature Range Maximum Junction Temperature (TJ Max) Storage Temperature Range Reflow Soldering Peak Temperature Time at Peak Temperature Package Power Dissipation Rating –0.3 V to +7.0 V –0.3 V to +7.0 V GND − 0.3 V to VDD + 0.3 V Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. THERMAL RESISTANCE θJA is defined by JEDEC specification JESD-51, and the value is dependent on the test board and test environment. ±6 mA/d2 ±1.5 mA/d2 Table 7. Thermal Resistance ±6 mA/√d2 ±1.5 mA/√d2 Package Type 8-Lead LFCSP ±6 mA ±1.5 mA −0.3 V to +7 V or VDD + 0.3 V (whichever is less) −40°C to +125°C 150°C −65°C to +150°C 1 θJA 901 JEDEC 2S2P test board, still air (0 m/sec air flow). ESD CAUTION 260°C 20 sec to 40 sec (TJ max − TA)/θJA 1 Maximum terminal current is bounded by the maximum current handling of the switches, maximum power dissipation of the package, and maximum applied voltage across any two of the A, B, and W terminals at a given resistance. 2 Pulse duty factor. 3 Includes programming of EEPROM memory. Rev. 0 | Page 10 of 24 θJC 25 Unit °C/W Data Sheet AD5111/AD5113/AD5115 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS A 2 W 3 B 4 AD5111/ AD5113/ AD5115 TOP VIEW (Not to Scale) 8 CS 7 U/D 6 CLK 5 GND NOTES 1. THE EXPOSED PAD IS INTERNALLY FLOATING. 09654-006 VDD 1 Figure 5. Pin Configuration Table 8. Pin Function Descriptions Pin No. 1 2 3 4 5 6 Mnemonic VDD A W B GND CLK 7 8 U/D CS EPAD Description Positive Power Supply. Decouple this pin with 0.1 µF ceramic capacitors and 10 µF capacitors. Terminal A of RDAC. GND ≤ VA ≤ VDD. Wiper Terminal of RDAC. GND ≤ VW ≤ VDD. Terminal B of RDAC. GND ≤ VB ≤ VDD. Ground Pin, Logic Ground Reference. Clock Input. Each clock pulse executes the step-up or step-down of the resistance. The direction is determined by the state of the U/D pin. CLK is a negative edge trigger. Data can be transferred at rates up to 50 MHz. Up/Down Selection Counter Control. Chip Select. Active Low. Exposed Pad. The exposed pad is internally floating. Rev. 0 | Page 11 of 24 AD5111/AD5113/AD5115 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS 0.10 10kΩ, 10kΩ, 10kΩ, 80kΩ, 80kΩ, 80kΩ, 0.08 10kΩ, –40°C 10kΩ, +25°C 10kΩ, +125°C 80kΩ, –40°C 80kΩ, +25°C 80kΩ, +125°C 0.01 0 –0.01 0.04 R-DNL (LSB) R-INL (LSB) 0.06 0.02 –40°C +25°C +125°C –40°C +25°C +125°C 0.02 0 –0.02 –0.03 –0.04 –0.02 119 127 112 98 105 91 84 77 70 63 56 49 42 35 28 21 14 0 CODE (Decimal) Figure 6. R-INL vs. Code (AD5111) 09654-010 CODE (Decimal) 09654-007 119 127 112 98 105 91 84 77 70 56 63 49 42 35 28 21 14 –0.07 0 –0.06 7 –0.06 7 –0.05 –0.04 Figure 9. R-DNL vs. Code (AD5111) 0.08 0.02 5kΩ, –40°C 5kΩ, +25°C 5kΩ, +125°C 10kΩ, –40°C 80kΩ, –40°C 10kΩ, +25°C 80kΩ, +25°C 10kΩ, +125°C 80kΩ, +125°C 0.01 0.06 0 0.04 R-DNL (LSB) 0 5kΩ, –40°C 5kΩ, +25°C 5kΩ, +125°C 10kΩ, –40°C 10kΩ, +25°C 10kΩ, +125°C 80kΩ, –40°C 80kΩ, +25°C 80kΩ, +125°C –0.04 –0.06 –0.02 –0.03 –0.04 –0.05 –0.06 0 3 6 9 12 15 18 21 24 27 30 33 36 39 42 45 48 51 54 57 60 63 CODE (Decimal) –0.07 0 3 6 9 12 15 18 21 24 27 30 33 36 39 42 45 48 51 54 57 60 63 CODE (Decimal) Figure 7. R-INL vs. Code (AD5113) Figure 10. R-DNL vs. Code (AD5113) 0.004 0.020 10kΩ, 10kΩ, 10kΩ, 80kΩ, 80kΩ, 80kΩ, 0.015 –40°C +25°C +125°C –40°C +25°C +125°C 0.002 0 –0.002 R-DNL (LSB) 0.010 0.005 0 –0.005 –0.004 –0.006 –0.008 –0.010 –0.012 –0.014 10kΩ, –40°C 80kΩ, –40°C –0.016 –0.015 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 31 CODE (Decimal) –0.018 0 2 4 6 8 10kΩ, +25°C 80kΩ, +25°C 10kΩ, +125°C 80kΩ, +125°C 10 12 14 16 18 20 22 24 26 28 31 CODE (Decimal) Figure 11. R-DNL vs. Code (AD5115) Figure 8. R-INL vs. Code (AD5115) Rev. 0 | Page 12 of 24 09654-012 –0.010 09654-009 R-INL (LSB) 09654-011 –0.02 09654-008 R-INL (LSB) –0.01 0.02 Data Sheet AD5111/AD5113/AD5115 0.08 10kΩ, 10kΩ, 10kΩ, 80kΩ, 80kΩ, 80kΩ, 0.06 0.04 0.02 –40°C +25°C +125°C –40°C +25°C +125°C 0.01 0 –0.01 DNL (LSB) 0 –0.02 –0.02 –0.03 –0.04 –0.04 –0.05 0.02 5kΩ, –40°C 5kΩ, +25°C 5kΩ, +125°C 10kΩ, –40°C 10kΩ, +25°C 10kΩ, +125°C 80kΩ, –40°C 80kΩ, +25°C 80kΩ, +125°C –0.05 09654-014 119 127 112 98 105 91 77 70 63 56 42 84 80kΩ, +125°C 0 3 6 9 12 15 18 21 24 27 30 33 36 39 42 45 48 51 54 57 60 63 CODE (Decimal) Figure 13. INL vs. Code (AD5113) Figure 16. DNL vs. Code (AD5113) 10kΩ, 10kΩ, 10kΩ, 80kΩ, 80kΩ, 80kΩ, 0.004 –40°C +25°C +125°C –40°C +25°C +125°C 10kΩ, –40°C 10kΩ, +25°C 10kΩ, +125°C 80kΩ, –40°C 80kΩ, +25°C 80kΩ, +125°C 0.002 0 DNL (LSB) –0.002 0 –0.005 –0.004 –0.006 –0.008 –0.010 –0.010 –0.012 –0.014 –0.020 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 31 CODE (Decimal) Figure 14. INL vs. Code (AD5115) –0.016 0 2 4 6 8 10 12 14 16 18 20 22 CODE (Decimal) Figure 17. DNL vs. Code (AD5115) Rev. 0 | Page 13 of 24 24 26 28 31 09654-018 –0.015 09654-015 INL (LSB) 80kΩ, +25°C 80kΩ, –40°C –0.06 09654-017 –0.06 0.005 49 –0.03 –0.04 0.010 35 –0.02 –0.04 0.015 5kΩ, +125°C 10kΩ, +125°C –0.01 –0.02 0 3 6 9 12 15 18 21 24 27 30 33 36 39 42 45 48 51 54 57 60 63 CODE (Decimal) 5kΩ, +25°C 10kΩ, +25°C 0 0 –0.08 5kΩ, –40°C 10kΩ, –40°C 0.01 DNL (LSB) INL (LSB) 0.02 10kΩ, +125°C 80kΩ, +125°C Figure 15. DNL vs. Code (AD5111) 0.08 0.04 10kΩ, +25°C 80kΩ, +25°C CODE (Decimal) Figure 12. INL vs. Code (AD5111) 0.06 28 21 14 0 10kΩ, –40°C 80kΩ, –40°C 09654-016 CODE (Decimal) 09654-013 119 127 112 98 105 91 84 77 70 63 56 49 42 35 28 21 –0.07 14 –0.08 0 –0.06 7 –0.06 7 INL (LSB) 0.02 AD5111/AD5113/AD5115 800 Data Sheet 1.2 VDD = 2.3V VDD = 3.3V VDD = 5V 700 VDD = 5V VDD = 3.3V VDD = 2.3V TA = 25°C 1.0 SUPPLY CURRENT (mA) SUPPLY CURRENT (nA) 600 500 400 300 200 0.8 0.6 0.4 100 0.2 –25 –10 5 35 65 20 50 TEMPERATURE (°C) 80 95 110 125 0 0.05 09654-019 –100 –40 2.45 3.05 3.65 200 4.25 4.85 VDD = 5V 10kΩ 80kΩ 5kΩ RHEOSTAT MODE TEMPCO (ppm/°C) 180 140 120 100 80 60 40 20 160 140 120 100 80 60 40 20 0 20 10 5 40 20 10 80 60 30 40 15 20 CODE (Decimal) 100 50 25 120 AD5111 60 AD5113 30 AD5115 0 0 0 09654-020 0 0 0 Figure 19. Potentiometer Mode Tempco ((ΔVW/VW)/ΔT × 106) vs. Code 20 10 5 0x40 (0x20) [0x10] 0x10 0x10 (0x08) [0x04] –20 GAIN (dB) 0x04 0x02 0x01 0x04 (0x02) [0x01] –30 0x02 (0x01) [0x00] 0x01 (0x00) –40 0x00 0x00 –50 –50 –60 100k 1M 10M FREQUENCY (Hz) 100M 09654-021 –60 10k 0x08 (0x04) [0x02] Figure 20. 5 kΩ Gain vs. Frequency vs. Code AD5111 (AD5113) [AD5115] –70 10k 100k 1M FREQUENCY (Hz) Figure 23. 10 kΩ Gain vs. Frequency vs. Code Rev. 0 | Page 14 of 24 10M 09654-024 –40 120 AD5111 60 AD5113 30 AD5115 –10 0x20 (0x10) [0x08] 0x08 –30 100 50 25 0 0x20 –20 60 80 30 40 15 20 CODE (Decimal) Figure 22. Rheostat Mode Tempco ((ΔRWB/RWB)/ΔT × 106) vs. Code 0 –10 40 20 10 09654-023 0 GAIN (dB) POTENTIOMETER MODE TEMPCO (ppm/°C) 160 1.85 Figure 21. Supply Current (IDD) vs. Digital Input Voltage VDD = 5V 10kΩ 80kΩ 5kΩ 180 1.25 DIGITAL INPUT VOLTAGE (V) Figure 18. Supply Current vs. Temperature 200 0.65 09654-022 0 Data Sheet AD5111/AD5113/AD5115 0 80 0x40 (0x20) [0x10] 60 0x04 (0x02) [0x01] –30 0x02 (0x01) [0x00] –40 0x01 (0x00) –50 40 30 20 1M FREQUENCY (Hz) 0 09654-025 AD5111 (AD5113) [AD5115] –80 10k 100k 10 5 150 –10 –20 –30 –40 –50 –60 RAB = 10kΩ FULL SCALE HALF SCALE QUARTER SCALE 1M 10M FREQUENCY (Hz) –20 5.5V 5V 3.3V 2.7V 2.3V 90 60 30 0 1 2 3 VDD (V) 4 0 5 6 5kΩ 10kΩ 80kΩ VDD = 5V VA = 2.5V + VIN –10 VB = 2.5V fIN = 1kHz –20 CODE = HALF SCALE NOISE FILTER = 22kHz –30 –30 THD + N (dB) THD + N (dB) AD5111 AD5113 AD5115 –40 –50 –60 –40 –50 –60 –70 –70 –90 –80 –100 20 200 2k FREQUENCY (Hz) 20k 200k 09654-027 –80 Figure 26. Total Harmonic Distortion + Noise (THD + N) vs. Frequency –90 0.001 0.01 0.1 AMPLITUDE (V rms) 1 09654-030 –10 60 30 15 Figure 28. Incremental Wiper On Resistance vs. VDD 5kΩ 10kΩ 80kΩ VDD = 5V VA = 2.5V + 1VRMS VB = 2.5V CODE = HALF SCALE NOISE FILTER = 22kHz 50 25 TA = 25°C Figure 25. Normalized Phase Flatness vs. Frequency 0 40 20 10 CODE (Decimal) 120 0 09654-049 100k 30 15 09654-029 INCREMENTAL WIPER ON RESISTANCE (Ω) 0 –80 10k 20 10 5 Figure 27. Maximum Bandwidth vs. Code vs. Net Capacitance Figure 24. 80 kΩ Gain vs. Frequency vs. Code PHASE (Degrees) 0 0 0 Figure 29. Total Harmonic Distortion + Noise (THD + N) vs. Amplitude Rev. 0 | Page 15 of 24 09654-028 10 –70 –70 80k + 150pF 80k + 250pF 5k + 0pF 5k + 75pF 5k + 150pF 10k + 0pF 50 0x00 –60 5k + 250pF 10k + 75pF 10k + 150pF 10k + 250pF 80k + 0pF 80k + 75pF 70 BANDWIDTH (MHz) GAIN (dB) –10 0x20 (0x10) [0x08] 0x10 (0x08) [0x04] –20 0x08 (0x04) [0x02] AD5111/AD5113/AD5115 Data Sheet 0.35 100 0.30 VDD = 5V VA = VDD VB = GND 80 5kΩ 10kΩ 80kΩ 40 0.20 60 VOLTAGE ( µV) 0.15 0.10 0.05 20 0 –20 –40 –60 0 –100 3 5 TIME (µs) 7 9 –120 0 0.5 CUMULATIVE PROBABILITY 0.6 0.0010 0.4 0.0005 300 400 500 –30 –40 –70 09654-050 200 5kΩ 10kΩ 80kΩ –60 0 600 RESISTOR DRIFT (ppm) 1k Figure 31. Resistor Lifetime Drift 10k 1M FREQUENCY (Hz) 10M Figure 34. Shutdown Isolation vs. Frequency 7 5kΩ 10kΩ 80kΩ 10kΩ 80kΩ 5kΩ 6 THEORETICAL IMAX (mA) VDD = 5V ± 10% AC VA = 4V VB = GND CODE = HALF SCALE TA = 25°C –20 –30 –40 –50 –60 5 4 3 2 1 100 1k 10k 100k 1M FREQUENCY (Hz) 09654-033 –70 10 4.0 –50 0.2 –10 3.5 –20 GAIN (dB) 0.0015 PSRR (dB) PROBABILITY DENSITY 0.8 0 3.0 –10 1.0 0.0020 100 2.5 0 1.2 0 2.0 Figure 33. Digital Feedthrough 0.0025 –600 –500 –400 –300 –200 –100 1.5 TIME (µs) Figure 30. Maximum Transition Glitch 0 1.0 09654-035 1 09654-048 –0.10 –1 09654-034 VDD = 5V VA = VDD VB = GND CODE = HALF SCALE –80 –0.05 0 0 0 0 20 10 5 40 20 10 60 80 30 40 15 20 CODE (Decimal) 100 50 25 120 AD5111 60 AD5113 30 AD5115 Figure 35. Theoretical Maximum Current vs. Code Figure 32. Power Supply Rejection Ratio (PSRR) vs. Frequency Rev. 0 | Page 16 of 24 09654-036 RELATIVE VOLTAGE (V) 0.25 Data Sheet AD5111/AD5113/AD5115 TEST CIRCUITS Figure 36 to Figure 41 define the test conditions used in the Specifications section. NC IW VA B B 09654-037 W VIN W B DUT B OFFSET GND VMS GND VDD DUT A GND TO VDD NC = NO CONNECT GND 09654-039 – 0.1V VDD ICM W + IWB –15V GND VDD B VOUT Figure 40. Gain and Phase vs. Frequency 0.1V RW = IWB DUT A W AD8652 2.5V Figure 37. Potentiometer Divider Nonlinearity Error (INL, DNL) NC +15V A V+ = VDD 1LSB = V+/2N 09654-038 A ∆VMS% ∆VDD% Figure 39. Power Supply Sensitivity (PSS, PSRR) Figure 36. Resistor Position Nonlinearity Error (Rheostat Operation: R-INL, R-DNL) V+ PSS (%/%) = VMS 09654-041 NC = NO CONNECT V+ = VDD ± 10% ∆VMS PSRR (dB) = 20 log ∆V DD W V+ ~ VMS DUT A 09654-040 VDD B VDD GND 09654-042 DUT A W Figure 41. Common-Mode Leakage Current Figure 38. Wiper Resistance Rev. 0 | Page 17 of 24 AD5111/AD5113/AD5115 Data Sheet THEORY OF OPERATION The AD5111/AD5113/AD5115 digital programmable resistors are designed to operate as true variable resistors for analog signals within the terminal voltage range of GND < VTERM < VDD. The resistor wiper position is determined by the RDAC register contents. The RDAC register acts as a scratchpad register that allows unlimited changes of resistance settings. The RDAC register can be programmed with any position setting using the up/down interface. Once a desirable wiper position is found, this value can be stored in the EEPROM. Thereafter, the wiper position is always restored to that position for subsequent power-up. The storing of EEPROM data takes approximately 30 ms; during this time, the device is locked and does not accept any new operation, thus preventing any changes from taking place. The AD5111/AD5113/AD5115 are designed to allow high speed digital control with clock rates up to 50 MHz. RDAC REGISTER AND EEPROM The RDAC register directly controls the position of the digital potentiometer wiper. For example, when the RDAC register is 0x40 (AD5111), the wiper is connected to midscale of the variable resistor. The RDAC register is a standard logic register; there is no restriction on the number of changes allowed. Once a desirable wiper position is found, this value can be saved into the EEPROM. Thereafter, the wiper position is always set at that position for any future on-off-on power supply sequence or recall operation. BASIC OPERATION When CS is pulled low, changing the resistance settings is achieved by clocking the CLK pin. It is negative edge triggered, and the direction of stepping into the RDAC register is determined by the state of the U/D input. When a specific state of the U/D remains, the device continues to change in the same direction under consecutive clocks until it comes to the end of the resistance setting. When the wiper reaches the maximum or minimum setting, additional CLK pulses do not change the wiper setting. Figure 2 shows a typical increment/decrement operation. LOW WIPER RESISTANCE FEATURE The AD5111/AD5113/AD5115 include a new feature to reduce the resistance between terminals. These extra steps are called bottom scale and top scale. At bottom scale, the typical wiper resistance decreases from 70 Ω to 45 Ω. At top scale, the resistance between Terminal A and Terminal W is decreased by 1 LSB and the total resistance is reduced to 70 Ω. The new extra steps are loaded automatically in the RDAC register after zeroscale or full-scale position has been reached. The extra steps are not equal to 1 LSB and are not included in the INL, DNL, R-INL, and R-DNL specifications. SHUTDOWN MODE This feature places Terminal A in open circuit, disconnected from the internal resistor, and connects Terminal W and Terminal B. A finite wiper resistance of 45 Ω is present between these two terminals. The command is sent by a low-to-high transition on the U/D pin, when CLK is high and CS is enabled. The command is executed on the CLK negative edge, as shown in Figure 4. The AD5111/AD5113/AD5115 return the wiper to prior shutdown position if any other operation is performed. EEPROM WRITE OPERATION The AD5111/AD5113/AD5115 contain an EEPROM that allows the wiper position storage. Once a desirable wiper position is found, this value can be saved into the EEPROM. Thereafter, the wiper position is always set at that position for any future power-up sequence or a memory recall operation. During the storage cycle, the device is locked and does not accept any new operation, thus preventing any changes from taking place. The write cycle is started by applying a pulse in the U/D pin when CS is enabled and CLK remains high, as shown in Figure 3. The write cycle takes approximately 20 ms. The U/D pin value can be changed only when the CLK pin is low. Rev. 0 | Page 18 of 24 Data Sheet AD5111/AD5113/AD5115 RDAC ARCHITECTURE PROGRAMMING THE VARIABLE RESISTOR To achieve optimum performance, Analog Devices, Inc., has patented the RDAC segmentation architecture for all the digital potentiometers. In particular, the AD5111/AD5113/AD5115 employ a two-stage segmentation approach as shown in Figure 42. The AD5111/AD5113/AD5115 wiper switch is designed with the transmission gate CMOS topology and with the gate voltage derived from VDD. Rheostat Operation—±8% Resistor Tolerance A A W TS B RL A W B W 09654-044 A The AD5111/AD5113/AD5115 operate in rheostat mode when only two terminals are used as a variable resistor. The unused terminal can be floating or tied to the W terminal as shown in Figure 43. B Figure 43. Rheostat Mode Configuration The nominal resistance between Terminal A and Terminal B, RAB, is available in 5 kΩ, 10 kΩ, and 80 kΩ and has 128/64/32 tap points accessed by the wiper terminal. The 5-/6-/7-bit data in the RDAC latch is decoded to select one of the 128/64/32 possible wiper settings. The general equations for determining the digitally programmed output resistance between the W terminal and B terminal are RL RS W RS 5-BIT/6-BIT/7-BIT ADDRESS DECODER AD5111: RWB RBS RL RWB (D ) RL BS Bottom scale (1) D R AB RW 128 From 0 to 128 (2) AD5113: B 09654-043 RWB RBS RWB (D ) Figure 42. AD5111/AD5113/AD5115 Simplified RDAC Circuit Low Wiper Resistance Feature Bottom scale (3) D R AB RW 64 From 0 to 64 (4) AD5115: In addition, the AD5111/AD5113/AD5115 include a new feature to reduce the resistance between terminals. These extra steps are called bottom scale and top scale. At bottom scale, the typical wiper resistance decreases from 70 Ω to 45 Ω. At top scale, the resistance between Terminal A and Terminal W is decreased by 1 LSB and the total resistance is reduced to 70 Ω. The extra steps are not equal to 1 LSB and are not included in the INL, DNL, R-INL, and R-DNL specifications. RWB RBS RWB ( D ) Bottom scale (5) D R AB RW 32 From 0 to 32 (6) where: D is the decimal equivalent of the binary code in the 5-/6-/7-bit RDAC register; 128, 64, and 32 refer to the top scale step. RAB is the end-to-end resistance. RW is the wiper resistance. RBS is the wiper resistance at bottom scale. Rev. 0 | Page 19 of 24 AD5111/AD5113/AD5115 Data Sheet AD5111: RAW = RAB + RW 128 − D RAW (D ) = × RAB + RW 128 RAW = RTS PROGRAMMING THE POTENTIOMETER DIVIDER Voltage Output Operation The digital potentiometer easily generates a voltage divider at W-to-B and W-to-A that is proportional to the input voltage at A-to-B, as shown in Figure 44. Unlike the polarity of VDD to GND, which must be positive, current across A-to-B, W-to-A, and W-to-B can be in either direction. Bottom scale (7) VI A From 0 to 127 (8) W B Top scale (9) AD5113: Figure 44. Potentiometer Mode Configuration RAW = RAB + RW RAW (D ) = 64 − D × RAB + RW 64 RAW = RTS Bottom scale (10) From 0 to 63 (11) Top scale (12) AD5115: RAW = RAB + RW RAW (D ) = RAW = RTS VO 09654-045 Similar to the mechanical potentiometer, the resistance of the RDAC between the W terminal and the A terminal also produces a digitally controlled complementary resistance, RWA. RWA starts at the maximum resistance value and decreases as the data loaded into the latch increases. The general equations for this operation are 32 − D × RAB + RW 32 If ignoring the effect of the wiper resistance for simplicity, connecting Terminal A to 5 V and Terminal B to ground produces an output voltage at W to B ranging from 0 V to 5 V. The general equation defining the output voltage at VW with respect to ground for any valid input voltage applied to Terminal A and Terminal B, is VW (D ) = Bottom scale (13) From 0 to 31 (14) Top scale (15) R (D ) RWB (D ) × VA + AW × VB RAB RAB (16) where: RWB(D) can be obtained from Equation 1 to Equation 6. RAW(D) can be obtained from Equation 7 to Equation 14. where: D is the decimal equivalent of the binary code in the 5-/6-/7-bit RDAC register; 128, 64, and 32 refer to top scale step. RAB is the end-to-end resistance. RW is the wiper resistance. RTS is the wiper resistance at top scale. Operation of the digital potentiometer in the divider mode results in a more accurate operation over temperature. Unlike the rheostat mode, the output voltage is dependent mainly on the ratio of the internal resistors, RWA and RWB, and not the absolute values. Therefore, the temperature drift reduces to 5 ppm/°C. Regardless of which setting the part is operating in, take care to limit the current between A to B, W to A, and W to B, to the maximum continuous current of ±6 mA (5 kΩ and 10 kΩ) or ±1.5 mA (80 kΩ), or pulse current specified in Table 6. Otherwise, degradation or possible destruction of the internal switch contact can occur. TERMINAL VOLTAGE OPERATING RANGE The AD5111/AD5113/AD5115 are designed with internal ESD diodes for protection. These diodes also set the voltage boundary of the terminal operating voltages. Positive signals present on the A, B, or W terminals that exceed VDD are clamped by the forward-biased diode. There is no polarity constraint between VA, VW, and VB, but they cannot be higher than VDD or lower than GND. Rev. 0 | Page 20 of 24 Data Sheet AD5111/AD5113/AD5115 LAYOUT AND POWER SUPPLY BIASING Because of the ESD protection diodes that limit the voltage compliance at the A, B, and W terminals (see Figure 45), it is important to power on VDD before applying any voltage to the A, B, and W terminals. Otherwise, the diodes are forwardbiased such that VDD is powered on unintentionally and can affect other parts of the circuit. Similarly, VDD should be powered down last. The ideal power-on sequence is in the following order: GND, VDD, and VA/VB/VW. The order of powering VA, VB, VW and the digital inputs is not important as long as they are powered on after VDD. It is always a good practice to use compact, minimum lead length layout design. The leads to the input should be as direct as possible with a minimum conductor length. Ground paths should have low resistance and low inductance. It is also good practice to bypass the power supplies with quality capacitors. Apply low equivalent series resistance (ESR) 1 μF to 10 μF tantalum or electrolytic capacitors at the supplies to minimize any transient disturbance and to filter low frequency ripple. Figure 46 illustrates the basic supply bypassing configuration for the AD5111/AD5113/AD5115. AD5111/ AD5113/ AD5115 VDD VDD A + C2 10µF C1 0.1µF VDD GND W AGND B 09654-046 GND Figure 46. Power Supply Bypassing Figure 45. Maximum Terminal Voltages Set by VDD and GND Rev. 0 | Page 21 of 24 09654-047 POWER-UP SEQUENCE AD5111/AD5113/AD5115 Data Sheet OUTLINE DIMENSIONS 1.70 1.60 1.50 2.00 BSC SQ 0.50 BSC 8 5 PIN 1 INDEX AREA 1.10 1.00 0.90 EXPOSED PAD 0.425 0.350 0.275 1 4 TOP VIEW SEATING PLANE 0.05 MAX 0.02 NOM 0.30 0.25 0.20 PIN 1 INDICATOR (R 0.15) FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. 0.20 REF 063009-A 0.60 0.55 0.50 BOTTOM VIEW Figure 47. 8-Lead Frame Chip Scale Package [LFCSP_UD] 2 mm × 2 mm Body, Very Thin, Dual Lead (CP-8-10) Dimensions shown in millimeters ORDERING GUIDE Model 1 AD5111BCPZ10-RL7 AD5111BCPZ10-500R7 AD5111BCPZ80-RL7 AD5111BCPZ80-500R7 AD5113BCPZ5-RL7 AD5113BCPZ5-500R7 AD5113BCPZ10-RL7 AD5113BCPZ10-500R7 AD5113BCPZ80-RL7 AD5113BCPZ80-500R7 AD5115BCPZ10-RL7 AD5115BCPZ10-500R7 AD5115BCPZ80-RL7 AD5115BCPZ80-500R7 EVAL-AD5111SDZ 1 RAB (kΩ) 10 10 80 80 5 5 10 10 80 80 10 10 80 80 Resolution 128 128 128 128 64 64 64 64 64 64 32 32 32 32 Temperature Range −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C Z = RoHS Compliant Part. Rev. 0 | Page 22 of 24 Package Description 8-Lead LFCSP_UD 8-Lead LFCSP_UD 8-Lead LFCSP_UD 8-Lead LFCSP_UD 8-Lead LFCSP_UD 8-Lead LFCSP_UD 8-Lead LFCSP_UD 8-Lead LFCSP_UD 8-Lead LFCSP_UD 8-Lead LFCSP_UD 8-Lead LFCSP_UD 8-Lead LFCSP_UD 8-Lead LFCSP_UD 8-Lead LFCSP_UD Evaluation Board Package Option CP-8-10 CP-8-10 CP-8-10 CP-8-10 CP-8-10 CP-8-10 CP-8-10 CP-8-10 CP-8-10 CP-8-10 CP-8-10 CP-8-10 CP-8-10 CP-8-10 Branding Code 7S 7S 7T 7T 85 85 84 84 86 86 7Y 7Y 7Z 7Z Data Sheet AD5111/AD5113/AD5115 NOTES Rev. 0 | Page 23 of 24 AD5111/AD5113/AD5115 Data Sheet NOTES ©2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D09654-0-10/11(0) Rev. 0 | Page 24 of 24