INTEGRATED CIRCUITS FBL22041 3.3V BTL 7-bit Futurebus + transceiver (standard A-port) Product specification Supersedes data of 1998 Feb 02 IC23 Data Handbook 1998 Aug 12 Philips Semiconductors Product specification 3.3V BTL 7-bit Futurebus+ transceiver (standard A-port) FBL22041 • Tight output skew • Supports live insertion • Pins for the optional JTAG boundary scan function are provided • High density packaging in plastic Quad Flatpack • 5V compatible I/O on A-port • The A port includes a series resistor of 30Ω making external FEATURES • 7-bit BTL transceiver • Separate I/O on TTL A-port • Inverting • Three separate pairs of driver enables in a 1 bit, 3 bit, 3 bit arrangement • Drives heavily loaded backplanes with equivalent load terminating resistors unnecessary impedances down to 10Ω. • High drive 100mA BTL open collector drivers on B-port • Allows incident wave switching in heavily loaded backplane buses • Reduced BTL voltage swing produces less noise and reduces DESCRIPTION The FBL22041 is a 7-bit bidirectional BTL transceiver and is intended to provide the electrical interface to a high performance wired-OR bus. The FBL22041 is an inverting transceiver. power consumption • Built-in precision band-gap reference provides accurate receiver The B-port drivers are Low-capacitance open collectors with controlled ramp and are designed to sink 100mA. Precision band gap references on the B-port insure very good noise margins by limiting the switching threshold to a narrow region centered at 1.55V. thresholds and improved noise immunity • Compatible with IEEE Futurebus+ or proprietary BTL backplanes • Controlled output ramp and multiple GND pins minimize ground The FBL22041 is designed with a 30Ω series resistance in both the HIGH and LOW states of the output. bounce • Each BTL driver has a dedicated Bus GND for a signal return • Glitch-free power up/power down operation • Low ICC current The FBL22041 is pin and function compatible with FB2041 but operates at a 3.3V supply voltage, greatly reducing power consumption. QUICK REFERENCE DATA SYMBOL PARAMETER TYPICAL tPLH Propagation delay 4.1 tPHL AIn to Bn 3.6 tPLH Propagation delay 5.2 tPHL Bn to AOn 5.1 COB Output capacitance (B0 - B6 only) 6 pF IOL Output current (B0 - B6 only) 100 mA Standby ICC Supply Current UNIT ns ns 6.0 AIn to Bn (outputs Low or High) 5.1 Bn to AOn (outputs Low) 13.4 Bn to AOn (outputs High) 10.6 mA ORDERING INFORMATION PACKAGE COMMERCIAL RANGE VCC = 3.3V±10%; Tamb = 0 to +70°C DWG No. 52-pin Plastic Quad Flatpack FBL22041BB SOT379-1 1998 Aug 12 2 853-2039 19863 Philips Semiconductors Product specification BUS GND FBL22041 B0 TMS (option) VCC OEB1 TCK (option) OEA1 OEB0 VCC BIAS V AI0 AO0 AO1 3.3V BTL 7-bit Futurebus+ transceiver (standard A-port) 52 51 50 49 48 47 46 45 44 43 42 41 40 LOGIC GND 1 39 BUS GND AI1 2 38 B1 AI2 3 37 BUS GND AO2 4 36 B2 LOGIC GND 5 35 BUS GND AO3 6 34 B3 LOGIC GND 7 33 BUS GND AI3 8 32 B4 AI4 9 31 BUS GND AO4 10 30 B5 LOGIC GND 11 29 BUS GND AO5 12 28 B6 LOGIC GND 13 27 N/C 7-Bit Transceiver 52-lead PQFP OEB3 OEB2 OEA3 VCC TDI (option) TDO (option) OEA2 BG GND AI6 BG VCC AO6 AI5 LOGIC GND 14 15 16 17 18 19 20 21 22 23 24 25 26 SG00084 The B-port interfaces to “Backplane Transceiver Logic” (See the IEEE 1194.1 BTL standard). BTL features low power consumption by reducing voltage swing (1Vp-p, between 1V and 2V) and reduced capacitive loading by placing an internal series diode on the drivers. BTL also provides incident wave switching, a necessity for high performance backplanes. The A-port operates at TTL levels with separate I/O. The 3-state A-port drivers are enabled when OEAn goes High after an extra 6ns delay which is built in to provide a break-before-make function. When OEAn goes Low, A-port drivers become High impedance without any extra delay. During power on/off cycles, the A-port drivers are held in a High impedance state when VCC is below 1.3V. There are three separate pairs of driver enables in a 1 bit, 3 bit, 3 bit arrangement. The TTL/BTL output drivers for bit 0 are enabled with OEA1/OEB1, output drivers for bits 1–2–3 are enabled with OEA2/OEB2 and output drivers for bits 4–5–6 are enabled with OEA3/OEB3. The B-port has an output enable, OEB0, which affects all seven drivers. When OEB0 is High and OEBn is Low the output driver will be enabled. When OEB0 is Low or if OEBn is High, the B-port drivers will be inactive and at the level of the backplane signal. 1998 Aug 12 3 Philips Semiconductors Product specification 3.3V BTL 7-bit Futurebus+ transceiver (standard A-port) FBL22041 PIN DESCRIPTION SYMBOL PIN NUMBER TYPE ai0 – ai6 51, 2, 3, 8, 9, 14, 18 Input NAME AND FUNCTION Data inputs (TTL) aO0 – aO6 50, 52, 4, 6, 10, 12, 16 Output 3-state outputs (TTL) b0 – b6 40, 38, 36, 34, 32, 30, 28 i/o Data inputs/Open Collector outputs, High current drive (BTL) OEB0 46 Input Enables the Bn outputs when High OEB1 45 Input Enables the B0 output when Low OEB2 25 Input Enables the B1 – B3 outputs when Low OEB3 26 Input Enables the B4 – B6 outputs when Low OEA1 47 Input Enables the A0 outputs when High OEA2 20 Input Enables the A1 – A3 outputs when High OEA3 24 Input Enables the A4 – A6 outputs when High bus gnd 41, 39, 37, 35, 33, 31, 29 GND Bus ground (0V) LOGIC gnd 1, 5, 7, 11, 13, 15 GND Logic ground (0V) LOGIC/bus VCC 23, 43, 49 Power Positive supply voltage BG VCC 17 Power Positive supply voltage BAND GAP BIAS V 48 Power Positive supply voltage TMS 42 Input Test Mode Select (no-connect) Tck 44 Input Test Clock (no-connect) Tdi 22 Input Test Data In (shorted to TDO) Tdo 21 Output Test Data Out (TDI) BG GND 19 GND BAND GAP GROUND (0V) 1998 Aug 12 4 Philips Semiconductors Product specification 3.3V BTL 7-bit Futurebus+ transceiver (standard A-port) FBL22041 FUNCTION TABLE MODE AIn to Bn AI0 to B0 AI1 – AI3 to B1 – B3 AI4 – AI6 to B4 – B6 Disable Bn outputs INPUTS OUTPUTS AIn Bn* OEB0 OEB1 OEB2 OEB3 OEA1 OEA2 OEA3 AOn Bn* L — H L L L L L L Z H** H — H L L L L L L Z L L — H L L L H H H L H** H — H L L L H H H H L L — H L X X L L L Z H** H — H L X X L L L Z L L — H L X X H H H L H** H — H L X X H H H H L L — H X L X L L L Z H** H — H X L X L L L Z L L — H X L X H H H L H** H — H X L X H H H H L L — H X X L L L L Z H** H — H X X L L L L Z L L — H X X L H H H L H** H — H X X L H H H H L X X L X X X X X X X H** X X X H H H X X X X H** Disable B0 outputs X X H H X X X X X X H** Disable B1 – B3 outputs X X H X H X X X X X H** Disable B4 – B6 outputs X X H X X H X X X X H** X L L X X X H H H H Input X H L X X X H H H L Input X L X H H H H H H H Input X H X H H H H H H L Input X L L X X X H X X H Input X H L X X X H X X L Input X L X H H H H X X H Input X H X H H H H X X L Input X L L X X X X H X H Input X H L X X X X H X L Input X L X H H H X H X H Input X H X H H H X H X L Input X L L X X X X X H H Input X H L X X X X X H L Input X L X H H H X X H H Input X H X H H H X X H L Input Disable AOn outputs X X X X X X L L L Z X Disable AO0 outputs X X X X X X L X X Z X Disable AO1 – AO3 outputs X X X X X X X L X Z X Disable AO4 – AO6 outputs X X X X X X X X L Z X Bn to AOn B0 to AO0 B1 – B3 to AO1 – AO3 B4 – B6 to AO4 – AO6 NOTES: H = L = X = Z = — = H** = B* = Z — H** B* High voltage level Low voltage level Don’t care High-impedance (OFF) state Input not externally driven Goes to level of pull-up voltage Precaution should be taken to ensure B inputs do not float. If they do, they are equal to Low state. 1998 Aug 12 5 = = = = High-impedance (OFF) state Input not externally driven Goes to level of pull-up voltage Precaution should be taken to ensure B inputs do not float. If they do, they are equal to Low state. Philips Semiconductors Product specification 3.3V BTL 7-bit Futurebus+ transceiver (standard A-port) FBL22041 LOGIC DIAGRAM OEB0 OEB1 OEA1 46 45 47 40 AI0 AO0 OEB2 OEA2 51 50 25 20 38 AI1 AO1 2 AO2 3 34 AO3 OEB3 OEA3 8 AO4 AO5 24 9 AO6 TMS TCK TDI TDO LOGIC VCC LOGIC GND BUS VCC BUS GND BIAS V = = = = = B4 10 14 B5 12 28 AI6 BTL Levels 26 30 AI5 B3 6 32 AI4 B2 4 TTL Levels AI3 B1 52 36 AI2 B0 18 B6 16 42 44 22 21 (Future JTAG Boundary Scan option) 17, 49 1, 5, 7, 11, 13, 15, 19 23, 43 27, 29, 31, 33, 35, 37, 39, 41 48 SG00071 1998 Aug 12 6 Philips Semiconductors Product specification 3.3V BTL 7-bit Futurebus+ transceiver (standard A-port) FBL22041 ABSOLUTE MAXIMUM RATINGS Operation beyond the limits set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the operating free-air temperature range. SYMBOL VCC PARAMETER Supply voltage VIN Input In ut voltage IIN Input current VOUT IOUT TSTG RATING UNIT -0.5 to +4.6 V AI0 – AI6, OEB0, OEBn, OEAn -0.5 to +7.0 V B0 – B6 -0.5 to +3.5 VIN 0 -50 Voltage applied to output in High output state Current applied to output in AO0 – AO6 Low output state/High output state B0 – B6 -0.5 to +7.0 V 48, –24 mA 200 Storage temperature °C -65 to +150 RECOMMENDED OPERATING CONDITIONS SYMBOL VCC Supply voltage VIH High-level in input ut voltage VIL Low-level in input ut voltage IIK Input clamp current IOH High-level output current IOL Low-level out output ut current COB Output capacitance on B port Tamb Operating free-air temperature range 1998 Aug 12 COMMERCIAL LIMITS VCC = 3.3V±10%; Tamb = 0 to +70°C PARAMETER UNIT MIN TYP MAX 3.0 3.3 3.6 Except B0–B6 2.0 B0 – B6 1.62 V V 1.55 Except B0–B6 0.8 B0 – B6 1.47 V -18 mA AO0 – AO6 -12 mA AO0 – AO6 12 mA B0 – B6 100 6 0 7 7 pF +70 °C Philips Semiconductors Product specification 3.3V BTL 7-bit Futurebus+ transceiver (standard A-port) FBL22041 LIVE INSERTION SPECIFICATIONS SYMBOL LIMITS PARAMETER Voltage difference between the Bias voltage and VCC after the PCB is plugged in. UNIT MIN TYP MAX – – 0.5 V VBIASV Bias pin voltage IBIASV S Bias pin ((IBIASV) input DC current VCC = 0 V, Bias V = 3.6V 1.2 mA VCC = 3.3V, Bias V = 3.6V 10 µA VBn Bus voltage during prebias B0 – B8 = 0V, Bias V = 3.3V ILM Fall current during prebias B0 – B8 = 2V, Bias V = 1.3 to 2.5V IHM Rise current during prebias B0 – B8 = 1V, Bias V = 3 to 3.6V IBnPEAK Peak bus current during insertion VCC = 0 to 3.3V, B0 – B8 = 0 to 2.0V, Bias V = 2.7 to 3.6V, OEB0 = 0.8V, tr = 2ns 10 IOL O OFF Power up current VCC = 0 to 3.3V, OEB0 = 0.8V 100 VCC = 0 to 1.2V, OEB0 = 0 to 5V 100 tGR Input glitch rejection VCC = 3.3V 1.62 2.1 V 1 µA µA -1 1.0 mA µA 1.35 ns DC ELECTRICAL CHARACTERISTICS Over recommended operating free-air temperature range unless otherwise noted. SYMBOL TEST CONDITIONS1 PARAMETER LIMITS MIN TYP2 MAX UNIT IOH High level output current B0 – B6 VCC = MAX, VIL = MAX, VOH = 1.9V 100 µA IOFF Power-off output current B0 – B6 VCC = 0V, VIL = MAX, VOH = 1.9V 100 µA VOH VOL High level output High-level out ut voltage Low-level output voltage AO0 – AO6 3 AO0 – AO6 3 B0 – B6 VIK II IIH Input clamp voltage Input leakage g current High-level input current VCC = MIN to MAX; IOH = -100µA VCC –0.2 V VCC = MIN; IOH = -4mA 2.4 V VCC = MIN; IOH = -12mA 2.0 V VCC = MIN; IOL = 4mA 0.4 V VCC = MIN; IOL = 12mA 0.8 V VCC = MIN, IOL = 4mA 0.5 VCC = MIN, IOL = 100mA VCC = MIN, II = IIK = –18mA 0.75 1.0 –0.85 1.20 -1.2 V ±1.0 Control pins VCC = 3.6V; VI = VCC or GND Control/ AI0 – AI6 VCC = 0V or 3.6V; VI = 5.5V 10 AI0 – AI6 VCC = 3.6V; VI = VCC 1 Note 4 VCC = 3.6V; VI = 0V –5 VCC = MAX, VI = 1.9V 100 B0 – B6 V µA µ µA VCC = MAX, VI = 3.5V, note 5 100 mA VCC = MAX, VI = 3.75V @ –40°C 100 mA IIL Low level input current Low-level B0 – B6 MAX VI = 0.75V 0 75V VCC = MAX, 100 -100 µA IOZH Off-state output current AO0 – AO6 VCC = MAX, VO =3V 5 µA IOZL Off-state output current AO0 – AO6 VCC = MAX, VO = 0.5V -5 µA ICCZ (standby) VCC = MAX ICCB, AIn to Bn ICCA, Bn to AOn ICCA, Bn to AOn ICC Supply current (total) 6.0 13.0 VCC = MAX, outputs Low or High 5.1 10.0 VCC = MAX, outputs Low 13.4 19.5 VCC = MAX, outputs High 10.6 16.0 mA NOTES: 1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operation conditions for the applicable type. 2. All typical values are at VCC = 3.3V, TA = 25°C. 3. Due to test equipment limitations, actual test conditions are VIH = 1.8V and VIL = 1.3V for the B side. 4. Unused pins are at VCC or GND. 5. For B port input voltage between 3 and 5 volt; IIH will be greater than 100mA but the part will continue to function normally (clamping circuit is active). 1998 Aug 12 8 Philips Semiconductors Product specification 3.3V BTL 7-bit Futurebus+ transceiver (standard A-port) FBL22041 AC ELECTRICAL CHARACTERISTICS (Commercial) A PORT LIMITS SYMBOL PARAMETER TEST CONDITION Tamb = +25°C, VCC = 3.3V, CL = 50pF, RL = 500Ω Tamb = 0 to 70°C, VCC = 3.3V±10%, CL = 50pF, RL = 500Ω UNIT MIN TYP MAX MIN MAX Waveform 1, 2 4.2 4.1 5.2 5.1 6.2 6.1 3.9 3.9 7.0 6.8 ns Output enable time, OEA to AOn Waveform 4, 5 5.8 2.7 7.1 4.5 8.5 8.0 5.4 2.5 9.4 8.5 ns tPHZ tPLZ Output disable time, OEA to AOn Waveform 4, 5 3.9 3.7 5.2 4.8 6.5 6.0 3.6 3.3 7.0 7.3 ns tTLH tTHL Transition time, AOn Port (10% to 90% or 90% to 10%) Test Circuit and Waveforms 0.8 0.6 1.6 1.1 2.8 1.7 0.7 0.5 3.0 2.0 ns 0.4 1.5 1.5 ns tPLH tPHL Propagation delay, Bn to AOn tPZH tPZL tSK(o) Output skew between receivers in same package1 Waveform 3 B PORT LIMITS SYMBOL PARAMETER tPLH tPHL Propagation delay, AIn to Bn tPLH tPHL Tamb = +25°C, VCC = 3.3V, CD = 30pF, RU = 9Ω TEST CONDITION Tamb = 0 to 70°C, VCC = 3.3V±10%, CD = 30pF, RU = 9Ω UNIT Waveform 1, 2 3.2 2.9 4.1 3.6 5.0 4.4 2.9 2.7 5.8 4.9 ns Enable/disable time, OEB0 to Bn Waveform 2 3.9 3.5 4.7 4.4 5.5 5.4 3.5 3.2 6.4 5.9 ns tPLH tPHL Enable/disable time, OEB1 to Bn Waveform 1 4.1 3.0 5.0 3.9 5.9 4.8 3.8 2.6 6.6 5.5 ns tTLH tTHL Transition time, Bn Port (1.3V to 1.8V) Test Circuit and Waveforms 1.3 0.4 1.9 0.8 2.8 1.4 1.2 0.4 3.0 1.5 ns 0.3 1.4 1.4 ns tSK(o) SYMBOL Output skew between drivers in same package1 Waveform 3 PARAMETER TEST CONDITION tPLH tPHL Propagation delay, AIn to Bn tPLH tPHL RU = 16.5Ω RU = 16.5Ω UNIT Waveform 1, 2 3.2 2.9 4.1 3.6 5.0 4.9 2.9 2.6 5.8 4.9 ns Enable/disable time, OEB0 to Bn Waveform 2 3.9 3.5 4.7 4.4 5.5 5.4 3.5 3.2 6.4 5.9 ns tPLH tPHL Enable/disable time, OEB1 to Bn Waveform 1 4.1 3.0 5.0 3.9 5.9 4.8 3.8 2.6 6.6 5.5 ns tTLH tTHL Transition time, Bn Port (1.3V to 1.8V) Test Circuit and Waveforms 1.3 0.4 1.9 0.8 2.8 1.4 1.2 0.4 3.0 1.5 ns 0.3 1.4 1.4 ns tSK(o) Output skew between drivers in same package1 Waveform 3 NOTES: 1. tPNactual – tPMactual for any data input to output path compared to any other data input to output path where N and M are either LH or HL. Skew times are valid only under same test conditions (temperature, VCC, loading, etc.). 1998 Aug 12 9 Philips Semiconductors Product specification 3.3V BTL 7-bit Futurebus+ transceiver (standard A-port) FBL22041 AC WAVEFORMS VM AIn, Bn or Bn OEBn AIn, Bn OEB0 VM tPLH VM AOn or Bn VM tPHL VM tPHL VM AOn, Bn Waveform 1. Propagation Delay for Data or Output Enable to Output tPLH VM VM Waveform 2. Propagation Delay for Data or Output Enable to Output VM AIn, Bn tSK(o) AOn, Bn OEA tPZH AOn Waveform 3. Output Skews VM VM VM OEA tPZL tPHZ VM VOH -0.3V AOn OV Waveform 4. 3-State Output Enable Time to High Level and Output Disable Time from High Level tPLZ VM VOL +0.3V Waveform 5. 3-State Output Enable Time to Low Level and Output Disable Time from Low Level NOTE: VM = 1.55V for Bn, VM = 1.5V for all others. 1998 Aug 12 VM VM 10 SG00086 Philips Semiconductors Product specification 3.3V BTL 7-bit Futurebus+ transceiver (standard A-port) FBL22041 TEST CIRCUIT AND WAVEFORMS BIAS V VCC 6.0V tW 90% VIN RL VOUT PULSE GENERATOR NEGATIVE PULSE VM VM 10% D.U.T. RT CL 10% tTHL (tf) tTLH (tr) tTHL POSITIVE PULSE VM VM CLOSED tPHZ, tPZH GND BIAS V VCC VIN Input Pulse Definitions 2.0V (for RU = 9 Ω) 2.1V (for RU = 16.5 Ω) VOUT PULSE GENERATOR INPUT PULSE REQUIREMENTS Family FB+ Amplitude Low V Rep. Rate A Port 3.0V 0.0V 1MHz 500ns 2.5ns 2.5ns B Port 2.0V 1.0V 1MHz 500ns 2.5ns 2.5ns tW tTLH tTHL RU D.U.T. RT LOW V VM = 1.55V for Bn, VM = 1.5V for all others. SWITCH tPLZ, tPZL 10% tW SWITCH POSITION FOR ALL A-PORTS (tf) VIN 90% 10% OPEN (tr) RL Test Circuit for 3-State Outputs on A Port tPLH, tPHL LOW V tTLH 90% TEST VIN 90% CD DEFINITIONS: RL = Load Resistor; see AC CHARACTERISTICS for value. CL = Load capacitance includes jig and probe capacitance; see AC CHARACTERISTICS for value. RT = Termination resistance should be equal to ZOUT of pulse generators. CD = Load capacitance includes jig and probe capacitance; see AC CHARACTERISTICS for value. RU = Pull up resistor; see AC CHARACTERISTICS for value. Test Circuit for Outputs on B Port SG00090 1998 Aug 12 11 Philips Semiconductors Product specification 3.3V BTL 7-bit Futurebus + transceiver (standard A-port) QFP52: plastic quad flat package; 52 leads (lead length 1.6 mm); body 10 x 10 x 2.0 mm 1998 Aug 12 12 FBL22041 SOT379-1 Philips Semiconductors Product specification 3.3V BTL 7-bit Futurebus + transceiver (standard A-port) NOTES 1998 Aug 12 13 FBL22041 Philips Semiconductors Product specification 3.3V BTL 7-bit Futurebus + transceiver (standard A–Port) 74FBL22041 Data sheet status Data sheet status Product status Definition [1] Objective specification Development This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. Preliminary specification Qualification This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make chages at any time without notice in order to improve design and supply the best possible product. Product specification Production This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. [1] Please consult the most recently issued datasheet before initiating or completing a design. Definitions Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Disclaimers Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Copyright Philips Electronics North America Corporation 1998 All rights reserved. Printed in U.S.A. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381 print code Document order number: yyyy mmm dd 14 Date of release: 05-96 9397-750-04279