Catalyst CAT24WC164PI-TE13 16k-bit serial eeprom, cascadable Datasheet

H
CAT24WC164
EE
GEN FR
ALO
16K-Bit Serial EEPROM, Cascadable
LE
FEATURES
A D F R E ETM
■ Self-timed write cycle with auto-clear
■ 400 kHz I C bus compatible*
■ 1,000,000 program/erase cycles
■ 1.8 to 6.0 volt operation
■ 100 year data retention
■ Low power CMOS technology
■ 8-pin DIP, 8-pin SOIC, 8-pin MSOP or
2
8 pin TSSOP
■ Write protect feature
- Entire array protected when WP at VIH
(Also available in "Green" packages)
■ Page write buffer
■ Industrial, automotive and
extended temperature ranges
DESCRIPTION
The CAT24WC164 is a16K-bit, cascadable Serial CMOS
EEPROM internally organized as 2048 words of 8 bits
each. Catalyst’s advanced CMOS technology substantially reduces device power requirements. The
CAT24WC164 features a 16-byte page write buffer. The
device operates via the I2C bus serial interface, has a
special write protection feature, and is available in 8-pin
DIP, 8-pin SOIC, 8-pin TSSOP and 8-lead MSOP.
PIN CONFIGURATION
BLOCK DIAGRAM
SOIC Package (J, W)
DIP Package (P, L)
A0
A1
A2
VSS
1
2
3
4
8
7
6
5
VCC
WP
SCL
SDA
A0
A1
A2
VSS
1
2
3
4
8
7
6
5
EXTERNAL LOAD
VCC
WP
SCL
SDA
VCC
VSS
5020 FHD F01
MSOP Package (R, Z)
A0
A1
A2
VSS
1
2
3
4
8
7
6
5
SCL
SDA
SDA
TSSOP Package (U, Y)
VCC
TEST
A0
A1
A2
VSS
1
2
3
4
8
7
6
5
SENSE AMPS
SHIFT REGISTERS
DOUT
ACK
VCC
WP
SCL
SDA WP
WORD ADDRESS
BUFFERS
COLUMN
DECODERS
START/STOP
LOGIC
XDEC
E2PROM
CONTROL
LOGIC
PIN FUNCTIONS
Pin Name
DATA IN STORAGE
Function
A0, A1, A2
Device Address Inputs
SDA
Serial Data/Address
SCL
Serial Clock
WP
Write Protect
VCC
+1.8V to +6.0V Power Supply
VSS
Ground
HIGH VOLTAGE/
TIMING CONTROL
SCL
A0
A1
A2
STATE COUNTERS
SLAVE
ADDRESS
COMPARATORS
* Catalyst Semiconductor is licensed by Philips Corporation to carry the I2C Bus Protocol.
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
1
Doc. No. 1026, Rev. I
CAT24WC164
ABSOLUTE MAXIMUM RATINGS*
*COMMENT
Temperature Under Bias ................. –55°C to +125°C
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
These are stress ratings only, and functional operation of
the device at these or any other conditions outside of those
listed in the operational sections of this specification is not
implied. Exposure to any absolute maximum rating for
extended periods may affect device performance and
reliability.
Storage Temperature ....................... –65°C to +150°C
Voltage on Any Pin with
Respect to Ground(1) ........... –2.0V to +VCC + 2.0V
VCC with Respect to Ground ............... –2.0V to +7.0V
Package Power Dissipation
Capability (Ta = 25°C) ................................... 1.0W
Lead Soldering Temperature (10 secs) ............ 300°C
Output Short Circuit Current(2) ........................ 100mA
RELIABILITY CHARACTERISTICS
Symbol
Parameter
Reference Test Method
Min
(3)
Endurance
MIL-STD-883, Test Method 1033
1,000,000
Cycles/Byte
Data Retention
MIL-STD-883, Test Method 1008
100
Years
ESD Susceptibility
MIL-STD-883, Test Method 3015
2000
Volts
JEDEC Standard 17
100
mA
NEND
TDR(3)
VZAP
(3)
ILTH(3)(4)
Latch-up
Typ
Max
Units
D.C. OPERATING CHARACTERISTICS
VCC = +1.8V to +6.0V, unless otherwise specified.
Symbol
Max
Units
fSCL = 100 kHz
3
mA
Standby Current (VCC = 5.0V)
VIN = GND or VCC
1
µA
ILI
Input Leakage Current
VIN = GND to VCC
10
µA
ILO
Output Leakage Current
VOUT = GND to VCC
10
µA
VIL
Input Low Voltage
–1
VCC x 0.3
V
VIH
Input High Voltage
VCC x 0.7
VCC + 0.5
V
ICC
ISB
(5)
Parameter
Power Supply Current
Test Conditions
Min
Typ
VOL1
Output Low Voltage (VCC = 3.0V)
IOL = 3 mA
0.4
V
VOL2
Output Low Voltage (VCC = 1.8V)
IOL = 1.5 mA
0.5
V
Max
Units
CAPACITANCE TA = 25°C, f = 1.0 MHz, VCC = 5V
Symbol
Parameter
Test Conditions
Min
Typ
CI/O(3)
Input/Output Capacitance (SDA)
VI/O = 0V
8
pF
CIN(3)
Input Capacitance
(A0, A1, A2, SCL, WP)
VIN = 0V
6
pF
Note:
(1) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC
voltage on output pins is VCC +0.5V, which may overshoot to VCC + 2.0V for periods of less than 20ns.
(2) Output shorted for no more than one second. No more than one output shorted at a time.
(3) This parameter is tested initially and after a design or process change that affects the parameter.
(4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to VCC +1V.
(5) Maximum standby current (ISB ) = 10µA for the Automotive and Extended Automotive temperature range.
Doc. No. 1026, Rev. I
2
CAT24WC164
A.C. CHARACTERISTICS
VCC = +1.8V to +6.0V, unless otherwise specified.
Read & Write Cycle Limits
Symbol
Parameter
1.8 V - 6.0 V
Min
Max
2.5 V - 6.0 V
Min
Max
Units
FSCL
Clock Frequency
100
400
kHz
TI(1)
Noise Suppression Time
Constant at SCL, SDA Inputs
200
200
ns
tAA
SCL Low to SDA Data Out
and ACK Out
3.5
1
µs
tBUF(1)
Time the Bus Must be Free Before
a New Transmission Can Start
tHD:STA
Start Condition Hold Time
tLOW
4.7
1.2
µs
4
0.6
µs
Clock Low Period
4.7
1.2
µs
tHIGH
Clock High Period
4
0.6
µs
tSU:STA
Start Condition Setup Time
(for a Repeated Start Condition)
4.7
0.6
µs
tHD:DAT
Data In Hold Time
0
0
ns
tSU:DAT
Data In Setup Time
50
50
ns
tR(1)
SDA and SCL Rise Time
1
0.3
µs
SDA and SCL Fall Time
300
300
ns
tF
(1)
tSU:STO
Stop Condition Setup Time
tDH
Data Out Hold Time
4
0.6
µs
100
100
ns
Power-Up Timing(1)(2)
Symbol
Parameter
Min
Typ
Max
Units
tPUR
Power-up to Read Operation
1
ms
tPUW
Power-up to Write Operation
1
ms
Max
Units
5
ms
Write Cycle Limits
Symbol
tWR
Parameter
Min
Typ
Write Cycle Time
interface circuits are disabled, SDA is allowed to remain
high, and the device does not respond to its slave
address.
The write cycle time is the time from a valid stop
condition of a write sequence to the end of the internal
program/erase cycle. During the write cycle, the bus
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated.
3
Doc. No. 1026, Rev. I
CAT24WC164
FUNCTIONAL DESCRIPTION
PIN DESCRIPTIONS
The CAT24WC164 supports the I 2 C Bus data
transmission protocol. This Inter-Integrated Circuit Bus
protocol defines any device that sends data to the bus to
be a transmitter and any device receiving data to be a
receiver. Data transfer is controlled by the Master device
which generates the serial clock and all START and
STOP conditions for bus access. The CAT24WC164
operates as a Slave device. Both the Master and Slave
devices can operate as either transmitter or receiver, but
the Master device controls which mode is activated. A
maximum of 8 devices may be connected to the bus as
determined by the device address inputs A0, A1, and A2.
SCL: Serial Clock
The CAT24WC164 serial clock input pin is used to clock
all data transfers into or out of the device. This is an input
pin.
SDA: Serial Data/Address
The CAT24WC164 bidirectional serial data/address pin
is used to transfer data into and out of the device. The
SDA pin is an open drain output and can be wire-ORed
with other open drain or open collector outputs.
A0, A1, A2: Device Address Inputs
These inputs set device address when cascading multiple
devices. When these pins are left floating the default
values are zeros.
A maximum of eight devices can be cascaded. If only
one CAT24WC164 is addressed on the bus, all three
Figure 1. Bus Timing
tF
tHIGH
tLOW
tR
tLOW
SCL
tSU:STA
tHD:DAT
tHD:STA
tSU:DAT
tSU:STO
SDA IN
tAA
tBUF
tDH
SDA OUT
Figure 2. Write Cycle Timing
SCL
SDA
8TH BIT
BYTE n
ACK
tWR
STOP
CONDITION
START
CONDITION
Figure 3. Start/Stop Timing
SDA
SCL
START BIT
Doc. No. 1026, Rev. I
STOP BIT
4
ADDRESS
CAT24WC164
address pins (A0, A1and A2) can be left floating or
connected to VSS.
DEVICE ADDRESSING
The bus Master begins a transmission by sending a
START condition. The Master then sends the address
of the particular slave device it is requesting. The most
significant bit of the 8-bit slave address is fixed as 1. (see
Fig. 5). The next three significant bits (A2, A1, A0) are
the device address bits and define which device or which
part of the device the Master is accessing (The A1 bit
must be the compliment of the A1 input pin signal). Up
to eight CAT24WC164 devices may be individually
addressed by the system. The next three bits are used
as the three most significant bits of the data word
address. The last bit of the slave address specifies
whether a Read or Write operation is to be performed.
When this bit is set to 1, a Read operation is selected,
and when set to 0, a Write operation is selected.
The CAT24WC164 can be made compatible with the
CAT24WC16 by tying A2, A1 and A0 to VSS or by
leaving A2, A1 and A0 float.
WP: Write Protect
If the WP pin is tied to VCC the entire memory array
becomes Write Protected (READ only). When the WP
pin is tied to VSS or left floating normal read/write
operations are allowed to the device.
I2C BUS PROTOCOL
The following defines the features of the I2C bus protocol:
(1) Data transfer may be initiated only when the bus is
not busy.
After the Master sends a START condition and the slave
address byte, the CAT24WC164 monitors the bus and
responds with an acknowledge (on the SDA line) when
its address matches the transmitted slave address. The
CAT24WC164 then performs a Read or Write operation
depending on the state of the R/W bit.
(2) During a data transfer, the data line must remain
stable whenever the clock line is high. Any changes
in the data line while the clock line is high will be
interpreted as a START or STOP condition.
START Condition
Acknowledge
The START Condition precedes all commands to the
device, and is defined as a HIGH to LOW transition of
SDA when SCL is HIGH. The CAT24WC164 monitor the
SDA and SCL lines and will not respond until this
condition is met.
After a successful data transfer, each receiving device is
required to generate an acknowledge. The Acknowledging device pulls down the SDA line during the ninth
clock cycle, signaling that it received the 8 bits of data.
The CAT24WC164 responds with an acknowledge after
receiving a START condition and its slave address. If the
device has been selected along with a write operation,
it responds with an acknowledge after receiving each 8bit byte.
STOP Condition
A LOW to HIGH transition of SDA when SCL is HIGH
determines the STOP condition. All operations must end
with a STOP condition.
Figure 4. Acknowledge Timing
SCL FROM
MASTER
1
8
9
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
ACKNOWLEDGE
START
5
Doc. No. 1026, Rev. I
CAT24WC164
When the CAT24WC164 is in a READ mode it transmits
8 bits of data, releases the SDA line, and monitors the
line for an acknowledge. Once it receives this
acknowledge, the CAT24WC164 will continue to transmit
data. If no acknowledge is sent by the Master, the device
terminates data transmission and waits for a STOP
condition.
address bits by one. The high order bits remain
unchanged.
If the Master transmits more than sixteen bytes prior to
sending the STOP condition, the address counter ‘wraps
around’, and previously transmitted data will be
overwritten.
Once all sixteen bytes are received and the STOP
condition has been sent by the Master, the internal
programming cycle begins. At this point all received data
is written to the CAT24WC164 in a single write cycle.
WRITE OPERATIONS
Byte Write
In the Byte Write mode, the Master device sends the
START condition and the slave address information
(with the R/W bit set to zero) to the Slave device. After
the Slave generates an acknowledge, the Master sends
the remainder of the byte address that is to be written into
the address pointer of the CAT24WC164. After receiving
another acknowledge from the Slave, the Master device
transmits the data byte to be written into the addressed
memory location. The CAT24WC164 acknowledge once
more and the Master generates the STOP condition, at
which time the device begins its internal programming
cycle to nonvolatile memory. While this internal cycle is
in progress, the device will not respond to any request
from the Master device.
Acknowledge Polling
The disabling of the inputs can be used to take advantage
of the typical write cycle time. Once the stop condition
is issued to indicate the end of the host’s write operation,
the CAT24WC164 initiates the internal write cycle. ACK
polling can be initiated immediately. This involves
issuing the start condition followed by the slave address
for a write operation. If the CAT24WC164 is still busy
with the write operation, no ACK will be returned. If the
CAT24WC164 has completed the write operation, an
ACK will be returned and the host can then proceed with
the next read or write operation.
Page Write
WRITE PROTECTION
The CAT24WC164 writes up to 16 bytes of data in a
single write cycle, using the Page Write operation. The
Page Write operation is initiated in the same manner as
the Byte Write operation, however instead of terminating
after the initial word is transmitted, the Master is allowed
to send up to fifteen additional bytes. After each byte has
been transmitted the CAT24WC164 will respond with an
acknowledge, and internally increment the low order
The Write Protection feature allows the user to protect
against inadvertent programming of the memory array.
If the WP pin is tied to VCC, the entire memory array is
protected and becomes read only. The CAT24WC164
will accept both slave and byte addresses, but the
memory location accessed is protected from
programming by the device’s failure to send an
acknowledge after the first byte of data is received.
Figure 5. Slave Address Bits
CAT24WC164
1
A2
A1
A0
a10
** a8, a9 and a10 correspond to the address of the memory array address word.
*** A0, A1 and A2 must compare to its corresponding hard wired input pins (pins 1, 2 and 3).
Doc. No. 1026, Rev. I
6
a9
a8
R/W
CAT24WC164
READ OPERATIONS
The READ operation for the CAT24WC164 is initiated in
the same manner as the write operation with the one
exception that the R/W bit is set to a one. Three different
READ operations are possible: Immediate Address
READ, Selective READ and Sequential READ.
and the slave address, this time with the R/W bit set to
one. The CAT24WC164 then responds with its
acknowledge and sends the 8-bit byte requested. The
master device does not send an acknowledge but will
generate a STOP condition.
Immediate Address Read
Sequential Read
The device address counter contains the address of the
last byte accessed, incremented by one. In other words,
if the last READ or WRITE access was to address N, the
READ immediately following would access data from
address N+1. If N=2047, then the counter will 'wrap
around' to addrss 0 and continue to clock out data.
The Sequential READ operation can be initiated by
either the immediate Address READ or Selective
READ operations. After the CAT24WC164 sends
initial 8-bit byte requested, the Master will respond
with an acknowledge which tells the device it requires
more data. The CAT24WC164 will continue to output
an 8-bit byte for each acknowledge sent by the Master.
The operation is terminated when the Master fails to
respond with an acknowledge, thus sending the STOP
condition.
After the CAT24WC164 receives its slave address
information (with the R/W bit set to one), it issues an
acknowledge, then transmits the 8-bit byte requested.
The master device does not send an acknowledge but
will generate a STOP condition.
The data being transmitted from the CAT24WC164 is
outputted sequentially with data from address N
followed by data from address N+1. The READ
operation address counter increments all of the
CAT24WC164 address bits so that the entire memory
array can be read during one operation. If more than
the 2047 bytes are read out, the counter will “wrap
around” and continue to clock out data bytes.
Selective Read
Selective READ operations allow the Master device to
select at random any memory location for a READ
operation. The Master device first performs a ‘dummy’
write operation by sending the START condition, slave
address and byte address of the location it wishes to
read. After the CAT24WC164 acknowledge the word
address, the Master device resends the START condition
Figure 6. Byte Write Timing
BUS ACTIVITY:
MASTER
SDA LINE
S
T
A
R
T
SLAVE
ADDRESS
BYTE
ADDRESS
S
T
O
P
DATA
S
P
A
C
K
A
C
K
A
C
K
Figure 7. Page Write Timing
BUS ACTIVITY:
MASTER
SDA LINE
S
T
A
R
T
SLAVE
ADDRESS
BYTE
ADDRESS (n)
DATA n
DATA n+1
S
T
O
P
DATA n+15
S
P
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
NOTE: IN THIS EXAMPLE n = XXXX 0000(B); X = 1 or 0
7
Doc. No. 1026, Rev. I
CAT24WC164
Figure 8. Immediate Address Read Timing
S
T
A
R
T
BUS ACTIVITY:
MASTER
SDA LINE
S
T
O
P
SLAVE
ADDRESS
S
P
A
C
K
DATA
N
O
A
C
K
SCL
8
SDA
9
8TH BIT
DATA OUT
NO ACK
STOP
Figure 9. Selective Read Timing
BUS ACTIVITY:
MASTER
SDA LINE
S
T
A
R
T
SLAVE
ADDRESS
S
T
A
R
T
BYTE
ADDRESS (n)
S
T
O
P
SLAVE
ADDRESS
P
S
S
A
C
K
A
C
K
A
C
K
DATA n
N
O
A
C
K
Figure 10. Sequential Read Timing
BUS ACTIVITY:
MASTER
SLAVE
ADDRESS
DATA n
DATA n+1
DATA n+2
S
T
O
P
DATA n+x
SDA LINE
P
A
C
K
A
C
K
A
C
K
A
C
K
N
O
A
C
K
Doc. No. 1026, Rev. I
8
CAT24WC164
ORDERING INFORMATION
Prefix
CAT
Optional
Company ID
Device #
Suffix
24WC164
Product Number
24WC164: 16K
J
I
-1.8
Temperature Range
I = Industrial (-40 to 85 C)
A = Automotive (-40 to 105 C)*
E = Extended (-40 to 125 C)
Package
P: PDIP
J: SOIC (JEDEC)
U: TSSOP
R: MSOP
L: PDIP (Lead free, Halogen free)
W: SOIC (Lead free, Halogen free)
Y: TSSOP (Lead free, Halogen free)
Z: MSOP (Lead free, Halogen free)
Rev F(2)
TE13
Tape & Reel
Die Revision
Operating Voltage
Blank: 2.5V - 6.0V
1.8: 1.8V - 6.0V
Notes:
(1) The device used in the above example is a CAT24WC164JI-1.8TE13 (SOIC, Industrial Temperature, 1.8 Volt to 6 Volt Operating Voltage,
Tape & Reel).
(2) Product die revision letter is marked on top of the package as a suffix to the production date code (e.g. AYWWF). For additional information, please contact your Catalyst sales office.
9
Doc. No. 1026, Rev. I
CAT24WC164
REVISION HISTORY
Date
Rev.
12/29/2003
F
Reason
Added 8-pin MSOP package to Features section
Deleted 2.5V - 6.0V from AC Characteristics
Changed 4.5V - 5.5V to 2.5V - 6.0V in AC Characteristics
Changed max to 5 in Write Cycle Limits (tWR)
Added overbar to A1 in Figure 5 (slave address bits)
7/23/2004
G
Added die revision to Ordering Information
8/3/2004
H
Update DC Operating Characteristics table & notes
03/10/2005
I
Update Ordering Information
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Corporate Headquarters
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Phone: 408.542.1000
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Doc. No. 1026, Rev. I
Publication #:
Revison:
Issue date:
10
1026
I
03/10/05
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