DATASHEET ICM7243 FN3162 Rev 5.00 October 2, 2015 8-Character, Microprocessor-Compatible, LED Display Decoder Driver The ICM7243 is an 8-character, alphanumeric display driver and controller which provides all the circuitry required to interface a microprocessor or digital system to a 14-segment or 16-segment display. It is primarily intended for use in microprocessor systems, where it minimizes hardware and software overhead. Incorporated on-chip are a 64-character ASClI decoder, 8x6 memory, high power character and segment drivers, and the multiplex scan circuitry. Features 6-bit ASCll data to be displayed is written into the memory directly from the microprocessor data bus. Data location depends upon the selection of either Sequential (MODE = 1) or Random access mode (MODE = 0). In the Sequential Access mode the first entry is stored in the lowest location and displayed in the “left-most” character position. Each subsequent entry is automatically stored in the next higher location and displayed to the immediate “right” of the previous entry. A DISPlay FULL signal is provided after 8 entries; this signal can be used for cascading devices together. A CLeaR pin is provided to clear the memory and reset the location counter. The Random Access mode allows the processor to select the memory address and display digit for each input word. • Cascadable Without Additional Hardware • 14-Segment and 16-Segment Fonts with Decimal Point • Mask Programmable for Other Font-Sets Up to 64 Characters • Microprocessor Compatible • Directly Drives LED Common Cathode Displays • Standby Feature Turns Display Off; Puts Chip in Low Power Mode • Sequential Entry or Random Entry of Data Into Display • Single +5V Operation • Character and Segment Drivers, All MUX Scan Circuitry, 8x6 Static Memory and 64-Character ASCll Font Generator Included On-Chip • Pb-Free Available (RoHS Compliant) The character multiplex scan runs whenever data is not being entered. It scans the memory and CHARacter drivers, and ensures that the decoding from memory to display is done in the proper sequence. Intercharacter blanking is provided to avoid display ghosting Ordering Information PART NUMBER PART MARKING TEMP. RANGE (°C) PACKAGE (Pb-Free) PKG. DWG. # ICM7243BlPL** (No longer available or supported) ICM7243BlPL -25 to +85 40 Ld PDIP E40.6 ICM7243BlPLZ ** (Note) ICM7243BlPLZ -25 to +85 40 Ld PDIP E40.6 ICM7243AIM44Z* (Note) (No longer available, recommended replacement: ICM7244AIM44Z, ICM7244AIM44ZT) ICM7243 AIM44Z -25 to +85 44 Ld MQFP Q44.10x10 ICM7243AIPLZ** (Note) (No longer available or supported) ICM7243AIPLZ -20 to +85 40 Ld PDIP E40.6 *Add “-T” suffix for tape and reel. Please refer to TB347 for details on reel specifications. **Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications. NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020 FN3162 Rev 5.00 October 2, 2015 Page 1 of 17 ICM7243 Pinouts ICM7243A (16-SEGMENT CHARACTER) (40 Ld PDIP) TOP VIEW FN3162 Rev 5.00 October 2, 2015 VDD 1 40 SEG l SEG m 2 39 SEG g2 SEG e 3 38 SEG b SEG g1 4 37 SEG i SEG k 5 36 SEG f SEG c 6 35 SEG d2 SEG d1 7 34 D.P. SEG a1 8 33 SEG h SEG a2 9 32 SEG j D0 10 31 MODE D1 11 30 A0/SEN D2 12 29 A1/CLR D3 13 28 A2/DISP FULL D4 14 27 OSC/OFF D5 15 26 CHAR 1 CS 16 25 CHAR 2 WR 17 24 CHAR 3 CHAR 8 18 23 CHAR 4 CHAR 7 19 22 VSS CHAR 6 20 21 CHAR 5 Page 2 of 17 ICM7243 Pinouts (Continued) ICM7243B (14-SEGMENT CHARACTER) (40 Ld PDIP) TOP VIEW VDD 1 40 SEG m SEG e 2 39 SEG l SEG g1 3 38 SEG g2 SEG k 4 37 SEG b SEG c 5 36 SEG i SEG d 6 35 SEG f SEG a 7 34 D.P. D0 8 33 SEG h D1 9 32 SEG j D2 10 31 MODE D3 11 30 A0/SEN D4 12 29 A1/CLR D5 13 28 A2/DISP FULL CS 14 27 OSC/OFF CS 15 26 CHAR 1 CS 16 25 CHAR 2 WR 17 24 CHAR 3 CHAR 8 18 23 CHAR 4 CHAR 7 19 22 VSS CHAR 6 20 21 CHAR 5 SEG f SEG i SEG b SEG g2 SEG l VDD SEG m SEG e SEG g1 SEG a1 44 43 42 41 40 39 38 37 36 35 34 33 2 32 SEG a2 3 D0 4 D1 5 D2 6 D3 7 D4 8 D5 9 CS 10 O R GE N LO LA AI V A E BL OR SU PP D TE31 R O DP SEG h SEG j 29 MODE 28 A0/SEN 27 A1/CLR 26 A2/DISP FULL 25 OSC/OFF 24 CHAR1 NC NC CHAR2 CHAR3 VSS CHAR4 CHAR5 CHAR6 CHAR7 CHAR8 SEG d2 30 11N 23 12 13 14 15 16 17 18 19 20 21 22 NC NC 1 WR SEG d1 FN3162 Rev 5.00 October 2, 2015 SEG k SEG c ICM7243A (16-SEGMENT CHARACTER) (44 Ld MQFP) TOP VIEW Page 3 of 17 ICM7243 Functional Block Diagram DATA INPUT D0 - D5 DATA D LATCHES Q CL 8x6 6 DATA D0 MEMORY CLR CL ADR D1 ONE SHOT WR (Note) CS CS CS 64 x 17 ROM (NOTE 1) CL D ADDRESS LATCHES MUX CL D Q CONTROL LATCH A0/SEN A1/CLR 8 D SEL A2/DISP FULL SEGMENT DRIVERS SEGMENT OUTPUTS SEG x 8 CL MODE 17 (Note) 3 8 CHARACTER CHARACTER DRIVERS CHAR N CHARACTER OUTPUTS SEL CL EN SEQUENTIAL SEQUENTIAL ADDRESS 3 COUNTER CLR ADDRESS MULITPLEXER MULTIPLEXER AND DECODER OVERFLOW 3 OSC/OFF OSCILLATOR MULTIPLEX OSCILLATOR CHARACTER MULTIPLEX COUNTER INTER-CHARACTER BLANKING NOTE: ICM7243A has only one CS and no CS. ICM7243B has 15 Segments. FN3162 Rev 5.00 October 2, 2015 Page 4 of 17 ICM7243 Absolute Maximum Ratings Thermal Information Supply Voltage VDD - VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . +6.0V Input Voltage (Any Terminal) . . . . . . . . . . VDD + 0.3V to VSS - 0.3V CHARacter Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . 300mA SEGment Output Current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30mA Thermal Resistance (Typical, Note 1) qJA (°C/W) qJC (°C/W) PDIP Package . . . . . . . . . . . . . . . . . . . 50 N/A MQFP Package . . . . . . . . . . . . . . . . . . 70 N/A Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +150°C Maximum Storage Temperature Range . . . . . . . . . .-65°C to +150°C Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp *Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications. Operating Conditions Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . .-25°C to +85°C CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES: 1. JA is measured with the component mounted on an evaluation PC board in free air. Electrical Specifications VDD = 5V, VSS = 0V, TA = +25°C, Unless Otherwise Specified. PARAMETER TEST CONDITIONS MIN TYP MAX UNITS 4.75 5.0 5.25 V DC CHARACTERISTICS Supply Voltage (VDD - VSS), VSUPP Operating Supply Current, IDD VSUPP = 5.25V, 10 Segments ON, All 8 Characters - 180 - mA Quiescent Supply Current, ISTBY VSUPP = 5.25V, OSC/OFF Pin < 0.5V, CS = VSS - 30 250 µA Input High Voltage, VIH 2 - - V Input Low Voltage, VIL - - 0.8 V -10 - +10 µA 140 190 - mA - - 100 µA 14 19 - mA - 0.01 10 µA Input Current, IIN CHARacter Drive Current, ICHAR VSUPP = 5V, VOUT = 1V CHARacter Leakage Current, ICHLK SEGment Drive Current, ISEG VSUPP = 5V, VOUT = 2.5V SEGment Leakage Current, ISLK DISPlay FULL Output Low, VOL IOL = 1.6mA - - 0.4 V DISPlay FULL Output High, VOH lIH = 100µA 2.4 - - V - 400 - Hz Display Scan Rate, fDS Electrical Specifications Drive levels 0.4V and 2.4V, timing measured at 0.8V and 2.0V. VDD = 5V, TA = +25°C, Unless Otherwise Specified. PARAMETER TEST CONDITIONS MIN TYP MAX UNITS 300 250 - ns WR, CLeaR Pulse Width High (Note 1), tWPH - 250 - ns Data Hold Time, tDH 0 -100 - ns Data Setup Time, tDS 250 150 - ns Address Hold Time, tAH 125 - - ns Address Setup Time, tAS 40 15 - ns CS, CS Setup Time, tCS 0 - - ns AC CHARACTERISTICS WR, CLeaR Pulse Width Low, tWPI Pulse Transition Time, tT - - 100 ns SEN Setup Time, tSEN 0 -25 - ns 700 480 - ns Display Full Delay, tWDF FN3162 Rev 5.00 October 2, 2015 Page 5 of 17 ICM7243 Capacitance PARAMETER TEST CONDITIONS MIN TYP MAX UNITS Input Capacitance, ClN (Note 3) - 5 - pF Output Capacitance, CO (Note 3) - 5 - pF NOTES: 2. In Sequential mode WR high must be tSEN +tWDF . 3. For design reference only, not tested. Timing Waveforms CS tCS CS tAS ADDRESS tAH VALID tWPI tWC tWHP WRITE tDS tT DATA tT tDH VALID FIGURE 1. RANDOM ACCESS TIMING WR CHAR 1 CHAR 2 CHAR 8 tSEN tWPH CLEAR SEN tWDF DISPLAY FULL FIGURE 2. SEQUENTIAL ACCESS MODE TIMING (MODE = 1) FN3162 Rev 5.00 October 2, 2015 Page 6 of 17 ICM7243 Timing Waveforms (Continued) ~300µs ~5µs INTERNAL INTER-CHARACTER BLANKING SIGNAL CHAR 1 CHAR 2 CHAR 3 CHARACTERS DRIVE SIGNALS CHAR 4 CHAR 5 INTER-CHARACTER BLANKING CHAR 6 CHAR 7 CHAR 8 FIGURE 3. DISPLAY CHARACTERS MULTIPLEX TIMING DIAGRAM Performance Curves 30 500 VDD = 5.5V VDD = 5.5V 20 ICHAR (mA) ISEG (mA) 400 5.0V 10 300 5.0V 200 4.5V 4.5V 100 0 0 1 2 3 SEGMENT VOLTAGE (V) FIGURE 4. SEGMENT CURRENT vs OUTPUT VOLTAGE FN3162 Rev 5.00 October 2, 2015 0 1 2 3 SEGMENT VOLTAGE (V) FIGURE 5. CHARACTER CURRENT vs OUPUT VOLTAGE Page 7 of 17 ICM7243 Pin Descriptions PIN NUMBER SYMBOL ICM7243B ICM7243A 40 Ld PDIP 40 Ld PDIP 44 Ld MQFP DESCRIPTION VDD 1 1 39 D0 to D5 8 to 13 10 to 15 4 to 9 Six-Bit ASCll Data input pins (active high). CS, CS 15, 16 16 10 Chip Select from µP address decoder, etc. WR 17 17 13 WRite pulse input pin (active low). For an active high write pulse, CS can be used, and WR can be used as CS. MODE 31 31 29 Selects data entry MODE. High selects Sequential Access (SA) mode where first entry is displayed in “leftmost” character and subsequent entries appear to the “right”. Low selects the Random Access (RA) mode where data is displayed on the character addressed via A0 - A2 Address pins. A0/SEN 30 30 28 In RA mode it is the LSB of the character Address. In SA mode it is used for cascading devices for displays of more than 8 characters (active high enables device controller). A1/CLeaR 29 29 27 In RA mode this is the second bit of the address. In SA mode, a low input will CLeaR the Serial Address Counter, the Data Memory and the display. A2/DISPlay FULL 28 28 26 In RA mode this is the MSB of the Address. In SA mode, the output goes high after eight entries, indicating DISPlay FULL. OSC/OFF 27 27 25 OSCillator input pin. Adding capacitance to VDD will lower the internal oscillator frequency. An external oscillator can be applied to this pin. A low at this input sets the device into a (shutdown) mode, shutting OFF the display and oscillator but retaining data stored in memory. SEGa SEGm 2 to 7, 32, 33, 35 to 40 2 to 9, 32, 33, 35 to 40 D.P. 34 34 CHARacter 1 to 8 23 to 26, 18 to 21 23 to 26, 18 to 21 VSS 22 22 18 NC N/A N/A 22, 23, 11 FN3162 Rev 5.00 October 2, 2015 - 1 to 3, 30, 31, 33 to 40, SEGment driver outputs. 38 to 44 32 24, 19 to 21, CHARacter driver outputs. 14 to 17 No Connect Page 8 of 17 ICM7243 Test Circuit 17 SEGMENTS CHAR 8 CHAR 7 CHAR 6 CHAR 5 CHAR 4 CHAR 3 CHAR 2 CHAR 1 VDD SEG m SEG e SEG g1 SEG k SEGMENTS SEG c SEG d1 SEG a1 SEG a2 D0 VDD D1 D2 D3 D4 D5 CS WR CHAR 8 CHAR 7 CHAR 6 1 40 2 39 3 38 4 37 5 36 6 35 7 34 8 33 9 32 10 ICM7243A 31 11 30 12 29 13 28 14 27 15 26 16 25 17 24 18 23 19 22 20 21 SEG l SEG g2 SEG b 8 CHARACTERS SEG i SEG f SEGMENTS SEG d2 DP SEG h SEG j MODE (SA/RA) A0/SEN VDD A1/CLR A2/DISP FULL OSC/OFF CHAR 1 CHAR 2 DISPLAY FULL OUTPUT VDD NC (FOR SA MODE) CHAR 3 CHAR 4 VSS CHAR 5 FIGURE 6. FN3162 Rev 5.00 October 2, 2015 Page 9 of 17 ICM7243 Typical Applications 8 CHARACTERS +5V CHAR RRI RBR8 CLR RBR7 CS CHAR CS ICM7243B SEN UART CS,WR RBR1 - RBR6 SEG DISP ICM7243B DISP SEN FULL FULL ETC. CS,WR D0 - D5 CS D0 - D5 CS D0 - D5 CS D0 - D5 CS 6 BIT BUS DR +5V +5V +5V 20K OUT SEG CLR IM6403 DRR 8 CHARACTERS V+ WR SEN SEN ICM7243B TR CS ICL7555 ICM7243B CS DISP ETC. FULL CLR CHAR TH DISP FULL CLR DELAY WR CS CS SEG CHAR SEG 200pF 8 CHARACTERS 8 CHARACTERS FIGURE 7. DRIVING TWO ROWS OF CHARACTERS FROM A SERIAL INPUT FN3162 Rev 5.00 October 2, 2015 Page 10 of 17 ICM7243 Typical Applications (Continued) 8-CHARACTER LED DISPLAY 8 CLR CLR 8-CHARACTER LED DISPLAY 8 (Note) CLR CHAR SEN +5V MODE DATA BUS +5V +5V VDD VSS CS 6 CLR 6 SEN MODE WR D0 - D5 SEG DISP FULL CS (Note) CHAR SEG DISP FULL WR D0 - D5 8 (Note) CHAR SEG +5V 8-CHARACTER LED DISPLAY SEN MODE WR D0 - D5 +5V +5V VDD VSS DISP FULL VDD VSS CS +5V 6 WR, (CS) CS, (WR) FIRST 8 CHARACTERS SECOND 8 CHARACTERS NTH 8 CHARACTERS NOTE: 17 for ICM7243A, 15 for ICM7243B. FIGURE 8. MULTICHARACTER DISPLAY USING SEQUENTIAL ACCESS MODE +5V +5V +5V +5V +5V 1k 1.4APEAK 2N6034 100 100 1mA SEG 2N2219 SEG 300 14 (100mAPEAK) ICM7243 1k ICM7243 25 R ON = 4 (100mAPEAK) CHAR R ON = 4 CHAR 14mA 2N2219 2N6034 1k 1.4APEAK GND GND GND FIGURE 9A. COMMON CATHODE DISPLAY GND GND FIGURE 9B. COMMON ANODE DISPLAY FIGURE 9. DRIVING LARGE DISPLAYS FN3162 Rev 5.00 October 2, 2015 Page 11 of 17 ICM7243 Typical Applications (Continued) 8 CHARACTERS 8 CHARACTERS 8 CHARACTERS 8 CHARACTERS ICM7243A/B ICM7243A/B ICM7243A/B ICM7243A/B CS A2 A1 A0 D0 - D5 WR CS A2 A1 A0 D0 - D5 WR CS A2 A1 A0 D0 - D5 WR CS A2 A1 A0 D0 - D5 WR P22 P21 P20 80C35 80C48 DB7 DB6 6 BIT BUS DB5 - DB0 WR FIGURE 10. RANDOM ACCESS 32-CHARACTER DISPLAY IN A 80C48 SYSTEM Display Font and Segment Assignments a1 f h a2 i g1 e m g2 l d2 D5, D4 0 0 0 1 1 0 1 1 b j k c d1 DP D3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 D2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 D1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 D0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 FIGURE 11. ICM7243A 16-SEGMENT CHARACTER FONT WITH DECIMAL POINT FN3162 Rev 5.00 October 2, 2015 Page 12 of 17 ICM7243 Display Font and Segment Assignments f (Continued) a1 a a2 h i j g1 e D5, D4 0 0 0 1 1 0 1 1 b g2 m l k c d2 d d1 DP D3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 D2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 D1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 D0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 NOTE: Segments a and d appear as 2 segments each, but both halves are driven together. FIGURE 12. ICM7243B 14-SEGMENT CHARACTER FONT WITH DECIMAL POINT VDD SEGMENT DRIVER VLED = 1.6V RTYPICAL = 100µ R SEG x DISPLAY CHARACTER DRIVER CHAR N RDS(ON) ~ 4Þ SEGMENT LEDs VSS FIGURE 13. SEGMENT AND CHARACTER DRIVERS OUTPUT CIRCUIT FN3162 Rev 5.00 October 2, 2015 Page 13 of 17 ICM7243 Detailed Description WR, CS, CS These pins are immediately functionally ANDed, so all actions described as occurring on an edge of WR, with CS and CS enabled, will occur on the equivalent (last) enabling or (first) disabling edge of any of these inputs. The delays from CS pins are slightly (about 5ns) greater than from WR or CS due to the additional inverter required on the former. MODE The MODE pin input is latched on the falling edge of WR (or its equivalent, see above). The location (in Data Memory) where incoming data will be placed is determined either from the Address pins or the Sequential Address Counter. This is controlled by MODE input. MODE also controls the function of A0/SEN, A1/CLR, and A2/DlSPlay FULL lines. Random Access Mode When the internal mode latch is set for Random Access (RA) (MODE latched low), the Address input on A0, A1 and A2 will be latched by the falling edge of WR (or its equivalent). Subsequent changes on the Address lines will not affect device operation. This allows use of a multiplexed 6-bit bus controlling both address and data, with timing controlled by WR. Sequential Access Mode If the internal latch is set for Sequential Access (SA), (MODE latched high), the Serial ENable input or SEN will be latched on the falling edge of WR (or its equivalent). The CLR input is asynchronous, and will force-clear the Sequential Address Counter to address 000 (CHARacter 1), and set all Data Memory contents to 100000 (blank) at any time. The DISPlay FULL output will be active in SA mode to indicate the overflow status of the Sequential Address Counter. If this output is low, and SEN is (latched) high, the contents of the Counter will be used to establish the Data Memory location for the Data input. The Counter is then incremented on the rising edge of WR. If SEN is low, or DISPlay FULL is high, no action will occur. This allows easy “daisy-chaining” of display drivers for multiple character displays in a Sequential Access mode. Changing Modes Care must be exercised in any application involving changing from one mode to another. The change will occur only on a falling edge of WR (or its equivalent). When changing mode from Sequential Access to Random Access, note that A2/DlSPlay FULL will be an output until WR has fallen low, and an Address drive here could cause a conflict. When changing from Random Access to Sequential Access, A1/CLR should be high to avoid inadvertent clearing of the Data Memory and Sequential Address Counter. DISPlay FULL will become active immediately after the rising edge of WR. FN3162 Rev 5.00 October 2, 2015 Data Entry The input Data is latched on the rising edge of WR (or its equivalent) and then stored in the Data Memory location determined as described above. The six Data bits can be multiplexed with the Address information on the same lines in Random Access mode. Timing is controlled by the WR input. OSC/OFF The device includes a relaxation oscillator with an internal capacitor and a nominal frequency of 200kHz. By adding external capacitance to VDD at the OSC/OFF pin, this frequency can be reduced as far as desired. Alternatively, an external signal can be injected on this pin. The oscillator (or external) frequency is pre-divided by 64, and then further divided by 8 in the Multiplex Counter, to drive the CHARacter drive lines (see Figure 3). An inter-character blanking signal is derived from the pre-divider. An additional comparator on the OSC/OFF input detects a level lower than the relaxation oscillator's range, and blanks the display, disables the DISPlay FULL output (if active), and clears the pre-divider and Multiplex Counter. This puts the circuit in a low-power-dissipation mode in which all outputs are effectively open circuits, except for parasitic diodes to the supply lines. Thus a display connected to the output may be driven by another circuit (including another ICM7243) without driver conflicts. Display Output The output of the Multiplex Counter is decoded and multiplexed into the address input of the Data Memory, except during WR operations (in Sequential Access mode, with SEN high and DISPlay FULL low), when it scans through the display data. The address decoder also drives the CHARacter outputs, except during the inter-character blanking interval (nominally about 5s). Each CHARacter output lasts nominally about 300s, and is repeated nominally every 2.5ms, i.e., at a 400Hz rate (times are based on internal oscillator without external capacitor). The 6 bits read from the Data Memory are decoded in the ROM to the 17 (15 for ICM7243B) segment signals, which drive the SEGment outputs. Both CHARacter and SEGment outputs are disabled during WR operations (with SEN high and DISPlay FULL Low for Sequential Access mode). The outputs may also be disabled by pulling OSC/OFF low. The decode pattern from 6 bits to 17 (15) segments is done by a ROM pattern according to the ASCll font shown. Custom decode patterns can be arranged, within these limitations, by consultation with the factory. Page 14 of 17 ICM7243 Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make sure that you have the latest revision. DATE REVISION October 2, 2015 FN3162.5 CHANGE Updated Ordering Information Table on page 1. Added Revision History and About Intersil sections. About Intersil Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets. For the most updated datasheet, application notes, related documentation and related parts, please see the respective product information page found at www.intersil.com. You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask. Reliability reports are also available from our website at www.intersil.com/support FN3162 Rev 5.00 October 2, 2015 Page 15 of 17 ICM7243 Dual-In-Line Plastic Packages (PDIP) E40.6 (JEDEC MS-011-AC ISSUE B) N 40 LEAD DUAL-IN-LINE PLASTIC PACKAGE E1 INDEX AREA 1 2 3 INCHES N/2 SYMBOL -B- -C- SEATING PLANE A2 e B1 D1 B 0.010 (0.25) M A1 eC C A B S MAX NOTES - 0.250 - 6.35 4 0.015 - 0.39 - 4 A2 0.125 0.195 3.18 4.95 - B 0.014 0.022 0.356 0.558 - C L B1 0.030 0.070 0.77 1.77 8 eA C 0.008 0.015 0.204 0.381 - A L D1 MIN A E BASE PLANE MAX A1 -AD MILLIMETERS MIN C eB NOTES: 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication No. 95. 4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3. 5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. E and eA are measured with the leads constrained to be perpendicular to datum -C- . D 1.980 2.095 D1 0.005 - 50.3 0.13 53.2 5 - 5 E 0.600 0.625 15.24 15.87 6 E1 0.485 0.580 12.32 14.73 5 e 0.100 BSC 2.54 BSC - eA 0.600 BSC 15.24 BSC 6 eB - 0.700 - 17.78 7 L 0.115 0.200 2.93 5.08 4 N 40 40 9 Rev. 0 12/93 7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. 10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm). FN3162 Rev 5.00 October 2, 2015 Page 16 of 17 ICM7243 Metric Plastic Quad Flatpack Packages (MQFP) D Q44.10x10 (JEDEC MS-022AB ISSUE B) 44 LEAD METRIC PLASTIC QUAD FLATPACK PACKAGE D1 -D- INCHES -A- -B- E E1 e PIN 1 -H- A SEATING PLANE MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A - 0.096 - 2.45 - A1 0.004 0.010 0.10 0.25 - A2 0.077 0.083 1.95 2.10 - b 0.012 0.018 0.30 0.45 6 b1 0.012 0.016 0.30 0.40 - D 0.515 0.524 13.08 13.32 3 D1 0.389 0.399 9.88 10.12 4, 5 E 0.516 0.523 13.10 13.30 3 E1 0.390 0.398 9.90 10.10 4, 5 L 0.029 0.040 0.73 1.03 N 44 44 e 0.032 BSC 0.80 BSC 7 Rev. 2 4/99 NOTES: 0.076 0.003 -C- 12o-16o 0.40 0.016 MIN 0.20 M 0.008 C A-B S 0o MIN D S b A2 A1 0o-7o L 12o-16o b1 2. All dimensions and tolerances per ANSI Y14.5M-1982. 3. Dimensions D and E to be determined at seating plane -C- . 4. Dimensions D1 and E1 to be determined at datum plane -H- . 5. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25mm (0.010 inch) per side. 0.13/0.17 0.005/0.007 6. Dimension b does not include dambar protrusion. Allowable dambar protrusion shall be 0.08mm (0.003 inch) total. BASE METAL WITH PLATING 1. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. 7. “N” is the number of terminal positions. 0.13/0.23 0.005/0.009 © Copyright Intersil Americas LLC 2003-2015. All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. For additional products, see www.intersil.com/en/products.html Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN3162 Rev 5.00 October 2, 2015 Page 17 of 17