ADC082S101 2 Channel, 1 MSPS, 8-Bit A/D Converter General Description Features The ADC082S101 is a low-power, two-channel CMOS 8-bit analog-to-digital converter with a high-speed serial interface. Unlike the conventional practice of specifying performance at a single sample rate only, the ADC082S101 is fully specified over a sample rate range of 500 kSPS to 1 MSPS. The converter is based on a successive-approximation register architecture with an internal track-and-hold circuit. It can be configured to accept one or two input signals at inputs IN1 and IN2. The output serial data is straight binary, and is compatible with several standards, such as SPI™, QSPI™, MICROWIRE, and many common DSP serial interfaces. n n n n The ADC082S101 operates with a single supply that can range from +2.7V to +5.25V. Normal power consumption using a +3V or +5V supply is 3.2 mW and 9.6 mW, respectively. The power-down feature reduces the power consumption to just 0.12 µW using a +3V supply, or 0.35 µW using a +5V supply. The ADC082S101 is packaged in an 8-lead MSOP package. Operation over the industrial temperature range of −40˚C to +85˚C is guaranteed. Specified over a range of sample rates. Two input channels Variable power management Single power supply with 2.7V - 5.25V range Key Specifications n n n n ± 0.10 LSB (typ) ± 0.13 LSB (typ) DNL INL SNR Power Consumption — 3V Supply — 5V Supply 49.6 dB (typ) 3.2 mW (typ) 9.6 mW (typ) Applications n Portable Systems n Remote Data Aquisitions n Instrumentation and Control Systems Pin-Compatible Alternatives by Resolution and Speed All devices are fully pin and function compatible. Resolution Specified for Sample Rate Range of: 50 to 200 kSPS 200 to 500 kSPS 500 kSPS to 1 MSPS 12-bit ADC122S021 ADC122S051 ADC122S101 10-bit ADC102S021 ADC102S051 ADC102S101 8-bit ADC082S021 ADC082S051 ADC082S101 Connection Diagram 20125405 Ordering Information Order Code Temperature Range Description Top Mark ADC082S101CIMM −40˚C to +85˚C 8-Lead MSOP Package X22C ADC082S101CIMMX −40˚C to +85˚C 8-Lead MSOP Package, Tape & Reel X22C ADC082S101EVAL Evaluation Board TRI-STATE ® is a trademark of National Semiconductor Corporation QSPI™ and SPI™ are trademarks of Motorola, Inc. © 2005 National Semiconductor Corporation DS201254 www.national.com ADC082S101 2 Channel, 1 MSPS, 8-Bit A/D Converter April 2005 ADC082S101 Block Diagram 20125407 Pin Descriptions and Equivalent Circuits Pin No. Symbol Description ANALOG I/O 5,4 IN1 and IN2 Analog inputs. These signals can range from 0V to VA. DIGITAL I/O 8 SCLK Digital clock input. This clock directly controls the conversion and readout processes. 7 DOUT Digital data output. The output samples are clocked out of this pin on falling edges of the SCLK pin. 6 DIN Digital data input. The ADC082S101’s Control Register is loaded through this pin on rising edges of the SCLK pin. 1 CS Chip select. On the falling edge of CS, a conversion process begins. Conversions continue as long as CS is held low. 2 VA Positive supply pin. This pin should be connected to a quiet +2.7V to +5.25V source and bypassed to GND with a 1 µF capacitor and a 0.1 µF monolithic capacitor located within 1 cm of the power pin. 3 GND POWER SUPPLY www.national.com The ground return for the analog supply and signals. 2 Operating Ratings (Notes 1, 2) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Operating Temperature Range −40˚C ≤ TA ≤ +85˚C VA Supply Voltage +2.7V to +5.25V Digital Input Pins Voltage Range −0.3V to 6.5V Analog Supply Voltage VA Voltage on Any Pin to GND Clock Frequency −0.3V to VA +0.3V Analog Input Voltage ± 10 mA ± 20 mA Input Current at Any Pin (Note 3) Package Input Current (Note 3) Power Consumption at TA = 25˚C 2500V 250V Junction Temperature +150˚C Storage Temperature −65˚C to +150˚C 0V to VA Package Thermal Resistance See (Note 4) ESD Susceptibility (Note 5) Human Body Model Machine Model −0.3V to VA 0.8 MHz to 16 MHz Package θJA 8-lead MSOP 250˚C / W Soldering process must comply with National Semiconductor’s Reflow Temperature Profile specifications. Refer to www.national.com/packaging.(Note 6) ADC082S101 Converter Electrical Characteristics (Note 9) The following specifications apply for VA = +2.7V to 5.25V, GND = 0V, fSCLK = 8 MHz to 16 MHz, fSAMPLE = 500 kSPS to 1 MSPS, CL = 50 pF, unless otherwise noted. Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25˚C. Symbol Parameter Conditions Typical Limits (Note 7) Units 8 Bits LSB (max) STATIC CONVERTER CHARACTERISTICS Resolution with No Missing Codes INL Integral Non-Linearity DNL Differential Non-Linearity ± 0.13 ± 0.10 VOFF Offset Error +0.53 OEM Channel to Channel Offset Error Match 0.005 FSE Full-Scale Error 0.52 ± 0.4 ± 0.4 ± 0.7 ± 0.3 ± 0.7 FSEM Channel to Channel Full-Scale Error Match 0.005 ± 0.3 LSB (max) LSB (max) LSB (max) LSB (max) LSB (max) DYNAMIC CONVERTER CHARACTERISTICS SINAD Signal-to-Noise Plus Distortion Ratio VA = +2.7V to 5.25V fIN = 40.3 kHz, −0.02 dBFS 49.6 49.1 dB (min) SNR Signal-to-Noise Ratio VA = +2.7V to 5.25V fIN = 40.3 kHz, −0.02 dBFS 49.6 49.2 dB (min) THD Total Harmonic Distortion VA = +2.7V to 5.25V fIN = 40.3 kHz, −0.02 dBFS −75 −62 dB (max) SFDR Spurious-Free Dynamic Range VA = +2.7V to 5.25V fIN = 40.3 kHz, −0.02 dBFS 67 63 dB (min) ENOB Effective Number of Bits VA = +2.7V to 5.25V fIN = 40.3 kHz, −0.02 dBFS 7.9 7.9 Bits (min) Channel-to-Channel Crosstalk VA = +5.25V fIN = 40.3 kHz −73 dB Intermodulation Distortion, Second Order Terms VA = +5.25V fa = 40.161 kHz, fb = 41.015 kHz −78 dB Intermodulation Distortion, Third Order Terms VA = +5.25V fa = 40.161 kHz, fb = 41.015 kHz −73 dB VA = +5V 11 MHz VA = +3V 8 MHz IMD FPBW -3 dB Full Power Bandwidth 3 www.national.com ADC082S101 Absolute Maximum Ratings (Notes 1, 2) ADC082S101 ADC082S101 Converter Electrical Characteristics (Note 9) (Continued) The following specifications apply for VA = +2.7V to 5.25V, GND = 0V, fSCLK = 8 MHz to 16 MHz, fSAMPLE = 500 kSPS to 1 MSPS, CL = 50 pF, unless otherwise noted. Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25˚C. Symbol Parameter Conditions Typical Limits (Note 7) Units ±1 µA (max) ANALOG INPUT CHARACTERISTICS VIN Input Range IDCL DC Leakage Current CINA Input Capacitance 0 to VA V Track Mode 33 pF Hold Mode 3 pF DIGITAL INPUT CHARACTERISTICS VIH Input High Voltage VIL Input Low Voltage IIN Input Current CIND Digital Input Capacitance VA = +5.25V 2.4 V (min) VA = +3.6V 2.1 V (min) 0.8 V (max) VIN = 0V or VA ± 10 µA (max) 2 4 pF (max) VA − 0.5 V (min) DIGITAL OUTPUT CHARACTERISTICS VOH Output High Voltage VOL Output Low Voltage IOZH, IOZL TRI-STATE ® Leakage Current COUT TRI-STATE ® Output Capacitance ISOURCE = 200 µA VA − 0.03 ISOURCE = 1mA VA − 0.1 ISINK = 200 µA 0.03 ISINK = 1 mA 0.1 V 0.4 V (max) V ± 0.01 ±1 µA (max) 2 4 pF (max) Output Coding Straight (Natural) Binary POWER SUPPLY CHARACTERISTICS (CL = 10 pF) VA Supply Voltage Supply Current, Normal Mode (Operational, CS low) IA Supply Current, Shutdown (CS high) PD 2.7 V (min) 5.25 V (max) VA = +5.25V, fSAMPLE = 1 MSPS, fIN = 40 kHz 1.82 2.4 mA (max) VA = +3.6V, fSAMPLE = 1 MSPS, fIN = 40 kHz 0.9 1.2 mA (max) VA = +5.25V, fSAMPLE = 0 kSPS 200 nA VA = +3.6V, fSAMPLE = 0 kSPS 200 nA Power Consumption, Normal Mode (Operational, CS low) VA = +5.25V 9.6 12.6 mW (max) VA = +3.6V 3.2 4.3 mW (max) Power Consumption, Shutdown (CS high) VA = +5.25V 0.35 µW VA = +3.6V 0.12 µW AC ELECTRICAL CHARACTERISTICS fSCLK Clock Frequency fS Sample Rate tCONV Conversion Time 8 (Note 8) (Note 8) MHz (min) 16 MHz (max) 500 kSPS (min) 1 MSPS (max) 13 SCLK cycles 30 % (min) 70 % (max) DC SCLK Duty Cycle fSCLK = 16 MHz tACQ Track/Hold Acquisition Time Full-Scale Step Input 3 SCLK cycles Throughput Time Acquisition Time + Conversion Time 16 SCLK cycles www.national.com 4 50 The following specifications apply for VA = +2.7V to 5.25V, GND = 0V, fSCLK = 8 MHz to 16 MHz, fSAMPLE = 500 kSPS to 1 MSPS, CL = 50 pF, Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25˚C. Symbol Parameter Conditions Typical VA = +3.0V −3.5 VA = +5.0V −0.5 VA = +3.0V +4.5 VA = +5.0V +1.5 Limits (Note 7) Units 10 ns (min) 10 ns (min) 30 ns (max) 30 ns (max) tCSU Setup Time SCLK High to CS Falling Edge (Note 10) tCLH Hold time SCLK Low to CS Falling Edge (Note 10) tEN Delay from CS Until DOUT active tACC Data Access Time after SCLK Falling Edge tSU Data Setup Time Prior to SCLK Rising Edge +3 10 ns (min) tH Data Valid SCLK Hold Time +3 10 ns (min) tCH SCLK High Pulse Width 0.5 x tSCLK 0.3 x tSCLK ns (min) tCL SCLK Low Pulse Width 0.5 x tSCLK 0.3 x tSCLK ns (min) 20 ns (max) Output Falling tDIS CS Rising Edge to DOUT High-Impedance Output Rising VA = +3.0V +4 VA = +5.0V +2 VA = +3.0V +16.5 VA = +5.0V +15 VA = +3.0V 1.7 VA = +5.0V 1.2 VA = +3.0V 1.0 VA = +5.0V 1.0 Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions. Note 2: All voltages are measured with respect to GND = 0V, unless otherwise specified. Note 3: When the input voltage at any pin exceeds the power supply (that is, VIN < GND or VIN > VA), the current at that pin should be limited to 10 mA. The 20 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 10 mA to two. The Absolute Maximum Rating specification does not apply to the VA pin. The current into the VA pin is limited by the Analog Supply Voltage specification. Note 4: The absolute maximum junction temperature (TJmax) for this device is 150˚C. The maximum allowable power dissipation is dictated by TJmax, the junction-to-ambient thermal resistance (θJA), and the ambient temperature (TA), and can be calculated using the formula PDMAX = (TJmax − TA)/θJA. The values for maximum power dissipation listed above will be reached only when the device is operated in a severe fault condition (e.g. when input or output pins are driven beyond the power supply voltages, or the power supply polarity is reversed). Obviously, such conditions should always be avoided. Note 5: Human body model is 100 pF capacitor discharged through a 1.5 kΩ resistor. Machine model is 220 pF discharged through zero ohms. Note 6: Reflow temperature profiles are different for lead-free and non-lead-free packages. Note 7: Tested limits are guaranteed to National’s AOQL (Average Outgoing Quality Level). Note 8: This is the frequency range over which the electrical performance is guaranteed. The device is functional over a wider range which is specified under Operating Ratings. Note 9: Datasheet min/max specification limits are guaranteed by design, test, or statistical analysis. Note 10: Clock may be in any state (high or low) when CS is asserted, with the restrictions on setup and hold time given by tCSU and tCLH. 5 www.national.com ADC082S101 ADC082S101 Timing Specifications ADC082S101 Timing Diagrams 20125451 ADC082S101 Operational Timing Diagram 20125408 Timing Test Circuit 20125406 ADC082S101 Serial Timing Diagram 20125450 SCLK and CS Timing Parameters www.national.com 6 ACQUISITION TIME is the time required to acquire the input voltage. That is, it is time required for the hold capacitor to charge up to the input voltage. MISSING CODES are those output codes that will never appear at the ADC outputs. The ADC082S101 is guaranteed not to have any missing codes. APERTURE DELAY is the time between the fourth falling SCLK edge of a conversion and the time when the input signal is acquired or held for conversion. OFFSET ERROR is the deviation of the first code transition (000...000) to (000...001) from the ideal (i.e. GND + 0.5 LSB). SIGNAL TO NOISE RATIO (SNR) is the ratio, expressed in dB, of the rms value of the input signal to the rms value of the sum of all other spectral components below one-half the sampling frequency, not including harmonics or d.c. CONVERSION TIME is the time required, after the input voltage is acquired, for the ADC to convert the input voltage to a digital word. CROSSTALK is the coupling of energy from one channel into the other channel, or the amount of signal energy from one analog input that appears at the measured analog input. SIGNAL TO NOISE PLUS DISTORTION (S/N+D or SINAD) Is the ratio, expressed in dB, of the rms value of the input signal to the rms value of all of the other spectral components below half the clock frequency, including harmonics but excluding d.c. DIFFERENTIAL NON-LINEARITY (DNL) is the measure of the maximum deviation from the ideal step size of 1 LSB. DUTY CYCLE is the ratio of the time that a repetitive digital waveform is high to the total time of one period. The specification here refers to the SCLK. EFFECTIVE NUMBER OF BITS (ENOB, or EFFECTIVE BITS) is another method of specifying Signal-to-Noise and Distortion or SINAD. ENOB is defined as (SINAD − 1.76) / 6.02 and says that the converter is equivalent to a perfect ADC of this (ENOB) number of bits. SPURIOUS FREE DYNAMIC RANGE (SFDR) is the difference, expressed in dB, between the rms values of the input signal and the peak spurious signal where a spurious signal is any signal present in the output spectrum that is not present at the input, excluding d.c. TOTAL HARMONIC DISTORTION (THD) is the ratio, expressed in dB or dBc, of the rms total of the first five harmonic components at the output to the rms level of the input signal frequency as seen at the output. THD is calculated as FULL POWER BANDWIDTH is a measure of the frequency at which the reconstructed output fundamental drops 3 dB below its low frequency value for a full scale input. GAIN ERROR is the deviation of the last code transition (111...110) to (111...111) from the ideal (VREF − 1.5 LSB), after adjusting for offset error. INTEGRAL NON-LINEARITY (INL) is a measure of the deviation of each individual code from a line drawn from negative full scale (1⁄2 LSB below the first code transition) through positive full scale (1⁄2 LSB above the last code transition). The deviation of any given code from this straight line is measured from the center of that code value. INTERMODULATION DISTORTION (IMD) is the creation of additional spectral components as a result of two sinusoidal frequencies being applied to the ADC input at the same time. It is defined as the ratio of the power in the second and third where Af1 is the RMS power of the input frequency at the output and Af2 through Af6 are the RMS power in the first 5 harmonic frequencies. THROUGHPUT TIME is the minimum time required between the start of two successive conversion. It is the acquisition time plus the conversion time. 7 www.national.com ADC082S101 order intermodulation products to the sum of the power in both of the original frequencies. IMD is usually expressed in dB. Specification Definitions ADC082S101 Typical Performance Characteristics TA = +25˚C, fSAMPLE = 500 kSPS to 1 MSPS, fSCLK = 8 MHz to 16 MHz, fIN = 40.3 kHz unless otherwise stated. DNL - VA = 3.0V INL - VA = 3.0V 20125420 20125421 DNL - VA = 5.0V INL - VA = 5.0V 20125462 20125463 DNL vs. Supply INL vs. Supply 20125422 www.national.com 20125423 8 DNL vs. Clock Frequency INL vs. Clock Frequency 20125424 20125425 DNL vs. Clock Duty Cycle INL vs. Clock Duty Cycle 20125426 20125427 DNL vs. Temperature INL vs. Temperature 20125428 20125429 9 www.national.com ADC082S101 Typical Performance Characteristics TA = +25˚C, fSAMPLE = 500 kSPS to 1 MSPS, fSCLK = 8 MHz to 16 MHz, fIN = 40.3 kHz unless otherwise stated. (Continued) ADC082S101 Typical Performance Characteristics TA = +25˚C, fSAMPLE = 500 kSPS to 1 MSPS, fSCLK = 8 MHz to 16 MHz, fIN = 40.3 kHz unless otherwise stated. (Continued) SNR vs. Supply THD vs. Supply 20125430 20125435 SNR vs. Clock Frequency THD vs. Clock Frequency 20125431 20125436 SNR vs. Clock Duty Cycle THD vs. Clock Duty Cycle 20125432 www.national.com 20125437 10 SNR vs. Input Frequency THD vs. Input Frequency 20125433 20125438 SNR vs. Temperature THD vs. Temperature 20125434 20125439 SFDR vs. Supply SINAD vs. Supply 20125440 20125445 11 www.national.com ADC082S101 Typical Performance Characteristics TA = +25˚C, fSAMPLE = 500 kSPS to 1 MSPS, fSCLK = 8 MHz to 16 MHz, fIN = 40.3 kHz unless otherwise stated. (Continued) ADC082S101 Typical Performance Characteristics TA = +25˚C, fSAMPLE = 500 kSPS to 1 MSPS, fSCLK = 8 MHz to 16 MHz, fIN = 40.3 kHz unless otherwise stated. (Continued) SFDR vs. Clock Frequency SINAD vs. Clock Frequency 20125441 20125446 SFDR vs. Clock Duty Cycle SINAD vs. Clock Duty Cycle 20125442 20125447 SFDR vs. Input Frequency SINAD vs. Input Frequency 20125443 www.national.com 20125448 12 SFDR vs. Temperature SINAD vs. Temperature 20125444 20125449 ENOB vs. Supply ENOB vs. Clock Frequency 20125452 20125453 ENOB vs. Clock Duty Cycle ENOB vs. Input Frequency 20125454 20125455 13 www.national.com ADC082S101 Typical Performance Characteristics TA = +25˚C, fSAMPLE = 500 kSPS to 1 MSPS, fSCLK = 8 MHz to 16 MHz, fIN = 40.3 kHz unless otherwise stated. (Continued) ADC082S101 Typical Performance Characteristics TA = +25˚C, fSAMPLE = 500 kSPS to 1 MSPS, fSCLK = 8 MHz to 16 MHz, fIN = 40.3 kHz unless otherwise stated. (Continued) ENOB vs. Temperature Spectral Response - 3V, 1 MSPS 20125456 20125464 Spectral Response - 5V, 1 MSPS Spectral Response - 3V, 500 kSPS 20125465 20125459 Spectral Response - 5V, 500 kSPS Power Consumption vs. Throughput 20125460 www.national.com 20125461 14 1.0 ADC082S101 OPERATION The ADC082S101 is a successive-approximation analog-todigital converter designed around a charge-redistribution digital-to-analog converter. Simplified schematics of the ADC082S101 in both track and hold modes are shown in Figures 1, 2, respectively. In Figure 1, the ADC082S101 is in track mode: switch SW1 connects the sampling capacitor to one of two analog input channels through the multiplexer, and SW2 balances the comparator inputs. The ADC082S101 is in this state for the first three SCLK cycles after CS is brought low. Figure 2 shows the ADC082S101 in hold mode: switch SW1 connects the sampling capacitor to ground, maintaining the 20125409 FIGURE 1. ADC082S101 in Track Mode 20125410 FIGURE 2. ADC082S101 in Hold Mode During the first 3 cycles of SCLK, the ADC is in the track mode, acquiring the input voltage. For the next 13 SCLK cycles the conversion is accomplished and the data is clocked out, MSB first, starting with the 5th clock. If there is more than one conversion in a frame, the ADC will re-enter the track mode on the falling edge of SCLK after the N*16th rising edge of SCLK, and re-enter the hold/convert mode on the N*16+4th falling edge of SCLK, where "N" is an integer. When CS is brought high, SCLK is internally gated off. If SCLK is stopped in the low state while CS is high, the subsequent fall of CS will generate a falling edge of the internal version of SCLK, putting the ADC into the track mode. This is seen by the ADC as the first falling edge of SCLK. If SCLK is stopped with SCLK high, the ADC enters the track mode on the first falling edge of SCLK after the falling edge of CS. During each conversion, data is clocked into the DIN pin on the first 8 rising edges of SCLK after the fall of CS. For each 2.0 USING THE ADC082S101 An ADC082S101 timing diagram and a serial interface timing diagram for the ADC082S101 are shown in the Timing Diagrams section. CS is chip select, which initiates conversions and frames the serial data transfers. SCLK (serial clock) controls both the conversion process and the timing of serial data. DOUT is the serial data output pin, where a conversion result is sent as a serial data stream, MSB first. Data to be written to the ADC082S101’s Control Register is placed on DIN, the serial data input pin. New data is written to DIN with each conversion. A serial frame is initiated on the falling edge of CS and ends on the rising edge of CS. Each frame must contain an integer multiple of 16 rising SCLK edges. The ADC output data (DOUT) is in a high impedance state when CS is high and is active when CS is low. Thus, CS acts as an output enable. Additionally, the device goes into a power down state when CS is high and also between continuous conversion cycles. 15 www.national.com ADC082S101 sampled voltage, and switch SW2 unbalances the comparator. The control logic then instructs the charge-redistribution DAC to add fixed amounts of charge to the sampling capacitor until the comparator is balanced. When the comparator is balanced, the digital word supplied to the DAC is the digital representation of the analog input voltage. The ADC082S101 is in this state for the fourth through sixteenth SCLK cycles after CS is brought low. The time when CS is low is considered a serial frame. Each of these frames should contain an integer multiple of 16 SCLK cycles, during which time a conversion is performed and clocked out at the DOUT pin and data is clocked into the DIN pin to indicate the multiplexer address for the next conversion. Applications Information ADC082S101 Applications Information There are no power-up delays or dummy conversions required with the ADC082S101. The ADC is able to sample and convert an input to full conversion immediately following power up. The first conversion result after power-up will be that of IN1. (Continued) conversion, it is necessary to clock in the data indicating the input that is selected for the conversion after the current one. See Tables 1, 2 and Table 3. If CS and SCLK go low simultaneously, it is the following rising edge of SCLK that is considered the first rising edge for clocking data into DIN. TABLE 1. Control Register Bits Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 DONTC DONTC ADD2 ADD1 ADD0 DONTC DONTC DONTC TABLE 2. Control Register Bit Descriptions Bit #: Symbol: 7 - 6, 2 - 0 DONTC 3 ADD0 4 ADD1 5 ADD2 Description Don’t care. The value of these bits do not affect the device. These bits determine which input channel will be sampled and converted in the next track/hold cycle. The mapping between codes and channels is shown in Table 3. TABLE 3. Input Channel Selection www.national.com ADD2 ADD1 ADD0 Input Channel x 0 0 IN1 (Default) x 0 1 IN2 x 1 x Not allowed. The output signal at the DOUT pin is indeterminate if ADD1 is high. 16 LSB values. The LSB width for the ADC082S101 is VA/256. The ideal transfer characteristic is shown in Figure 3. The transition from an output code of 0000 0000 to a code of 0000 0001 is at 1/2 LSB, or a voltage of VA/512. Other code transitions occur at steps of one LSB. (Continued) 3.0 ADC082S101 TRANSFER FUNCTION The output format of the ADC082S101 is straight binary. Code transitions occur midway between successive integer 20125411 FIGURE 3. Ideal Transfer Characteristic 4.0 TYPICAL APPLICATION CIRCUIT A typical application of the ADC082S101 is shown in Figure 4. Power is provided in this example by the National Semiconductor LP2950 low-dropout voltage regulator, available in a variety of fixed and adjustable output voltages. The power supply pin is bypassed with a capacitor network located close to the ADC082S101. Because the reference for the ADC082S101 is the supply voltage, any noise on the supply will degrade device noise performance. To keep noise off the supply, use a dedicated linear regulator for this device, or provide sufficient decoupling from other circuitry to keep noise off the ADC082S101 supply pin. Because of the ADC082S101’s low power requirements, it is also possible to use a precision reference as a power supply to maximize performance. The four-wire interface is also shown connected to a microprocessor or DSP. 20125413 FIGURE 4. Typical Application Circuit 17 www.national.com ADC082S101 Applications Information ADC082S101 Applications Information The user may trade off throughput for power consumption by simply performing fewer conversions per unit time. The Power Consumption vs. Sample Rate curve in the Typical Performance Curves section shows the typical power consumption of the ADC082S101 versus throughput. To calculate the power consumption, simply multiply the fraction of time spent in the normal mode by the normal mode power consumption , and add the fraction of time spent in shutdown mode multiplied by the shutdown mode power dissipation. (Continued) 5.0 ANALOG INPUTS An equivalent circuit for one of the ADC082S101’s input channels is shown in Figure 5. Diodes D1 and D2 provide ESD protection for the analog inputs. At no time should any input go beyond (VA + 300 mV) or (GND − 300 mV), as these ESD diodes will begin conducting, which could result in erratic operation. The capacitor C1 in Figure 5 has a typical value of 3 pF, and is mainly the package pin capacitance. Resistor R1 is the on resistance of the multiplexer and track / hold switch, and is typically 500 ohms. Capacitor C2 is the ADC082S101 sampling capacitor and is typically 30 pF. The ADC082S101 will deliver best performance when driven by a low-impedance source to eliminate distortion caused by the charging of the sampling capacitance. This is especially important when using the ADC082S101 to sample AC signals. Also important when sampling dynamic signals is a band-pass or low-pass filter to reduce harmonics and noise, improving dynamic performance. 7.1 Power Management When the ADC082S101 is operated continuously in normal mode, the maximum throughput is fSCLK/16. Throughput may be traded for power consumption by running fSCLK at its maximum 16 MHz and performing fewer conversions per unit time, putting the ADC082S101 into shutdown mode between conversions. A plot of typical power consumption versus throughput is shown in the Typical Performance Curves section. To calculate the power consumption for a given throughput, multiply the fraction of time spent in the normal mode by the normal mode power consumption and add the fraction of time spent in shutdown mode multiplied by the shutdown mode power consumption. Generally, the user will put the part into normal mode and then put the part back into shutdown mode. Note that the curve of power consumption vs. throughput is nearly linear. This is because the power consumption in the shutdown mode is so small that it can be ignored for all practical purposes. 7.2 Power Supply Noise Considerations The charging of any output load capacitance requires current from the power supply, VA. The current pulses required from the supply to charge the output capacitance will cause voltage variations on the supply. If these variations are large enough, they could degrade SNR and SINAD performance of the ADC. Furthermore, discharging the output capacitance when the digital output goes from a logic high to a logic low will dump current into the die substrate, which is resistive. Load discharge currents will cause "ground bounce" noise in the substrate that will degrade noise performance if that current is large enough. The larger is the output capacitance, the more current flows through the die substrate and the greater is the noise coupled into the analog channel, degrading noise performance. To keep noise out of the power supply, keep the output load capacitance as small as practical. If the load capacitance is greater than 50 pF, use a 100 Ω series resistor at the ADC output, located as close to the ADC output pin as practical. This will limit the charge and discharge current of the output capacitance and improve noise performance. 20125414 FIGURE 5. Equivalent Input Circuit 6.0 DIGITAL INPUTS AND OUTPUTS The ADC082S101’s digital output DOUT is limited by, and cannot exceed, the supply voltage, VA. The digital input pins are not prone to latch-up and, and although not recommended, SCLK, CS and DIN may be asserted before VA without any latchup risk. 7.0 POWER SUPPLY CONSIDERATIONS The ADC082S101 is fully powered-up whenever CS is low, and fully powered-down whenever CS is high, with one exception: the ADC082S101 automatically enters powerdown mode between the 16th falling edge of a conversion and the 1st falling edge of the subsequent conversion (see Timing Diagrams). The ADC082S101 can perform multiple conversions back to back; each conversion requires 16 SCLK cycles. The ADC082S101 will perform conversions continuously as long as CS is held low. www.national.com 18 ADC082S101 2 Channel, 1 MSPS, 8-Bit A/D Converter Physical Dimensions inches (millimeters) unless otherwise noted 8-Lead MSOP Order Number ADC082S101CIMM, ADC082S101CIMMX NS Package Number P0MUA08A National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications. For the most current product information visit us at www.national.com. LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. 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