TI1 ADS8339IDGSR Ads8339 16-bit, 250-ksps, serial interface, micro-power, miniature, sar analog-to-digital converter Datasheet

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ADS8339
SBAS677A – JUNE 2014 – REVISED OCTOBER 2014
ADS8339 16-Bit, 250-kSPS, Serial Interface, Micro-Power, Miniature,
SAR Analog-to-Digital Converter
1 Features
3 Description
•
•
•
•
The ADS8339 is a 16-bit, 250-kSPS, analog-to-digital
converter (ADC). The device operates with a 2.25-V
to 5.5-V external reference. The device includes a
capacitor-based, successive-approximation register
(SAR) ADC with an inherent sample-and-hold circuit.
1
•
•
•
•
•
•
•
Sample Rate: 250 kHz
16-Bit Resolution
Zero Latency at Full Speed
Unipolar Single-Ended Input Range:
– 0 V to Vref
SPI™-Compatible Serial Interface with DaisyChain Option
Uses Internal Clock for Conversion
Excellent Performance:
– 93.6 dB SNR (typ) at 10-kHz Input
– –106 dB THD (typ) at 10-kHz Input
– ±2.0 LSB INL (max)
– ±1.0 LSB DNL (max)
Low-Power Dissipation:
– 17.5 mW (typ) at 250 kSPS
Power Scales Linearly with Speed:
– 1.75 mW at 25 kSPS
Power Dissipation During Power-Down State:
– 0.25 μW (typ)
Package: VSSOP-10
The device includes a 25-MHz, SPI-compatible serial
interface. The interface is designed to support daisychaining or cascading of multiple devices.
Furthermore, a busy indicator makes synchronizing
with the digital host easy. The unipolar, single-ended
input range for the device supports an input swing of
0 V to Vref.
The device is optimized for low-power operation and
power consumption scales directly with speed. This
feature makes the device attractive for lower speed
applications. The ADS8339 is available in a VSSOP10 package.
Device Information(1)
PART NUMBER
ADS8339
BODY SIZE (NOM)
3.00 mm × 3.00 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
space
2 Applications
space
•
•
•
•
•
space
Battery-Powered Equipment
Data Acquisition Systems
Instrumentation and Process Controls
Medical Electronics
Optical Networking
PACKAGE
VSSOP (10)
+100 mV
REF
2.25 V to +VA + 0.1 V
IN+
2.375 V to +VA
4.5 V to 5.5 V
+VA
100 mV
0V
REFIN
SDO
IN+
VDIFF = (IN+) t (IN) = 0 V to REF
NOTE: (IN+) • (IN)
ADS8339
r100 mV
SDI
SCLK
IN
100 mV
+VBD
CONVST
GND
IN
0V
Pseudo-Differential Input
100 mV
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
ADS8339
SBAS677A – JUNE 2014 – REVISED OCTOBER 2014
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Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Device Family .........................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
3
4
7.1
7.2
7.3
7.4
7.5
7.6
7.7
4
4
4
5
5
7
8
Absolute Maximum Ratings ......................................
Handling Ratings.......................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Timing Requirements ................................................
Typical Characteristics ..............................................
8
Parametric Measurement Information ............... 15
9
Detailed Description ............................................ 16
8.1 Timing Diagrams ..................................................... 15
9.1 Overview ................................................................. 16
9.2 Functional Block Diagram ....................................... 16
9.3 Feature Description................................................. 17
9.4 Device Functional Modes........................................ 18
10 Application and Implementation........................ 26
10.1 Application Information.......................................... 26
10.2 Typical Application ................................................ 30
10.3 Do's and Don'ts ..................................................... 31
11 Power-Supply Recommendations ..................... 31
12 Layout................................................................... 32
12.1 Layout Guidelines ................................................. 32
12.2 Layout Example .................................................... 32
13 Device and Documentation Support ................. 33
13.1
13.2
13.3
13.4
Documentation Support ........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
33
33
33
33
14 Mechanical, Packaging, and Orderable
Information ........................................................... 33
4 Revision History
Changes from Original (June 2014) to Revision A
•
2
Page
Made changes to product preview data sheet........................................................................................................................ 1
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SBAS677A – JUNE 2014 – REVISED OCTOBER 2014
5 Device Family (1)
(1)
SAMPLING RATE
16-BIT, SINGLE-ENDED
16-BIT, DIFFERENTIAL
18-BIT, DIFFERENTIAL
100 kSPS
ADS8866
ADS8867
ADS8887
250 kSPS
ADS8339
—
—
400 kSPS
ADS8864
ADS8865
ADS8885
500 kSPS
ADS8319
ADS8318
—
680 kSPS
ADS8862
ADS8863
ADS8883
1 MSPS
ADS8860
ADS8861
ADS8881
All devices are pin-to-pin compatible. The ADS8339, ADS8319, and ADS8318 require a 4.5-V to 5.5-V analog supply. The remaining
devices use a 2.7-V to 3.6-V analog supply.
6 Pin Configuration and Functions
DGS Package
VSSOP-10
(Top View)
REFIN
1
10
+VA
2
9
SDI
IN+
3
8
SCLK
IN
4
7
SDO
GND
5
6
CONVST
+VBD
Pin Functions
PIN
FUNCTION
DESCRIPTION
REFIN
Input
Reference (positive) input. Decouple to GND with a 0.1-μF bypass capacitor and a 10-μF storage
capacitor.
2
+VA
Supply
3
+IN
Input
Noninverting analog signal input
4
–IN
Input
Inverting analog signal input. Note that this input has a limited range of ±0.1 V and is typically
grounded at the input decoupling capacitor.
5
GND
Supply
6
CONVST
Input
7
SDO
Output
8
SCLK
Input
Serial I/O clock input. Data (on the SDO output) are synchronized with this clock.
9
SDI
Input
Serial data input. The SDI level at the start of a conversion selects the mode of operation (such
as CS or daisy-chain mode). SDI also serves as the CS input in 4-wire interface mode. Refer to
the Description and Timing Diagrams sections for more details.
10
+VBD
Supply
NO.
NAME
1
Analog power supply. Decouple with the GND pin.
Device ground. Note that this pin is a common ground pin for both the analog power supply
(+VA) and digital I/O supply (+VBD).
Convert input. CONVST also functions as the CS input in 3-wire interface mode. Refer to the
Description and Timing Diagrams sections for more details.
Serial data output
Digital I/O power supply. Decouple with the GND pin.
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
Voltage
+IN, –IN input
Momentary current
MIN
MAX
UNIT
–0.3
+VA + 0.3
V
130
mA
±10
mA
7
V
(2)
Continuous current
+VA to GND
–0.3
+VBD to GND
–0.3
7
V
Digital input voltage to GND
–0.3
+VBD + 0.3
V
Digital output voltage to GND
–0.3
+VBD + 0.3
V
Operating free-air range, TA
Temperature
VSSOP package
85
°C
Junction, TJ max
–40
150
°C
Power dissipation
(TJmax – TA) / θJA
°C
121.1
°C/W
260
°C
θJA thermal impedance
Maximum VSSOP reflow temperature (3)
(1)
(2)
(3)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Limit the duration for this current to less than 10 ms.
The device is rated at MSL2, 260°C, as per the JSTD-020 specification.
7.2 Handling Ratings
MIN
MAX
UNIT
–65
150
°C
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all
pins (1)
–1000
1000
Charged device model (CDM), per JEDEC specification
JESD22-C101, all pins (2)
–250
250
Tstg
Storage temperature range
V(ESD)
Electrostatic discharge
(1)
(2)
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
V+VA
Analog power-supply voltage
V+VBD
Digital I/O-supply voltage
Vref
Reference voltage
f(SCLK)
SCLK frequency
TA
Operating temperature range
4
MIN
NOM
MAX
UNIT
4.5
5.0
5.5
V
2.375
3.3
5.5
V
2.25
4.096
V+VA + 0.1
V
–40
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25
MHz
85
°C
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7.4 Thermal Information
ADS8339
THERMAL METRIC (1)
DGS (VSSOP)
UNIT
10 PINS
RθJA
Junction-to-ambient thermal resistance
121.1
RθJC(top)
Junction-to-case (top) thermal resistance
29.4
RθJB
Junction-to-board thermal resistance
32.0
ψJT
Junction-to-top characterization parameter
0.7
ψJB
Junction-to-board characterization parameter
31.5
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
(1)
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
7.5 Electrical Characteristics
All minimum and maximum specifications are at TA = –40°C to 85°C, +VA = 5 V, +VBD = 5 V to 2.375 V, Vref = 4 V, and fsample
= 250 kHz, unless otherwise noted. Typical specifications are at TA = 25°C.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ANALOG INPUT
Full-scale input span (1)
Operating input range
Ci
+IN – (–IN)
0
Vref
V
+IN
–0.1
Vref + 0.1
V
–IN
–0.1
0.1
V
Input capacitance
Input leakage current
During acquisition
59
pF
1000
pA
16
Bits
SYSTEM PERFORMANCE
Resolution
NMC
No missing codes
16
INL
Integral linearity (2)
–2.0
±1.2
2.0
LSB (3)
DNL
Differential linearity
–0.99
±0.65
1.0
LSB
EO
Offset error (4)
–1.5
±0.3
1.5
mV
EG
Gain error
–0.03
±0.0045
0.03
%FSR
CMRR
Common-mode rejection ratio
With common-mode input signal = 200 mVPP
at 250 kHz
PSRR
Power-supply rejection ratio
At FFF0h output code
At 16-bit level
Bits
78
Transition noise
dB
80
dB
0.5
LSB
SAMPLING DYNAMICS
tcnv
Conversion time
500 (5)
tacq
Acquisition time
700
3300
ns
Maximum throughput rate
with or without latency
0.25
Aperture delay
Aperture jitter, RMS
(1)
(2)
(3)
(4)
(5)
ns
MHz
2.5
ns
6
ps
Step response
Settling to 16-bit accuracy
600
ns
Overvoltage recovery
Settling to 16-bit accuracy
600
ns
Ideal input span, does not include gain or offset error.
This parameter is the endpoint INL, not best-fit INL.
LSB = least significant bit.
Measured relative to actual measured reference.
Refer to the CS Mode for a 3-Wire Interface section in the Device Functional Modes.
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Electrical Characteristics (continued)
All minimum and maximum specifications are at TA = –40°C to 85°C, +VA = 5 V, +VBD = 5 V to 2.375 V, Vref = 4 V, and fsample
= 250 kHz, unless otherwise noted. Typical specifications are at TA = 25°C.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DYNAMIC CHARACTERISTICS
Total harmonic distortion (6)
THD
SNR
Signal-to-noise ratio
SINAD
SFDR
Signal-to-noise + distortion
Spurious-free dynamic range
VIN = 0.4 dB below fS at 1 kHz, Vref = 5 V
–111
dB
VIN = 0.4 dB below fS at 10 kHz, Vref = 5 V
–106
dB
VIN = 0.4 dB below fS at 1 kHz, Vref = 5 V
93.9
dB
VIN = 0.4 dB below fS at 10 kHz, Vref = 5 V
93.6
dB
VIN = 0.4 dB below fS at 1 kHz, Vref = 5 V
93.8
dB
VIN = 0.4 dB below fS at 10 kHz, Vref = 5 V
93.4
dB
VIN = 0.4 dB below fS at 1 kHz, Vref = 5 V
113
dB
VIN = 0.4 dB below fS at 10 kHz, Vref = 5 V
107
dB
15
MHz
–3-dB small-signal bandwidth
EXTERNAL REFERENCE INPUT
Vref
Input range
2.25
Reference input current (7)
During conversion
4.096
VA + 0.1
V
μA
75
POWER-SUPPLY REQUIREMENTS
Power-supply voltage
+VBD
+VA
ICC
Supply current
+VA
PVA
Power dissipation
+VA = 5 V, 250-kHz sample rate
IVApd
Device power-down current (8)
+VA = 5 V
2.375
3.3
5.5
4.5
5
5.5
V
3.5
4.0
mA
17.5
20.0
mW
50
300
nA
250-kHz sample rate
V
LOGIC FAMILY CMOS
VIH
High-level input voltage
IIH = 5 μA
0.7 × VBD
VBD + 0.3
V
VIL
Low-level input voltage
IIL = 5 μA
–0.3
0.3 × VBD
V
VOH
High-level output voltage
IOH = 2 TTL loads
VBD – 0.3
VBD
V
VOL
Low-level output voltage
IOL = 2 TTL loads
0
0.4
V
–40
85
°C
TEMPERATURE RANGE
TA
(6)
(7)
(8)
6
Operating free-air temperature
Calculated on the first nine harmonics of the input frequency.
Can vary by ±20%.
The device automatically enters a power-down state at the end of every conversion and remains in a power-down state as long as the
device is in an acquisition phase.
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7.6 Timing Requirements
All specifications are at TA = –40°C to 85°C, +VA = 5 V, and 5.5 V > +VBD ≥ 2.375 V, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SAMPLING AND CONVERSION
tacq
Acquisition time
(see Figure 47, Figure 49, Figure 50, Figure 53)
700
tcnv
Conversion time
(see Figure 47, Figure 49, Figure 50, Figure 53)
500 (1)
tcyc
Time between conversions
(see Figure 47, Figure 49, Figure 50, Figure 53)
4000
ns
t1
Pulse duration, CONVST high (see Figure 47, Figure 49)
10
ns
t6
Pulse duration, CONVST low
(see Figure 50, Figure 53, Figure 55)
20
ns
ns
ns
3300
ns
INPUTS AND OUTPUTS (I/O)
tclk
SCLK period (see Figure 47, Figure 49, Figure 50, Figure 53,
Figure 55, Figure 57)
40.0
tclkl
SCLK low time (see Figure 47, Figure 49, Figure 50, Figure 53,
Figure 55, Figure 57)
0.45
0.55
tclk
tclkh
SCLK high time (see Figure 47, Figure 49, Figure 50, Figure 53,
Figure 55, Figure 57)
0.45
0.55
tclk
t2
SCLK falling edge to data remains valid (see Figure 47, Figure 49,
Figure 50, Figure 53, Figure 55, Figure 57)
t3
SCLK falling edge to next data valid delay (see Figure 47,
Figure 49, Figure 50, Figure 53, Figure 55, Figure 57)
5.5 V ≥ +VBD ≥ 4.5 V
16
ns
4.5 V > +VBD ≥ 2.375 V
24
ns
ten
CONVST or SDI low to MSB valid
(see Figure 47, Figure 50)
5.5 V ≥ +VBD ≥ 4.5 V
15
ns
4.5 V > +VBD ≥ 2.375 V
22
ns
5.5 V ≥ +VBD ≥ 4.5 V
12
ns
tdis
CONVST or SDI high or last SCLK falling edge to SDO
3-state (CS mode)
(see Figure 47, Figure 49, Figure 50, Figure 53)
4.5 V > +VBD ≥ 2.375 V
15
ns
t4
SDI valid setup time to CONVST rising edge
(see Figure 50, Figure 53)
5
ns
t5
SDI valid hold time from CONVST rising edge
(see Figure 50, Figure 53)
5
ns
t7
SCLK valid setup time to CONVST rising edge
(see Figure 55)
5
ns
t8
SCLK valid hold time from CONVST rising edge
(see Figure 55)
5
ns
(1)
5
ns
Refer to the CS Mode for a 3-Wire Interface subsection in the Device Functional Modes section.
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7.7 Typical Characteristics
At TA = 30°C, +VA = 5 V, +VBD = 2.7 V, Vref = 4.096 V, and fsample = 250 kHz, unless otherwise noted.
0.005
±0.2
0.0045
0.004
Gain Error (%FSR)
Offset Error (mV)
±0.25
±0.3
±0.35
±0.4
0.0035
0.003
0.0025
0.002
0.0015
0.001
±0.45
0.0005
0
±0.5
4.5
4.75
5
5.25
5.5
Supply Voltage (V)
4.5
4.75
5
5.25
5.5
Supply Voltage (V)
C001
+VBD = 2.7 V, Vref = 4.096 V, fS = 250 kSPS, TA = 30°C
C002
+VBD = 2.7 V, Vref = 4.096 V, fS = 250 kSPS, TA = 30°C
Figure 1. Offset Error vs Supply Voltage
Figure 2. Gain Error vs Supply Voltage
0
0.0045
0.004
±0.05
Gain Error (%FSR)
Offset Error (mV)
0.0035
±0.1
±0.15
±0.2
±0.25
0.003
0.0025
0.002
0.0015
0.001
±0.3
0.0005
0
±0.35
2
2.5
3
3.5
4
4.5
Reference Voltage (V)
5
2
3.5
4
4.5
5
C004
+VBD = 2.7 V, +VA = 5 V, fS = 250 kSPS, TA = 30°C
Figure 3. Offset Error vs Reference Voltage
Figure 4. Gain Error vs Reference Voltage
0
0.01
±0.1
0.009
±0.2
0.008
Gain Error (%FSR)
Offset Error (mV)
3
Reference Voltage (V)
+VBD = 2.7 V, +VA = 5 V, fS = 250 kSPS, TA = 30°C
±0.3
±0.4
±0.5
±0.6
±0.7
0.007
0.006
0.005
0.004
0.003
±0.8
0.002
±0.9
0.001
0
±1
±40
±20
0
20
40
60
80
Free-Air Temperature (ƒC)
100
±40
Figure 5. Offset Error vs Free-Air Temperature
±20
0
20
40
60
80
Free-Air Temperature (ƒC)
C005
+VBD = 2.7 V, +VA = 5 V, Vref = 5 V, fS = 250 kSPS
8
2.5
C003
100
C006
+VBD = 2.7 V, +VA = 5 V, Vref = 5 V, fS = 250 kSPS
Figure 6. Gain Error vs Free-Air Temperature
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Typical Characteristics (continued)
At TA = 30°C, +VA = 5 V, +VBD = 2.7 V, Vref = 4.096 V, and fsample = 250 kHz, unless otherwise noted.
14
25
12
12
12
20
10
Number of Devices
Number of Devices
20
8
6
4
3
3
15
10
5
5
±0.2
±0.1
ppm/ƒC
1
0
0
0.5
0
0.3
0
0.2
0
0.1
0
0
0
±0.3
0
±0.4
0
0.5
0.4
0.3
0.2
0.1
0
0
±0.1
0
±0.2
0
±0.3
±0.4
±0.5
0
0
±0.5
1
0
0.4
5
2
ppm/ƒC
C007
C008
+VBD = 2.7 V, +VA = 5 V, fS = 250 kSPS
+VBD = 2.7 V, +VA = 5 V, Vref = 5 V, fS = 250 kSPS
Figure 7. Gain Error Drift Histogram
Figure 8. Offset Error Drift Histogram
1.5
DNL Max
0.8
DNL Min
0.6
Integral Nonlinearity (LSBs)
Differential Nonlinearity (LSBs)
1.
1
0.4
0.2
0.
0
±0.2
±0.4
±0.6
INL Max
INL Min
1.
1
0.5
0
0.
±0.5
±1
±0.8
±1
±1.5
4.5
4.75
5
5.25
4.5
5.5
Supply Voltage (V)
+VBD = 2.7 V, Vref = 4.096 V, fS = 250 kSPS, TA = 30°C
Integral Nonlinearity (LSBs)
Differential Nonlinearity (LSBs)
5.5
C010
Figure 10. INL vs Supply Voltage
1.5
DNL Min
0.6
5.25
+VBD = 2.7 V, Vref = 4.096 V, fS = 250 kSPS, TA = 30°C
DNL Max
0.8
5
Supply Voltage (V)
Figure 9. DNL vs Supply Voltage
1.
1
4.75
C009
0.4
0.2
0.
0
±0.2
±0.4
±0.6
INL Max
DNL Min
1.1
0.5
0.0
±0.5
±1
±0.8
±1
±1.5
2
2.5
3
3.5
4
4.5
Reference Voltage (V)
5
2
+VBD = 2.7 V, +VA = 5 V, fS = 250 kSPS, TA = 30°C
2.5
3
3.5
4
4.5
Reference Voltage (V)
C011
5
C012
+VBD = 2.7 V, +VA = 5 V, fS = 250 kSPS, TA = 30°C
Figure 11. DNL vs Reference Voltage
Figure 12. INL vs Reference Voltage
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Typical Characteristics (continued)
At TA = 30°C, +VA = 5 V, +VBD = 2.7 V, Vref = 4.096 V, and fsample = 250 kHz, unless otherwise noted.
1.
1
DNL Max
0.8
DNL Min
Integral Nonlinearity (LSBs)
Differential Nonlinearity (LSBs)
1.1
0.8
0.6
0.4
0.2
0.0
±0.2
±0.4
±0.6
±0.8
0.6
0.4
0.2
INL Max
0.
0
INL Min
±0.2
±0.4
±0.6
±0.8
±1
±1
±40
±20
0
20
40
60
80
Free-Air Temperature (ƒC)
100
±40
40
60
80
100
C014
Figure 14. INL vs Free-Air Temperature
16
16
15.9
15.8
Effective Number Of Bits (LSBs)
Effective Number Of Bits (LSBs)
20
+VBD = 2.7 V, +VA = 5 V, Vref = 5 V, fS = 250 kSPS
Figure 13. DNL vs Free-Air Temperature
15.8
15.7
15.6
15.5
15.4
15.3
15.2
15.1
15
15.6
15.4
15.2
15
14.8
14.6
14.4
14.2
14
4.5
4.75
5
5.25
5.5
Supply Voltage (V)
2
2.5
3
3.5
4
4.5
Reference Voltage (V)
C015
+VBD = 2.7 V, Vref = 5 V, fIN = 1.9 kHz, fS = 250 kSPS,
TA = 30°C
5
C016
+VBD = 2.7 V, +VA = 5 V, fIN = 1.9 kHz, fS = 250 kSPS, TA = 30°C
Figure 15. ENOB vs Supply Voltage
Figure 16. ENOB vs Reference Voltage
119
Spurious-Free Dynamic Range (dB)
16
Effective Number Of Bits (LSBs)
0
Free-Air Temperature (ƒC)
+VBD = 2.7 V, +VA = 5 V, Vref = 5 V, fS = 250 kSPS
15.9
15.8
15.7
15.6
15.5
15.4
15.3
15.2
15.1
15
117
115
113
111
109
107
105
±40
±20
0
20
40
60
80
Free-Air Temperature (ƒC)
100
4.5
4.75
5
5.25
Supply Voltage (V)
C017
+VBD = 2.7 V, +VA = 5 V, Vref = 5 V, fIN = 1.9 kHz,
fS = 250 kSPS
5.5
C018
+VBD = 2.7 V, Vref = 4.096 V, fIN = 1.9 kHz, fS = 250 kSPS,
TA = 30°C
Figure 17. ENOB vs Free-Air Temperature
10
±20
C013
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Figure 18. SFDR vs Supply Voltage
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Typical Characteristics (continued)
94.5
94.5
94
94
Signal-to-Noise Ratio (dB)
Signal-to-Noise and Distortion (dB)
At TA = 30°C, +VA = 5 V, +VBD = 2.7 V, Vref = 4.096 V, and fsample = 250 kHz, unless otherwise noted.
93.5
93
92.5
92
93.5
93
92.5
92
4.5
4.75
5
5.25
5.5
Supply Voltage (V)
4.5
+VBD = 2.7 V, Vref = 4.096 V, fIN = 1.9 kHz, fS = 250 kSPS,
TA = 30°C
5.25
5.5
C020
+VBD = 2.7 V, Vref = 4.096 V, fIN = 1.9 kHz, fS = 250 kSPS,
TA = 30°C
Figure 19. SINAD vs Supply Voltage
Figure 20. SNR vs Supply Voltage
119
Spurious-Free Dynamic Range (dB)
Total Harmonic Distortion (dB)
5
Supply Voltage (V)
119
117
115
113
111
109
107
105
117
115
113
111
109
107
105
4.5
4.75
5
5.25
5.5
Supply Voltage (V)
2
2.5
3
3.5
4
4.5
Reference Voltage (V)
C021
+VBD = 2.7 V, Vref = 4.096 V, fIN = 1.9 kHz, fS = 250 kSPS,
TA = 30°C
5
C022
+VBD = 2.7 V, +VA = 5 V, fIN = 1.9 kHz, fS = 250 kSPS, TA = 30°C
Figure 21. THD vs Supply Voltage
Figure 22. SFDR vs Reference Voltage
95
95
94.5
94.5
94
Signal-to-Noise Ratio (dB)
Signal-to-Noise and Distortion (dB)
4.75
C019
93.5
93
92.5
92
91.5
91
90.5
94
93.5
93
92.5
92
91.5
91
90.5
90
90
2
2.5
3
3.5
4
4.5
Reference Voltage (V)
5
2
+VBD = 2.7 V, +VA = 5 V, fIN = 1.9 kHz, fS = 250 kSPS, TA = 30°C
2.5
3
3.5
4
4.5
Reference Voltage (V)
C023
5
C024
+VBD = 2.7 V, +VA = 5 V, fIN = 1.9 kHz, fS = 250 kSPS, TA = 30°C
Figure 23. SINAD vs Reference Voltage
Figure 24. SNR vs Reference Voltage
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Typical Characteristics (continued)
At TA = 30°C, +VA = 5 V, +VBD = 2.7 V, Vref = 4.096 V, and fsample = 250 kHz, unless otherwise noted.
119
Spurious-Free Dynamic Range (dB)
Total Harmonic Distortion (dB)
119
117
115
113
111
109
107
105
117
115
113
111
109
107
105
103
2
2.5
3
3.5
4
4.5
Reference Voltage (V)
5
±40
40
60
80
100
C026
Figure 26. SFDR vs Free-Air Temperature
96
96
95
95
Signal-to-Noise Ratio (dB)
Signal-to-Noise and Distortion (dB)
20
+VBD = 2.7 V, +VA = 5 V, Vref = 5 V, fIN = 1.9 kHz,
fS = 250 kSPS
Figure 25. THD vs Reference Voltage
94
93
92
91
90
94
93
92
91
90
±40
±20
0
20
40
60
80
Free-Air Temperature (ƒC)
100
±40
±20
0
20
40
60
80
100
Free-Air Temperature (ƒC)
C027
+VBD = 2.7 V, +VA = 5 V, Vref = 5 V, fIN = 1.9 kHz,
fS = 250 kSPS
C028
+VBD = 2.7 V, +VA = 5 V, Vref = 5 V, fIN = 1.9 kHz,
fS = 250 kSPS
Figure 27. SINAD vs Free-Air Temperature
Figure 28. SNR vs Free-Air Temperature
117
95
Signal-to-Noise and Distortion (dB)
Total Harmonic Distortion (dB)
0
Free-Air Temperature (ƒC)
+VBD = 2.7 V, +VA = 5 V, fIN = 1.9 kHz, fS = 250 kSPS, TA = 30°C
115
113
111
109
107
105
103
SINAD at ±10 dB
94
SINAD at ±0.5 dB
93
92
91
90
89
88
87
±40
±20
0
20
40
60
80
Free-Air Temperature (ƒC)
100
1
10
Signal Input Frequency (kHz)
C029
+VBD = 2.7 V, +VA = 5 V, Vref = 5 V, fIN = 1.9 kHz,
fS = 250 kSPS
Figure 29. THD vs Free-Air Temperature
12
±20
C025
100
C030
+VBD = 2.7 V, +VA = 5 V, Vref = 5 V, fS = 250 kSPS, TA = 30°C
Figure 30. SINAD vs Signal Input Frequency
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Typical Characteristics (continued)
At TA = 30°C, +VA = 5 V, +VBD = 2.7 V, Vref = 4.096 V, and fsample = 250 kHz, unless otherwise noted.
300000
THD at ±10 dB
262043
THD at ±0.5 dB
125
250000
115
Number of Hits
Total Harmonic Distortion (dB)
135
105
95
200000
150000
100000
85
50000
75
0
101
C031
32767
100
Signal Input Frequency (kHz)
32766
10
32765
1
0
Codes
+VBD = 2.7 V, +VA = 5 V, Vref = 5 V, fS = 250 kSPS, TA = 30°C
C032
+VBD = 2.7 V, +VA = 5 V, Vref = 5 V, fS = 250 kSPS, TA = 30°C
Figure 32. DC Histogram of ADC Close-to-Center Code
Figure 31. THD vs Signal Input Frequency
3.5
0 pF
100 pF
680 pF
112
3.45
IVA Supply Current (mA)
Total Harmonic Distortion (dB)
114
110
108
106
104
3.4
3.35
3.3
3.25
102
100
3.2
0
100
200
300
400
500
Source Resistance (
600
4.5
+VBD = 2.7 V, +VA = 5 V, Vref = 5 V, fIN = 1.9 kHz,
fS = 250 kSPS, TA = 30°C
5
5.25
5.5
Supply Voltage (V)
C034
+VBD = 2.7 V, Vref = 4.096 V, fS = 250 kSPS, TA = 30°C
Figure 33. THD vs Source Resistance
Figure 34. Supply Current vs Supply Voltage
3.8
4
3.7
3.5
3.6
IVA Supply Current (mA)
IVA Supply Current (mA)
4.75
C033
3.5
3.4
3.3
3.2
3.1
3.0
3
2.5
2
1.5
1
0.5
2.9
2.8
0
±40
±20
0
20
40
60
80
Free-Air Temperature (ƒC)
100
0
+VBD = 2.7 V, +VA = 5 V, fS = 250 kSPS
Figure 35. Supply Current vs Free-Air Temperature
50
100
150
200
Sampling Frequency (kSPS)
C035
250
C036
+VBD = 2.7 V, +VA = 5 V, TA = 30°C
Figure 36. Supply Current vs Sampling Frequency
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Typical Characteristics (continued)
20
15
18
14
IVA Power-Down Current (nA)
IVA Power Dissipation (mW)
At TA = 30°C, +VA = 5 V, +VBD = 2.7 V, Vref = 4.096 V, and fsample = 250 kHz, unless otherwise noted.
16
14
12
10
8
6
4
2
13
12
11
10
9
8
7
6
0
5
0
50
100
150
200
250
Sampling Frequency (kSPS)
4.5
4.75
5
5.25
5.5
Supply Voltage (V)
C037
+VBD = 2.7 V, +VA = 5 V, Vref = 5 V, TA = 30°C
C038
+VBD = 2.7 V, Vref = 4.096 V, fS = 250 kSPS, TA = 30°C
Figure 37. Power Dissipation vs Sampling Frequency
Figure 38. Power-Down Current vs Supply Voltage
60
1.
1
0.6
0.4
40
DNL (LSB)
IVA Power-Down Current (nA)
0.8
50
30
20
0.2
0.
0
±0.2
±0.4
±0.6
10
±0.8
0
±1
±40
±20
0
20
40
60
80
100
Free-Air Temperature (ƒC)
0
+VBD = 2.7 V, +VA = 5 V, Vref = 4.096 V, fS = 250 kSPS
30000
40000
50000
60000
C040
+VBD = 2.7 V, +VA = 5 V, Vref = 5 V, fS = 250 kSPS, TA = 30°C
Figure 40. DNL Error vs Output Code
1.
1
0
0.8
±20
0.6
±40
0.4
±60
Amplitude (dB)
INL (LSB)
20000
Codes
Figure 39. Power-Down Current vs Free-Air Temperature
0.2
0.
0
±0.2
±80
±100
±120
±0.4
±140
±0.6
±160
±0.8
±180
±1
±200
0
10000
20000
30000
40000
50000
Codes
0
60000
50000
100000
150000
200000
Frequency (Hz)
C041
+VBD = 2.7 V, +VA = 5 V, Vref = 5 V, fS = 250 kSPS, TA = 30°C
250000
C042
+VBD = 2.7 V, +VA = 5 V, Vref = 5 V, fIN = 1.9 kHz,
fS = 250 kSPS, TA = 30°C
Figure 41. INL Error vs Output Code
14
10000
C039
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Figure 42. Signal Strength vs Frequency
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8 Parametric Measurement Information
8.1 Timing Diagrams
500 mA
IOL
From SDO
1.4 V
20 pF
500 mA
IOH
Figure 43. Digital Interface Timing Load Circuit
0.7 VBD
0.3 VBD
tDELAY
tDELAY
2V
2V
0.8 V
0.8 V
Figure 44. Timing Voltage Levels
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9 Detailed Description
9.1 Overview
The ADS8339 is a 250-kSPS, low-power, successive-approximation register (SAR), analog-to-digital converter
(ADC) that uses an external reference. The architecture is based on charge redistribution, which inherently
includes a sample-and-hold function.
The ADS8339 is a single-channel device. The analog input is provided to two input pins: +IN and –IN, where –IN
is a pseudo-differential input and has a limited range of ±0.1 V. When a conversion is initiated, the differential
input on these pins is sampled on the internal capacitor array. While a conversion is in progress, both the +IN
and –IN inputs are disconnected from any internal functions.
The device has an internal clock that is used to run the conversion. Therefore, the conversion requires a fixed
amount of time. After a conversion is completed, the device reconnects the sampling capacitors to the +IN and
–IN pins and the device is in the acquisition phase. During this phase, the device is powered down and
conversion data can be read.
The device digital output is available in SPI-compatible format. The device easily interfaces with
microprocessors, digital signal processors (DSPs), or field-programmable gate arrays (FPGAs).
9.2 Functional Block Diagram
+VBD
+VA
SAR
Output
Drive
SDO
Input
Shift
Register
SDI
Comparator
IN+
CDAC
IN-
REFIN
Conversion and I/O
Control Logic
SCLK
Device
GND
16
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CONVST
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9.3 Feature Description
9.3.1 Analog Input
When the converter samples the input, the voltage difference between the +IN and –IN inputs is captured on the
internal capacitor array. The differential signal range is [(+IN) – (–IN)]. The voltage on +IN is limited between
GND – 0.1 V and Vref + 0.1 V and the voltage on –IN is limited between GND – 0.1 V to GND + 0.1 V. The input
rejects any small signal that is common to both the +IN and –IN input.
The (peak) input current through the analog input depends upon a number of factors: sample rate, input voltage,
and source impedance. The current into the device charges the internal capacitor array (as shown in Figure 45)
during the sample period. When this capacitance is fully charged, there is no further input current. The source of
the analog input voltage must be able to charge the input capacitance (59 pF) to a 18-bit settling level within the
minimum acquisition time. When the converter goes into hold mode, the input impedance is greater than 1 GΩ.
Care must be taken regarding the absolute analog input voltage. To maintain linearity of the converter, the +IN
input, –IN input, and span [+IN – (–IN)] must be within the limits specified. Outside of these ranges, the converter
linearity may not meet specifications.
Care must also be taken to ensure that the output impedance of the sources driving the +IN input and the –IN
input is matched. If this output impedance is not well matched, the two inputs can have different settling times.
This mismatch may result in an offset error, gain error, and linearity error that changes with temperature and
input voltage. Typically, the –IN input is grounded at the input decoupling capacitor.
Device in Hold Mode
218 W
+IN
55 pF
4 pF
+VA
AGND
4 pF
218 W
-IN
55 pF
Figure 45. Input Equivalent Circuit
9.3.2 Power Saving
The device has an auto power-down feature. The device powers down at the end of every conversion. The input
signal is acquired on sampling capacitors when the device is in power-down state. At the same time, the
conversion results are available for reading. The device powers up automatically at the start of the conversion.
The conversion runs on an internal clock and requires a fixed time. As a result, device power consumption is
directly proportional to the speed of operation.
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Feature Description (continued)
9.3.3 Digital Output
As discussed in the Description and Timing Diagrams sections, the device digital output is SPI-compatible.
Table 1 lists the output codes corresponding to various analog input voltages.
Table 1. Output Codes
DESCRIPTION
ANALOG VALUE (V)
Full-scale range
Least significant bit (LSB)
Positive full-scale
Mid-scale
Mid-scale – 1 LSB
Zero
DIGITAL OUTPUT STRAIGHT BINARY
BINARY CODE
HEX CODE
—
Vref
—
Vref / 65536
—
—
+Vref – 1 LSB
1111 1111 1111 1111
FFFF
Vref / 2
1000 0000 0000 0000
8000
Vref / 2 – 1 LSB
0111 1111 1111 1111
7FFF
0
0000 0000 0000 0000
0000
9.3.4 SCLK Input
The device uses SCLK for the serial data output. Data are read after the conversion is complete and the device
is in acquisition phase. A free-running SCLK can be used, but TI recommends stopping the clock during
conversion time because the clock edges can couple with the internal analog circuit that, in turn, can affect the
conversion results.
9.4 Device Functional Modes
The ADS8339 supports three interface options. Under each option, the device can be used with or without a
busy indicator.
1. CS mode for a 3-wire interface (with or without a busy indicator): This mode is useful for applications where
a single ADS8339 device is connected to the digital host.
2. CS mode for a 4-wire interface (with or without a busy indicator): This mode can be used when more than
one ADS8339 device is connected to the digital host on a common data bus.
3. Daisy-chain mode (with or without a busy indicator): This mode is provided to connect multiple ADS8339
devices in a chain (such as a shift register) and is useful when reducing the number of signal traces on the
board or the component count.
The busy indicator is generated as the bit preceding the 16-bit serial data.
18
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Device Functional Modes (continued)
9.4.1 CS Mode for a 3-Wire Interface
CS mode is selected if SDI is high at the CONVST rising edge. As previously indicated, the device can be used
without or with a busy indicator. This section discusses this interface and the two options in detail.
9.4.1.1 3-Wire CS Mode Without a Busy Indicator
In a 3-wire CS mode, SDI is permanently tied to +VBD, as shown in Figure 46. CONVST functions like CS. As
shown in Figure 47, the device samples the input signal and enters the conversion phase on the CONVST rising
edge. SDO goes to 3-state at the same time. Conversion is done with the internal clock and continues regardless
of the state of CONVST. As a result, CONVST (functioning as CS) can be brought low after the start of the
conversion to select other devices on the board.
CONVST must return to high before the minimum conversion time (tcnv_min in the Timing Requirements table)
elapses. A high level on CONVST at the end of the conversion ensures the device does not generate a busy
indicator.
Digital Host
Device
+VBD
SDI
CONVST
CNV
SCLK
CLK
SDO
SDI
Figure 46. Connection Diagram: 3-Wire CS Mode without a Busy Indicator (SDI = 1)
t cyc
t1
CONVST
t cnv_min
t cnv
Phase
Acquisition
t acq
Conversion
Acquisition
t clkl
t2
SCLK
1
15
16
t clkh
t en
t3
D15
SDO
2
D14
t dis
t clk
D1
D0
Figure 47. Interface Timing Diagram: 3-Wire CS Mode Without a Busy Indicator (SDI = 1)
When the conversion is complete, the device enters acquisition phase and powers down. On the CONVST falling
edge, SDO comes out of 3-state and the device outputs the MSB of the data. Afterwards, the device outputs the
next lower data bits on every subsequent SCLK falling edge. A minimum of 15 SCLK falling edges must occur
during the low period of CONVST. SDO goes to 3-state after the 16th SCLK falling edge or when CONVST is
high, whichever occurs first.
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Device Functional Modes (continued)
9.4.1.2 3-Wire CS Mode With a Busy Indicator
As stated in the 3-Wire CS Mode Without a Busy Indicator section, SDI is permanently tied to +VBD, as shown in
Figure 48. CONVST functions like CS. As shown in Figure 49, the device samples the input signal and enters the
conversion phase on the CONVST rising edge. SDO goes to 3-state at the same time. Conversion is done with
the internal clock and continues regardless of the state of CONVST. As a result, CONVST (functioning as CS)
can be toggled after the start of the conversion to select other devices on the board.
CONVST must return to low before the minimum conversion time (tcnv_min in the Timing Requirements table)
elapses and remains low until the end of the maximum conversion time. A low level on the CONVST input at the
end of a conversion ensures the device generates a busy indicator (low level on SDO). For fast settling, a 10-kΩ
pull-up resistor tied to +VBD is recommended to provide the necessary current to drive SDO low.
Digital Host
Device
CNV
CONVST
+VBD
SDI
CLK
SCLK
+VBD
SDO
SDI
IRQ
Figure 48. Connection Diagram: 3-Wire CS Mode With a Busy Indicator
t cyc
t1
CONVST
t cnv_min
t acq
t cnv
Phase
Acquisition
Conversion
Acquisition
t clkl
t2
SCLK
1
2
3
16
17
t clkh
t3
D 15
SDO
D 14
t dis
t clk
D1
D0
Figure 49. Interface Timing Diagram: 3-Wire CS Mode With a Busy Indicator (SDI = 1)
When the conversion is complete, the device enters acquisition phase, powers down, forces SDO out of 3-state,
and outputs a busy indicator bit (low level). The device outputs the MSB of data on the first SCLK falling edge
after the conversion is complete and continues to output the next lower data bits on every subsequent SCLK
falling edge. A minimum of 16 SCLK falling edges must occur during the low period of CONVST. SDO goes to 3state after the 17th SCLK falling edge or when CONVST is high, whichever occurs first.
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Device Functional Modes (continued)
9.4.2 CS Mode for a 4-Wire Interface
This interface is similar to the CS mode for 3-wire interface except that SDI is controlled by the digital host. This
section discusses in detail the interface option with and without a busy indicator.
9.4.2.1 4-Wire CS Mode Without a Busy Indicator
As mentioned previously, in order to select CS mode, SDI must be high at the time of the CONVST rising edge.
Unlike in the 3-wire interface option, SDI is controlled by the digital host and functions like CS. As shown in
Figure 50, SDI goes to a high level before the CONVST rising edge. When SDI is high, the CONVST rising edge
selects CS mode, forces SDO to 3-state, samples the input signal, and the device enters the conversion phase.
In the 4-wire interface option, CONVST must be at a high level from the start of the conversion until all data bits
are read. Conversion is done with the internal clock and continues regardless of the state of SDI. As a result, SDI
(functioning as CS) can be brought low to select other devices on the board.
SDI must return to high before the minimum conversion time (tcnv_min in the Timing Requirements table) elapses.
t6
CONVST
SDI (CS) 1
t4
t5
SDI (CS) 2
t cnv_min
tacq
tcnv
Phase
Acquisition
Conversion
ten
Acquisition
tclkl
t2
SCLK
1
2
16
tclkh
ten
t3
D15 #1
SDO
15
D14 #1
17
18
31
tdis
32
tdis
tclk
D1 #1
D0 #1
D15 #2
D14 #2
D1 #2
D0 #2
Figure 50. Interface Timing Diagram: 4-Wire CS Mode Without a Busy Indicator
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Device Functional Modes (continued)
When the conversion is complete, the device enters the acquisition phase and powers down. An SDI falling edge
can occur after the maximum conversion time (tcnv in the Timing Requirements table). Note that SDI must be high
at the end of the conversion so that the device does not generate a busy indicator. The SDI falling edge brings
SDO out of 3-state and the device outputs the MSB of the data. Subsequently, the device outputs the next lower
data bits on every subsequent SCLK falling edge. SDO goes to 3-state after the 16th SCLK falling edge or when
SDI (CS) is high, whichever occurs first. As shown in Figure 51, multiple devices can be chained on the same
data bus. In this case, the second device SDI (functioning as CS) can go low after the first device data are read
and the device 1 SDO is in 3-state.
Care must be taken so that CONVST and SDI are not both low at any time during the cycle.
CS1
CS2
CNV
CONVST
SDI
SDI
CONVST
SDI
SDO
SDO
SCLK
SCLK
Device 1
Device 2
CLK
Digital Host
Figure 51. Connection Diagram: 4-Wire CS Mode Without a Busy Indicator
9.4.2.2 4-Wire CS Mode With a Busy Indicator
As mentioned previously, in order to select CS mode, SDI must be high at the time of the CONVST rising edge.
In this mode of operation, the connection is made as shown in Figure 52.
CS
SDI
CNV
CONVST
SCLK
SDO
Device
+VBD
CLK
SDI
IRQ
Digital Host
Figure 52. Connection Diagram: 4-Wire CS Mode With a Busy Indicator
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Device Functional Modes (continued)
Unlike in the 3-wire interface option, SDI is controlled by the digital host and functions like CS. As shown in
Figure 53, SDI goes to a high level before the CONVST rising edge. When SDI is high, the CONVST rising edge
selects the CS mode, forces SDO to 3-state, samples the input signal, and the device enters the conversion
phase.
In the 4-wire interface option, CONVST must be at a high level from the start of the conversion until all data bits
are read. Conversion is done with the internal clock and continues regardless of the state of SDI. As a result, SDI
(functioning as CS) can be toggled to select other devices on the board.
SDI must return low before the minimum conversion time (tcnv_min in the Timing Requirements table) elapses and
must remain low until the end of the maximum conversion time. A low level on the SDI input at the end of a
conversion ensures the device generates a busy indicator (low on SDO). For fast settling, a 10-kΩ pull-up
resistor tied to +VBD is recommended to provide the necessary current to drive SDO low.
t cyc
t6
CNVST
t5
SDI ( CS )
t4
t cnv_min
t acq
t cnv
Phase
Acquisition
Conversion
Acquisition
t clkh
t2
SCLK
1
2
3
16
17
t clkl
t3
t dis
t clk
SDO
D 15
D 14
D1
D0
Figure 53. Interface Timing Diagram: 4-Wire CS Mode With a Busy Indicator
When the conversion is complete, the device enters acquisition phase, powers down, forces SDO out of 3-state,
and outputs a busy indicator bit (low level). The device outputs the MSB of the data on the first SCLK falling
edge after the conversion is complete and continues to output the next lower data bits on every subsequent
SCLK falling edge. SDO goes to 3-state after the 17th SCLK falling edge or when SDI (CS) is high, whichever
occurs first.
Care must be taken so that CONVST and SDI are not both low at any time during the cycle.
9.4.3 Daisy-Chain Mode
Daisy-chain mode is selected if SDI is low at the time of the CONVST rising edge. This mode is useful to reduce
wiring and hardware requirements (such as digital isolators in applications where multiple ADC devices are
used). In this mode, all devices are connected in a chain (the SDO of one device is connected to the SDI of the
next device) and data transfer is analogous to a shift register.
As in CS mode, this mode offers operation with or without a busy indicator. This section discusses these
interface options in detail.
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Device Functional Modes (continued)
9.4.3.1 Daisy-Chain Mode Without a Busy Indicator
A connection diagram for this mode is shown in Figure 54. The SDI for device 1 is tied to ground and the SDO of
device 1 goes to the SDI of device 2, and so on. The SDO of the last device in the chain goes to the digital host.
CONVST for all devices in the chain are tied together. There is no CS signal in this mode.
CNV
CONVST
SDI
CONVST
SDO
SDI
SDO
SCLK
SCLK
Device 1
Device 2
SDI
CLK
Digital Host
Figure 54. Connection Diagram: Daisy-Chain Mode Without a Busy Indicator (SDI = 0)
The device SDO is driven low when SDI low selects daisy-chain mode and the device samples the analog input
and enters the conversion phase. SCLK must be low at the CONVST rising edge (as shown in Figure 55) so that
the device does not generate a busy indicator at the end of the conversion. In this mode, CONVST remains high
from the start of the conversion until all data bits are read. When started, the conversion continues regardless of
the state of SCLK.
tcyc
CONVST
t6
tcnv
Phase
Acquisition
tacq
Conversion
Acquisition
t7
t2
SCLK
1
tclkl
2
15
16
17
18
31
32
#1-D1
#1-D0
tclkh
t8
tclk
SDO 1, SDI 2
#1-D15
#1-D14
#1-D1
#1-D0
#2-D1
#2-D0
t3
SDO 2
#2-D15
#2-D14
#1-D15 #1-D14
Figure 55. Interface Timing Diagram: Daisy-Chain Mode Without a Busy Indicator
At the end of the conversion, every device in the chain initiates an output of its conversion data starting with the
MSB bit. Furthermore, the next lower data bit is output on every subsequent SCLK falling edge. While every
device outputs its data on the SDO pin, each device also receives the previous device data on the SDI pin (other
than device 1) and stores the data in the shift register. The device latches incoming data on every SCLK falling
edge. The SDO of the first device in the chain goes low after the 16th SCLK falling edge. All subsequent devices
in the chain output the stored data from the previous device in MSB-first format immediately following their own
data word. 16 × N clocks must read data for N devices in the chain.
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Device Functional Modes (continued)
9.4.3.2 Daisy-Chain Mode With a Busy Indicator
A connection diagram for this mode is shown in Figure 56. The SDI for device 1 is wired to its CONVST and the
CONVST for all devices in the chain are wired together. The SDO of device 1 goes to the SDI of device 2, and
so on. The SDO of the last device in the chain goes to the digital host. There is no CS signal in this mode.
CNV
CONVST
+VBD
CONVST
SDI
SDO
SDI
SDO
SCLK
SCLK
Device 1
Device 2
SDI
IRQ
CLK
Digital Host
Figure 56. Connection Diagram: Daisy Chain Mode With a Busy Indicator (SDI = 0)
On the CONVST rising edge, all devices in the chain sample the analog input and enter the conversion phase.
For the first device, SDI and CONVST are wired together and the setup time of SDI to the CONVST rising edge
is adjusted so that the device still enters daisy-chain mode even though SDI and CONVST rise together. SCLK
must be high at the CONVST rising edge (as shown in Figure 57) so that the device generates a busy indicator
at the end of the conversion. In this mode, CONVST remains high from the start of the conversion until all data
bits are read. When started, the conversion continues regardless of the state of SCLK.
tcyc
t6
CONVST
tcnv
Phase
Acquisition
tacq
Conversion
Acquisition
t7
tclkl
t2
1
SCLK
2
3
t8
#1-D15
SDO 1, SDI 2
16
tclk
#1-D14
17
18
19
32
33
#1-D1
#1-D0
t clkh
#1-D1
#1-D0
#2-D1
#2-D0
t3
#2-D15
SDO 2
#2-D14
#1-D15 #1-D14
Figure 57. Interface Timing Diagram: Daisy Chain Mode With a Busy Indicator
At the end of the conversion, all devices in the chain generate busy indicators. On the first SCLK falling edge
following the busy indicator bit, all devices in the chain output their conversion data starting with the MSB bit.
Afterwards, the next lower data bit is output on every SCLK falling edge. While every device outputs its data on
the SDO pin, each device also receives the previous device data on the SDI pin (except for device 1) and stores
the data in the shift register. Each device latches incoming data on every SCLK falling edge. The SDO of the first
device in the chain goes high after the 17th SCLK falling edge. All subsequent devices in the chain output the
stored data from the pervious device in MSB-first format immediately following their own data word. 16 × N + 1
clock pulses are required to read data for N devices in the chain.
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10 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Application Information
To obtain the best performance from a high-precision successive approximation register (SAR) analog-to-digital
converter (ADC), the reference driver and the input driver circuit must be optimized. This section details general
principles for designing such drivers, followed by typical application circuits designed using the ADS8339.
10.1.1 ADC Reference Driver
A simplified circuit diagram for such a reference driver is shown in Figure 58.The external voltage reference must
provide a low-noise, low-drift, highly-accurate voltage for the ADC reference input pin. The output broadband
noise of most voltage references can be in the order of a few hundred μVRMS, which degrades the conversion
result. To prevent any noticeable degradation in the noise performance of the ADC, the noise from the voltage
reference must be filtered. This filtering can be done by using a low-pass filter with a cutoff frequency of a few
hundred hertz.
RREF_FLT
Buffer
CREF_FLT
RBUF_FLT
Voltage
Reference
REFIN
ADC
CBUF_FLT
Figure 58. Reference Driver Schematic
During the conversion process, the ADS8339 switches binary-weighted capacitors onto the reference pin
(REFIN). The switching frequency is proportional to the internal conversion clock frequency. The dynamic charge
required by the capacitors is a function of the ADC input voltage and the reference voltage. Design the reference
driver circuit such that the dynamic loading of the capacitors can be handled without degrading the noise and
linearity performance of the ADC.
When the noise of the voltage reference is band-limited the next step is to design a reference buffer that can
drive the dynamic load posed during the conversion cycle. The buffer must regulate the voltage at the REFIN pin
of the device such that the reference voltage to the ADC stays within 1 LSB of an error at the start of each
conversion. This condition necessitates the use of a large capacitor, CBUF_FLT (as shown in Figure 58). The
amplifier selected as the buffer must have very low offset, temperature drift, and output impedance to drive the
internal binary-weighted capacitors at the REFIN pin of the ADC without any stability issues.
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Application Information (continued)
10.1.1.1 Reference Driver Circuit
A more detailed circuit shows the schematic (as shown in Figure 59) of a complete reference driver circuit that
generates 4.5 V dc using a single 5-V supply. This circuit can drive the reference pin of the ADS8339 at
sampling rates of up to 250 kSPS. The 4.5-V reference voltage is generated using a high-precision, low-noise
REF5045. The output broadband noise of the reference is further filtered using a low-pass filter with a 3-dB cutoff
frequency of 16 Hz.
20 k
AVDD
1 µF
REF5045
-
VIN
-
1 µF
+
10 k
GND
1k
+
OUT
+
OPA333
+
AVDD
THS4281
0.2
1 µF
AVDD
REFIN
AVDD
1 µF
10 µF
+VA
IN+
V+
Device
-IN
GND
Figure 59. Reference Driver Circuit Schematic
The driver also includes a THS4281 and an OPA333. This composite architecture provides superior ac and dc
performance at reduced power levels compared to a single high-performance amplifier.
The THS4281 is a high-bandwidth amplifier with very low output impedance of 1 Ω at a frequency of 1 MHz. The
low output impedance makes the THS4281 a good choice for driving large capacitive loads. The high offset and
drift specifications of the THS4281 are corrected using a dc-correcting amplifier (OPA333) inside the feedback
loop. Thus, the composite scheme also inherits the extremely low offset and temperature drift specifications of
the OPA333.
10.1.2 ADC Input Driver
The input driver circuit for a high-precision ADC mainly consists of two parts: a driving amplifier and an RC filter.
An amplifier is used for signal conditioning the input voltage. The low output impedance of the amplifier functions
as a buffer between the signal source and the sampling capacitor input of the ADC. The RC filter functions as an
antialiasing filter that band-limits the wideband noise contributed by the front-end circuit. The RC filter also helps
attenuate the sampling capacitor charge injection from the switched-capacitor input stage of the ADC. Careful
design of the front-end circuit is critical to meet the linearity and noise performance of a high-precision, 16-bit
ADC such as the ADS8339.
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Application Information (continued)
10.1.2.1 Input Amplifier Selection
Selection criteria for the input amplifier is dependent on the input signal type as well as performance goals of the
data acquisition system. Some key specifications to consider when selecting an amplifier to drive the inputs of
the ADS8339 are:
• Small-signal bandwidth. The small-signal bandwidth of the input amplifier must be as high as possible for a
given power budget. Higher bandwidth reduces the closed-loop output impedance of the amplifier, thus
allowing the amplifier to more easily drive the RC filter (with low cutoff frequency) at the inputs of the ADC.
Higher bandwidth also minimizes harmonic distortion at higher input frequencies. In order to maintain overall
stability, the amplifier bandwidth must satisfy Equation 1:
§
1
Unity Gain Bandwidth t 4 u ¨¨
© 2S u ( RFLT RFLT ) u C FLT
•
·
¸¸
¹
(1)
Noise. Noise contribution of the front-end amplifiers must be as low as possible to prevent any degradation in
the overall SNR performance of the system. As a rule of thumb, to ensure that the noise performance of the
data acquisition system is not limited by the front-end circuit, keep the total noise contribution from the frontend circuit below 20% of the input-referred noise of the ADC. Noise from the input driver circuit gets bandlimited by the RC filter, as given in Equation 2.
2
§ V 1 _ AM P_ PP ·
S
¨
¸
NG u 2 u ¨ f
en2 _ RM S u u f3dB
¸
6.6
2
¨
¸
©
¹
d
§ SNR dB ·
¸
20
¹
¨
1 VREF
u
u 10 ©
5
2
where:
•
•
•
•
•
V1 / f_AMP_PP is the peak-to-peak flicker noise in µV,
en_RMS is the amplifier broadband noise density in nV/√Hz,
f–3dB is the 3-dB bandwidth of the RC filter, and
NG is the noise gain of the front-end circuit, which is equal to 1 in a buffer configuration.
Distortion. The ADC and the input driver introduce nonlinearity in a data acquisition block. As a rule of thumb,
to ensure that the distortion performance of the data acquisition system is not limited by the front-end circuit,
the distortion of the input driver must be at least 10 dB lower than the distortion of the ADC, as given in
Equation 3.
THD AMP d THD ADC 10 dB
•
(2)
(3)
Settling Time. For dc signals with fast transients that are common in a multiplexed application, the input signal
must settle to a 16-bit accuracy level at the device inputs during the acquisition time. This condition is critical
in maintaining the overall linearity of the ADC. Typically, the amplifier data sheets specify the output settling
performance only up to 0.1% to 0.001%, which may not be sufficient for the desired 16-bit accuracy.
Therefore, the settling behavior of the input driver must always be verified by TINA™-SPICE simulations
before selecting the amplifier.
10.1.2.2 Antialiasing Filter
Converting analog-to-digital signals requires sampling the input signal at a constant rate. Any frequency content
in the input signal that is beyond half the sampling frequency is folded back into the low-frequency spectrum,
which is undesirable. This process is called aliasing. An analog antialiasing filter must be used to remove the
high-frequency component (beyond half the sampling frequency) from the input signal before being sampled by
the ADC.
An antialiasing filter is designed as a low-pass, RC filter for which the 3-dB bandwidth is optimized based on
specific application requirements. For dc signals with fast transients (including multiplexed input signals), a highbandwidth filter is designed to allow for accurate settling of the signal at the input of the ADC. For ac signals,
keep the filter bandwidth as low as possible to band-limit the noise fed into the ADC, which improves the signalto-noise ratio (SNR) performance of the system.
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Application Information (continued)
The RC filter also helps absorb the sampling charge injection from the switched-capacitor input of the ADC. A
filter capacitor, CFLT, is connected across the inputs of the ADC (as shown in Figure 60). This capacitor helps
absorb the sampling capacitor charge injection in addition to functioning as a charge bucket to quickly charge the
internal sample-and-hold capacitors during the acquisition phase.
When selecting this capacitor, as a rule of thumb, the capacitor value must be at least 10 times the ADC
sampling capacitor specified on the data sheet. The input sampling capacitance is approximately 59 pF for the
ADS8339. The value of CFLT must be greater than 590 pF. The capacitor must be a COG- or NPO-type because
these capacitor types have a high-Q, low-temperature coefficient and stable electrical characteristics under
varying voltages, frequency, and time.
RFLT ”44
f 3 dB
2S u R FLT
1
R FLT u CFLT
VIN+
+
CFLT •590 pF
Device
-IN
GND
RFLT ”44
Figure 60. Antialiasing Filter
NOTE
Driving capacitive loads can degrade the phase margin of the input amplifiers, thus
making the amplifier marginally unstable. To avoid stability issues, series isolation
resistors (RFLT) are used at the output of the amplifiers. A higher value of RFLT is helpful
from the amplifier stability perspective. Distortion increases with source impedance, input
signal frequency, and input signal amplitude. The selection of RFLT thus requires a balance
between stability and distortion of the design.
TI recommends limiting the value of RFLT to a maximum of 44 Ω in order to avoid any
significant degradation in linearity performance for the ADS8339. The tolerance of
resistors can be 1% because the differential capacitor at the input balances the effects
resulting from resistor mismatch.
The input amplifier bandwidth must be much higher than the cutoff frequency of the
antialiasing filter. TI strongly recommends running a SPICE simulation to confirm that the
amplifier has more than 40° phase margin with the filter that is designed. Simulation is
critical because some amplifiers may require more bandwidth than others to drive similar
filters. If an amplifier has less than 40° phase margin with 44-Ω resistors, using a different
amplifier with higher bandwidth or reducing the filter cutoff frequency with a larger
differential capacitor is advisable.
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10.2 Typical Application
This section describes a typical application circuit using the ADS8339. The circuit is optimized to derive the best
ac performance. For simplicity, power-supply decoupling capacitors are not shown in these circuit diagrams.
Reference Drive Circuit
20 k:
1 PF
-
THS4281
+
0.2 :
-
1 k:
+
AVDD
OPA333
1 PF
+
1 k:
+
Vout
AVDD
AVDD
10 PF
REF5045
Vin
1 PF
1 PF
GND
Input Driver
1 k:
1 k:
AVDD
16-Bit, 250-kSPS
SAR ADC
AVDD
VIN
-
+
4.7 :
OPA836
+
VCM
REFIN
IN+
V+
10 nF
AVDD
CONVST
Device
IN
4.7 :
GND
CONVST
Figure 61. Single-Ended Input DAQ Circuit for Lowest Distortion and Noise at 250 kSPS
10.2.1 Design Requirements
The application circuit for the ADS8339 (as shown in Figure 61) is optimized for lowest distortion and noise for a
10-kHz input signal to achieve:
• –106-dB THD and 93-dB SNR at a maximum specified throughput of 250 kSPS.
10.2.2 Detailed Design Procedure
In the application circuit, the input signal is processed through a high-bandwidth, low-distortion, inverting amplifier
and a low-pass RC filter before being fed to the ADC.
The reference driver circuit illustrated in Figure 59 generates 4.5 V dc using a single 5-V supply. This circuit is
suitable to drive the reference at sampling rates of up to 250 kSPS. To keep the noise low, a high-precision
REF5045 is used. The output broadband noise of the reference is heavily filtered by a low-pass filter with a 3-dB
cutoff frequency of 16 Hz.
The reference buffer is designed in a composite architecture to achieve superior dc and ac performance at
reduced power consumption. The low output impedance makes the THS4281 a good choice for driving large
capacitive loads that regulate the voltage at the reference input pin of the ADC. The high offset and drift
specifications of the THS4281 are corrected by using a dc-correcting amplifier (such as the OPA333) inside the
feedback loop.
For the input driver, as a rule of thumb, the distortion of the amplifier must be at least 10 dB less than the ADC
distortion. The distortion resulting from variation in the common-mode signal is eliminated by using the driver in
an inverting gain configuration. This configuration also eliminates the need for an amplifier that supports rail-torail input. The OPA836 is a good choice for an input driver because of its low-power consumption and
exceptional ac performance (such as low distortion and high bandwidth).
Finally, the components of the antialiasing filter are chosen such that the noise from the front-end circuit is kept
low without adding distortion to the input signal.
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Typical Application (continued)
10.2.3 Application Curve
To ensure that the circuit meets the design requirements, the dc noise performance and the frequency content of
the digitized output is verified. The input is set to a fixed dc value at half the reference. The histogram of the
output code shows a peak-to-peak noise distribution of four codes which translates to 14 bits of noise-free bits.
An ac signal at 10 kHz is then fed to the input. The FFT of the output shows a THD of –106 dB and an SNR of
92 dB, which is close to the design requirements.
1800
1685
1600
1200
Power (dBc)
Hits Per Code
1400
1000
800
600
400
200
0
290
72
32760
1
32761
32762
32763
0
±10
±20
±30
±40
±50
±60
±70
±80
±90
±100
±110
±120
±130
±140
±150
HD2 -107.45
0
25
ADC Output Code
VDIFF = Vref / 2, 2048 data points, standard deviation = 0.41 bits
Figure 62. DC Input Histogram at Mid-Code
50
75
100
Frequency (kHz)
C043
125
C044
SNR = 92 dB, THD = – 106 dB, number of samples = 1024
Figure 63. 0.4-dBFS, 10-kHz Sine Input FFT
10.3 Do's and Don'ts
•
•
Use multiple capacitors to decouple the dynamic current transients at various input pins including the
reference, supply, and input signal.
Parasitic inductance can induce ringing on the clock signal. Include a resistor on the SCLK pin to clean up the
clock edges.
11 Power-Supply Recommendations
The ADS8339 is designed to operate from an analog supply voltage range between 4.5 V and 5.5 V and a digital
supply voltage range between 2.375 V and 5.5 V. Both supplies must be well regulated. The analog supply must
always be greater than or equal to the digital supply. A 1-μF ceramic decoupling capacitor is required at each
supply pin and must be placed as close as possible to the device.
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12 Layout
12.1 Layout Guidelines
Figure 64 shows one of the board layouts as an example when using ADS8339 in a circuit.
• A printed circuit board (PCB) board with at least four layers is recommended to keep all critical components
on the top layer.
• Analog input signals and the reference input signals must be kept away from noise sources. Crossing digital
lines with the analog signal path should be avoided. The analog input and the reference signals are routed on
to the left side of the board and the digital connections are routed on the right side of the device.
• Due to the dynamic currents that occur during conversion and data transfer, each supply pin (AVDD and
DVDD) must have a decoupling capacitor that keeps the supply voltage stable. TI recommends using one 1μF ceramic capacitor at each supply pin.
• A layout that interconnects the converter and accompanying capacitors with the low inductance path is critical
for achieving optimal performance. Using 15-mil vias to interconnect components to a solid analog ground
plane at the subsequent inner layer minimizes stray inductance. Avoid placing vias between the supply pin
and the decoupling capacitor. Any inductance between the supply capacitor and the supply pin of the
converter must be kept to less than 5 nH by placing the capacitor within 0.2 inches from the supply or input
pins of the ADS8339 and by using 20-mil traces, as shown in Figure 64.
• Dynamic currents are also present at the REFIN pin during the conversion phase. Therefore, good decoupling
is critical to achieve optimal performance. The inductance between the reference capacitor and the REFIN pin
must be kept to less than 2 nH by placing the capacitor within 0.1 inches from the REFIN pin and by using
20-mil traces.
• A single 10-μF, X7R-grade, 0805-size ceramic capacitor with at least a 10-V rating is recommended for good
performance over temperature range.
• A small, 0.1-Ω to 0.47-Ω, 0603-size resistor placed in series with the reference capacitor keeps the overall
impedance low and constant, especially at very high frequencies.
• Avoid using additional lower value capacitors because the interactions between multiple capacitors can affect
the ADC performance at higher sampling rates.
• Place the RC filters immediately next to the input pins. Among surface-mount capacitors, COG (NPO)
ceramic capacitors provide the best capacitance precision. The type of dielectric used in COG (NPO) ceramic
capacitors provides the most stable electrical properties over voltage, frequency, and temperature changes.
R
AVDD
12.2 Layout Example
EF
GND
DVDD
REF
1: REF
Analog Input
GND
DVDD
GND
1PF
1PF
0.1Ot 0.47O
AVDD
10PF
GND
47O
10: DVDD
2: AVDD
9: SDI
3: AINP
8: SCLK
4: AINN
7: SDO
5: GND
6: CONVST
47O
GND
SDO
47O
Figure 64. Board Layout Example
32
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Copyright © 2014, Texas Instruments Incorporated
Product Folder Links: ADS8339
ADS8339
www.ti.com
SBAS677A – JUNE 2014 – REVISED OCTOBER 2014
13 Device and Documentation Support
13.1 Documentation Support
13.1.1 Related Documentation
REF5045 Data Sheet, SBOS410
THS4281 Data Sheet, SLOS432
OPA333 Data Sheet, SBOS351
OPA836 Data Sheet, SLOS713
ADS886xEVM-PDK and ADS83x9EVM-PDK User Guide, SBAU233
13.2 Trademarks
TINA is a trademark of Texas Instruments Inc..
SPI is a trademark of Motorola.
All other trademarks are the property of their respective owners.
13.3 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
13.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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Product Folder Links: ADS8339
33
PACKAGE OPTION ADDENDUM
www.ti.com
29-Oct-2014
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
ADS8339IDGSR
ACTIVE
VSSOP
DGS
10
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
8339
ADS8339IDGST
ACTIVE
VSSOP
DGS
10
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
8339
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
29-Oct-2014
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
23-Oct-2014
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
ADS8339IDGSR
VSSOP
DGS
10
2500
330.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
ADS8339IDGST
VSSOP
DGS
10
250
180.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
23-Oct-2014
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
ADS8339IDGSR
VSSOP
DGS
10
2500
367.0
367.0
35.0
ADS8339IDGST
VSSOP
DGS
10
250
210.0
185.0
35.0
Pack Materials-Page 2
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