IDT IDT70V3579S High-speed 3.3v 32k x 36 synchronous pipelined dual-port static ram Datasheet

Š
HIGH-SPEED 3.3V 32K x 36
SYNCHRONOUS PIPELINED
DUAL-PORT STATIC RAM
WITH 3.3V OR 2.5V INTERFACE
Features:
◆
◆
◆
◆
◆
◆
True Dual-Port memory cells which allow simultaneous
access of the same memory location
High-speed clock to data access
– Commercial: 4.2/5/6ns (max.)
– Industrial: 5ns (max)
Pipelined output mode
Counter enable and reset features
Dual chip enables allow for depth expansion without
additional logic
Full synchronous operation on both ports
– 7.5ns cycle time, 133MHz operation (9.6 Gbps bandwidth)
– Fast 4.2ns clock to data out
– 1.8ns setup to clock and 0.7ns hold on all control, data, and
address inputs @ 133MHz
IDT70V3579S
– Data input, address, byte enable and control registers
– Self-timed write allows fast cycle time
Separate byte controls for multiplexed bus and bus
matching compatibility
LVTTL- compatible, single 3.3V (±150mV) power supply for
core
LVTTL compatible, selectable 3.3V (±150mV)/2.5V (±125mV)
power supply for I/Os and control signals on each port
Industrial temperature range (-40°C to +85°C) is
available for selected speeds
Available in a 208-pin Plastic Quad Flatpack (PQFP) and
208-pin fine pitch Ball Grid Array, and 256-pin Ball Grid
Array
Green parts available, see ordering information
◆
◆
◆
◆
◆
◆
Functional Block Diagram
BE3L
BE 3R
BE2L
BE 2R
BE1L
BE 1R
BE0L
BE 0R
R/WL
R/WR
B
W
0
L
CE0L
B
W
1
L
B B
WW
2 3
L L
B
W
3
R
BB
WW
2 1
RR
B
W
0
R
CE0R
CE1R
CE1L
OE L
OER
Dout0-8_L
Dout9-17_L
Dout18-26_L
Dout27-35_L
Dout0-8_R
Dout9-17_R
Dout18-26_R
Dout27-35_R
32K x 36
MEMORY
ARRAY
I/O0L- I/O35L
Din_L
I/O0R - I/O35R
Din_R
CLKL
CLKR
A14L
A 0L
CNTRSTL
ADSL
CNTENL
Counter/
Address
Reg.
,
A14R
ADDR_L
ADDR_R
Counter/
Address
Reg.
A0R
CNTRSTR
ADSR
CNTENR
4830 tbl 01
OCTOBER 2014
1
©2014 Integrated Device Technology, Inc.
DSC 4830/17
IDT70V3579S
High-Speed 32K x 36 Dual-Port Synchronous Pipelined Static RAM
Description:
The IDT70V3579 is a high-speed 32K x 36 bit synchronous DualPort RAM. The memory array utilizes Dual-Port memory cells to allow
simultaneous access of any address from both ports. Registers on
control, data, and address inputs provide minimal setup and hold
times. The timing latitude provided by this approach allows systems
to be designed with very short cycle times. With an input data register, the
IDT70V3579 has been optimized for applications having unidirectional or
Industrial and Commercial Temperature Ranges
bidirectional data flow in bursts. An automatic power down feature,
controlled by CE0 and CE1, permits the on-chip circuitry of each port to
enter a very low standby power mode.
The 70V3579 can support an operating voltage of either 3.3V or 2.5V
on one or both ports, controllable by the OPT pins. The power supply for
the core of the device (VDD) remains at 3.3V.
Pin Configuration(1,2,3,4)
12/12/01
A1
A2
IO19L IO18L
B1
I/O20R
C1
B2
VSS
C2
A3
VSS
B3
I/O18R
C3
A4
NC
B4
VSS
C4
VDDQL I/O19R VDDQR VDD
D1
I/O22L
E1
D2
VSS
E2
D3
D4
I/O21L I/O20L
E3
A5
NC
B5
NC
C5
NC
D5
NC
A6
NC
B6
A13L
C6
A14L
D6
A11L
A7
A12L
B7
A9L
C7
A10L
D7
A7L
A8
A8L
B8
BE2L
C8
A9
BE1L
B9
CE0L
C9
BE3L CE1L
D8
BE0L
D9
VDD
A10
VDD
B10
VSS
C10
VSS
D10
A11
A12
A13
CLKL CNTEN L A4L
B11
ADSL
C11
R/WL
D11
OEL CNTRSTL
B12
A5L
C12
A6L
D12
A3L
B13
A1L
C13
A2L
D13
VDD
A14
A0L
B14
VSS
C14
B15
D14
C15
D15
E15
F1
F14
VDDQL I/O23R I/O24L
G1
G2
I/O26L VSS
H1
VDD
J1
VDDQL
K1
I/O28R
L1
H2
G3
F4
VSS
VSS
G4
G14
I/O25L I/O24R
H3
VDD
K2
VSS
L2
J3
VSS
K3
I/O27R
L3
H4
H14
70V3579BF
BF-208(5)
VDD
J4
J14
VSS
VSS
208-Pin fpBGA
Top View(6)
K4
VSS
K14
M2
M3
VDDQL I/O29L I/O30R
N1
I/O31L
P1
N2
VSS
P2
N3
L4
L14
R1
VSS
T1
R2
P3
R3
T3
I/O33R I/O34L VDDQL
U1
VSS
U2
I/O35L
M14
VSS
VSS
N4
N14
P4
U3
VDD
R4
NC
T4
VSS
U4
NC
D16
VSS
D17
F15
E16
E17
VSS
I/O13L
F17
F16
I/O12R I/O11L VDDQR
G15
G16
G17
H15
IO9R
J15
VDD
K15
H16
H17
VSS
J16
L15
I/O7L
M15
P5
NC
R5
NC
T5
NC
U5
NC
P6
NC
R6
A13R
T6
A14R
U6
A11R
P7
A12R
R7
A9R
T7
A10R
U7
A7R
P8
A8R
R8
P9
BE1R
R9
BE2R CE0R
T8
T9
BE3R CE1R
U8
BE0R
U9
VDD
P10
VDD
R10
VSS
T10
VSS
U10
OER
P11
P12
P13
CLKR CNTENR A4R
R11
ADSR
T11
R/WR
R12
A5R
T12
A6R
U12
A3R
R13
A1R
T13
A2R
U13
A0R
P14
I/O2L
R14
VSS
T14
VSS
U14
VDD
I/O10R
J17
VSS VDDQR
K16
K17
VSS
L17
L16
VSS
I/O8L
M17
M16
I/O6L I/O5R VDDQR
N15
N16
N17
I/O3R VDDQL I/O4R
I/O31R I/O30L
I/O33L I/O34R
T2
I/O6R
M4
I/O32R I/O32L VDDQR I/O35R
C17
I/O7R VDDQL I/O8R
I/O29R I/O28L VDDQR I/O27L
M1
C16
I/O9L VDDQL I/O10L I/O11R
I/O26R VDDQR I/O25R
J2
B17
B16
I/O17R VDDQL I/O14L I/O14R
I/O12L I/O13R
F3
VSS
VDDQR I/O16L I/O15R
I/O23L I/O22R VDDQR I/O21R
F2
A17
A16
OPTL I/O17L
VDD I/O16R I/O15L
E14
E4
A15
P15
I/O3L
R15
P16
I/O5L
P17
VSS
R16
I/O4L
R17
VDDQL I/O1R VDDQR
T15
I/O0R
U15
T16
T17
VSS
I/O2R
U17
U16
OPTR I/O0L
I/O1L
,
4830 drw 02c
NOTES:
1. All VDD pins must be connected to 3.3V power supply.
2. All VDDQ pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to VIH (3.3V), and 2.5V if OPT pin for that port is
set to VIL (0V).
3. All VSS pins must be connected to ground supply.
4. Package body is approximately 15mm x 15mm x 1.4mm, with 0.8mm ball-pitch.
5. This package code is used to reference the package diagram.
6. This text does not indicate orientation of the actual part-marking.
6.42
2
IDT70V3579S
High-Speed 32K x 36 Dual-Port Synchronous Pipelined Static RAM
Industrial and Commercial Temperature Ranges
Pin Configuration(1,2,3,4) (con't.)
70V3579BC
BC-256(5)
256-Pin BGA
Top View(6)
12/12/01
A1
NC
B1
I/O18L
C1
A2
NC
B2
NC
C2
I/O18R I/O19L
D1
D2
A3
NC
B3
NC
C3
VSS
D3
I/O20R I/O19R I/O20L
E1
E2
E3
A4
NC
B4
NC
C4
NC
D4
F2
F3
E4
F4
I/O23L I/O22R I/O23R VDDQL
G1
G2
G3
G4
I/O24R I/O24L I/O25L VDDQR
H1
H2
H3
A6
A14L
A11L
B5
NC
C5
A13L
D5
H4
E5
VDD
F5
VDD
G5
VSS
H5
I/O26L I/O25R I/O26R VDDQR VSS
J1
J2
J3
J4
I/O27L I/O28R I/O27R VDDQL
K1
K2
K3
K4
I/O29R I/O29L I/O28L VDDQL
L1
L2
L3
L4
I/O30L I/O31R I/O30R VDDQR
M1
M2
M3
M4
I/O32R I/O32L I/O31L VDDQR
N1
N2
N3
I/O33L I/O34R I/O33R
P1
P2
I/O35R I/O34L
R1
I/O35L
T1
NC
R2
NC
T2
NC
P3
NC
R3
NC
T3
NC
B6
A12L
C6
A10L
D6
A7
A8L
B7
A9L
C7
A7L
D7
A8
A9
BE2L
CE1L
B9
B8
BE3L
C8
B10
B11
C10
C11
BE0L CLKL ADSL
D9
D8
A11
OEL CNTENL
CE0L R/WL CNTRSTL
C9
BE1L
A10
D10
D11
A12
A5L
B12
A4L
C12
A6L
D12
A13
A2L
B13
A1L
C13
A3L
D13
VDD VDDQL VDDQL VDDQR VDDQR VDDQL VDDQL VDDQR VDDQR VDD
I/O21R I/O21L I/O22L VDDQL
F1
A5
N4
VDD
P4
NC
R4
NC
T4
NC
J5
VSS
K5
VSS
L5
VDD
M5
VDD
N5
E6
VDD
F6
VSS
G6
VSS
H6
VSS
J6
VSS
K6
VSS
L6
VSS
M6
VDD
N6
E7
VSS
F7
VSS
G7
VSS
H7
VSS
J7
VSS
K7
VSS
L7
VSS
M7
VSS
N7
E8
E9
VSS
F9
F8
VSS
VSS
G8
G9
VSS
VSS
H8
H9
VSS
VSS
J8
J9
VSS
K8
VSS
K9
VSS
L8
VSS
L9
VSS
M8
VSS
M9
VSS
N8
VSS
VSS
N9
E10
VSS
F10
VSS
G10
VSS
H10
VSS
J10
VSS
K10
VSS
L10
VSS
M10
VSS
N10
E11
VDD
F11
VSS
G11
VSS
H11
VSS
J11
VSS
K11
VSS
L11
VSS
M11
VDD
N11
E12
A13R
R5
NC
T5
A14R
P6
A10R
R6
A12R
T6
A11R
P7
A7R
R7
A9R
T7
A8R
P8
P9
P10
P11
BE1R BE0R CLKR ADSR
R8
R9
R10
R11
BE3R CE0R R/WR CNTRSTR
T8
T9
BE2R CE1R
T10
T11
OER CNTENR
A0L
B14
VDD
C14
A15
A16
NC
B15
NC
B16
I/O17L
NC
C16
C15
OPTL I/O17R I/O16L
D14
D16
D15
I/O15R I/O15L I/O16R
E14
E16
E15
VDD VDDQR I/O13L I/O14L I/O14R
F12
F13
F14
F15
F16
VDD VDDQR I/O12R I/O13R I/O12L
G12
VSS
H12
VSS
J12
VSS
K12
VSS
L12
VDD
M12
VDD
N12
VDDQR VDDQR VDDQL VDDQL VDDQR VDDQR VDDQL VDDQL
P5
E13
A14
P12
A6R
R12
A4R
T12
A5R
G13
G14
G15
G16
VDDQL I/O10L I/O11L I/O11R
H13
H14
VDDQL I/O9R
J13
J14
H16
H15
IO9L I/O10R
J15
J16
VDDQR I/O8R I/O7R
K13
K14
VDDQR I/O6R
L13
L14
VDDQL I/O5L
M13
M14
VDDQL I/O3R
N13
VDD
P13
A3R
R13
A1R
T13
A2R
N14
I/O2L
P14
K15
K16
I/O6L
L15
OPTR
T14
A0R
I/O7L
L16
I/O4R I/O5R
M16
M15
I/O3L
I/O4L
N16
N15
I/O1R I/O2R
P15
P16
I/O0L I/O0R
R14
I/O8L
I/O1L
R16
R15
NC
T15
NC
,
T16
NC
NC
4830 drw 02d
NOTES:
1. All VDD pins must be connected to 3.3V power supply.
2. All VDDQ pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to VIH (3.3V), and 2.5V if OPT pin for that port is
set to VIL (0V).
3. All VSS pins must be connected to ground supply.
4. Package body is approximately 17mm x 17mm x 1.4mm, with 1.0mm ball-pitch.
5. This package code is used to reference the package diagram.
6. This text does not indicate orientation of the actual part-marking.
6.42
3
,
IDT70V3579S
High-Speed 32K x 36 Dual-Port Synchronous Pipelined Static RAM
Industrial and Commercial Temperature Ranges
VSS
VDDQR
I/O18R
I/O18L
VSS
VDD
VSS
NC
NC
NC
NC
NC
NC
A14L
A13L
A12L
A11L
A10L
A9L
A8L
A7L
BE3L
BE2L
BE1L
BE0L
CE1L
CE0L
VDD
VDD
VSS
VSS
CLKL
OEL
R/WL
ADSL
CNTENL
CNTRSTL
A6L
A5L
A4L
A3L
A2L
A1L
A0L
VDD
VDD
VSS
OPTL
I/O17L
I/O17R
VDDQR
VSS
Pin Configuration(1,2,3,4) (con't.)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
70V3579DR
DR-208(5)
208-Pin PQFP
Top View(6)
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
I/O19L
I/O19R
I/O20L
I/O20R
VDDQL
VSS
I/O21L
I/O21R
I/O22L
I/O22R
VDDQR
VSS
I/O23L
I/O23R
I/O24L
I/O24R
VDDQL
VSS
I/O25L
I/O25R
I/O26L
I/O26R
VDDQR
VSS
VDD
VDD
VSS
VSS
VDDQL
VSS
I/O27R
I/O27L
I/O28R
I/O28L
VDDQR
VSS
I/O29R
I/O29L
I/O30R
I/O30L
VDDQL
VSS
I/O31R
I/O31L
I/O32R
I/O32L
VDDQR
VSS
I/O33R
I/O33L
I/O34R
I/O34L
208
207
206
205
204
203
202
201
200
199
198
197
196
195
194
193
192
191
190
189
188
187
186
185
184
183
182
181
180
179
178
177
176
175
174
173
172
171
170
169
168
167
166
165
164
163
162
161
160
159
158
157
12/12/01
I/O16L
I/O16R
I/O15L
I/O15R
VSS
VDDQL
I/O14L
I/O14R
I/O13L
I/O13R
VSS
VDDQR
I/O12L
I/O12R
I/O11L
I/O11R
VSS
VDDQL
I/O10L
I/O10R
I/O9L
I/O9R
VSS
VDDQR
VDD
VDD
VSS
VSS
VSS
VDDQL
I/O8R
I/O8L
I/O7R
I/O7L
VSS
VDDQR
I/O6R
I/O6L
I/O5R
I/O5L
VSS
VDDQL
I/O4R
I/O4L
I/O3R
I/O3L
VSS
VDDQR
I/O2R
I/O2L
I/O1R
I/O1L
VSS
VDDQL
I/O35R
I/O35L
VDD
VSS
NC
NC
NC
NC
NC
NC
NC
A14R
A13R
A12R
A11R
A10R
A9R
A8R
A7R
BE3R
BE2R
BE1R
BE0R
CE1R
CE0R
VDD
VDD
VSS
VSS
CLKR
OER
R/WR
ADSR
CNTENR
CNTRSTR
A6R
A5R
A4R
A3R
A2R
A1R
A0R
VDD
VSS
VSS
OPTR
I/O0L
I/O0R
VDDQL
VSS
,
4830 drw 02a
NOTES:
1. All VDD pins must be connected to 3.3V power supply.
2. All VDDQ pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to VIH (3.3V), and 2.5V if OPT pin for that port is set to VIL (0V).
3. All VSS pins must be connected to ground supply.
4. Package body is approximately 28mm x 28mm x 3.5mm.
5. This package code is used to reference the package diagram.
6. This text does not indicate orientation of the actual part-marking.
6.42
4
IDT70V3579S
High-Speed 32K x 36 Dual-Port Synchronous Pipelined Static RAM
Industrial and Commercial Temperature Ranges
Pin Names
Left Port
Right Port
Names
CE0L, CE1L
CE0R, CE1R
Chip Enables
R/WL
R/WR
Read/Write Enable
OEL
OER
Output Enable
A0L - A14L
A0R - A14R
Address
I/O0L - I/O35L
I/O0R - I/O35R
Data Input/Output
CLKL
CLKR
Clock
ADSL
ADSR
Address Strobe Enable
CNTENL
CNTENR
Counter Enable
CNTRSTL
CNTRSTR
Counter Reset
BE0L - BE3L
BE0R - BE3R
Byte Enables (9-bit bytes)
VDDQL
VDDQR
Power (I/O Bus) (3.3V or 2.5V)(1)
OPTL
OPTR
Option for selecting VDDQX(1,2)
VDD
Power (3.3V)(1)
VSS
Ground (0V)
NOTES:
1. VDD, OPTX, and VDDQX must be set to appropriate operating levels prior to
applying inputs on the I/Os and controls for that port.
2. OPTX selects the operating voltage levels on that port. If OPTX is set to VIH (3.3V),
then that port's I/Os and controls will operate at 3.3V levels and VDDQX must be
supplied at 3.3V. If OPTX is set to VIL (0V), then that port's I/Os and controls will
operate at 2.5V levels and VDDQX must be supplied at 2.5V. The OPT pins are
independent of one another—both ports can operate at 3.3V levels, both can
operate at 2.5V levels, or either can operate at 3.3V with the other at 2.5V.
4830 tbl 01
Truth Table I—Read/Write and Enable Control(1,2,3,4)
OE
CLK
CE0
CE1
BE3
BE2
BE1
BE0
R/W
Byte 3
I/O27-35
Byte 2
I/O18-26
Byte 1
I/O9-17
Byte 0
I/O0-8
MODE
X
↑
H
X
X
X
X
X
X
High-Z
High-Z
High-Z
High-Z
Deselected–Power Down
X
↑
X
L
X
X
X
X
X
High-Z
High-Z
High-Z
High-Z
Deselected–Power Down
X
↑
L
H
H
H
H
H
X
High-Z
High-Z
High-Z
High-Z
All Bytes Deselected
X
↑
L
H
H
H
H
L
L
High-Z
High-Z
High-Z
DIN
Write to Byte 0 Only
X
↑
L
H
H
H
L
H
L
High-Z
High-Z
DIN
High-Z
Write to Byte 1 Only
X
↑
L
H
H
L
H
H
L
High-Z
DIN
High-Z
High-Z
Write to Byte 2 Only
X
↑
L
H
L
H
H
H
L
DIN
High-Z
High-Z
High-Z
Write to Byte 3 Only
X
↑
L
H
H
H
L
L
L
High-Z
High-Z
DIN
DIN
Write to Lower 2 Bytes Only
X
↑
L
H
L
L
H
H
L
DIN
DIN
High-Z
High-Z
Write to Upper 2 bytes Only
X
↑
L
H
L
L
L
L
L
DIN
DIN
DIN
DIN
Write to All Bytes
L
↑
L
H
H
H
H
L
H
High-Z
High-Z
High-Z
DOUT
Read Byte 0 Only
L
↑
L
H
H
H
L
H
H
High-Z
High-Z
DOUT
High-Z
Read Byte 1 Only
L
↑
L
H
H
L
H
H
H
High-Z
DOUT
High-Z
High-Z
Read Byte 2 Only
H
L
H
H
H
H
DOUT
L
↑
L
High-Z
High-Z
High-Z
Read Byte 3 Only
L
↑
L
H
H
H
L
L
H
High-Z
High-Z
DOUT
DOUT
Read Lower 2 Bytes Only
L
↑
L
H
L
L
H
H
H
DOUT
DOUT
High-Z
High-Z
Read Upper 2 Bytes Only
L
↑
L
H
L
L
L
L
H
DOUT
DOUT
DOUT
DOUT
Read All Bytes
H
↑
L
H
L
L
L
L
X
High-Z
High-Z
High-Z
High-Z
Outputs Disabled
NOTES:
1. "H" = VIH, "L" = VIL, "X" = Don't Care.
2. ADS, CNTEN, CNTRST = X.
3. OE is an asynchronous input signal.
4. It is possible to read or write any combination of bytes during a given access. A few representative samples have been illustrated here.
6.42
5
4830 tbl 02
IDT70V3579S
High-Speed 32K x 36 Dual-Port Synchronous Pipelined Static RAM
Industrial and Commercial Temperature Ranges
Truth Table II—Address Counter Control(1,2)
Address
Previous
Address
Addr
Used
CLK(6)
ADS
CNTEN
CNTRST
I/O(3)
X
X
0
↑
X
X
L(4)
DI/O(0)
Counter Reset to Address 0
An
X
An
↑
L(4)
X
H
DI/O (n)
External Address Used
An
Ap
Ap
↑
H
H
H
DI/O(p)
External Address Blocked—Counter disabled (Ap reused)
X
Ap
Ap + 1
↑
H
L(5)
H
DI/O(p+1)
MODE
Counter Enabled—Internal Address generation
4830 tbl 03
NOTES:
1. "H" = VIH, "L" = VIL, "X" = Don't Care.
2. Read and write operations are controlled by the appropriate setting of R/W, CE0, CE1, BEn and OE.
3. Outputs are in Pipelined mode: the data out will be delayed by one cycle.
4. ADS and CNTRST are independent of all other memory control signals including CE0, CE 1 and BEn
5. The address counter advances if CNTEN = VIL on the rising edge of CLK, regardless of all other memory control signals including CE0, CE1, BEn.
Recommended DC Operating
Conditions with VDDQ at 2.5V
Recommended Operating
Temperature and Supply Voltage(1)
Parameter
GND
VDD
V DD
Core Supply Voltage
0OC to +70OC
0V
3.3V + 150mV
VDDQ
I/O Supply Voltage
(3)
-40 C to +85 C
0V
3.3V + 150mV
V SS
Ground
Commercial
Industrial
Symbol
Ambient
Temperature
Grade
O
O
4830 tbl 04
NOTE:
1. Industrial temperature: for specific speeds, packages and powers contact your
sales office.
(3)
Min.
Typ.
Max.
Unit
3.15
3.3
3.45
V
2.375
2.5
2.625
V
0
0
0
V DDQ + 125mV
(2)
V
V
VIH
Input High Voltage
(Address & Control Inputs)
1.7
____
VIH
Input High Voltage - I/O(3)
1.7
____
V DDQ + 125mV(2)
V
____
0.7
V
VIL
Input Low Voltage
-0.3
(1)
4830 tbl 05a
Absolute Maximum Ratings
Symbol
Rating
Commercial
& Industrial
Unit
VTERM(2)
Terminal Voltage
with Respect to
GND
-0.5 to +4.6
V
TBIAS
Temperature
Under Bias
-55 to +125
o
C
TSTG
Storage
Temperature
-65 to +150
o
C
IOUT
DC Output Current
NOTES:
1. VIL > -1.5V for pulse width less than 10 ns.
2. VTERM must not exceed VDDQ + 125mV.
3. To select operation at 2.5V levels on the I/Os and controls of a given port, the
OPT pin for that port must be set to V IL (0V), and VDDQX for that port must be supplied
as indicated above.
(1)
Recommended DC Operating
Conditions with VDDQ at 3.3V
Symbol
50
mA
4830 tbl 06
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
2. VTERM must not exceed VDD + 150mV for more than 25% of the cycle time or 4ns
maximum, and is limited to < 20mA for the period of VTERM > VDD + 150mV.
Parameter
Min.
Typ.
Max.
Unit
V DD
Core Supply Voltage
3.15
3.3
3.45
V
VDDQ
I/O Supply Voltage
(3)
3.15
3.3
3.45
V
V SS
Ground
0
0
0
VIH
Input High Voltage
(Address & Control Inputs)(3)
2.0
____
VDDQ + 150mV
(2)
V
VIH
Input High Voltage - I/O(3)
2.0
____
VDDQ + 150mV(2)
V
____
0.8
V
VIL
Input Low Voltage
-0.3
(1)
V
4830 tbl 05b
NOTES:
1. VIL > -1.5V for pulse width less than 10 ns.
2. VTERM must not exceed VDDQ + 150mV.
3. To select operation at 3.3V levels on the I/Os and controls of a given port, the
OPT pin for that port must be set to VIH (3.3V), and VDDQX for that port must be
supplied as indicated above.
6.42
6
IDT70V3579S
High-Speed 32K x 36 Dual-Port Synchronous Pipelined Static RAM
Industrial and Commercial Temperature Ranges
Capacitance(1)
(TA = +25°C, F = 1.0MHZ) PQFP ONLY
Symbol
Parameter
Input Capacitance
CIN
(3)
COUT
Output Capacitance
Conditions(2)
Max.
Unit
VIN = 3dV
8
pF
VOUT = 3dV
10.5
pF
4830 tbl 07
NOTES:
1. These parameters are determined by device characterization, but are not
production tested.
2. 3dV references the interpolated capacitance when the input and output switch
from 0V to 3V or from 3V to 0V.
3. COUT also references CI/O.
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range (VDD = 3.3V ± 150mV)
70V3579S
Symbol
Parameter
Test Conditions
Min.
Max.
Unit
|ILI|
Input Leakage Current(1)
VDDQ = Max., VIN = 0V to V DDQ
___
10
µA
|ILO|
Output Leakage Current
CE0 = VIH or CE1 = VIL, VOUT = 0V to VDDQ
___
10
µA
(2)
IOL = +4mA, VDDQ = Min.
___
0.4
V
VOH (3.3V)
Output High Voltage
(2)
IOH = -4mA, VDDQ = Min.
2.4
___
V
VOL (2.5V)
Output Low Voltage(2)
IOL = +2mA, VDDQ = Min.
___
0.4
V
VOH (2.5V)
Output High Voltage (2)
IOH = -2mA, VDDQ = Min.
2.0
___
VOL (3.3V)
Output Low Voltage
V
4830 tbl 08
NOTES:
1. At VDD < - 2.0V input leakages are undefined.
2. VDDQ is selectable (3.3V/2.5V) via OPT pins. Refer to p.4 for details.
6.42
7
IDT70V3579S
High-Speed 32K x 36 Dual-Port Synchronous Pipelined Static RAM
Industrial and Commercial Temperature Ranges
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range(3) (VDD = 3.3V ± 150mV)
70V3579S4
Com'l Only
Symbol
IDD
ISB1
ISB2
ISB3
ISB4
Parameter
Test Condition
Version
70V3579S5
Com'l
& Ind
70V3579S6
Com'l Only
Typ. (4)
Max.
Typ. (4)
Max.
Typ. (4)
Max.
Unit
mA
Dynamic Operating
Current (Both
Ports Active)
CEL and CER= VIL,
Outputs Disabled,
f = fMAX(1)
COM'L
S
375
460
285
360
245
310
IND
S
____
____
285
415
245
360
Standby Current
(Both Ports - TTL
Level Inputs)
CEL = CER = VIH
f = fMAX(1)
COM'L
S
145
190
105
145
95
125
IND
S
____
____
105
175
95
150
Standby Current
(One Port - TTL
Level Inputs)
CE"A" = VIL and CE"B" = VIH
Active Port Outputs Disabled,
f=fMAX(1)
COM'L
S
265
325
190
260
175
225
IND
S
____
____
190
300
175
260
Full Standby Current
(Both Ports - CMOS
Level Inputs)
Both Ports CEL and
CER > VDDQ - 0.2V,
VIN > VDDQ - 0.2V or VIN < 0.2V,
f = 0(2)
COM'L
S
6
15
6
15
6
15
IND
S
____
____
6
30
6
30
Full Standby Current
(One Port - CMOS
Level Inputs)
CE"A" < 0.2V and
CE"B" > VDDQ - 0.2V(5)
VIN > VDDQ - 0.2V or VIN < 0.2V,
Active Port, Outputs Disabled,
f = fMAX(1)
COM'L
S
265
325
180
260
170
225
IND
S
____
____
180
300
170
260
(5)
mA
mA
mA
mA
4830 tbl 09
NOTES:
1. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency clock cycle of 1/tCYC , using "AC TEST CONDITIONS" at input levels of
GND to 3V.
2. f = 0 means no address, clock, or control lines change. Applies only to input at CMOS level standby.
3. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
4. VDD = 3.3V, TA = 25°C for Typ, and are not production tested. IDD DC(f=0) = 120mA (Typ).
5. CEX = V IL means CE0X = V IL and CE1X = VIH
CEX = VIH means CE0X = VIH or CE1X = VIL
CEX < 0.2V means CE0X < 0.2V and CE1X > VDDQ - 0.2V
CEX > VDDQ - 0.2V means CE0X > VDDQ - 0.2V or CE1X - 0.2V
"X" represents "L" for left port or "R" for right port.
6.42
8
IDT70V3579S
High-Speed 32K x 36 Dual-Port Synchronous Pipelined Static RAM
Industrial and Commercial Temperature Ranges
AC Test Conditions (VDDQ - 3.3V/2.5V)
Input Pulse Levels (Address & Controls)
GND to 3.0V/GND to 2.35V
Input Pulse Levels (I/Os)
GND to 3.0V/GND to 2.35V
Input Rise/Fall Times
2.5V
833Ω
3ns
Input Timing Reference Levels
1.5V/1.25V
Output Reference Levels
1.5V/1.25V
Output Load
DATAOUT
5pF*
770Ω
Figures 1, 2, and 3
4830 tbl 10
,
3.3V
590Ω
50Ω
50Ω
DATAOUT
1.5V/1.25
10pF
(Tester)
,
DATAOUT
435Ω
5pF*
4830 drw 03
Figure 1. AC Output Test load.
4830 drw 04
Figure 2. Output Test Load
(For tCKLZ, tCKHZ, tOLZ , and tOHZ).
*Including scope and jig.
10.5pF is the I/O capacitance of this
device, and 10pF is the AC Test Load
Capacitance.
7
6
5
4
ΔtCD
(Typical, ns) 3
2
•
1
•
20.5
•
30
•
50
80
100
200
-1
Capacitance (pF)
4830 drw 05
Figure 3. Typical Output Derating (Lumped Capacitive Load).
6.42
9
,
,
IDT70V3579S
High-Speed 32K x 36 Dual-Port Synchronous Pipelined Static RAM
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the Operating
Temperature Range (Read and Write Cycle Timing)(1,2)
(VDD = 3.3V ± 150mV, TA = 0°C to +70°C)
70V3579S4
Com'l Only
Symbol
Parameter
70V3579S5
Com'l
& Ind
70V3579S6
Com'l Only
Min.
Max.
Min.
Max.
Min.
Max.
Unit
ns
tCYC2
Clock Cycle Time (Pipelined)
7.5
____
10
____
12
____
tCH2
Clock High Time (Pipelined)
3
____
4
____
5
____
ns
tCL2
Clock Low Time (Pipelined)
3
____
4
____
5
____
ns
tR
Clock Rise Time
____
3
____
3
____
3
ns
tF
Clock Fall Time
____
3
____
3
____
3
ns
tSA
Address Setup Time
1.8
____
2.0
____
2.0
____
ns
tHA
Address Hold Time
0.7
____
0.7
____
1.0
____
ns
tSC
Chip Enable Setup Time
1.8
____
2.0
____
2.0
____
ns
tHC
Chip Enable Hold Time
0.7
____
0.7
____
1.0
____
ns
tSB
Byte Enable Setup Time
1.8
____
2.0
____
2.0
____
ns
tHB
Byte Enable Hold Time
0.7
____
0.7
____
1.0
____
ns
tSW
R/W Setup Time
1.8
____
2.0
____
2.0
____
ns
tHW
R/W Hold Time
0.7
____
0.7
____
1.0
____
ns
tSD
Input Data Setup Time
1.8
____
2.0
____
2.0
____
ns
tHD
Input Data Hold Time
0.7
____
0.7
____
1.0
____
ns
tSAD
ADS Setup Time
1.8
____
2.0
____
2.0
____
ns
tHAD
ADS Hold Time
0.7
____
0.7
____
1.0
____
ns
tSCN
CNTEN Setup Time
1.8
____
2.0
____
2.0
____
ns
tHCN
CNTEN Hold Time
0.7
____
0.7
____
1.0
____
ns
tSRST
CNTRST Setup Time
1.8
____
2.0
____
2.0
____
ns
tHRST
CNTRST Hold Time
0.7
____
0.7
____
1.0
____
ns
Output Enable to Data Valid
____
4
____
5
____
6
ns
0
____
0
____
0
____
ns
tOE
(1)
tOLZ
Output Enable to Output Low-Z
tOHZ
Output Enable to Output High-Z
1
4
1
4.5
1
5
ns
tCD2
Clock to Data Valid (Pipelined)
____
4.2
____
5
____
6
ns
tDC
Data Output Hold After Clock High
1
____
1
____
1
____
ns
tCKHZ
Clock High to Output High-Z
1
3
1
4.5
1.5
6
ns
tCKLZ
Clock High to Output Low-Z
1
____
1
____
1
____
ns
6
____
8
____
10
____
Port-to-Port Delay
tCO
Clock-to-Clock Offset
NOTES:
1. All input signals are synchronous with respect to the clock except for the asynchronous Output Enable (OE).
2. These values are valid for either level of VDDQ (3.3V/2.5V). See page 4 for details on selecting the desired I/O voltage levels for each port.
6.42
10
ns
4830 tbl 11
IDT70V3579S
High-Speed 32K x 36 Dual-Port Synchronous Pipelined Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Read Cycle for Pipelined Operation(2)
tCYC2
tCH2
tCL2
CLK
CE0
tSC
tSC
tHC
tHC
(3)
CE1
tSB
tHB
tSB
BE(0-3)
R/W
ADDRESS
(4)
tSW
tHW
tSA
tHA
An
An + 1
(1 Latency)
An + 2
An + 3
tDC
tCD2
DATAOUT
Qn
tCKLZ
OE
tHB
(5)
Qn + 1
Qn + 2
(5)
(1)
tOHZ
tOLZ
(1)
tOE
NOTES:
4830 drw 06
1. OE is asynchronously controlled; all other inputs are synchronous to the rising clock edge.
2. ADS = VIL, CNTEN and CNTRST = VIH.
3. The output is disabled (High-Impedance state) by CE 0 = VIH , CE1 = VIL, BEn = VIH following the next rising edge of the clock. Refer to Truth Table 1.
4. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers
are for reference use only.
5. If BEn was HIGH, then the appropriate Byte of DATA OUT for Qn + 2 would be disabled (High-Impedance state).
Timing Waveform of a Multi-Device Pipelined Read(1,2)
tCH2
tCYC2
tCL2
CLK
tSA
tHA
A0
ADDRESS(B1)
tSC
tHC
CE0(B1)
tSC
tHC
tCD2
tCD2
Q0
DATAOUT(B1)
tCKHZ
A1
tSC
tCKHZ
A6
A5
A4
A3
A2
tSC
CE0(B2)
Q3
tCKLZ
tDC
tHA
A0
ADDRESS(B2)
tCD2
Q1
tDC
tSA
A6
A5
A4
A3
A2
A1
tHC
tHC
tCD2
DATAOUT(B2)
tCKHZ
tCD2
Q4
Q2
tCKLZ
NOTES:
1. B1 Represents Device #1; B2 Represents Device #2. Each Device consists of one IDT70V3579 for this waveform,
and are setup for depth expansion in this example. ADDRESS(B1) = ADDRESS(B2) in this situation.
2. BEn, OE, and ADS = V IL; CE1(B1), CE1(B2) , R/W, CNTEN, and CNTRST = VIH.
6.42
11
tCKLZ
4830 drw 07
IDT70V3579S
High-Speed 32K x 36 Dual-Port Synchronous Pipelined Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Left Port Write to Pipelined Right Port Read(1,2)
CLKL
tSW
tHW
tSA
tHA
R/WL
ADDRESSL
NO
MATCH
MATCH
tSD
DATAINL
tHD
VALID
tCO(3)
CLKR
tCD2
R/WR
ADDRESSR
tSW
tHW
tSA
tHA
NO
MATCH
MATCH
DATAOUTR
VALID
tDC
4830 drw 08
NOTES:
1. CE0, BEn, and ADS = VIL; CE1, CNTEN, and CNTRST = VIH.
2. OE = VIL for the Right Port, which is being read from. OE = VIH for the Left Port, which is being written to.
3. If tCO < minimum specified, then data from right port read is not valid until following right port clock cycle (ie, time from write to valid read on opposite port will
be tCO + 2 tCYC2 + tCD2 ). If tCO > minimum, then data from right port read is available on first right port clock cycle (ie, time from write to valid read on opposite
port will be tCO + tCYC2 + tCD2).
Timing Waveform of Pipelined Read-to-Write-to-Read
tCYC2
(OE = VIL)(2)
tCH2
tCL2
CLK
CE0
tSC
tHC
tSB
tHB
CE1
BEn
tSW tHW
R/W
(3)
ADDRESS
tSW tHW
An
tSA tHA
An +1
An + 2
An + 3
An + 2
An + 4
tSD tHD
DATAIN
Dn + 2
tCD2
(1)
tCKHZ
tCKLZ
tCD2
Qn + 3
Qn
DATAOUT
READ
NOP
(4)
WRITE
READ
NOTES:
1. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.
2. CE 0, BEn, and ADS = VIL; CE1, CNTEN, and CNTRST = VIH. "NOP" is "No Operation".
3. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers
are for reference use only.
4. "NOP" is "No Operation." Data in memory at the selected address may be corrupted and should be re-written to guarantee data integrity.
6.42
12
4830 drw 09
IDT70V3579S
High-Speed 32K x 36 Dual-Port Synchronous Pipelined Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Pipelined Read-to-Write-to-Read ( OE Controlled)(2)
tCH2
tCYC2
tCL2
CLK
CE0
tSC
tHC
tSB
tHB
CE1
BEn
tSW tHW
R/W
tSW tHW
(3)
ADDRESS
An
tSA tHA
An +1
An + 2
tSD
DATAIN
Dn + 2
tCD2
(1)
Qn
DATAOUT
An + 4
An + 3
An + 5
tHD
Dn + 3
tCKLZ
tCD2
Qn + 4
(4)
tOHZ
OE
READ
WRITE
READ
4830 drw 10
NOTES:
1. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.
2. CE 0, BEn, and ADS = VIL; CE1, CNTEN, and CNTRST = VIH.
3. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for reference use only.
4. This timing does not meet requirements for fastest speed grade. This waveform indicates how logically it could be done if timing so allows.
Timing Waveform of Pipelined Read with Address Counter Advance(1)
tCH2
tCYC2
tCL2
CLK
tSA
ADDRESS
tHA
An
tSAD tHAD
ADS
tSAD tHAD
CNTEN
tSCN tHCN
tCD2
DATAOUT
Qx - 1(2)
Qn + 2(2)
Qn + 1
Qn
Qx
Qn + 3
tDC
READ
EXTERNAL
ADDRESS
READ WITH COUNTER
COUNTER
HOLD
READ
WITH
COUNTER
4830 drw 11
NOTES:
1. CE0, OE, BEn = VIL; CE1, R/W, and CNTRST = VIH.
2. If there is no address change via ADS = VIL (loading a new address) or CNTEN = VIL (advancing the address), i.e. ADS = V IH and CNTEN = V IH, then
the data output remains constant for subsequent clocks.
6.42
13
IDT70V3579S
High-Speed 32K x 36 Dual-Port Synchronous Pipelined Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Write with Address Counter Advance(1)
tCH2
tCYC2
tCL2
CLK
tSA
tHA
An
ADDRESS
INTERNAL(3)
ADDRESS
An(7)
An + 2
An + 1
An + 4
An + 3
tSAD tHAD
ADS
tSCN tHCN
CNTEN
tSD tHD
Dn + 1
Dn
DATAIN
WRITE
EXTERNAL
ADDRESS
Dn + 1
Dn + 4
Dn + 3
Dn + 2
WRITE
WRITE
WITH COUNTER COUNTER HOLD
WRITE WITH COUNTER
4830 drw 12
Timing Waveform of Counter Reset(2)
tCH2
tCYC2
tCL2
CLK
tSA tHA
(4)
An
ADDRESS
INTERNAL(3)
ADDRESS
Ax
0
1
An + 2
An + 1
An
An + 1
tSW tHW
R/W
ADS
tSAD tHAD
CNTEN
tSCN tHCN
tSRST tHRST
CNTRST
tSD
tHD
D0
DATAIN
(5)
Q1
Q0
DATAOUT
(6)
COUNTER
RESET
WRITE
ADDRESS 0
READ
ADDRESS 0
READ
ADDRESS 1
READ
ADDRESS n
Qn
READ
ADDRESS n+1
NOTES:
4830 drw 13
1. CE0, BEn, and R/W = V IL; CE1 and CNTRST = VIH.
2. CE0, BEn = VIL; CE1 = VIH.
3. The "Internal Address" is equal to the "External Address" when ADS = VIL and equals the counter output when ADS = VIH.
4. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for reference
use only.
5. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.
6. No dead cycle exists during counter reset. A READ or WRITE cycle may be coincidental with the counter reset cycle: ADDR 0 will be accessed. Extra cycles
are shown here simply for clarification.
7. CNTEN = VIL advances Internal Address from ‘An’ to ‘An +1’. The transition shown indicates the time required for the counter to advance. The ‘An +1’Address is
written to during this cycle.
6.42
14
IDT70V3579S
High-Speed 32K x 36 Dual-Port Synchronous Pipelined Static RAM
Industrial and Commercial Temperature Ranges
Functional Description
Depth and Width Expansion
The IDT70V3579 provides a true synchronous Dual-Port Static
RAM interface. Registered inputs provide minimal set-up and hold
times on address, data, and all critical control inputs. All internal
registers are clocked on the rising edge of the clock signal, however,
the self-timed internal write pulse is independent of the LOW to HIGH
transition of the clock signal.
An asynchronous output enable is provided to ease asynchronous bus interfacing. Counter enable inputs are also provided to
stall the operation of the address counters for fast interleaved
memory applications.
A HIGH on CE0 or a LOW on CE1 for one clock cycle will power
down the internal circuitry to reduce static power consumption.
Multiple chip enables allow easier banking of multiple IDT70V3579s
for depth expansion configurations. Two cycles are required with CE0
LOW and CE1 HIGH to re-activate the outputs.
The IDT70V3579 features dual chip enables (refer to Truth
Table I) in order to facilitate rapid and simple depth expansion with no
requirements for external logic. Figure 4 illustrates how to control the
various chip enables in order to expand two devices in depth.
The IDT70V3579 can also be used in applications requiring
expanded width, as indicated in Figure 4. Through combining the
control signals, the devices can be grouped as necessary to accommodate applications needing 72-bits or wider.
A15
CE0
IDT70V3579
CE1
CE1
CE1
VDD
IDT70V3579
VDD
CE1
CE0
CE0
Control Inputs
CE0
Control Inputs
Control Inputs
IDT70V3579
IDT70V3579
Control Inputs
4830 drw 14
Figure 4. Depth and Width Expansion with IDT70V3579
6.42
15
BE,
R/W,
OE,
CLK,
ADS,
CNTRST,
CNTEN
IDT70V3579S
High-Speed 32K x 36 Dual-Port Synchronous Pipelined Static RAM
Industrial and Commercial Temperature Ranges
Ordering Information
NOTES:
1. Contact your local sales office for Industrial temp range in other speeds, packages and powers.
2. Green parts available. For specific speeds, packages and powers contact your local sales office.
Datasheet Document History
12/9/98:
3/12/99:
4/28/99:
6/8/99:
6/15/99:
8/4/99:
10/4/99:
10/19/99:
11/12/99:
4/10/00:
1/12/01:
Initial Public Release
Added fpBGA package
Fixed typo on page 10
Changed drawing format
Page 2 Changed package body dimensions
Page 5 Deleted note 6 for Table II
Page 6 Improved power numbers
Upgraded speed to 133MHz, added 2.5V I/O capability
Page 4 Corrected I/O numbers in Truth Table I
Replaced IDT logo
Added new BGA package, added full 2.5V interface capability
Page 6 Updated Truth Table II
Increased storage temperature parameter
Clarified TA Parameter
Page 8 DC Electrical parameters–changed wording from "open" to "disabled"
Removed note 7 on DC Electrical Characteristics table
Removed Preliminary status
6.42
16
IDT70V3579S
High-Speed 32K x 36 Dual-Port Synchronous Pipelined Static RAM
Industrial and Commercial Temperature Ranges
Datasheet Document History (cont'd)
4/10/01:
7/19/01:
12/12/01:
02/07/06:
07/25/08:
10/23/08:
10/10/14:
Added Industrial Temperature Ranges and removed related notes
Page 3 Replaced incorrect BGA package drawing
Page 2, 3 & 4 Added date revision to pin configurations
Page 6 Removed industrial temp footnote from table 04
Page 8 & 10 Removed industrial temp for 6ns from DC & AC Electrical Characteristics
Page 16 Removed industrial temp from 6ns in ordering information
Added industrial temp footnote
Page 1 & 17 Replaced TM logo with ® logo
Page 1 Added green availability to features
Page 5 Changed footnote 2 for Truth Table I from ADS, CNTEN, CNTRST = VIH to ADS, CNTEN, CNTRST = X
Page 16 Added green indicator to ordering information
Page 8 Corrected a typo in the DC Chars table
Page 16 Removed "IDT" from orderable part number
Page 15 Added Tape and Reel to the Ordering Information
Š
CORPORATE HEADQUARTERS
6024 Silver Creek Valley Road
San Jose, CA 95138
for SALES:
800-345-7015 or 408-284-8200
fax: 408-284-2775
www.idt.com
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
6.42
17
for Tech Support:
408-284-2794
[email protected]
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