Product Folder Sample & Buy Support & Community Tools & Software Technical Documents LMH6601, LMH6601-Q1 SNOSAK9F – JUNE 2006 – REVISED JUNE 2015 LMH6601 and LMH6601-Q1 250-MHz, 2.4-V CMOS Operational Amplifier With Shutdown 1 Features 3 Description • The LMH6601 device is a low-voltage (2.4 V to 5.5 V), high-speed voltage feedback operational amplifier suitable for use in a variety of consumer and industrial applications. With a bandwidth of 125 MHz at a gain of +2 and ensured high-output current of 100 mA, the LMH6601 is an ideal choice for video line driver applications, including HDTV. Low-input bias current (50 pA maximum), rail-to-rail output, and low current noise allow the use of the LMH6601 in various industrial applications such as transimpedance amplifiers, active filters, or highimpedance buffers. The LMH6601 is an attractive solution for systems which require high performance at low supply voltages. The LMH6601 is available in a 6-pin SC70 package, and includes a micropower shutdown feature. • • • • • • • • • LMH6601-Q1 Qualified for Automotive Applications – AEC-Q100 Grade 3 – –40°C to 85°C Ambient Operating Temperature Range VS = 3.3 V, TA = 25°C, AV = 2 V/V, RL = 150 Ω to V−, Unless Specified 125 MHz −3 dB Small Signal Bandwidth 75 MHz −3 dB Large Signal Bandwidth 30 MHz Large Signal 0.1-dB Gain Flatness 260 V/μs Slew Rate 0.25%/0.25° Differential Gain and Differential Phase Rail-to-Rail Output 2.4-V to 5.5-V Single-Supply Operating Range 6-Pin SC70 Package 2 Applications • • • • • • • • Video Amplifiers Charge Amplifiers Set-Top Boxes Sample and Holds Transimpedance Amplifiers Line Drivers High-Impedance Buffers Automotive Device Information(1) PART NUMBER LMH6601 PACKAGE BODY SIZE (NOM) SC70 (6) LMH6601-Q1 2.00 mm × 1.25 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Response at a Gain of +2 for Various Supply Voltages 7 6 5 MAGNITUDE (dB) 1 2.7V 4 5V 3 3.3V 2 1 0 -1 1 10 100 1000 FREQUENCY (MHz 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. LMH6601, LMH6601-Q1 SNOSAK9F – JUNE 2006 – REVISED JUNE 2015 www.ti.com Table of Contents 1 2 3 4 5 6 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8 6.9 6.10 6.11 6.12 7 1 1 1 2 3 3 Absolute Maximum Ratings ...................................... 3 ESD Ratings - for LMH6601 ..................................... 3 ESD Ratings - for LMH6601-Q1 ............................... 4 Recommended Operating Conditions....................... 4 Thermal Information .................................................. 4 Electrical Characteristics, 5 V ................................... 4 Electrical Characteristics, 3.3 V ................................ 6 Electrical Characteristics, 2.7 V ................................ 8 Switching Characteristics, 5 V ................................ 10 Switching Characteristics, 3.3 V ........................... 11 Switching Characteristics, 2.7 V ........................... 11 Typical Characteristics .......................................... 12 Detailed Description ............................................ 20 7.1 Overview ................................................................. 20 7.2 Feature Description................................................. 20 7.3 Device Functional Modes........................................ 21 8 Application and Implementation ........................ 23 8.1 Application Information............................................ 23 8.2 Typical Application .................................................. 29 9 Power Supply Recommendations...................... 32 10 Layout................................................................... 32 10.1 Layout Guidelines ................................................. 32 10.2 Layout Examples................................................... 32 11 Device and Documentation Support ................. 33 11.1 11.2 11.3 11.4 11.5 11.6 Documentation Support ........................................ Related Links ........................................................ Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 33 33 33 33 33 33 12 Mechanical, Packaging, and Orderable Information ........................................................... 33 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision E (March 2013) to Revision F Page • Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1 • Removed IOS over temperature limit in Electrical Characteristics, 2.7 V ............................................................................... 8 • Moved the SAG Compensation section to the Typical Application section.......................................................................... 25 • Changed section titled Other Applications to Charge Preamplifier ..................................................................................... 28 Changes from Revision D (March 2013) to Revision E • 2 Page Changed layout of National Data Sheet to TI format ............................................................................................................. 1 Submit Documentation Feedback Copyright © 2006–2015, Texas Instruments Incorporated Product Folder Links: LMH6601 LMH6601-Q1 LMH6601, LMH6601-Q1 www.ti.com SNOSAK9F – JUNE 2006 – REVISED JUNE 2015 5 Pin Configuration and Functions DCK Package 6-Pin SC70 Top View 6 1 OUTPUT 5 V - 2 + +IN V + SD - 4 3 -IN Pin Functions PIN NO. NAME I/O DESCRIPTION 1 OUTPUT O Output 2 V- I Negative supply 3 +IN I Noninverting input 4 -IN I Inverting input 5 SD I Shutdown 6 V+ I Positive supply 6 Specifications 6.1 Absolute Maximum Ratings (1) MIN MAX UNIT VIN Differential ±2.5 V Input Current (2) ±10 mA Output Current 200 mA (3) mA + − Supply Voltage (V – V ) Voltage at Input/Output Pins Junction Temperature Soldering Information (2) (3) V V 150 °C Infrared or Convection (20 sec.) 235 Wave Soldering (10 sec.) 260 −65 Storage Temperature (1) 6 V++0.5, V−−0.5 150 °C °C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Negative input current implies current flowing out of the device. The maximum continuous output current (IOUT) is determined by device power dissipation limitations. 6.2 ESD Ratings - for LMH6601 VALUE Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 V(ESD) (1) (2) Electrostatic discharge (1) Charged-device model (CDM), per JEDEC specification JESD22C101 (2) UNIT ±2000 ±1000 V Human Body Model, applicable std. MIL-STD-883, Method 3015.7. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Copyright © 2006–2015, Texas Instruments Incorporated Product Folder Links: LMH6601 LMH6601-Q1 Submit Documentation Feedback 3 LMH6601, LMH6601-Q1 SNOSAK9F – JUNE 2006 – REVISED JUNE 2015 www.ti.com 6.3 ESD Ratings - for LMH6601-Q1 VALUE V(ESD) (1) Electrostatic discharge Human body model (HBM), per AEC Q100-002 (1) ±2000 Charged-device model (CDM), per AEC Q100-011 ±1000 UNIT V AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification. 6.4 Recommended Operating Conditions (1) + MIN MAX 2.4 5.5 V −40 85 °C − Supply Voltage (V – V ) Operating Temperature (1) UNIT Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 6.5 Thermal Information THERMAL METRIC LMH6601, LMH6601-Q1 (1) UNIT DCK (SC70) 6 PINS RθJA (1) Junction-to-ambient thermal resistance 414 °C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. 6.6 Electrical Characteristics, 5 V Single-Supply with VS= 5 V, AV = +2, RF = 604 Ω, SD tied to V+, VOUT = VS/2, RL = 150 Ω to V− unless otherwise specified. (1) PARAMETER MIN (2) TEST CONDITIONS TYP (2) MAX (2) UNIT FREQUENCY DOMAIN RESPONSE SSBW SSBW_1 –3-dB Bandwidth Small Signal VOUT = 0.25 VPP 130 VOUT = 0.25 VPP, AV = +1 250 2.5 MHz Peak Peaking VOUT = 0.25 VPP, AV = +1 Peak_1 Peaking VOUT = 0.25 VPP LSBW –3-dB Bandwidth Large Signal VOUT = 2 VPP Peak_2 Peaking VOUT = 2 VPP 0 dB 0.1 dB BW 0.1-dB Bandwidth VOUT = 2 VPP 30 MHz GBWP_1k GBWP_150 AVOL Gain Bandwidth Product dB 81 MHz Unity Gain, RL = 1 kΩ to VS/2 155 Unity Gain, RL = 150 Ω to VS/2 125 56 dB 0 MHz Large Signal Open-Loop Gain 0.5 V < VOUT < 4.5 V 66 dB PBW Full Power BW –1 dB, AV = +4, VOUT = 4.2 VPP, RL = 150 Ω to VS/2 30 MHz DG Differential Gain 4.43 MHz, 1.7 V ≤ VOUT ≤ 3.3 V, RL = 150 Ω to V− 0.06% DP Differential Phase 4.43 MHz, 1.7 V ≤ VOUT ≤ 3.3 V RL = 150 Ω to V− 0.10 10% deg TIME DOMAIN RESPONSE OS Overshoot 0.25-V Step CL Capacitor Load Tolerance AV = −1, 10% Overshoot, 75 Ω in Series (1) (2) 4 50 pF Electrical Characteristics, 5 V values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very limited self-heating of the device such that TJ = TA. No specification of parametric performance is indicated in the electrical tables under conditions of internal self-heating where TJ > TA. Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary over time and will also depend on the application and configuration. The typical values are not tested and are not ensured on shipped production material. Submit Documentation Feedback Copyright © 2006–2015, Texas Instruments Incorporated Product Folder Links: LMH6601 LMH6601-Q1 LMH6601, LMH6601-Q1 www.ti.com SNOSAK9F – JUNE 2006 – REVISED JUNE 2015 Electrical Characteristics, 5 V (continued) Single-Supply with VS= 5 V, AV = +2, RF = 604 Ω, SD tied to V+, VOUT = VS/2, RL = 150 Ω to V− unless otherwise specified.(1) PARAMETER TEST CONDITIONS MIN (2) TYP (2) MAX (2) UNIT DISTORTION and NOISE PERFORMANCE HD2 HD2_1 HD3 HD3_1 THD VN1 Harmonic Distortion (2nd) Harmonic Distortion (3rd) Total Harmonic Distortion IN −56 4 VPP, 10 MHz, RL = 1 kΩ to VS/2 −61 2 VPP, 10 MHz −73 4 VPP, 10 MHz, RL = 1 kΩ to VS/2 −64 4 VPP, 10 MHz, RL = 1 kΩ to VS/2 −58 >10 MHz Input Voltage Noise VN2 2 VPP, 10 MHz Input Current Noise dBc dBc 7 1 MHz 10 >1 MHz 50 nV/√Hz fA/√Hz STATIC, DC PERFORMANCE ±1 VIO Input Offset Voltage DVIO Input Offset Voltage Average Drift At temperature extremes (3) −5 5 50 2 25 IB Input Bias Current See IOS Input Offset Current See (4) RIN Input Resistance 0 V ≤ VIN ≤ 3.5 V CIN Input Capacitance +PSRR Positive Power Supply Rejection Ratio DC At temperature extremes −PSRR Negative Power Supply Rejection Ratio DC At temperature extremes CMRR Common-Mode Rejection Ratio DC CMVR Input Voltage Range CMRR > 50 dB (At temperature extremes) 55 Supply Current Shutdown SD tied to ≤ 0.5 V VOH2 Output High Voltage (Relative to V+) At temperature extremes (3) (4) (5) dB 61 dB 68 dB – V+ – 1.5 9.6 11.5 mA nA –190 –190 At temperature extremes V –480 –60 RL = 10 kΩ to V– 59 100 RL = 75 Ω to VS/2 VOH3 pF 13.5 –210 RL = 150 Ω to V– VOH1 1.3 At temperature extremes (5) pA TΩ 53 V− – 0.20 pA 10 50 56 Normal Operation VOUT = VS/2 μV/°C 51 53 At temperature extremes mV ±5 See (4) ICC ±2.4 mV –12 –110 Drift determined by dividing the change in parameter at temperature extremes by the total temperature change. This parameter is ensured by design and/or characterization and is not tested in production. SD logic is CMOS compatible. To ensure proper logic level and to minimize power supply current, SD should typically be less than 10% of total supply voltage away from either supply rail. Copyright © 2006–2015, Texas Instruments Incorporated Product Folder Links: LMH6601 LMH6601-Q1 Submit Documentation Feedback 5 LMH6601, LMH6601-Q1 SNOSAK9F – JUNE 2006 – REVISED JUNE 2015 www.ti.com Electrical Characteristics, 5 V (continued) Single-Supply with VS= 5 V, AV = +2, RF = 604 Ω, SD tied to V+, VOUT = VS/2, RL = 150 Ω to V− unless otherwise specified.(1) PARAMETER RL = 150 Ω to V– VOL1 Output Low Voltage (Relative to V–) VOL2 MIN (2) TEST CONDITIONS TYP (2) MAX (2) 5 45 At temperature extremes 125 RL = 75 Ω to VS/2 120 5 VOL3 RL = 10 kΩ to V– At temperature extremes IO VOUT < 0.6 V from Respective Supply Source 150 Sink 180 Output Current VOUT = VS/2, VID = ±18 mV IO_1 UNIT mV 45 125 mA ±100 (6) Load Output Load Rating THD < −30 dBc, f = 200 kHz, RL tied to VS/2, VOUT = 4 VPP 20 Ω RO_Enabled Output Resistance Enabled, AV = +1 0.2 Ω RO_Disabled Output Resistance Shutdown >100 MΩ CO_Disabled Output Capacitance Shutdown 5 pF MISCELLANEOUS PERFORMANCE VDMAX Voltage Limit for Disable (Pin 5) See (5) (At temperature extremes) 0 0.5 VDMIN Voltage Limit for Enable (Pin 5) See (5) (At temperature extremes) 4.5 5 Ii Logic Input Current (Pin 5) SD = 5 V (5) V_glitch Turnon Glitch IsolationOFF Off Isolation (6) 1 MHz, RL = 1 kΩ V V 10 pA 2.2 V 60 dB “VID” is input differential voltage (input overdrive). 6.7 Electrical Characteristics, 3.3 V Single-Supply with VS= 3.3 V, AV = +2, RF = 604Ω, SD tied to V+, VOUT = VS/2, RL = 150 Ω to V− unless otherwise specified. (1) PARAMETER MIN (2) TEST CONDITIONS TYP (2) MAX (2) UNIT FREQUENCY DOMAIN RESPONSE SSBW SSBW_1 –3-dB Bandwidth Small Signal VOUT = 0.25 VPP 125 VOUT = 0.25 VPP, AV = +1 250 Peak Peaking VOUT = 0.25 VPP, AV = +1 Peak_1 Peaking VOUT = 0.25 VPP LSBW –3-dB Bandwidth Large Signal VOUT = 2 V PP Peak_2 Peaking VOUT = 2 VPP 0 dB 0.1 dB BW 0.1-dB Bandwidth VOUT = 2 VPP 30 MHz GBWP_1k GBWP_150 AVOL Gain Bandwidth Product 3 MHz 0.05 75 Unity Gain, RL = 1 kΩ to VS/2 115 Unity Gain, RL = 150 Ω to VS/2 105 Large Signal Open-Loop Gain 0.3 V < VOUT < 3 V PBW Full Power BW –1 dB, AV = +4, VOUT = 2.8 VPP, RL = 150 Ω to VS/2 DG Differential Gain 4.43 MHz, 0.85 V ≤ VOUT ≤ 2.45 V, RL = 150 Ω to V− 0.06% DP Differential Phase 4.43 MHz, 0.85 V ≤ VOUT ≤ 2.45 V RL = 150 Ω to V− 0.23 (1) (2) 6 56 dB dB MHz MHz 67 dB 30 MHz deg Electrical Characteristics, 3.3 V values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very limited self-heating of the device such that TJ = TA. No specification of parametric performance is indicated in the electrical tables under conditions of internal self-heating where TJ > TA. Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary over time and will also depend on the application and configuration. The typical values are not tested and are not ensured on shipped production material. Submit Documentation Feedback Copyright © 2006–2015, Texas Instruments Incorporated Product Folder Links: LMH6601 LMH6601-Q1 LMH6601, LMH6601-Q1 www.ti.com SNOSAK9F – JUNE 2006 – REVISED JUNE 2015 Electrical Characteristics, 3.3 V (continued) Single-Supply with VS= 3.3 V, AV = +2, RF = 604Ω, SD tied to V+, VOUT = VS/2, RL = 150 Ω to V− unless otherwise specified.(1) PARAMETER TEST CONDITIONS MIN (2) TYP (2) MAX (2) UNIT TIME DOMAIN RESPONSE OS Overshoot 0.25-V Step CL Capacitor Load Tolerance AV = −1, 10% Overshoot, 82 Ω in Series 10% 50 pF DISTORTION and NOISE PERFORMANCE HD2 HD2_1 Harmonic Distortion (2nd) HD3 HD3_2 THD VN1 Harmonic Distortion (3rd) Total Harmonic Distortion IN −61 2 VPP, 10 MHz RL = 1 kΩ to VS/2 −79 2 VPP, 10 MHz −53 2 VPP, 10 MHz RL = 1 kΩ to VS/2 −69 2 VPP, 10 MHz RL = 1 kΩ to VS/2 −66 >10 MHz Input Voltage Noise VN2 2 VPP, 10 MHz Input Current Noise dBc dBc dBc 7 1 MHz 10 >1 MHz 50 nV/√Hz fA/√Hz STATIC, DC PERFORMANCE ±1 VIO Input Offset Voltage DVIO Input Offset Voltage Average Drift At temperature extremes See (3) Input Bias Current See IOS Input Offset Current See RIN Input Resistance 0 V ≤ VIN ≤ 1.8 V CIN Input Capacitance −4.5 (4) +PSRR Positive Power Supply Rejection Ratio DC At temperature extremes 51 −PSRR Negative Power Supply Rejection Ratio DC 57 At temperature extremes 52 CMRR Common-Mode Rejection Ratio DC 58 At temperature extremes 55 CMVR Input Voltage ICC CMRR > 50 dB (At temperature extremes) Normal Operation VOUT = VS/2 Supply Current 61 VOH2 Output High Voltage (Relative to V+) (3) (4) (5) 25 pA 15 TΩ 1.4 pF 80 At temperature extremes dB 72 dB 73 dB V+ – 1.5 100 mA nA –190 –360 –190 At temperature extremes V 11 13 –50 RL = 10 kΩ to V− pA 2 9.2 RL = 75 Ω to VS/2 VOH3 50 At temperature extremes –210 RL = 150 Ω to V– μV/°C 5 V− – 0.20 Shutdown: SD tied to ≤ 0.33 V (5) VOH1 mV ±5.5 (4) IB ±2.6 mV –10 –100 Drift determined by dividing the change in parameter at temperature extremes by the total temperature change. This parameter is ensured by design and/or characterization and is not tested in production. SD logic is CMOS compatible. To ensure proper logic level and to minimize power supply current, SD should typically be less than 10% of total supply voltage away from either supply rail. Copyright © 2006–2015, Texas Instruments Incorporated Product Folder Links: LMH6601 LMH6601-Q1 Submit Documentation Feedback 7 LMH6601, LMH6601-Q1 SNOSAK9F – JUNE 2006 – REVISED JUNE 2015 www.ti.com Electrical Characteristics, 3.3 V (continued) Single-Supply with VS= 3.3 V, AV = +2, RF = 604Ω, SD tied to V+, VOUT = VS/2, RL = 150 Ω to V− unless otherwise specified.(1) PARAMETER RL = 150 Ω to V– VOL1 Output Low Voltage (Relative to V–) VOL2 MIN (2) TEST CONDITIONS TYP (2) MAX (2) 4 45 At temperature extremes 125 RL = 75 Ω to VS/2 105 4 VOL3 RL = 10 kΩ to V– IO VOUT < 0.6 V from Source Respective Sink Supply Output Current At temperature extremes mV 45 125 50 VOUT = VS/2, VID = ±18 mV (6) IO_1 UNIT 75 mA ±75 Load Output Load Rating THD < −30 dBc, f = 200 kHz, RL tied to VS/2, VOUT = 2.6 VPP 25 Ω RO_Enabled Output Resistance Enabled, AV = +1 0.2 Ω RO_Disabled Output Resistance Shutdown >100 MΩ CO_Disabled Output Capacitance Shutdown 5.6 pF MISCELLANEOUS PERFORMANCE VDMAX Voltage Limit for Disable (Pin 5) See (5) (At temperature extremes) 0 (5) (At temperature extremes) 2.97 VDMIN Voltage Limit for Enable (Pin 5) See Ii Logic Input Current (Pin 5) SD = 3.3 V (5) V_glitch Turnon Glitch IsolationOFF Off Isolation (6) 1 MHz, RL = 1 kΩ 0.33 3.3 V V 8 pA 1.6 V 60 dB “VID” is input differential voltage (input overdrive). 6.8 Electrical Characteristics, 2.7 V Single-Supply with VS = 2.7 V, AV = +2, RF = 604 Ω, SD tied to V+, VOUT = VS/2, RL = 150 Ω to V− unless otherwise specified. (1) PARAMETER MIN (2) TEST CONDITIONS TYP (2) MAX (2) UNIT FREQUENCY DOMAIN RESPONSE SSBW SSBW_1 –3-dB Bandwidth Small Signal VOUT = 0.25 VPP 120 VOUT = 0.25 VPP, AV = +1 250 MHz Peak Peaking VOUT = 0.25 VPP, AV = +1 3.1 Peak_1 Peaking VOUT = 0.25 VPP 0.1 dB LSBW –3-dB Bandwidth Large Signal VOUT = 2 V PP 73 MHz Peak_2 Peaking VOUT = 2 VPP 0 dB 0.1 dB BW 0.1-dB Bandwidth VOUT = 2 VPP 30 MHz GBWP_1k GBWP_150 AVOL Gain Bandwidth Product Unity Gain, RL = 1 kΩ to VS/2 Unity Gain, RL = 150 Ω to VS/2 Large Signal Open-Loop Gain 0.25 V < VOUT < 2.5 V PBW Full Power BW –1 dB, AV = +4, VOUT = 2 VPP, RL = 150 Ω to VS/2 DG Differential Gain 4.43 MHz, 0.45 V ≤ VOUT ≤ 2.05 V RL = 150 Ω to V− (1) (2) 8 110 81 56 dB MHz 65 dB 13 MHz 0.12% Electrical Characteristics, 2.7 V values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very limited self-heating of the device such that TJ = TA. No specification of parametric performance is indicated in the electrical tables under conditions of internal self-heating where TJ > TA. Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary over time and will also depend on the application and configuration. The typical values are not tested and are not ensured on shipped production material. Submit Documentation Feedback Copyright © 2006–2015, Texas Instruments Incorporated Product Folder Links: LMH6601 LMH6601-Q1 LMH6601, LMH6601-Q1 www.ti.com SNOSAK9F – JUNE 2006 – REVISED JUNE 2015 Electrical Characteristics, 2.7 V (continued) Single-Supply with VS = 2.7 V, AV = +2, RF = 604 Ω, SD tied to V+, VOUT = VS/2, RL = 150 Ω to V− unless otherwise specified.(1) PARAMETER DP TEST CONDITIONS Differential Phase MIN (2) TYP (2) 4.43 MHz, 0.45 V ≤ VOUT ≤ 2.05 V RL = 150 Ω to V− 0.62 0.25-V Step 10% MAX (2) UNIT deg TIME DOMAIN RESPONSE OS Overshoot DISTORTION and NOISE PERFORMANCE HD2 Harmonic Distortion (2nd) 1 VPP, 10 MHz −58 dBc HD3 Harmonic Distortion (3rd) 1 VPP, 10 MHz −60 dBc VN1 Input Voltage Noise VN2 IN Input Current Noise >10 MHz 8.4 1 MHz 12 >1 MHz 50 nV/√Hz fA/√Hz STATIC, DC PERFORMANCE ±1 VIO Input Offset Voltage DVIO Input Offset Voltage Average Drift At temperature extremes (3) −6.5 (4) 5 50 2 25 Input Bias Current See IOS Input Offset Current See RIN Input Resistance 0V ≤ VIN ≤ 1.2V CIN Input Capacitance +PSRR Positive Power Supply Rejection Ratio DC At temperature extremes −PSRR Negative Power Supply Rejection Ratio DC At temperature extremes CMRR Common-Mode Rejection Ratio DC CMVR Input Voltage CMRR > 50 dB (At temperature extremes) (4) 58 Supply Current VOH2 Output High Voltage (Relative to V+) At temperature extremes (3) (4) (5) dB 69 dB 77 dB – V+ – 1.5 9 10.6 mA nA –200 –200 At temperature extremes V –420 –50 RL = 10 kΩ to V– 68 100 RL = 75 Ω to VS/2 VOH3 pF 12.5 –260 RL = 150 Ω to V– VOH1 1.6 At temperature extremes Shutdown SD tied to ≤ 0.27 V (5) pA TΩ 52 V− – 0.20 pA 20 53 57 Normal Operation VOUT = VS/2 μV/°C 53 56 At temperature extremes mV ±6.5 See IB ICC ±3.5 mV –10 100 Drift determined by dividing the change in parameter at temperature extremes by the total temperature change. This parameter is ensured by design and/or characterization and is not tested in production. SD logic is CMOS compatible. To ensure proper logic level and to minimize power supply current, SD should typically be less than 10% of total supply voltage away from either supply rail. Copyright © 2006–2015, Texas Instruments Incorporated Product Folder Links: LMH6601 LMH6601-Q1 Submit Documentation Feedback 9 LMH6601, LMH6601-Q1 SNOSAK9F – JUNE 2006 – REVISED JUNE 2015 www.ti.com Electrical Characteristics, 2.7 V (continued) Single-Supply with VS = 2.7 V, AV = +2, RF = 604 Ω, SD tied to V+, VOUT = VS/2, RL = 150 Ω to V− unless otherwise specified.(1) PARAMETER MIN (2) TEST CONDITIONS TYP (2) MAX (2) 4 45 RL = 150 Ω to V– VOL1 VOL2 125 RL = 75 Ω to VS/2 Output Low Voltage (Relative to V–) 125 4 VOL3 RL = 10 kΩ to V– IO VOUT ≤ 0.6 V from Source Respective Sink Supply Output Current VOUT = VS/2, VID = ±18 mV (6) IO_1 UNIT At temperature extremes mV 45 125 25 62 Source 25 Sink 35 mA Load Output Load Rating THD < −30 dBc, f = 200 kHz, RL tied to VS/2, VOUT = 2.2 VPP RO_Enable Output Resistance Enabled, AV = +1 RO_Disabled Output Resistance Shutdown >100 MΩ CO_Disabled Output Capacitance Shutdown 5.6 pF Ω 40 Ω 0.2 MISCELLANEOUS PERFORMANCE VDMAX Voltage Limit for Disable (Pin 5) See (5) (At temperature extremes) 0 (5) (At temperature extremes) 2.43 VDMIN Voltage Limit for Enable (Pin 5) See Ii Logic Input Current (Pin 5) SD = 2.7 V (5) V_glitch Turnon Glitch IsolationOFF Off Isolation (6) 0.27 2.7 4 V V pA 1.2 V 60 dB 1 MHz, RL = 1 kΩ “VID” is input differential voltage (input overdrive). 6.9 Switching Characteristics, 5 V Single-Supply with VS= 5 V, AV = +2, RF = 604 Ω, SD tied to V+, VOUT = VS/2, RL = 150 Ω to V− unless otherwise specified. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT TIME DOMAIN RESPONSE TRS/TRL Rise and Fall Time 0.25-V Step 2.6 ns SR Slew Rate 2-V Step 275 V/μs TS TS_1 PD Settling Time Propagation Delay 1-V Step, ±0.1% 50 1-V Step, ±0.02% 220 Input to Output, 250-mV Step, 50% 2.4 ns 1.4 µs ns MISCELLANEOUS PERFORMANCE Ton Turnon Time Toff Turnoff Time 520 ns T_OL Overload Recovery <20 ns 10 Submit Documentation Feedback Copyright © 2006–2015, Texas Instruments Incorporated Product Folder Links: LMH6601 LMH6601-Q1 LMH6601, LMH6601-Q1 www.ti.com SNOSAK9F – JUNE 2006 – REVISED JUNE 2015 6.10 Switching Characteristics, 3.3 V Single-Supply with VS= 3.3 V, AV = +2, RF = 604Ω, SD tied to V+, VOUT = VS/2, RL = 150 Ω to V− unless otherwise specified. (1) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT TIME DOMAIN RESPONSE TRS/TRL Rise and Fall Time 0.25-V Step 2.7 ns SR Slew Rate 2-V Step 260 V/μs TS TS_1 PD Settling Time Propagation Delay 1-V Step, ±0.1% 70 1-V Step, ±0.02% 300 Input to Output, 250-mV Step, 50% 2.6 ns ns MISCELLANEOUS PERFORMANCE Ton Turnon Time 3.5 µs Toff Turnoff Time 500 ns (1) Electrical Characteristics, 3.3 V values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very limited self-heating of the device such that TJ = TA. No specification of parametric performance is indicated in the electrical tables under conditions of internal self-heating where TJ > TA. 6.11 Switching Characteristics, 2.7 V Single-Supply with VS = 2.7 V, AV = +2, RF = 604 Ω, SD tied to V+, VOUT = VS/2, RL = 150 Ω to V− unless otherwise specified. (1) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT TIME DOMAIN RESPONSE TRS/TRL Rise and Fall Time 0.25-V Step 2.7 ns SR Slew Rate 2-V Step 260 V/μs 1-V Step, ±0.1% 147 1-V Step, ±0.02% 410 Input to Output, 250-mV Step, 50% 3.4 ns TS TS_1 PD Settling Time Propagation Delay ns MISCELLANEOUS PERFORMANCE Ton Turnon Time 5.2 µs Toff Turnoff Time 760 ns (1) Electrical Characteristics, 2.7 V values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very limited self-heating of the device such that TJ = TA. No specification of parametric performance is indicated in the electrical tables under conditions of internal self-heating where TJ > TA. Copyright © 2006–2015, Texas Instruments Incorporated Product Folder Links: LMH6601 LMH6601-Q1 Submit Documentation Feedback 11 LMH6601, LMH6601-Q1 SNOSAK9F – JUNE 2006 – REVISED JUNE 2015 www.ti.com 6.12 Typical Characteristics Unless otherwise noted, all data is with AV = +2, RF = RG = 604 Ω, VS = 3.3V, VOUT = VS/2, SD tied to V+, RL = 150 Ω to V−, T = 25°C. 80 0 40 0.25 VPP -40 -6 1 VPP -9 -80 2 VPP -120 -3 -80 -9 1 VPP -12 -120 2 VPP -15 -18 -200 -18 100 -40 -6 -160 10 -160 1 1000 10 Figure 1. Frequency Response for Various Output Amplitudes 3 80 0 150 AV = +2 0.25 VPP 40 0.25 VPP -3 125 PHASE -40 -6 1 VPP -80 2 VPP -12 -3 dB BW (MHz) 0 PHASE (°) NORMALIZED GAIN (dB) Figure 2. Frequency Response for Various Output Amplitudes VS = 2.7V -9 100 1 VPP -120 -15 75 2 VPP -160 -18 1 10 100 -200 1000 50 2.5 3 3.5 60 AV = +1 60 GAIN 40 0 20 -3 AV = -1 -6 0 -9 -20 AV = +1 -12 -40 AV = +2 -15 -60 AV = +5 -18 -80 AV = +10 VOUT = 0.25 VPP -21 1 10 100 -100 1000 NORMALIZED GAIN (dB) AV = +10 PHASE (°) NORMALIZED GAIN (dB) AV = +5 PHASE AV = -2 -6 -9 AV = -5 0 -20 -40 -12 -60 -15 AV = -10 -18 -80 VOUT = 0.25 VPP -21 1 10 100 -100 1000 FREQUENCY (MHz) Figure 5. Noninverting Frequency Response for Various Gain Submit Documentation Feedback 40 20 PHASE FREQUENCY (MHz) 12 5 3 AV = +2 0 -3 4.5 Figure 4. −3 dB BW vs. Supply Voltage for Various Output Swings Figure 3. Frequency Response for Various Output Amplitudes GAIN 4 VS (V) FREQUENCY (MHz) 3 -200 1000 100 FREQUENCY (MHz) FREQUENCY (MHz) GAIN 0 PHASE -15 1 40 0.25 VPP PHASE (°) -12 PHASE (°) 0 -3 PHASE VS = 3.3V GAIN NORMALIZED GAIN (dB) 0 NORMALIZED GAIN (dB) 3 80 VS = 5V GAIN PHASE (°) 3 Figure 6. Inverting Frequency Response for Various Gain Copyright © 2006–2015, Texas Instruments Incorporated Product Folder Links: LMH6601 LMH6601-Q1 LMH6601, LMH6601-Q1 www.ti.com SNOSAK9F – JUNE 2006 – REVISED JUNE 2015 Typical Characteristics (continued) 6 VOUT = 0.25 VPP 3 RL TIED TO V- 3 0 1 k: -3 50: -6 150: -9 -12 0 -60 -90 -9 -120 2.7V -12 -150 3.3V -15 -18 100 1000 AV = +1 -180 1 -210 1000 100 10 FREQUENCY (MHz) Figure 7. Frequency Response for Various Loads Figure 8. Frequency Response for Various Supply Voltages 6 140 130 NORMALIZED GAIN (dB) 5V 120 3.3V 110 100 AV = +2 5 pF 0 0 pF -3 -6 -9 20 pF -20 VOUT = 0.25 VPP -15 0 0 pF -12 VOUT = 2 VPP 80 -40 20 pF 10 pF 3 -3 dB BW (MHz) 5V VOUT = 0.25 VPP FREQUENCY (MHz) 90 -30 5V GAIN -6 -18 10 0 3.3V -3 -15 1 30 2.7V PHASE PHASE (°) 6 NORMALIZED GAIN (dB) NORMALIZED GAIN (dB) Unless otherwise noted, all data is with AV = +2, RF = RG = 604 Ω, VS = 3.3V, VOUT = VS/2, SD tied to V+, RL = 150 Ω to V−, T = 25°C. - RL = 1 k: || CL to V 20 40 60 -18 100 80 1 TEMPERATURE (°C) 10 100 1000 FREQUENCY (MHz) Figure 9. −3 dB BW vs. Ambient Temperature Figure 10. Frequency Response for Various Capacitor Load 7 6 6 5 2.7V 4 VOUT (VPP) MAGNITUDE (dB) 5 5V 3 3.3V 2 4 THD < -30 dBc 3 2 1 VS = 5V 1 AV = +2 0 -1 1 10 100 1000 RL = 150: to VS/2 0 10k 100k 1M 10M 100M FREQUENCY (Hz) FREQUENCY (MHz Figure 11. Frequency Response for Various Supply Voltage Figure 12. Maximum Output Swing vs. Frequency Copyright © 2006–2015, Texas Instruments Incorporated Product Folder Links: LMH6601 LMH6601-Q1 Submit Documentation Feedback 13 LMH6601, LMH6601-Q1 SNOSAK9F – JUNE 2006 – REVISED JUNE 2015 www.ti.com Typical Characteristics (continued) Unless otherwise noted, all data is with AV = +2, RF = RG = 604 Ω, VS = 3.3V, VOUT = VS/2, SD tied to V+, RL = 150 Ω to V−, T = 25°C. 2.5 1 5V 3.3V VOUT FROM V (V) 3.3V - PEAK SWING (VP) 2 1.5 2.7V 1 AV = +5 V/V RL to VS/2 5V 0.1 VOUT_DC = VS/2 0.5 UNDISORTED OUTPUT SWING (LIMITED BY SOURCE CURRENT) 0 10 20 30 40 50 60 70 80 0.01 90 100 0 20 40 RL (:) 60 80 100 ISINK (mA) Figure 14. Output Swing vs. Sink Current for Various Supply Voltages Figure 13. Peak Output Swing vs. RL -30 10 -35 VOUT = 2 VPP -45 1 -50 3.3V HD2 (dBc) + VOUT FROM V (V) -40 5V 0.1 -55 2.7V -60 -65 5V -70 -75 -80 -85 -90 0.1 0.01 0 20 40 60 80 100 3.3V 1 ISOURCE (mA) Figure 15. Output Swing vs. Source Current for Various Supply Voltages -30 -35 -40 RL = 1 k: to VS/2 -40 -50 THD (dBc) HD3 (dBc) 10 MHz -60 -55 -60 -65 VS = 5V 2.7V -50 100 Figure 16. HD2 vs. Frequency VOUT = 2 VPP -45 10 FREQUENCY (MHz) 3.3V -70 -70 -80 -75 1 MHz -80 -90 5V -85 -90 0.1 1 10 100 FREQUENCY (MHz) -100 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 OUTPUT (VPP) Figure 17. HD3 vs. Frequency 14 Submit Documentation Feedback Figure 18. THD vs. Output Swing Copyright © 2006–2015, Texas Instruments Incorporated Product Folder Links: LMH6601 LMH6601-Q1 LMH6601, LMH6601-Q1 www.ti.com SNOSAK9F – JUNE 2006 – REVISED JUNE 2015 Typical Characteristics (continued) Unless otherwise noted, all data is with AV = +2, RF = RG = 604 Ω, VS = 3.3V, VOUT = VS/2, SD tied to V+, RL = 150 Ω to V−, T = 25°C. -20 310 RL = 1 k: to VS/2 -30 SLEW RATE (V/Ps) -40 THD (dBc) 5V, FALLING 290 VS = 3.3V -50 -60 10 MHz -70 -80 270 3.3V, FALLING 250 5V, RISING 230 3.3V RISING 210 190 170 AV = +2 VOUT = 2 VPP 150 -40 -20 0 -90 1 MHz -100 0.5 0 1 1.5 2 2.5 3 60 60 80 100 AV = -1 RL = 150: to VS/2 VS = 5V (0.2%/DIV) SETTLING TIME (ns) 70 40 Figure 20. Slew Rate vs. Ambient Temperature Figure 19. THD vs. Output Swing 80 20 TEMPERATURE (°C) OUTPUT (VPP) 50 40 30 VS = 5V RL = 150: to VS/2 20 AV = -1 10 VOUT = 1 VPP 0 TIME (20 ns/DIV) 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 VOUT (VPP) Figure 22. Output Settling Figure 21. Settling Time (±1%) vs. Output Swing 250 25 250 20 200 25 SETTLING TIME 15 AV = -1 100 RL = RF = 1 k: 10 VS = 5V VO = 1 VPP STEP 50 5 20 10% OVERSHOOT 150 ACROSS CL 100 RL = RF = 1 k: 0 50 100 150 10 VS = 3.3V VO = 1 VPP STEP 50 ISOLATION RESISTOR 0 15 AV = -1 5 ±5% SETTLING TIME (ns) 150 RISO (:) RISO (:) 10% OVERSHOOT ACROSS CL ±5% SETTLING TIME (ns) SETTLING TIME 200 ISOLATION RESISTOR 0 250 200 0 0 50 100 150 200 0 250 CL (pF) CL (pF) Figure 23. Isolation Resistor and Settling Time vs. CL Figure 24. Isolation Resistor and Settling Time vs. CL Copyright © 2006–2015, Texas Instruments Incorporated Product Folder Links: LMH6601 LMH6601-Q1 Submit Documentation Feedback 15 LMH6601, LMH6601-Q1 SNOSAK9F – JUNE 2006 – REVISED JUNE 2015 www.ti.com Typical Characteristics (continued) Unless otherwise noted, all data is with AV = +2, RF = RG = 604 Ω, VS = 3.3V, VOUT = VS/2, SD tied to V+, RL = 150 Ω to V−, T = 25°C. 0 100 VS = 5V AV = +1 -10 ISOLATION (dB) -20 |ZOUT| (:) 10 2.7V 3.3V 1 -30 AV = +2 RF = RG = 510: RL = 100 k: -40 -50 -60 5V -70 -80 1k 10k 100k 10M 1M -90 100k 100M 1M 10M Figure 25. Closed-Loop Output Impedance vs. Frequency for Various Supply Voltages Figure 26. Off Isolation vs. Frequency 250 10000 1000 2.7V GAIN (dB) NOISE VOLTAGE (nV/ Hz) 100M FREQUENCY (Hz) FREQUENCY (Hz) 3.3V 100 5V 60 200 50 150 PHASE 40 100 30 50 20 0 GAIN 10 PHASE (°) 0.1 100 0 10 1 10 100 1k 10k 100k 1M 1k 10M 10k 100k 1M 10M 100M 500M FREQUENCY (Hz) FREQUENCY (Hz) Figure 27. Noise Voltage vs. Frequency Figure 28. Open-Loop Gain and Phase 80 90 70 80 3.3V 2.7V 70 50 +PSRR (dB) CMRR (dB) 60 40 30 60 50 5V 40 30 20 20 10 10 0 1k 0 10k 100k 1M 10M 100M 10k FREQUENCY (Hz) Submit Documentation Feedback 1M 10M 100M FREQUENCY (Hz) Figure 29. CMRR vs. Frequency 16 100k Figure 30. +PSRR vs. Frequency Copyright © 2006–2015, Texas Instruments Incorporated Product Folder Links: LMH6601 LMH6601-Q1 LMH6601, LMH6601-Q1 www.ti.com SNOSAK9F – JUNE 2006 – REVISED JUNE 2015 Typical Characteristics (continued) Unless otherwise noted, all data is with AV = +2, RF = RG = 604 Ω, VS = 3.3V, VOUT = VS/2, SD tied to V+, RL = 150 Ω to V−, T = 25°C. 80 10 3.3V 2.7V 70 9.8 9.4 5V 50 IS (mA) -PSRR (dB) 5V 9.6 60 40 30 3.3V 9.2 9 2.7V 8.8 20 8.6 10 8.4 8.2 -40 0 10k 100k 1M 10M 100M -20 0 20 40 60 80 100 TEMPERATURE (°C) FREQUENCY (Hz) Figure 31. −PSRR vs. Frequency Figure 32. Supply Current vs. Ambient Temperature 18 12 VS = 5V 16 125°C - VCM MEASURE FROM V 10 14 85°C 8 ICC (mA) ICC (mA) 12 10 8 25°C -40°C 6 -40°C 25°C 6 4 4 2 2 0 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 2 2.5 3 3.5 4 4.5 5 VS (V) Figure 33. Supply Current vs. VCM Figure 34. Supply Current vs. Supply Voltage 1.00 VS = 2.7V RELATIVE FREQUENCY (%) UNIT 2 0.80 0.60 0.40 VIO (mV) 1.5 VCM (V) 0.20 UNIT 1 0.00 UNIT 3 -0.20 -0.40 -0.60 -0.80 -40 -20 0 20 40 60 80 100 7 6.5 6 5.5 5 4.5 4 3.5 3 2.5 2 1.5 1 0.5 0 -1.8 -1.4 -1 -0.6 -0.2 0.2 0.6 TEMPERATURE (°C) VS = 3.3V 1 1.4 1.8 2.2 VIO (mV) Figure 35. Offset Voltage vs. Ambient Temperature for 3 Representative Units Figure 36. Offset Voltage Distribution Copyright © 2006–2015, Texas Instruments Incorporated Product Folder Links: LMH6601 LMH6601-Q1 Submit Documentation Feedback 17 LMH6601, LMH6601-Q1 SNOSAK9F – JUNE 2006 – REVISED JUNE 2015 www.ti.com Typical Characteristics (continued) Unless otherwise noted, all data is with AV = +2, RF = RG = 604 Ω, VS = 3.3V, VOUT = VS/2, SD tied to V+, RL = 150 Ω to V−, T = 25°C. 4 1000 125°C 85°C 2 25°C 100 125° OPERATION IS NOT RECOMMENDED -2 10 |IB| (pA) VIO (mV) 0 -40°C -4 1 25°C -6 .1 VS = 3.3V -8 - VCM MEASURED FROM V 0 0.5 1 1.5 VS = 5V .01 -10 2 2.5 -1 0 1 2 3 5 6 VCM (V) Figure 37. Offset Voltage vs. VCM (Typical Part) Figure 38. Input Bias Current vs. Common Mode Voltage 1.5 2.5 VOUT = 0.25 VPP VOUT = 2 VPP AV = +2 AV = +2 2 VS = 2.7V OUTPUT (V) 1.4 OUTPUT (V) 4 VCM (V) 1.3 VS = 2.7V 1.5 1 1.2 0.5 0 1.1 0 20 40 60 80 100 0 20 40 60 80 100 TIME (ns) TIME (ns) Figure 39. Small Signal Step Response Figure 40. Large Signal Step Response 2.5 - SD 2 V/DIV RL = 100: to V AV = +1 0V 1.5 0V OUTPUT 0.5 V/DIV VOUT (V) 2 1 VS = ±1.65V RL = 150: to VS/2 0.5 0 10 20 2.5 Ps/DIV 30 TIME (ns) Figure 41. Large Signal Step Response 18 Submit Documentation Feedback Figure 42. Turn On/Off Waveform Copyright © 2006–2015, Texas Instruments Incorporated Product Folder Links: LMH6601 LMH6601-Q1 LMH6601, LMH6601-Q1 www.ti.com SNOSAK9F – JUNE 2006 – REVISED JUNE 2015 Typical Characteristics (continued) Unless otherwise noted, all data is with AV = +2, RF = RG = 604 Ω, VS = 3.3V, VOUT = VS/2, SD tied to V+, RL = 150 Ω to V−, T = 25°C. 0.2 0.2 - VS = 5V RL = 150: TO V DC COUPLED DG MEASURED RELATIVE 0.1 0 -0.1 DP (°) DG (%) 0.1 TO V OUT = VS/2 IN EACH CASE 0 VS = 2.5V VS = 5V - -0.3 -0.4 RL = 150: TO V DC COUPLED DP MEASURED -0.5 RELATIVE TO VOUT = VS = 3.3V -0.1 VS = 2.5V -0.2 -2.5 -2 -0.5 -1 -0.5 0 0.5 1 1.5 VS/2 IN EACH CASE -0.6 -2.5 -2 -1.5 -1 -0.5 0 0.5 1 1.5 2 2 VOUT FROM VS/2 (V) VOUT FROM VS/2 (V) Figure 43. DG vs. VOUT for Various VS Figure 44. DP vs. VOUT for Various VS 0.4 1 VS = 5V 0.8 0.3 RL = 150: DG MEASURED 0.2 RELATIVE TO VOUT = VS/2 IN EACH CASE AC COUPLED 0.6 0.4 DC COUPLED 0.2 DP (°) DG (%) VS = 3.3V -0.2 0.1 0 -0.1 0 -0.2 AC COUPLED DC COUPLED -0.4 VS = 5V -0.6 RL = 150: DP MEASURED RELATIVE TO -0.8 -0.2 -1 -0.6 -0.2 0.2 0.6 1 -1 -1 VOUT = VS/2 IN EACH CASE -0.6 -0.2 0.2 0.6 1 VOUT FROM VS/2 (V) VOUT FROM VS/2 (V) Figure 45. DG vs. VOUT (DC- and AC-Coupled Load Compared) Figure 46. DP vs. VOUT (DC- and AC-Coupled Load Compared) Copyright © 2006–2015, Texas Instruments Incorporated Product Folder Links: LMH6601 LMH6601-Q1 Submit Documentation Feedback 19 LMH6601, LMH6601-Q1 SNOSAK9F – JUNE 2006 – REVISED JUNE 2015 www.ti.com 7 Detailed Description 7.1 Overview The high-speed, ultra-high input impedance of the LMH6601 and its fast slew rate make the device an ideal choice for video amplifier and buffering applications. There are cost benefits in having a single operating supply. Single-supply video systems can take advantage of the low supply voltage operation of the LMH6601 along with its ability to operate with input common-mode voltages at or slightly below the V− rail. Additional cost savings can be achieved by eliminating or reducing the value of the input and output AC-coupling capacitors commonly employed in single-supply video applications. 7.2 Feature Description 7.2.1 Shutdown Capability and Turn On/Off Behavior With the device in shutdown mode, the output goes into high-impedance (ROUT > 100 MΩ) mode. In this mode, the only path between the inputs and the output pin is through the external components around the device. So, for applications where there is active signal connection to the inverting input, with the LMH6601 in shutdown, the output could show signal swings due to current flow through these external components. For noninverting amplifiers in shutdown, no output swings would occur, because of complete input-output isolation, with the exception of capacitive coupling. For maximum power saving, the LMH6601 supply current drops to around 0.1 μA in shutdown. All significant power consumption within the device is disabled for this purpose. Because of this, the LMH6601 turnon time is measured in microseconds whereas its turnoff is fast (nanoseconds) as would be expected from a high speed device like this. The LMH6601 SD pin is a CMOS compatible input with a pico-ampere range input current drive requirement. This pin must be tied to a level or otherwise the device state would be indeterminate. The device shutdown threshold is half way between the V+ and V− pin potentials at any supply voltage. For example, with V+ tied to 10 V and V− equal to 5 V, you can expect the threshold to be at 7.5 V. The state of the device (shutdown or normal operation) is ensured over temperature as long as the SD pin is held to within 10% of the total supply voltage. For V+ = 10 V, V− = 5 V, as an example: • Shutdown Range 5 V ≤ SD ≤ 5.5 V • Normal Operation Range 9.5 V ≤ SD ≤ 10 V 7.2.2 Overload Recovery and Swing Close to Rails The LMH6601 can recover from an output overload in less than 20 ns. See Figure 47 for the input and output scope photos: (VOLTS) VS = ±2.5V INPUT (4 VPP) OUTPUT (1V/DIV) TIME (10 ns/DIV) Figure 47. LMH6601 Output Overload Recovery Waveform In Figure 47, the input step function is set so that the output is driven to one rail and then the other and then the output recovery is measured from the time the input crosses 0 V to when the output reaches this point. 20 Submit Documentation Feedback Copyright © 2006–2015, Texas Instruments Incorporated Product Folder Links: LMH6601 LMH6601-Q1 LMH6601, LMH6601-Q1 www.ti.com SNOSAK9F – JUNE 2006 – REVISED JUNE 2015 Feature Description (continued) Also, when the LMH6601 input voltage range is exceeded near the V+ rail, the output does not experience output phase reversal, as do some op amps. This is particularly advantageous in applications where output phase reversal must be avoided at all costs, such as in servo loop control among others. This adds to the set of features of the LMH6601, which make this device easy to use. INPUT In addition, the LMH6601 output swing close to either rail is well-behaved as shown in the scope photo of Figure 48. (1 V/DIV) 0V OUTPUT 0V VS = ±2.5V 1 ms/DIV Figure 48. Clean Swing of the LMH6601 to Either Rail With some op amps, when the output approaches either one or both rails and saturation starts to set in, there is significant increase in the transistor parasitic capacitances which leads to loss of Phase Margin. That is why with these devices, there are sometimes hints of instability with output close to the rails. With the LMH6601, as can be seen in Figure 48, the output waveform remains free of instability throughout its range of voltages. 7.3 Device Functional Modes 7.3.1 Optimizing Performance With many op amps, additional device nonlinearity and sometimes less loop stability arises when the output must switch from current-source mode to current-sink mode or vice versa. When it comes to achieving the lowest distortion and the best Differential Gain/ Differential Phase (DG/ DP, broadcast video specs), the LMH6601 is optimized for single-supply DC-coupled output applications where the load current is returned to the negative rail (V−). That is where the output stage is most linear (lowest distortion) and which corresponds to unipolar current flowing out of this device. To that effect, it is easy to see that the distortion specifications improve when the output is only sourcing current which is the distortion-optimized mode of operation for the LMH6601. In an application where the LMH6601 output is AC-coupled or when it is powered by separate dual supplies for V+ and V−, the output stage supplies both source and sink current to the load and results in less than optimum distortion (and DG/DP). Figure 49 compares the distortion results between a DC- and an AC-coupled load to show the magnitude of this difference. See the DG/DP plots, Figure 43 through Figure 46, in Typical Characteristics, for a comparison between DC- and AC-coupling of the video load. Copyright © 2006–2015, Texas Instruments Incorporated Product Folder Links: LMH6601 LMH6601-Q1 Submit Documentation Feedback 21 LMH6601, LMH6601-Q1 SNOSAK9F – JUNE 2006 – REVISED JUNE 2015 www.ti.com Device Functional Modes (continued) -20 VS = 3.3V VOUT = 2 VPP -30 VOUT_DC = VS/2 -40 HD3, AC COUPLED HD (dBc) -50 -60 -70 HD2, AC COUPLED -80 HD3, DC COUPLED -90 HD2, DC COUPLED -100 0.1 1 10 100 FREQUENCY (MHz) Figure 49. Distortion Comparison between DC- and AC-Coupling of the Load In certain applications, it may be possible to optimize the LMH6601 for best distortion (and DG/DP) even though the load may require bipolar output current by adding a pulldown resistor to the output. Adding an output pulldown resistance of appropriate value could change the LMH6601 output loading into source-only. This comes at the price of higher total power dissipation and increased output current requirement. Figure 50 shows how to calculate the pulldown resistor value for both the dual-supply and for the AC-coupled load applications. V + + V IL-MAX LMH6601 VO LMH6601 RP V RL VO CO RP RL - V - (a) DUAL SUPPLY (b) AC-COUPLED LOAD – RP ≤ RL (V V -1) O_MIN VO_MIN is the most negative swing at output RP ≤ VO_MIN IL_MAX VO_MIN is the most negative swing at output and IL_MAX is maximum load current with direction shown Figure 50. Output Pulldown Value for Dual-Supply and AC-Coupling Furthermore, with a combination of low closed-loop gain setting (that is, AV = +1 for example where device bandwidth is the highest), light output loading (RL > 1 kΩ) , and with a significant capacitive load (CL > 10 pF) , the LMH6601 is most stable if output sink current is kept to less than about 5 mA. The pulldown method described in Figure 50 is applicable in these cases as well where the current that would normally be sunk by the op amp is diverted to the RP path instead. 22 Submit Documentation Feedback Copyright © 2006–2015, Texas Instruments Incorporated Product Folder Links: LMH6601 LMH6601-Q1 LMH6601, LMH6601-Q1 www.ti.com SNOSAK9F – JUNE 2006 – REVISED JUNE 2015 8 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 8.1 Application Information 8.1.1 DC-Coupled, Single-Supply Baseband Video Amplifier and Driver The LMH6601 output can swing very close to either rail to maximize the output dynamic range which is of particular interest when operating in a low-voltage, single-supply environment. Under light output load conditions, the output can swing as close as a few mV of either rail. This also allows a video amplifier to preserve the video black level for excellent video integrity. In the example shown in Figure 51, the baseband video output is amplified and buffered by the LMH6601 which then drives the 75-Ω back-terminated video cable for an overall gain of +1 delivered to the 75-Ω load. The input video would normally have a level between 0 V to approximately 0.75 V. VIDEO IN (0-0.75V) VS = 2.7V + 75: CABLE VLOAD LMH6601 - RT 75: RG 620: RS 75: RL 75: RF 620: Figure 51. Single-Supply Video Driver Capable of Maintaining Accurate Video Black Level With the LMH6601 input common-mode range including the V− (ground) rail, there will be no need for ACcoupling or level shifting and the input can directly drive the noninverting input which has the additional advantage of high amplifier input impedance. With LMH6601’s wide rail-to-rail output swing, as stated earlier, the video black level of 0 V is maintained at the load with minimal circuit complexity and using no AC-coupling capacitors. Without true rail-to-rail output swing of the LMH6601, and more importantly without the LMH6601’s ability of exceedingly close swing to V−, the circuit would not operate properly as shown at the expense of more complexity. This circuit will also work for higher input voltages. The only significant requirement is that there is at least 1.8 V from the maximum input voltage to the positive supply (V+). The Composite Video Output of some low-cost consumer video equipment consists of a current source which develops the video waveform across a load resistor (usually 75 Ω), as shown in Figure 52. With these applications, the same circuit configuration just described and shown in Figure 52 will be able to buffer and drive the Composite Video waveform which includes sync and video combined. However, with this arrangement, the LMH6601 supply voltage must be at least 3.3 V or higher to allow proper input common-mode voltage headroom because the input can be as high as 1-V peak. Copyright © 2006–2015, Texas Instruments Incorporated Product Folder Links: LMH6601 LMH6601-Q1 Submit Documentation Feedback 23 LMH6601, LMH6601-Q1 SNOSAK9F – JUNE 2006 – REVISED JUNE 2015 www.ti.com Application Information (continued) VIDEO DAC CURRENT OUTPUT COMPOSITE VIDEO IN 0-1V VS = 3.3V + iO 75: VLOAD LMH6601 U1 - RS 75: RL 75: RF 620: RG 620: Figure 52. Single-Supply Composite Video Driver for Consumer Video Outputs If the Video In signal is Composite Video with negative going Sync tip, a variation of the previous configurations should be used. This circuit produces a unipolar (more than 0 V) DC-coupled single-supply video signal as shown in Figure 53. 3.3V R1 30 k: R2 10 k: 0.8VPP 0.61V ± 1.41V VS = 3.3V 0V - 2V + LMH6601 U1 - 3.3V VLOAD RS 75: RL 75: R3 1.3 k: VIDEO IN -0.3V to 0.75V RT 75: RG 560: RF 620: Figure 53. Single-Supply, DC-Coupled Composite Video Driver for Negative Going Sync Tip In the circuit of Figure 53, the input is shifted positive by means of R1, R2, and RT in order to satisfy the commonmode input range of the U1. The signal will loose 20% of its amplitude in the process. The closed-loop gain of U1 must be set to make up for this 20% loss in amplitude. This gives rise to the gain expression shown in Equation 1, which is based on a getting a 2 VPP output with a 0.8 VPP input: RF RG||R3 2V = 0.8V -1 = 1.5V/V (1) R3 will produce a negative shift at the output due to VS (3.3 V in this case). R3 must be set so that the Video In sync tip (−0.3 V at RT or 0.61 V at U1 noninverting input) corresponds to near 0 V at the output. § ¨ ¨ © § ¨ ¨ © § § RF 0.61 ¨1 + RF = 0.227 ¨1 + RF = R3 3.3V ± 0.61 ¨ RG RG ¨ © © (2) Equation 1 and Equation 2 must be solved simultaneously to arrive at the values of R3, RF, and RG which will satisfy both. From the data sheet, one can set RF = 620 Ω to be close to the recommended value for a gain of +2. It is easier to solve for RG and R3 by starting with a good estimate for one and iteratively solving Equation 1 and Equation 2 to arrive at the results. Here is one possible iteration cycle for reference: RF = 620 Ω 24 Submit Documentation Feedback (3) Copyright © 2006–2015, Texas Instruments Incorporated Product Folder Links: LMH6601 LMH6601-Q1 LMH6601, LMH6601-Q1 www.ti.com SNOSAK9F – JUNE 2006 – REVISED JUNE 2015 Application Information (continued) Table 1. Finding External Resistor Values by Iteration for Figure 53 ESTIMATE RG (Ω) CALCULATED (from Equation 2) R3 (Ω) Equation 1 LHS CALCULATED COMMENT (COMPARE Equation 1 LHS calculated to RHS) 1k 1.69k 0.988 Increase Equation 1 LHS by reducing RG 820 1.56k 1.15 Increase Equation 1 LHS by reducing RG 620 1.37k 1.45 Increase Equation 1 LHS by reducing RG 390 239 4.18 Reduce Equation 1 LHS by increasing RG 560 1.30k 1.59 Close to target value of 1.5V/V for Equation 1 The final set of values for RG and R3 in Table 1 are values which will result in the proper gain and correct video levels (0 V to 1 V) at the output (VLOAD). 8.1.2 How to Pick the Right Video Amplifier Apart from output current drive and voltage swing, the op amp used for a video amplifier and cable driver should also possess the minimum requirement for speed and slew rate. For video type loads, it is best to consider Large Signal Bandwidth (or LSBW in the TI data sheet tables) as video signals could be as large as 2 VPP when applied to the commonly used gain of +2 configuration. Because of this relatively large swing, the op amp Slew Rate (SR) limitation should also be considered. Table 2 shows these requirements for various video line rates calculated using a rudimentary technique and intended as a first-order estimate only. Table 2. Rise Time, −3 dB BW, and Slew Rate Requirements for Various Video Line Rates VIDEO STANDARD LINE RATE (HxV) REFRESH RATE (Hz) HORIZONTA L ACTIVE (KH%) VERTICAL ACTIVE (KV%) PIXEL TIME (ns) RISE TIME (ns) LSBW (MHz) SR (V/μs) TV_NTSC 451x483 30 84 92 118.3 39.4 9 41 VGA 640x480 75 80 95 33 11 32 146 SVGA 800x600 75 76 96 20.3 6.8 52 237 XGA 1024x768 75 77 95 12.4 4.1 85 387 SXGA 1280x1024 75 75 96 7.3 2.4 143 655 UXGA 1600x1200 75 74 96 4.9 1.6 213 973 For any video line rate (HxV corresponding to the number of Active horizontal and vertical lines), the speed requirements can be estimated if the Horizontal Active (KH%) and Vertical Active (KV%) numbers are known. These percentages correspond to the percentages of the active number of lines (horizontal or vertical) to the total number of lines as set by VESA standards. Here are the general expressions and the specific calculations for the SVGA line rate shown in Table 2. 1 x KH x KV REFRESH_RATE HxV 1 = 5 x 1 x 10 PIXEL_TIME (ns) = 75 Hz x 76 x 96 5 x 1 x 10 = 20.3 ns 800 x 600 (4) Requiring that an “On” pixel is illuminated to at least 90 percent of its final value before changing state will result in the rise/fall time equal to, at most, ⅓ the pixel time as shown in Equation 5: PIXEL_TIME RISE/FALL_TIME = 3 = 20.3 ns 3 = 6.8 ns (5) Assuming a single pole frequency response roll-off characteristic for the closed-loop amplifier used, we have: -3 dB_BW = 0.35 0.35 = = 52 MHz 6.8 ns RISE/FALL_TIME Copyright © 2006–2015, Texas Instruments Incorporated Product Folder Links: LMH6601 LMH6601-Q1 (6) Submit Documentation Feedback 25 LMH6601, LMH6601-Q1 SNOSAK9F – JUNE 2006 – REVISED JUNE 2015 www.ti.com Rise/Fall times are 10%-90% transition times, which for a 2 VPP video step would correspond to a total voltage shift of 1.6V (80% of 2 V). So, the Slew Rate requirement can be calculated as follows: SR(V/Ps) = 1.6V x 1 x 103 = 1.6V = 237(V/Ps) 6.8 ns RISE/FALL_TIME (ns) (7) The LMH6601 specifications show that it would be a suitable choice for video amplifiers up to and including the SVGA line rate as demonstrated above. For more information about this topic and others relating to video amplifiers, see Application Note 1013, Video Amplifier Design for Computer Monitors (SNVA031). 8.1.3 Current to Voltage Conversion (Transimpedance Amplifier (TIA) Being capable of high speed and having ultra low input bias current makes the LMH6601 a natural choice for Current to Voltage applications such as photodiode I-V conversion. In these type of applications, as shown in Figure 54, the photodiode is tied to the inverting input of the amplifier with RF set to the proper gain (gain is measured in Ω). CF RF D1 CD LMH6601 U1 CA VOUT + VBIAS Figure 54. Typical Connection of a Photodiode Detector to an Op Amp With the LMH6601 input bias current in the femto-amperes range, even large values of gain (RF) do not increase the output error term appreciably. This allows circuit operation to a lower light intensity level which is always of special importance in these applications. Most photo-diodes have a relatively large capacitance (CD) which would be even larger for a photo-diode designed for higher sensitivity to light because of its larger area. Some applications may run the photodiode with a reverse bias to reduce its capacitance with the disadvantage of increased contributions from both dark current and noise current. Figure 55 shows a typical photodiode capacitance plot vs. reverse bias for reference. 600 T = 23°C CAPACITANCE (pF) 500 PIN-RD100 400 PIN-RD100A 300 200 PIN-RD15 100 PIN-RD07 0 0.1 1 10 100 REVERSED BIAS VOLTAGE (V) Figure 55. Typical Capacitance vs. Reverse Bias (Source: OSI Optoelectronics) 26 Submit Documentation Feedback Copyright © 2006–2015, Texas Instruments Incorporated Product Folder Links: LMH6601 LMH6601-Q1 LMH6601, LMH6601-Q1 www.ti.com SNOSAK9F – JUNE 2006 – REVISED JUNE 2015 The diode capacitance (CD) combined with the input capacitance of the LMH6601 (CA) has a bearing on the stability of this circuit and how it is compensated. With large transimpedance gain values (RF), the total combined capacitance on the amplifier inverting input (CIN = CD + CA) will work against RF to create a zero in the Noise Gain (NG) function (see Figure 56). If left untreated, at higher frequencies where NG equals the open-loop transfer function excess phase shift around the loop (approaching 180°) and therefore, the circuit could be unstable. This is illustrated in Figure 56. OP AMP OPENLOOP GAIN GAIN (dB) I-V GAIN (Ω) NOISE GAIN (NG) 1 + sRF (CIN + CF) 1 + sRFCF 1+ CIN CF 0 dB FREQUENCY fz = 1 2πRFCIN fP = 1 GBWP 2πRFCF Figure 56. Transimpedance Amplifier Graphical Stability Analysis and Compensation Figure 56 shows that placing a capacitor, CF, with the proper value, across RF will create a pole in the NG function at fP. For optimum performance, this capacitor is usually picked so that NG is equal to the open-loop gain of the op amp at fP. This will cause a “flattening” of the NG slope beyond the point of intercept of the two plots (open-loop gain and NG) and will results in a Phase Margin (PM) of 45° assuming fP and fZ are at least a decade apart. This is because at the point of intercept, the NG pole at fP will have a 45° phase lead contribution which leaves 45° of PM. For reference, Figure 56 also shows the transimpedance gain (I-V (Ω)) Here is the theoretical expression for the optimum CF value and the expected −3-dB bandwidth: CF = CIN 2S(GBWP)RF f-3 dB # (8) GBWP 2SRFCIN (9) Table 3 lists the results, along with the assumptions and conditions, of testing the LMH6601 with various photodiodes having different capacitances (CD) at a transimpedance gain (RF) of 10 kΩ. Table 3. Transimpedance Amplifier Compensation and Performance Results for Figure 54 CD (pF) CIN (pF) CF_CALCULATED (pF) CF USED (pF) −3 dB BW CALCULATED (MHz) −3 dB BW MEASURED (MHz) STEP RESPONSE OVERSHOOT (%) 10 12 1.1 1 14 15 6 50 52 2.3 3 7 7 4 500 502 7.2 8 2 2.5 9 CA = 2 pF GBWP = 155 MHz VS = 5 V (10) 8.1.4 Transimpedance Amplifier Noise Considerations When analyzing the noise at the output of the I-V converter, it is important to note that the various noise sources (that is, op amp noise voltage, feedback resistor thermal noise, input noise current, photodiode noise current) do not all operate over the same frequency band. Therefore, when the noise at the output is calculated, this should be taken into account. Copyright © 2006–2015, Texas Instruments Incorporated Product Folder Links: LMH6601 LMH6601-Q1 Submit Documentation Feedback 27 LMH6601, LMH6601-Q1 SNOSAK9F – JUNE 2006 – REVISED JUNE 2015 www.ti.com The op amp noise voltage will be gained up in the region between the noise gain’s “zero” and its “pole” (fz and fp in Figure 56). The higher the values of RF and CIN, the sooner the noise gain peaking starts and therefore its contribution to the total output noise would be larger. It is obvious to note that it is advantageous to minimize CIN (for example, by proper choice of op amp, by applying a reverse bias across the diode at the expense of excess dark current and noise). However, most low noise op amps have a higher input capacitance compared to ordinary op amps. This is due to the low noise op amp’s larger input stage. 8.1.5 Charge Preamplifier RF = 10 M: to 10 G: RS = 1 M: or SMALLER FOR HIGH COUNTING RATES CF = 1 pF CD = 1 pF to 10 PF VOUT = Q/CF WHERE Q is CHARGE CREATED BY ONE PHOTON or PARTICLE ADJUST VBIAS FOR MAXIMUM SNR CF RF 10 k: CD RS LMH6601 U1 + - VBIAS D1 1000 pF VOUT + Figure 57. Charge Preamplifier Taking Advantage of the Femto-Ampere Range Input Bias Current of the LMH6601 8.1.6 Capacitive Load The LMH6601 can drive a capacitive load of up to 1000 pF with correct isolation and compensation. Figure 58 illustrates the in-loop compensation technique to drive a large capacitive load. RF RG CF VIN RS VOUT LMH6601 U1 + RL 2 k: CL Figure 58. In-Loop Compensation Circuit for Driving a Heavy Capacitive Load When driving a high-capacitive load, an isolation resistor (RS) should be connected in series between the op amp output and the capacitive load to provide isolation and to avoid oscillations. A small-value capacitor (CF) is inserted between the op amp output and the inverting input as shown such that this capacitor becomes the dominant feedback path at higher frequency. Together these components allow heavy capacitive loading while keeping the loop stable. There are few factors which affect the driving capability of the op amp: • Op amp internal architecture • Closed-loop gain and output capacitor loading Table 4 shows the measured step response for various values of load capacitors (CL), series resistor (RS) and feedback resistor (CF) with gain of +2 (RF = RG = 604 Ω) and RL = 2 kΩ: 28 Submit Documentation Feedback Copyright © 2006–2015, Texas Instruments Incorporated Product Folder Links: LMH6601 LMH6601-Q1 LMH6601, LMH6601-Q1 www.ti.com SNOSAK9F – JUNE 2006 – REVISED JUNE 2015 Table 4. LMH6601 Step Response Summary for the Circuit of Figure 58 (1) CL (pF) RS (Ω) CF (pF) trise/ tfall (ns) OVERSHOOT (%) 10 0 1 6 (1) 8 (1) 50 0 1 7 110 47 1 10 16 6 300 6 10 12 20 500 80 10 33 10 910 192 10 65 10 Response limited by input step generator rise time of 5 ns Figure 59 shows the increase in rise/fall time (bandwidth decrease) at VOUT with larger capacitive loads, illustrating the trade-off between the two: 70 60 RISE TIME (ns) 50 40 30 20 10 0 10 100 1000 CAP LOAD CL (pF) Figure 59. LMH6601 In-Loop Compensation Response 8.2 Typical Application 8.2.1 SAG Compensation for AC-Coupled Video Many monitors and displays accept AC-coupled inputs. This simplifies the amplification and buffering task in some respects. The capacitors shown in Figure 60 (except CG2), and especially CO, are the large electrolytic type which are considerably costly and take up valuable real estate on the board. It is possible to reduce the value of the output coupling capacitor, CO, which is the largest of all, by using what is called SAG compensation. SAG refers to what the output video experiences due to the low frequency video content it contains which cannot adequately go through the output AC-coupling scheme due to the low frequency limit of this circuit. The −3 dB low frequency limit of the output circuit is given by: f_low_frequency (−3 dB)= 1/ (2*π* 75*2(Ω) * Co) = ∼ 4.82 Hz for CO = 220 μF (11) 5V R1 510 k: 5V VIN RO 75: + RIN 75: LMH6601 U1 R2 510 k: - CABLE + CIN 0.47 PF CO 220 PF VOUT RL 75: RF 620: RG 620: CG2 CG 47 PF + Figure 60. AC-Coupled Video Amplifier and Driver Copyright © 2006–2015, Texas Instruments Incorporated Product Folder Links: LMH6601 LMH6601-Q1 Submit Documentation Feedback 29 LMH6601, LMH6601-Q1 SNOSAK9F – JUNE 2006 – REVISED JUNE 2015 www.ti.com Typical Application (continued) 8.2.2 Design Requirements As shown in Figure 60, R1 and R2 simply set the input to the center of the input linear range while CIN AC couples the video onto the input of the op amp. The op amp is set for a closed-loop gain of 2 with RF and RG. CG is there to make sure the device output is also biased at mid-supply. Because of the DC bias at the output, the load must be AC-coupled as well through CO. Some applications implement a small valued ceramic capacitor (not shown) in parallel with CO which is electrolytic. The reason for this is that the ceramic capacitor will tend to shunt the inductive behavior of the Electrolytic capacitor at higher frequencies for an improved overall low impedance output. CG2 is intended to boost the high-frequency gain to improve the video frequency response. This value is to be set and trimmed on the board to meet the specific system requirements of the application. A possible implementation of the SAG compensation is shown in Figure 61. VCC_5V CIN 0.47 PF R1 510 k: VCC_5V + VIN RT 75: R2 510 k: LMH6601 U1 CO 68 PF VO + - RO 75: CABLE VL - R4 2 k: C1 22 PF RL 75: R3 1 k: + - R5 680: Figure 61. AC-Coupled Video Amplifier/Driver With SAG Compensation 8.2.3 Detailed Design Procedure In the circuit of Figure 61, the output coupling capacitor value and size is reduced at the expense of a slightly more complicated circuitry. Note that C1 is not only part of the SAG compensation, but it also sets the amplifier’s DC gain to 0 dB so that the output is set to mid-rail for linearity purposes. Also, exceptionally high values are chosen for the R1 and R2 biasing resistors (510 kΩ). The LMH6601 has extremely low input bias current which allows this selection thereby reducing the CIN value in this circuit such that CIN can even be a nonpolar capacitor which will reduce cost. At high enough frequencies where both CO and C1 can be considered to be shorted out, R3 shunts R4 and the closed-loop gain is determined by: Closed_loop_Gain (V/V) = VL/VIN = (1+ (R3||R4)/ R5) x [RL/(RL+RO)]= 0.99 V/V (12) At intermediate frequencies, where the CO, RO, RL path experiences low frequency gain loss, the R3, R5, C1 path provides feedback from the load side of CO. With the load side gain reduced at these lower frequencies, the feedback to the op amp inverting node reduces, causing an increase at the output of the op amp as a response. For NTSC video, low values of CO influence how much video black level shift occurs during the vertical blanking interval (∼1.5 ms) which has no video activity and thus is sensitive to the charge dissipation of the CO through the load which could cause output SAG. An especially tough pattern is the NTSC pattern called “Pulse & Bar.” With this pattern the entire top and bottom portion of the field is black level video where, for about 11 ms, CO is discharging through the load with no video activity to replenish that charge. 30 Submit Documentation Feedback Copyright © 2006–2015, Texas Instruments Incorporated Product Folder Links: LMH6601 LMH6601-Q1 LMH6601, LMH6601-Q1 www.ti.com SNOSAK9F – JUNE 2006 – REVISED JUNE 2015 Typical Application (continued) 8.2.4 Application Curves Figure 62 shows the output of the Figure 61 circuit highlighting the SAG. Figure 62. AC-Coupled Video Amplifier/Driver Output Scope Photo Showing Video SAG With the circuit of Figure 61 and any other AC-coupled pulse amplifier, the waveform duty cycle variations exert additional restrictions on voltage swing at any node. This is illustrated in the waveforms shown in Figure 63. If a stage has a 3 VPP unclipped swing capability available at a given node, as shown in Figure 63, the maximum allowable amplitude for an arbitrary waveform is ½ of 3 V or 1.5 VPP. This is due to the shift in the average value of the waveform as the duty cycle varies. Figure 63 shows what would happen if a 2 VPP signal were applied. A low duty cycle waveform, such as the one in Figure 63B, would have high positive excursions. At low enough duty cycles, the waveform could get clipped on the top, as shown, or a more subtle loss of linearity could occur prior to full-blown clipping. The converse of this occurs with high duty cycle waveforms and negative clipping, as depicted in Figure 63C. 4.0V (+) CLIPPING (A) 50% DUTY CYCLE NO CLIPPING 2Vp-p 2.5V 1.0V (-) CLIPPING 4.0V (+) CLIPPING (B) LOW DUTY CYCLE CLIPPED POSITIVE 2Vp-p 2.5V 1.0V (-) CLIPPING 4.0V (+) CLIPPING (C) HIGH DUTY CYCLE CLIPPED NEGATIVE 2.5V 2Vp-p 1.0V (-) CLIPPING Figure 63. Headroom Considerations With AC-Coupled Amplifiers Copyright © 2006–2015, Texas Instruments Incorporated Product Folder Links: LMH6601 LMH6601-Q1 Submit Documentation Feedback 31 LMH6601, LMH6601-Q1 SNOSAK9F – JUNE 2006 – REVISED JUNE 2015 www.ti.com 9 Power Supply Recommendations The LMH6601 can operate off a single-supply or with dual supplies. The input CM capability of the parts (CMVR) extends all the way down to the V- rail to simplify single-supply applications. Supplies should be decoupled with low-inductance, often ceramic, capacitors to ground less than 0.5 inches from the device pins. TI recommends the use of ground plane, and as in most high-speed devices, it is advisable to remove ground plane close to device sensitive pins such as the inputs. 10 Layout 10.1 Layout Guidelines Generally, a good high-frequency layout will keep power supply and ground traces away from the inverting input and output pins. Parasitic capacitances on these nodes to ground will cause frequency response peaking and possible circuit oscillations (see Application Note OA-15, Frequent Faux Pas in Applying Wideband Current Feedback Amplifiers, SNOA367, for more information). 10.2 Layout Examples SC-70 Board Layout (Actual size = 1.5 in × 1.5 in Figure 64. Layer 1 Silk SC-70 Board Layout (Actual size = 1.5 in × 1.5 in Figure 65. Layer 2 Silk 32 Submit Documentation Feedback Copyright © 2006–2015, Texas Instruments Incorporated Product Folder Links: LMH6601 LMH6601-Q1 LMH6601, LMH6601-Q1 www.ti.com SNOSAK9F – JUNE 2006 – REVISED JUNE 2015 11 Device and Documentation Support 11.1 Documentation Support 11.1.1 Related Documentation For additional information, see the following: • Application Note 1013, Video Amplifier Design for Computer Monitors, SNVA031 • Application Note OA-15, Frequent Faux Pas in Applying Wideband Current Feedback Amplifiers, SNOA367 11.2 Related Links The table below lists quick access links. Categories include technical documents, support and community resources, tools and software, and quick access to sample or buy. Table 5. Related Links PARTS PRODUCT FOLDER SAMPLE & BUY TECHNICAL DOCUMENTS TOOLS & SOFTWARE SUPPORT & COMMUNITY LMH6601 Click here Click here Click here Click here Click here LMH6601-Q1 Click here Click here Click here Click here Click here 11.3 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 11.4 Trademarks E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. 11.5 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 11.6 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 12 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Copyright © 2006–2015, Texas Instruments Incorporated Product Folder Links: LMH6601 LMH6601-Q1 Submit Documentation Feedback 33 PACKAGE OPTION ADDENDUM www.ti.com 2-Apr-2015 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) LMH6601MG/NOPB ACTIVE SC70 DCK 6 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 A95 LMH6601MGX/NOPB ACTIVE SC70 DCK 6 3000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 A95 LMH6601QMG/NOPB ACTIVE SC70 DCK 6 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 AKA LMH6601QMGX/NOPB ACTIVE SC70 DCK 6 3000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 AKA (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 2-Apr-2015 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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OTHER QUALIFIED VERSIONS OF LMH6601, LMH6601-Q1 : • Catalog: LMH6601 • Automotive: LMH6601-Q1 NOTE: Qualified Version Definitions: • Catalog - TI's standard catalog product • Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 2-Apr-2015 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant LMH6601MG/NOPB SC70 DCK 6 1000 178.0 8.4 2.25 2.45 1.2 4.0 8.0 Q3 LMH6601MGX/NOPB SC70 DCK 6 3000 178.0 8.4 2.25 2.45 1.2 4.0 8.0 Q3 LMH6601QMG/NOPB SC70 DCK 6 1000 178.0 8.4 2.25 2.45 1.2 4.0 8.0 Q3 LMH6601QMGX/NOPB SC70 DCK 6 3000 178.0 8.4 2.25 2.45 1.2 4.0 8.0 Q3 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 2-Apr-2015 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LMH6601MG/NOPB SC70 DCK 6 1000 210.0 185.0 35.0 LMH6601MGX/NOPB SC70 DCK 6 3000 210.0 185.0 35.0 LMH6601QMG/NOPB SC70 DCK 6 1000 210.0 185.0 35.0 LMH6601QMGX/NOPB SC70 DCK 6 3000 210.0 185.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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