3.3 VOLT CMOS SyncBiFIFOTM 64 x 36 x 2 • FEATURES: • • • • • • • • • • • Two independent clocked FIFOs (64 x 36 storage capacity each) buffering data in opposite directions Supports clock frequencies up to 83 MHz Fast access times of 8ns Free-running CLKA and CLKB can be asynchronous or coincident (simultaneous reading and writing of data on a single clock edge is permitted) Mailbox bypass Register for each FIFO Programmable Almost-Full and Almost-Empty Flags Microprocessor interface control logic EFA , FFA , AEA , and AFA flags synchronized by CLKA EFB , FFB , AEB , and AFB flags synchronized by CLKB • • IDT72V3612 Passive parity checking on each port Parity generation can be selected for each port Available in 132-pin plastic quad flat package (PQF), or space saving 120-pin thin quad flat package (TQFP) Pin and functionally compatible version of the 5V operating IDT723612 Industrial temperature range (–40°°C +85°°C) is available DESCRIPTION: The IDT72V3612 is a pin and functionally compatible version of the IDT723612, designed to run off a 3.3V supply for exceptionally low-power consumption. This device is a monolithic high-speed, low-power CMOS bidirectional clocked FIFO memory. It supports clock frequencies up to 83 MHz FUNCTIONAL BLOCK DIAGRAM Port-A Control Logic MBF1 RAM ARRAY 64 x 36 Device Control Write Pointer FFA AFA EFA AEA Read Pointer EFB AEB Status Flag Logic 36 FS0 FS1 A0 - A35 FIFO1 Programmable Flag Offset Register B0 - B36 FIFO2 FFB AFB Status Flag Logic Parity Generation Output Register Read Pointer PGA PEFA 36 Write Pointer RAM ARRAY 64 x 36 36 Input Register ODD/ EVEN PGB Parity Generation Input Register RST PEFB Parity Gen/Check Mail 1 Register Output Register CLKA CSA W/RA ENA MBA Mail 2 Register Parity Gen/Check Port-B Control Logic MBF2 CLKB CSB W/RB ENB MBB 4659 drw 01 IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. SyncBiFIFO is a trademark of Integrated Device Technology, Inc. COMMERCIAL TEMPERATURE RANGE MAY 2003 1 2003 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. DSC-4659/1 IDT72V3612 3.3V, CMOS SyncBiFIFOTM 64 x 36 x 2 COMMERCIAL TEMPERATURE RANGE and has read access times as fast as 8ns. The FIFO operates in IDT Standard mode. Two independent 64 x 36 dual-port SRAM FIFOs on board the chip buffer data in opposite directions. Each FIFO has flags to indicate empty and full conditions and two programmable flags (Almost-Full and Almost-Empty) to indicate when a selected number of words is stored in memory. Communication between each port can bypass the FIFOs via two 36-bit mailbox registers. Each mailbox register has a flag to signal when new mail has been stored. Parity is checked passively on each port and may be ignored if not desired. Parity generation can be selected for data read from each port. Two or more devices can be used in parallel to create wider data paths. This device is a clocked FIFO, which means each port employs a synchronous interface. All data transfers through a port are gated to the LOW-to-HIGH transition of a port clock by enable signals. The clocks for each port are independent of one another and can be asynchronous or coincident. The enables for each port are arranged to provide a simple bidirectional interface between microprocessors and/or buses with synchronous control. The Full Flag (FFA, FFB) and Almost-Full (AFA, AFB) flag of a FIFO are two-stage synchronized to the port clock that writes data to its array. The Empty Flag (EFA, EFB) and Almost-Empty (AEA, AEB) flag of a FIFO are two stage synchronized to the port clock that reads data from its array. The IDT72V3612 is characterized for operation from 0°C to 70°C. Industrial temperature range (–40°C to +85°C) is available by special order. This device is fabricated using IDT's high speed, submicron CMOS technology. * 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 GND AEB EFB B0 B1 B2 GND B3 B4 B5 B6 VCC B7 B8 B9 GND B10 B11 VCC B12 B13 B14 GND B15 B16 B17 B18 B19 B20 GND B21 B22 B23 VCC A24 A25 A26 GND A27 A28 A29 VCC A30 A31 A32 GND A33 A34 A35 GND B35 B34 B33 GND B32 B31 B30 VCC B29 B28 B27 GND B26 B25 B24 VCC GND AEA EFA A0 A1 A2 GND A3 A4 A5 A6 VCC A7 A8 A9 GND A10 A11 VCC A12 A13 A14 GND A15 A16 A17 A18 A19 A20 GND A21 A22 A23 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 AFA FFA CSA ENA CLKA W/RA VCC PGA PEFA GND MBF2 MBA FS1 FS0 ODD/EVEN RST GND NC NC NC NC MBB MBF1 GND PEFB PGB VCC W/RB CLKB ENB CSB FFB AFB PIN CONFIGURATIONS * 4659 drw 02 Electrical pin 1 in center of beveled edge. Pin 1 identifier in corner. NOTES: 1. NC - No internal connection 2. Uses Yamaichi socket IC51-1324-828 PQFP(2) (PQ132-1, order code: PQF) TOP VIEW 2 IDT72V3612 3.3V, CMOS SyncBiFIFOTM 64 x 36 x 2 COMMERCIAL TEMPERATURE RANGE 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 A24 A25 A26 VCC A27 A28 A29 GND A30 A31 A32 A33 A34 A35 GND B35 B34 B33 B32 B31 B30 GND B29 B28 B27 VCC B26 B25 B24 B23 PIN CONFIGURATIONS (CONTINUED) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 B22 B21 GND B20 B19 B18 B17 B16 B15 B14 B13 B12 B11 B10 GND B9 B8 B7 VCC B6 B5 B4 B3 GND B2 B1 B0 EFB AEB AFB NOTE: 1. NC - No internal connection AFA FFA CSA ENA CLKA W/RA VCC PGA PEFA MBF2 MBA FS1 FS0 ODD/EVEN RST GND NC NC NC NC MBB MBF1 PEFB PGB VCC W/RB CLKB ENB CSB FFB 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 A23 A22 A21 GND A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 GND A9 A8 A7 VCC A6 A5 A4 A3 GND A2 A1 A0 EFA AEA TQFP (PN120-1, order code: PF) TOP VIEW 3 4659 drw 03 IDT72V3612 3.3V, CMOS SyncBiFIFOTM 64 x 36 x 2 COMMERCIAL TEMPERATURE RANGE PIN DESCRIPTION Symbol Name I/O I/O Description A0-A35 Port A Data 36-bit bidirectional data port for side A. AEA Port A Almost-Empty Flag O (Port A) Programmable Almost-Empty flag synchronized to CLKA. It is LOW when the number of words in the FIFO2 is less than or equal to the value in the offset register, X. AEB Port B Almost-Empty Flag O (PortB) Programmable Almost-Empty flag synchronized to CLKB. It is LOW when the number of words in FIFO1 is less than or equal to the value in the offset register, X. AFA Port A Almost-Full Flag O Programmable Almost-Full flag synchronized to CLKA. It is LOW when the number of empty (Port A) locations in FIFO1 is less than or equal to the value in the offset register, X. AFB Port B Almost-Full Flag O Programmable Almost-Full flag synchronized to CLKB. It is LOW when the number of empty (Port B) locations in FIFO2 is less than or equal to the value in the offset register, X. B0-B35 Port B Data. I/O CLKA Port A Clock I CLKA is a continuous clock that synchronizes all data transfers through port A and can be asynchronous or coincident to CLKB. EFA, FFA, AFA, and AEA are synchronized to the LOW-toHIGH transition of CLKA. 36-bit bidirectional data port for side B. CLKB Port B Clock I CLKB is a continuous clock that synchronizes all data transfers through port B and can be asynchronous or coincident to CLKA. EFB, FFB, AFB, and AEB are synchronized to the LOW-toHIGH transition of CLKB. CSA Port A Chip Select I CSA must be LOW to enable a LOW-to-HIGH transition of CLKA to read or write data on port A. The A0-A35 outputs are in the high-impedance state when CSA is HIGH. CSB Port B Chip Select I CSB must be LOW to enable a LOW-to-HIGH transition of CLKB to read or write data on port B. The B0-B35 outputs are in the high-impedance state when CSB is HIGH. EFA Port A Empty Flag O EFA is synchronized to the LOW-to-HIGH transition of CLKA. When EFA is LOW, FIFO2 is empty, (Port A) and reads from its memory are disabled. Data can be read from FIFO2 to the output register when EFA is HIGH. EFA is forced LOW when the device is reset and is set HIGH by the second LOW-to-HIGH transition of CLKA after data is loaded into empty FIFO2 memory. EFB Port B Empty Flag O EFB is synchronized to the LOW-to-HIGH transition of CLKB. When EFB is LOW, the FIFO1 is (Port B) empty, and reads from its memory are disabled. Data can be read from FIFO1 to the output register when EFB is HIGH. EFB is forced LOW when the device is reset and is set HIGH by the second LOW-to-HIGH transition of CLKB after data is loaded into empty FIFO1 memory. ENA Port A Enable I ENA must be HIGH to enable a LOW-to-HIGH transition of CLKA to read or write data on port A. ENB Port B Enable I ENB must be HIGH to enable a LOW-to-HIGH transition of CLKB to read or write data on port B. FFA Port A Full Flag O FFA is synchronized to the LOW-to-HIGH transition of CLKA. When FFA is LOW, FIFO1 is full, (Port A) and writes to its memory are disabled. FFA is forced LOW when the device is reset and is set HIGH by the second LOW-to-HIGH transition of CLKA after reset. FFB Port B Full Flag O FFB is synchronized to the LOW-to-HIGH transition of CLKB. When FFB is LOW, FIFO2 is full, (Port B) and writes to its memory are disabled. FFB is forced LOW when the device is reset and is set HIGH by the second LOW-to-HIGH transition of CLKB after reset. FS1, FS0 Flag Offset Selects I The LOW-to-HIGH transition of RST latches the values of FS0 and FS1, which selects one of four preset values for the Almost-Full flag and Almost-Empty flag. MBA Port A Mailbox Select I A HIGH level on MBA chooses a mailbox register for a port A read or write operation. When the A0-A35 outputs are active, a HIGH level on MBA selects data from the mail2 register for output, and a LOW level selects FIFO2 output register data for output. MBB Port B Mailbox Select I A HIGH level on MBB chooses a mailbox register for a port B read or write operation. When the B0-B35 outputs are active, a HIGH level on MBB selects data from the mail1 register for output, and a LOW level selects FIFO1 output register data for output. MBF1 Mail1 Register Flag O MBF1 is set LOW by a LOW-to-HIGH transition of CLKA that writes data to the mail1 register. Writes to the mail1 register are inhibited while MBF1 is set LOW. MBF1 is set HIGH by a LOW-toHIGH transition of CLKB when a port B read is selected and MBB is HIGH. MBF1 is set HIGH when the device is reset. 4 IDT72V3612 3.3V, CMOS SyncBiFIFOTM 64 x 36 x 2 COMMERCIAL TEMPERATURE RANGE PIN DESCRIPTION (CONTINUED) Symbol Name I/O Description MBF2 Mail2 Register Flag O MBF2 is set LOW by a LOW-to-HIGH transition of CLKB that writes data to the mail2 register. Writes to the mail2 register are inhibited while MBF2 is set LOW. MBF2 is set HIGH by a LOW-toHIGH transition of CLKA when a port A read is selected and MBA is HIGH. MBF2 is set HIGH when the device is reset. ODD/ EVEN Odd/Even Parity Select I Odd parity is checked on each port when ODD/EVEN is HIGH, and even parity is checked when ODD/EVEN is LOW. ODD/EVEN also selects the type of parity generated for each port if parity generation is enabled for a read operation. PEFA Port A Parity Error Flag O (Port A) When any byte applied to terminals A0-A35 fails parity, PEFA is LOW. Bytes are organized as A0-A8, A9-A17, A18-A26, and A27-A35, with the most significant bit of each byte serving as the parity bit. The type of parity checked is determined by the state of the ODD/EVEN input. The parity trees used to check the A0-A35 inputs are shared by the mail2 register to generate parity if parity generation is selected by PGA. Therefore, if a mail2 read with parity generation is setup by having W/RA LOW, MBA HIGH, and PGA HIGH, the PEFA flag is forced HIGH regardless of the A0-A35 inputs. PEFB Port B Parity Error Flag O (Port B) When any byte applied to terminals B0-B35 fails parity, PEFB is LOW. Bytes are organized as B0-B8, B9-B17, B18-B26, B27-B35 with the most significant bit of each byte serving as the parity bit. The type of parity checked is determined by the state of the ODD/EVEN input. The parity trees used to check the B0-B35 inputs are shared by the mail1 register to generate parity if parity generation is selected by PGB. Therefore, if a mail1 read with parity generation is setup by having W/RB LOW, MBB HIGH, and PGB HIGH, the PEFB flag is forced HIGH regardless of the state of the B0-B35 inputs. PGA Port A Parity Generation I Parity is generated for data reads from port A when PGA is HIGH. The type of parity generated is selected by the state of the ODD/EVEN input. Bytes are organized as A0-A8, A9-A17, A18-A26, and A27-A35. The generated parity bits are output in the most significant bit of each byte. PGB Port B Parity Generation I Parity is generated for data reads from port B when PGB is HIGH. The type of parity generated is selected by the state of the ODD/EVEN input. Bytes are organized as B0-B8, B9-B17, B18-B26, and B27-B35. The generated parity bits are output in the most significant bit of each byte. RST Reset I To reset the device, four LOW-to-HIGH transitions of CLKA and four LOW-to-HIGH transitions of CLKB must occur while RST is LOW. This sets the AFA, AFB, MBF1, and MBF2 flags HIGH and the EFA, EFB, AEA, AEB, FFA, and FFB flags LOW. The LOW-to-HIGH transition of RST latches the status of the FS1 and FS0 inputs to select Almost-Full and Almost-Empty flag offset. W/RA Port A Write/Read Select I A HIGH selects a write operation and a LOW selects a read operation on port A for a LOW-toHIGH transition of CLKA. The A0-A35 outputs are in the high-impedance state when W/RA is HIGH. W/RB Port B Write/Read Select I A HIGH selects a write operation and a LOW selects a read operation on port B for a LOW-toHIGH transition of CLKB. The B0-B35 outputs are in the high-impedance state when W/RB is HIGH. 5 IDT72V3612 3.3V, CMOS SyncBiFIFOTM 64 x 36 x 2 COMMERCIAL TEMPERATURE RANGE ABSOLUTE MAXIMUM RATINGS OVER OPERATING FREE-AIR TEMPERATURE RANGE (Unless otherwise noted)(2) Symbol Rating Commercial Unit VCC Supply Voltage Range –0.5 to +4.6 V VI(2) Input Voltage Range –0.5 to VCC+0.5 V VO(2) Output Voltage Range –0.5 to VCC+0.5 V IIK Input Clamp Current, (VI < 0 or VI > VCC) ±20 mA IOK Output Clamp Current, (VO < 0 or VO > VCC) ±50 mA IOUT Continuous Output Current, (VO = 0 to VCC) ±50 mA ICC Continuous Current Through VCC or GND ±500 mA TSTG Storage Temperature Range –65 to 150 °C NOTES: 1. Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "Recommended Operating Conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The input and output voltage ratings may be exceeded provided the input and output current ratings are observed. RECOMMENDED OPERATING CONDITIONS Symbol Parameter Min. Typ. Supply Voltage VCC(1) 3.0 Max. Unit 3.3 3.6 V VIH HIGH Level Input Voltage 2 — VCC+0.5 V VIL LOW-Level Input Voltage — — 0.8 V IOH HIGH-Level Output Current — — –4 mA IOL LOW-Level Output Current — — 8 mA TA Operating Free-air Temperature 0 — 70 °C NOTE: 1. For 12ns (83MHz operation), Vcc=3.3V +/-0.15V, JEDEC JESD8-A compliant ELECTRICAL CHARACTERISTICS OVER RECOMMENDED OPERATING FREEAIR TEMPERATURE RANGE (Unless otherwise noted) IDT72V3612 Commercial tCLK = 12, 15, 20 ns Symbol Parameter Test Conditions Min. Typ.(1) Max. Unit VOH Output Logic "1" Voltage VCC = 3.0V, IOH = –4 mA 2.4 — — V VOL Output Logic "0" Voltage VCC = 3.0V, IOL = 8 mA — — 0.5 V ILI Input Leakage Current (Any Input) VCC = 3.6V, VI = VCC or 0 — — ±5 µA Output Leakage Current VCC = 3.6V, VO = VCC or 0 — — ±5 µA Standby Current VCC = 3.6V, VI = VCC - 0.2V or 0 — — 500 µA CIN Input Capacitance VI = 0, f = 1 MHz — 4 — pF C OUT Output Capacitance VO = 0, f = 1 MHZ — 8 — pF ILO ICC (2) NOTES: 1. All typical values are at VCC = 3.3V, TA = 25°C. 2. For additional ICC information, see Figure 1, Typical Characteristics: Supply Current (ICC) vs. Clock Frequency (fS). 6 IDT72V3612 3.3V, CMOS SyncBiFIFOTM 64 x 36 x 2 COMMERCIAL TEMPERATURE RANGE DETERMINING ACTIVE CURRENT CONSUMPTION AND POWER DISSIPATION The ICC(f) current for the graph in Figure 1 was taken while simultaneously reading and writing the FIFO on the IDT72V3612 with CLKA and CLKB set to fS. All data inputs and data outputs change state during each clock cycle to consume the highest supply current. Data outputs were disconnected to normalize the graph to a zero-capacitance load. Once the capacitance load per data-output channel is known, the power dissipation can be calculated with the equation below. CALCULATING POWER DISSIPATION With ICC(f) taken from Figure 1, the maximum power dissipation (PT) of the IDT72V3612 may be calculated by: PT = VCC x ICC(f) + Σ(CL x (VOH - VOL)2 x fO) N where: N CL fo VOH VOL = = = = = number of outputs = 36 output capacitance load switching frequency of an output output HIGH level voltage output LOW level voltage When no reads or writes are occurring on this device, the power dissipated by a single clock (CLKA or CLKB) input running at frequency fS is calculated by: PT = VCC x fS x 0.025 mA/MHz 175 150 ICC(f) Supply Current mA fdata = 1/2 fS TA = 25°C 125 CL = 0 pF VCC = 3.6V VCC = 3.3V 100 VCC = 3.0V 75 50 25 0 0 10 20 30 40 50 60 70 fS Clock Frequency MHz Figure 1. Typical Characteristics: Supply Current (ICC) vs. Clock Frequency (fS) 7 80 90 4663 drw 04 IDT72V3612 3.3V, CMOS SyncBiFIFOTM 64 x 36 x 2 COMMERCIAL TEMPERATURE RANGE DC ELECTRICAL CHARACTERISTICS OVER RECOMMENDED RANGES OF SUPPLY VOLTAGE AND OPERATING FREE-AIR TEMPERATURE Commercial: Vcc=3.3V± 0.30V; for 12ns (83MHz) operation, Vcc=3.3V ±0.15V; TA = 0° C to +70°C; JEDEC JESD8-A compliant Symbol IDT72V3612L12 Min. Max. Parameter IDT72V3612L15 Min. Max. IDT72V3612L20 Min. Max. Unit fS Clock Frequency, CLKA or CLKB – 83 – 66.7 – 50 MHz tCLK Clock Cycle Time, CLKA or CLKB 12 – 15 – 20 – ns tCLKH Pulse Duration, CLKA and CLKB HIGH 5 – 6 – 8 – ns tCLKL Pulse Duration, CLKA and CLKB LOW 5 – 6 – 8 – ns tDS Setup Time, A0-A35 before CLKA↑ and B0-B35 before CLKB↑ 4 – 4 – 5 – ns tENS1 Setup Time, CSA, W/RA before CLKA↑; CSB, W/RB before CLKB↑ 3.5 – 6 – 6 – ns tENS2 Setup Time, ENA, before CLKA↑; ENB before CLKB↑ 3.5 – 4 – 5 – ns tENS3 Setup Time, MBA before CLKA↑: MBB before CLKB↑ 3.5 – 4 – 5 – ns tPGS Setup Time, ODD/EVEN and PGA before CLKA↑; ODD/EVEN and PGB before CLKB↑(1) 3 – 4 – 5 – ns tRSTS Setup Time, RST LOW before CLKA↑ or CLKB↑(2) 4 – 5 – 6 – ns tFSS Setup Time, FS0/FS1 before RST HIGH 4 – 5 – 6 – ns tDH Hold Time, A0-A35 after CLKA↑ and B0-B35 after CLKB↑ 0.5 – 1 – 1 – ns tENH1 Hold Time, CSA W/RA after CLKA↑; CSB, W/RB after CLKB↑ 0.5 – 1 – 1 – ns tENH2 Hold Time, ENA, after CLKA↑; ENB after CLKB↑ 1 – 1 – 1 – ns tENH3 Hold Time, MBA after CLKA↑; MBB after CLKB↑ 1 – 1 – 1 – ns tPGH Hold Time, ODD/EVEN and PGA after CLKA↑; ODD/EVEN and PGB after CLKB↑(1) 0 – 1 – 1 – ns tRSTH Hold Time, RST LOW after CLKA↑ or CLKB↑(2) 4 – 5 – 6 – ns Hold Time, FS0 and FS1 after RST HIGH 4 – 4 – 4 – ns tFSH tSKEW1 Skew Time, between CLKA↑ and CLKB↑ for EFA, EFB, FFA, and FFB 5.5 – 8 – 8 – ns tSKEW2(3,4) Skew Time, between CLKA↑ and CLKB↑ for AEA, AEB, AFA, and AFB 14 – 14 – 16 – ns (3) NOTES: 1. Only applies for a clock edge that does a FIFO read. 2. Requirement to count the clock edge as one of at least four needed to reset a FIFO. 3. Skew time is not a timing constraint for proper device operation and is only included to illustrate the timing relationship between CLKA cycle and CLKB cycle. 4. Design simulated, not tested. 8 IDT72V3612 3.3V, CMOS SyncBiFIFOTM 64 x 36 x 2 COMMERCIAL TEMPERATURE RANGE SWITCHING CHARACTERISTICS OVER RECOMMENDED RANGES OF SUPPLY VOLTAGE AND OPERATING FREE-AIR TEMPERATURE, CL = 30pF Commercial: Vcc=3.3V± 0.30V; for 12ns (83MHz) operation, Vcc=3.3V ±0.15V; TA = 0°C to +70°C; JEDEC JESD8-A compliant Symbol IDT72V3612L12 Min. Max. Parameter IDT72V3612L15 Min. Max. IDT72V3612L20 Min. Max. Unit tA Access Time, CLKA↑ to A0-A35 and CLKB↑ to B0-B35 1 8 2 10 2 12 ns tWFF Propagation Delay Time, CLKA↑ to FFA and CLKB↑ to FFB 1 8 2 10 2 12 ns tREF Propagation Delay Time, CLKA↑ to EFA and CLKB↑ to EFB 1 8 2 10 2 12 ns tPAE Propagation Delay Time, CLKA↑ to AEA and CLKB↑ to AEB 1 8 2 10 2 12 ns tPAF Propagation Delay Time, CLKA↑ to AFA and CLKB↑ to AFB 1 8 2 10 2 12 ns tPMF Propagation Delay Time, CLKA↑ to MBF1 LOW or MBF2 HIGH and CLKB↑ to MBF2 LOW or MBF1 HIGH 1 8 1 9 1 12 ns tPMR Propagation Delay Time, CLKA↑ to B0-B35(1) and CLKB↑ to A0-A35(2) 2 8 2 10 2 12 ns tMDV Propagation Delay Time, MBA to A0-A35 valid and MBB to B0-B35 valid 1 8 1 10 1 11.5 ns tPDPE Propagation Delay Time, A0-A35 valid to PEFA valid; B0-B35 valid to PEFB valid 2 8 2 10 2 11 ns Propagation Delay Time, ODD/EVEN to PEFA and PEFB 2 8 2 10 2 12 ns tPOPB Propagation Delay Time, ODD/EVEN to parity bits (A8, A17, A26, A35) and (B8, B17, B26, B35) 2 8 2 10 2 12 ns tPEPE Propagation Delay Time, W/RA, CSA, ENA, MBA or PGA to PEFA; W/RB, CSB, ENB. MBB, PGB to PEFB 1 8 1 10 1 12 ns tPEPB(3) Propagation Delay Time, W/RA, CSA, ENA, MBA or PGA to parity bits (A8, A17, A26, A35); W/RB, CSB, ENB. MBB or PGB to parity bits (B8, B17, B26, B35) 2 8 2 10 2 12 ns tRSF Propagation Delay Time, RST to (AEA, AEB) LOW and (AFA, AFB, MBF1, MBF2) HIGH 1 10 1 15 1 20 ns tEN Enable Time, CSA and W/RA LOW to A0-A35 active and CSB LOW and W/RB HIGH to B0-B35 active 2 6 2 10 2 12 ns tDIS Disable Time, CSA or W/RA HIGH to A0-A35 at highimpedance and CSB HIGH or W/RB LOW to B0-B35 at high impedance 1 6 1 8 1 9 ns tPOPE (3) NOTES: 1. Writing data to the mail1 register when the B0-B35 outputs are active and MBB is HIGH. 2. Writing data to the mail2 register when the A0-A35 outputs are active and MBA is HIGH. 3. Only applies when reading data from a mail register. 9 IDT72V3612 3.3V, CMOS SyncBiFIFOTM 64 x 36 x 2 COMMERCIAL TEMPERATURE RANGE Table 1. For the relevant Reset and preset value loading timing diagram, see Figure 2. SIGNAL DESCRIPTIONS RESET The IDT72V3612 is reset by taking the Reset (RST) input LOW for at least four port A Clock (CLKA) and four port B Clock (CLKB) LOW-to-HIGH transitions. The Reset input can switch asynchronously to the clocks. A device reset initializes the internal read and write pointers of each FIFO and forces the Full Flags (FFA, FFB) LOW, the Empty Flags (EFA, EFB) LOW, the Almost-Empty flags (AEA, AEB) LOW and the Almost-Full flags (AFA, AFB) HIGH. A reset also forces the Mailbox Flags (MBF1, MBF2) HIGH. After a reset, FFA is set HIGH after two LOW-to-HIGH transitions of CLKA and FFB is set HIGH after two LOW-to-HIGH transitions of CLKB. The device must be reset after power up before data is written to its memory. A LOW-to-HIGH transition on the RST input loads the Almost-Full and Almost-Empty registers (X) with the values selected by the Flag Select (FS0, FS1) inputs. The values that can be loaded into the registers are shown in TABLE 1 – FLAG PROGRAMMING FS1 FS0 RST ALMOST-FULL AND ALMOST-EMPTY FLAG OFFSET REGISTER (X) H H ↑ 16 H L ↑ 12 L H ↑ 8 L L ↑ 4 FIFO WRITE/READ OPERATION The state of port A data A0-A35 outputs is controlled by the port A Chip Select (CSA) and the port A Write/Read select (W/RA). The A0-A35 outputs are in the high-impedance state when either CSA or W/RA is HIGH. The A0A35 outputs are active when both CSA and W/RA are LOW. Data is loaded into FIFO1 from the A0-A35 inputs on a LOW-to-HIGH transition of CLKA when CSA is LOW, W/RA is HIGH, ENA is HIGH, MBA is LOW, and FFA is HIGH. Data is read from FIFO2 to the A0-A35 outputs by a LOW-to-HIGH transition of CLKA when CSA is LOW, W/RA is LOW, ENA is HIGH, MBA is LOW, and EFA is HIGH (see Table 2). Relevant Write and Read timing diagrams for Port A can be found in Figure 3 and Figure 6. The port B control signals are identical to those of port A. The state of the port B data (B0-B35) outputs is controlled by the port B Chip Select (CSB) and the port B Write/Read select (W/RB). The B0-B35 outputs are in the high-impedance state when either CSB or W/RB is HIGH. The B0B35 outputs are active when both CSB and W/RB are LOW. Data is loaded into FIFO2 from the B0-B35 inputs on a LOW-to-HIGH transition of CLKB when CSB is LOW, W/RB is HIGH, ENB is HIGH, MBB is LOW, and FFB is HIGH. Data is read from FIFO1 to the B0-B35 outputs by a LOW-to-HIGH transition of CLKB when CSB is LOW, W/RB is LOW, ENB is HIGH, MBB is LOW, and EFB is HIGH (see Table 3). Relevant Write and Read timing diagrams for Port B can be found in Figure 4 and Figure 5. The setup and hold time constraints to the port clocks for the port Chip Selects (CSA, CSB) and Write/Read selects (W/RA, W/RB) are only for enabling write TABLE 2 – PORT-A ENABLE FUNCTION TABLE CSA W/RA ENA MBA CLKA Data A (A0-A35) I/O Port Functions H X X X X Input None L H L X X Input None L H H L ↑ Input FIFO1 Write L H H H ↑ Input Mail1 Write L L L L X Output None L L H L ↑ Output FIFO2 Read L L L H X Output None L L H H ↑ Output Mail2 Read (Set MBF2 HIGH) TABLE 3 – PORT-B ENABLE FUNCTION TABLE CSB W/RB ENB MBB CLKB Data B (B0-B35) I/O Port Functions H X X X X Input None L H L X X Input None L H H L ↑ Input FIFO2 Write L H H H ↑ Input Mail2 Write L L L L X Output None L L H L ↑ Output FIFO1 read L L L H X Output None L L H H ↑ Output Mail1 Read (Set MBF1 HIGH) 10 IDT72V3612 3.3V, CMOS SyncBiFIFOTM 64 x 36 x 2 COMMERCIAL TEMPERATURE RANGE From the time a word is read from a FIFO, the previous memory location is ready to be written in a minimum of three cycles of the Full Flag synchronizing clock. Therefore, a Full Flag is LOW if less than two cycles of the Full Flag synchronizing clock have elapsed since the next memory write location has been read. The second LOW-to-HIGH transition on the Full Flag synchronization clock after the read sets the Full Flag HIGH and the data can be written in the following clock cycle. A LOW-to-HIGH transition on a Full Flag synchronizing clock begins the first synchronization cycle of a read if the clock transition occurs at time tSKEW1 or greater after the read. Otherwise, the subsequent clock cycle can be the first synchronization cycle (see Figure 9 and Figure 10). and read operations and are not related to high-impedance control of the data outputs. If a port enable is LOW during a clock cycle, the port chip select and write/read select may change states during the setup and hold time window of the cycle. SYNCHRONIZED FIFO FLAGS Each FIFO is synchronized to its port clock through two flip-flop stages. This is done to improve flag reliability by reducing the probability of metastable events on the output when CLKA and CLKB operate asynchronously to one another. EFA, AEA, FFA, and AFA are synchronized by CLKA. EFB, AEB, FFB, and AFB are synchronized to CLKB. Tables 4 and 5 show the relationship of each port flag to FIFO1 and FIFO2. EMPTY FLAGS (EFA, EFB) The Empty Flag of a FIFO is synchronized to the port clock that reads data from its array. When the Empty Flag is HIGH, new data can be read to the FIFO output register. When the Empty Flag is LOW, the FIFO is empty and attempted FIFO reads are ignored. The read pointer of a FIFO is incremented each time a new word is clocked to the output register. The state machine that controls an Empty Flag monitors a write-pointer and read-pointer comparator that indicates when the FIFO memory status is empty, empty+1, or empty+2. A word written to a FIFO can be read to the FIFO output register in a minimum of three cycles of the Empty Flag synchronizing clock. Therefore, an Empty Flag is LOW if a word in memory is the next data to be sent to the FIFO output register and two cycles of the port clock that reads data from the FIFO have not elapsed since the time the word was written. The Empty Flag of the FIFO is set HIGH by the second LOW-to-HIGH transition of the synchronizing clock, and the new data word can be read to the FIFO output register in the following cycle. A LOW-to-HIGH transition on an Empty Flag synchronizing clock begins the first synchronization cycle of a write if the clock transition occurs at time tSKEW1 or greater after the write. Otherwise, the subsequent clock cycle can be the first synchronization cycle (see Figure 7 and Figure 8). ALMOST EMPTY FLAGS (AEA, AEB) The Almost-Empty flag of a FIFO is synchronized to the port clock that reads data from its array. The state machine that controls an Almost-Empty flag monitors a write-pointer comparator that indicates when the FIFO memory status is almost-empty, almost-empty+1, or almost-empty+2. The almost-empty state is defined by the value of the Almost-Full and AlmostEmpty Offset register (X). This register is loaded with one of four preset values during a device reset (see Reset section). An Almost-Empty flag is LOW when the FIFO contains X or less words in memory and is HIGH when the FIFO contains (X+1) or more words. Two LOW-to-HIGH transitions of the Almost-Empty flag synchronizing clocks are required after a FIFO write for the Almost-Empty flag to reflect the new level of fill. Therefore, the Almost-Empty flag of a FIFO containing (X+1) or more words remains LOW if two cycles of the synchronizing clock have not elapsed since the write that filled the memory to the (X+1) level. An Almost-Empty flag is set HIGH by the second LOW-to-HIGH transition of the synchronizing clock after the FIFO write that fills memory to the (X+1) level. A LOW-to-HIGH transition of an Almost-Empty flag synchronizing clock begins the first synchronization cycle if it occurs at time tSKEW2 or greater after the write that fills the FIFO to (X+1) words. Otherwise, the subsequent synchronizing clock cycle can be the first synchronization cycle (see Figure 11 and 12). FULL FLAG (FFA, FFB) The Full Flag of a FIFO is synchronized to the port clock that writes data to its array. When the Full Flag is HIGH, a memory location is free in the FIFO to receive new data. No memory locations are free when the Full Flag is LOW and attempted writes to the FIFO are ignored. Each time a word is written to a FIFO, the write pointer is incremented. The state machine that controls a Full Flag monitors a write-pointer and read pointer comparator that indicates when the FIFO memory status is full, full-1, or full-2. ALMOST FULL FLAGS (AFA, AFB) The Almost-Full flag of a FIFO is synchronized to the port clock that writes data to its array. The state machine that controls an Almost-Full flag monitors a write-pointer and read-pointer comparator that indicates when the FIFO memory status is almost-full, almost-full-1, or almost-full-2. The almost-full state is defined by the value of the Almost-Full and Almost-Empty Offset register (X). This register is loaded with one of four preset values during a device reset (see Reset section). An Almost-Full flag is LOW when the FIFO contains (64- TABLE 4 – FIFO1 FLAG OPERATION TABLE 5 – FIFO2 FLAG OPERATION Synchronized Synchronized to CLKB to CLKA Number of Words Synchronized to CLKB to CLKA Number of Words in the FIFO1 EFB AEB AFA FFA in the FIFO2 0 L L H H 1 to X H L H (X+1) to [64-(X+1)] H H (64-X) to 63 H 64 H (1) Synchronized EFA AEA AFB FFB 0 L L H H H 1 to X H L H H H H (X+1) to [64-(X+1)] H H H H H L H (64-X) to 63 H H L H H L L 64 H H L L NOTE: 1. X is the value in the Almost-Empty flag and Almost-Full flag offset register. 11 (1) IDT72V3612 3.3V, CMOS SyncBiFIFOTM 64 x 36 x 2 X) or more words in memory and is HIGH when the FIFO contains [64-(X+1)] or less words. Two LOW-to-HIGH transitions of the Almost-Full flag synchronizing clock are required after a FIFO read for the Almost-Full flag to reflect the new level of fill. Therefore, the Almost-Full flag of a FIFO containing [64-(X+1)] or less words remains LOW if two cycles of the synchronizing clock have not elapsed since the read that reduced the number of words in memory to [64-(X+1)]. An Almost-Full flag is set HIGH by the second LOW-to-HIGH transition of the synchronizing clock after the FIFO read that reduces the number of words in memory to [64-(X+1)]. A second LOW-to-HIGH transition of an Almost-Full flag synchronizing clock begins the first synchronization cycle if it occurs at time tSKEW2 or greater after the read that reduces the number of words in memory to [64-(X+1)]. Otherwise, the subsequent synchronizing clock cycle can be the first synchronization cycle (see Figure 13 and 14). MAILBOX REGISTERS Each FIFO has a 36-bit bypass register to pass command and control information between port A and port B without putting it in queue. The Mailbox select (MBA, MBB) inputs choose between a mail register and a FIFO for a port data transfer operation. A LOW-to-HIGH transition on CLKA writes A0-A35 data to the mail1 register when a port A write is selected by CSA, W/RA, and ENA and MBA HIGH. A LOW-to-HIGH transition on CLKB writes B0-B35 data to the mail2 register when a port B write is selected by CSB, W/RB, and ENB and MBB is HIGH. Writing data to a mail register sets the corresponding flag (MBF1 or MBF2) LOW. Attempted writes to a mail register are ignored while the mail flag is LOW. When a port's data outputs are active, the data on the bus comes from the FIFO output register when the port Mailbox select input (MBA, MBB) is LOW and from the mail register when the port mailbox select input is HIGH. The Mail1 register Flag (MBF1) is set HIGH by a LOW-to-HIGH transition on CLKB when a port B read is selected by CSB, W/RB, and ENB and MBB is HIGH. The Mail2 register Flag (MBF2) is set HIGH by a LOW-to-HIGH transition on CLKA when port A read is selected by CSA, W/RA, and ENA and MBA is HIGH. The data in a mail register remains intact after it is read and changes only when new data is written to the register. Mail register and Mail Register Flag timing can be found in Figure 15 and Figure 16. PARITY CHECKING The port A inputs (A0-A35) and port B inputs (B0-B35) each have four parity trees to check the parity of incoming (or outgoing) data. A parity failure on one or more bytes of the input bus is reported by a LOW level on the port Parity Error Flag (PEFA, PEFB). Odd or even parity checking can be selected, and the Parity Error Fags can be ignored if this feature is not desired. Parity status is checked on each input bus according to the level of the Odd/Even parity (ODD/EVEN) select input. A parity error on one or more bytes of a port is reported by a LOW level on the corresponding port Parity Error Flag (PEFA, PEFB) output. Port A bytes are arranged as A0-A8, A9-A17, A18- COMMERCIAL TEMPERATURE RANGE A26, and A27-A35 with the most significant bit of each byte used as the parity bit. Port B bytes are arranged as B0-B8, B9-B17, B18-B26, and B27-B35, with the most significant bit of each byte used as the parity bit. When odd/even parity is selected, a port Parity Error Flag (PEFA, PEFB) is LOW if any byte on the port has an odd/even number of LOW levels applied to the bits. The four parity trees used to check the A0-A35 inputs are shared by the mail2 register when parity generation is selected for port A reads (PGA = HIGH). When a port A read from the mail2 register with parity generation is selected with W/RA LOW, CSA LOW, ENA HIGH, MBA HIGH, and PGA HIGH, the port A Parity Error Flag (PEFA) is held HIGH regardless of the levels applied to the A0-A35 inputs. Likewise, the parity trees used to check the B0-B35 inputs are shared by the mail1 register when parity generation is selected for port B reads (PGB = HIGH). When a port B read from the mail1 register with parity generation is selected with W/RB LOW, CSB LOW, ENB HIGH, MBB HIGH, and PGB HIGH, the port B Parity Error Flag (PEFB) is held HIGH regardless of the levels applied to the B0-B35 inputs (see Figure 17 and Figure 18). PARITY GENERATION A HIGH level on the port A Parity Generate select (PGA) or port B Parity Generate select (PGB) enables the IDT72V3612 to generate parity bits for port reads from a FIFO or mailbox register. Port A bytes are arranged as A0-A8, A9-A17, A18-26, and A27-A35, with the most significant bit of each byte used as the parity bit. Port B bytes are arranged as B0-B8, B9B17, B18-B26, and B27-B35, with the most significant bit of each byte used as the parity bit. A write to a FIFO or mail register stores the levels applied to all thirty-six inputs regardless of the state of the Parity Generate select (PGA, PGB) inputs. When data is read from a port with parity generation selected, the lower eight bits of each byte are used to generate a parity bit according to the level on the ODD/EVEN select. The generated parity bits are substituted for the levels originally written to the most significant bits of each byte as the word is read to the data outputs. Parity bits for FIFO data are generated after the data is read from SRAM and before the data is written to the output register. Therefore, the port A Parity Generate select (PGA) and Odd/Even parity select (ODD/ EVEN) have setup and hold time constraints to the port A Clock (CLKA) and the port B Parity Generate select (PGB) and ODD/EVEN have setup and hold-time constraints to the port B Clock (CLKB). These timing constraints only apply for a rising clock edge used to read a new word to the FIFO output register. The circuit used to generate parity for the mail1 data is shared by the port B bus (B0-B35) to check parity and the circuit used to generate parity for the mail2 data is shared by the port A bus (A0-A35) to check parity. The shared parity trees of a port are used to generate parity bits for the data in a mail register when the port Write/Read select (W/RA, W/RB) input is LOW, the port Mail select (MBA, MBB) input is HIGH, Chip Select (CSA, CSB) is LOW, Enable (ENA, ENB) is HIGH, and port Parity Generate select (PGA, PGB) is HIGH. Generating parity for mail register data does not change the contents of the register (see Figure 19 and Figure 20). 12 IDT72V3612 3.3V, CMOS SyncBiFIFOTM 64 x 36 x 2 COMMERCIAL TEMPERATURE RANGE CLKA tRSTH CLKB tRSTS tFSS tFSH RST 0,1 FS1,FS0 tWFF tWFF FFA tREF EFA tWFF tWFF FFB tREF EFB tPAE AEA tPAF AFA MBF1, MBF2 tRSF tPAE AEB tPAF AFB 4659 drw 05 Figure 2. Device Reset and Loading the X Register with the Value of Eight 13 IDT72V3612 3.3V, CMOS SyncBiFIFOTM 64 x 36 x 2 COMMERCIAL TEMPERATURE RANGE tCLK tCLKH tCLKL CLKA FFA HIGH tENS1 tENH1 tENS1 tENH1 tENS3 tENH3 tENS2 tENH2 CSA W/RA MBA tENS2 tENH2 tENS2 tENH2 ENA tDS tDH W1(1) A0 - A35 ODD/ EVEN W2(1) tPDPE tPDPE Valid PEFA No Operation Valid 4659 drw 06 NOTE: 1. Written to FIFO1. Figure 3. Port A Write Cycle Timing for FIFO1 tCLK tCLKH tCLKL CLKB FFB HIGH tENS1 tENH1 tENS1 tENH1 tENS3 tENH3 tENS2 tENH2 CSB W/RB MBB tENS2 tENH2 tENS2 tENH2 ENB tDS B0 - B35 ODD/ EVEN PEFB tDH W1(1) W2(1) tPDPE Valid No Operation tPDPE Valid 4659 drw 07 NOTE: 1. Written to FIFO2. Figure 4. Port B Write Cycle Timing for FIFO2 14 IDT72V3612 3.3V, CMOS SyncBiFIFOTM 64 x 36 x 2 COMMERCIAL TEMPERATURE RANGE tCLK tCLKH tCLKL CLKB EFB HIGH CSB W/RB tENS2 MBB tENH2 tENS2 tENH2 ENB tMDV tEN B0 - B35 tA Previous Data (1) tPGH tPGS PGB, ODD/ EVEN tA Word 1(1) tPGS tENS2 tENH2 No Operation tDIS Word 2 (1) tPGH 4659 drw 08 NOTE: 1. Read from FIFO1. Figure 5. Port B Read Cycle Timing for FIFO1 tCLK tCLKH tCLKL CLKA EFA HIGH CSA W/RA tENS2 MBA tENH2 tENS2 tENH2 tENS2 tENH2 ENA A0 - A35 PGA, ODD/ EVEN tEN tMDV tA Previous Data (1) tPGH tPGS tA Word 1(1) tPGS No Operation tDIS Word 2 (1) tPGH 4659 drw 09 NOTE: 1. Read from FIFO2. Figure 6. Port A Read Cycle Timing for FIFO2 15 IDT72V3612 3.3V, CMOS SyncBiFIFOTM 64 x 36 x 2 COMMERCIAL TEMPERATURE RANGE tCLK tCLKH tCLKL CLKA CSA LOW W/RA HIGH tENS3 tENH3 tENS2 tENH2 MBA ENA FFA HIGH tDS tDH W1 A0 - A35 (1) tSKEW1 CLKB EFB tCLK tCLKH tCLKL 1 2 tREF tREF FIFO1 Empty CSB LOW W/RB LOW MBB LOW tENS2 tENH2 ENB tA W1 B0 -B35 4659 drw 10 NOTE: 1. tSKEW1 is the minimum time between a rising CLKA edge and a rising CLKB edge for EFB to transition HIGH in the next CLKB cycle. If the time between the rising CLKA edge and rising CLKB edge is less than tSKEW1, then the transition of EFB HIGH may occur one CLKB cycle later than shown. Figure 7. EFB Flag Timing and First Data Read when FIFO1 is Empty 16 IDT72V3612 3.3V, CMOS SyncBiFIFOTM 64 x 36 x 2 COMMERCIAL TEMPERATURE RANGE tCLK tCLKH tCLKL CLKB CSB LOW W/RB HIGH tENS3 tENH3 tENS2 tENH2 MBB ENB FFB HIGH tDS tDH W1 B0 - B35 (1) tSKEW1 CLKA EFA FIFO2 Empty CSA LOW W/RA LOW MBA LOW tCLK tCLKH tCLKL 1 2 tREF tENS2 tREF tENH2 ENA tA A0 -A35 W1 4659 drw 11 NOTE: 1. tSKEW1 is the minimum time between a rising CLKB edge and a rising CLKA edge for EFA to transition HIGH in the next CLKA cycle. If the time between the rising CLKB edge and rising CLKA edge is less than tSKEW1, then the transition of EFA HIGH may occur one CLKA cycle later than shown. Figure 8. EFA Flag Timing and First Data Read when FIFO2 is Empty 17 IDT72V3612 3.3V, CMOS SyncBiFIFOTM 64 x 36 x 2 tCLKH tCLK COMMERCIAL TEMPERATURE RANGE tCLKL CLKB CSB LOW W/RB LOW MBB LOW tENS2 tENH2 ENB EFB B0 - B35 HIGH tA Previous Word in FIFO1 Output Register tSKEW1 CLKA Next Word From FIFO1 (1) tCLKH 1 tCLK tCLKL 2 tWFF tWFF FFA FIFO1 Full CSA LOW W/RA HIGH tENS3 tENH3 tENS2 tENH2 MBA ENA tDH tDS A0 - A35 To FIFO1 4659 drw 12 NOTE: 1. tSKEW1 is the minimum time between a rising CLKB edge and a rising CLKA edge for FFA to transition HIGH in the next CLKA cycle. If the time between the rising CLKB edge and rising CLKA edge is less than tSKEW1, then FFA may transition HIGH one CLKA cycle later than shown. Figure 9. FFA Flag Timing and First Available Write when FIFO1 is Full. 18 IDT72V3612 3.3V, CMOS SyncBiFIFOTM 64 x 36 x 2 COMMERCIAL TEMPERATURE RANGE tCLK tCLKH tCLKL CLKA CSA LOW W/RA LOW MBA LOW tENS2 tENH2 ENA EFA A0 - A35 HIGH tA Previous Word in FIFO2 Output Register Next Word From FIFO2 tSKEW1(1) CLKB tCLKH 1 tCLK tCLKL 2 tWFF tWFF FFB FIFO2 Full CSB LOW W/RB HIGH tENS3 tENH3 tENS2 tENH2 MBB ENB tDH tDS B0 - B35 To FIFO2 4659 drw 13 NOTE: 1. tSKEW1 is the minimum time between a rising CLKA edge and a rising CLKB edge for FFB to transition HIGH in the next CLKB cycle. If the time between the rising CLKA edge and rising CLKB edge is less than tSKEW1, then FFB may transition HIGH one CLKB cycle later than shown. Figure 10. FFB Flag Timing and First Available Write when FIFO2 is Full CLKA tENS2 tENH2 ENA tSKEW2 CLKB (1) 1 2 tPAE AEB X Words in FIFO1 tPAE (X+1) Words in FIFO1 tENS2 tENH2 ENB 4659 drw 14 NOTES: 1. tSKEW2 is the minimum time between a rising CLKA edge and a rising CLKB edge for AEB to transition HIGH in the next CLKB cycle. If the time between the rising CLKA edge and rising CLKB edge is less than tSKEW2, then AEB may transition HIGH one CLKB cycle later than shown. 2. FIFO1 Write (CSA = LOW, W/RA = HIGH, MBA = LOW), FIFO1 read (CSB = LOW, W/RB = LOW, MBB = LOW). Figure 11. Timing for AEB when FIFO1 is Almost Empty 19 IDT72V3612 3.3V, CMOS SyncBiFIFOTM 64 x 36 x 2 COMMERCIAL TEMPERATURE RANGE CLKB tENS2 tENH2 ENB (1) tSKEW2 1 CLKA 2 tPAE tPAE AEA X Words in FIFO2 (X+1) Words in FIFO2 tENS2 tENH2 ENA 4659 drw 15 NOTES: 1. tSKEW2 is the minimum time between a rising CLKB edge and a rising CLKA edge for AEA to transition HIGH in the next CLKA cycle. If the time between the rising CLKB edge and rising CLKA edge is less than tSKEW2, then AEA may transition HIGH one CLKA cycle later than shown. 2. FIFO2 Write (CSB = LOW, W/RB = HIGH, MBB = LOW), FIFO2 read (CSA = LOW, W/RA = LOW, MBA = LOW). Figure 12. Timing for AEA when FIFO2 is Almost Empty tSKEW2 (1) 1 CLKA tENS2 2 tENH2 ENA tPAF AFA tPAF (64-X) Words in FIFO1 [64-(X+1)] Words in FIFO1 CLKB tENS2 tENH2 ENB 4659 drw 16 NOTES: 1. tSKEW2 is the minimum time between a rising CLKA edge and a rising CLKB edge for AFA to transition HIGH in the next CLKA cycle. If the time between the rising CLKA edge and rising CLKB edge is less than tSKEW2, then AFA may transition HIGH one CLKA cycle later than shown. 2. FIFO1 Write (CSA = LOW, W/RA = HIGH, MBA = LOW), FIFO1 read (CSB = LOW, W/RB = LOW, MBB = LOW). Figure 13. Timing for AFA when FIFO1 is Almost Full tSKEW2 (1) 1 CLKB tENS2 2 tENH2 ENB AFB tPAF tPAF [64-(X+1)] Words in FIFO2 (64-X) Words in FIFO2 CLKA tENS2 tENH2 ENA 4659 drw 17 NOTES: 1. tSKEW2 is the minimum time between a rising CLKB edge and a rising CLKA edge for AFB to transition HIGH in the next CLKB cycle. If the time between the rising CLKB edge and rising CLKA edge is less than tSKEW2, then AFB may transition HIGH one CLKB cycle later than shown. 2. FIFO2 Write (CSB = LOW, W/RB = HIGH, MBB = LOW), FIFO2 read (CSA = LOW, W/RA = LOW, MBA = LOW). Figure 14. Timing for AFB when FIFO2 is Almost Full 20 IDT72V3612 3.3V, CMOS SyncBiFIFOTM 64 x 36 x 2 COMMERCIAL TEMPERATURE RANGE CLKA tENS1 tENH1 tENS1 tENH1 tENS1 tENH1 tENS1 tENH1 CSA W/RA MBA ENA tDS W1 A0 - A35 tDH CLKB tPMF tPMF MBF1 CSB W/RB MBB tENS2 tENH2 ENB tEN B0 - B35 tMDV tPMR tDIS W1 (Remains valid in Mail1 Register after read) FIFO1 Output Register 4659 drw 18 NOTE: 1. Port B parity generation off (PGB = LOW). Figure 15. Timing for Mail1 Register and MBF1 Flag 21 IDT72V3612 3.3V, CMOS SyncBiFIFOTM 64 x 36 x 2 COMMERCIAL TEMPERATURE RANGE CLKB tENS1 tENH1 tENS1 tENH1 tENS1 tENH1 tENS1 tENH1 CSB W/RB MBB ENB tDS W1 B0 - B35 tDH CLKA tPMF tPMF MBF2 CSA W/RA MBA tENS2 tENH2 ENA tMDV tEN FIFO2 Output Register A0 - A35 tPMR tDIS W1 (Remains valid in Mail2 Register after read) 4659 drw 19 NOTE: 1. Port A parity generation off (PGA = LOW). Figure 16. Timing for Mail2 Register and MBF2 Flag ODD/ EVEN W/RA MBA PGA tPOPE PEFA Valid tPEPE tPOPE Valid Valid tPEPE Valid 4659 drw 20 NOTE: 1. ENA is HIGH, and CSA is LOW. Figure 17. ODD/EVEN W/RA, MBA, and PGA to PEFA Timing 22 IDT72V3612 3.3V, CMOS SyncBiFIFOTM 64 x 36 x 2 COMMERCIAL TEMPERATURE RANGE ODD/ EVEN W/RB MBB PGB tPOPE PEFB Valid tPEPE tPOPE Valid Valid tPEPE Valid 4659 drw 21 NOTE: 1. ENB is HIGH, and CSB is LOW. Figure 18. ODD/EVEN W/RB, MBB, and PGB to PEFB Timing ODD/ EVEN CSA LOW W/RA MBA PGA tEN tPEPB tMDV A8, A17, A26, A35 tPOPB Generated Parity tPEPB Generated Parity Mail2 Data Mail2 Data 4659 drw 22 NOTE: 1. ENA is HIGH. Figure 19. Parity Generation Timing when Reading from Mail2 Register ODD/ EVEN CSB LOW W/RB MBB PGB tEN B8, B17, B26, B35 tPEPB tMDV tPOPB Generated Parity tPEPB Generated Parity Mail1 Data Mail1 Data 4659 drw 23 NOTE: 1. ENB is HIGH. Figure 20. Parity Generation Timing when Reading from Mail1 Register 23 IDT72V3612 3.3V, CMOS SyncBiFIFOTM 64 x 36 x 2 COMMERCIAL TEMPERATURE RANGE PARAMETER MEASUREMENT INFORMATION 3.3V 330Ω From Output Under Test 30 pF (1) 510Ω LOAD CIRCUIT 3V 1.5 V Timing Input GND tS GND tW 3V 1.5 V 1.5 V 1.5 V 1.5 V th 3V Data, Enable Input Low-Level Input GND VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 1.5 V 1.5 V GND VOLTAGE WAVEFORMS PULSE DURATIONS 3V Output Enable 1.5 V tPLZ 1.5 V tPZL GND ≈ 3V Input 1.5 V Low-Level Output VOL tPZH VOH High-Level Output 3V High-Level Input 1.5 V tPHZ 3V 1.5 V 1.5 V tPD tPD GND VOH In-Phase Output 1.5 V 1.5 V ≈ OV VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES 4659 drw 24 NOTE: 1. Includes probe and jig capacitance Figure 21. Load Circuit and Voltage Waveforms 24 ORDERING INFORMATION IDT XXXXXX Device Type X Power XX Speed X Package X Process/ Temperature Range BLANK Commercial (0°C to +70°C) PF PQF Thin Quad Flat Pack (TQFP, PN120-1) Plastic Quad Flat Pack (PQFP, PQ132-1) 12 15 20 Commercial Only L Low Power Clock Cycle Time (tCLK) Speed in Nanoseconds 72V3612 64 x 36 x 2 3.3V SyncBiFIFO 4659 drw 25 NOTE: 1. Industrial temperature range is available by special order. DATASHEET DOCUMENT HISTORY 07/10/2000 05/27/2003 pg. 1. pg. 6. CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054 for SALES: 800-345-7015 or 408-727-6116 fax: 408-492-8674 www.idt.com 25 for Tech Support: 408-330-1753 email: [email protected]