STMicroelectronics M28C64-25BS1T 64 kbit 8k x 8 parallel eeprom with software data protection Datasheet

M28C64
64 Kbit (8K x 8) Parallel EEPROM
With Software Data Protection
■
Fast Access Time:
– 90 ns at VCC=5 V for M28C64 and M28C64-A
– 120 ns at VCC=3 V for M28C64-xxW
■
Single Supply Voltage:
– 4.5 V to 5.5 V for M28C64 and M28C64-A
– 2.7 V to 3.6 V for M28C64-xxW
■
Low Power Consumption
■
Fast BYTE and PAGE WRITE (up to 64 Bytes)
– 1 ms at VCC=4.5 V for M28C64-A
28
1
PLCC32 (KA)
PDIP28 (BS)
– 3 ms at VCC=4.5 V for M28C64
– 5 ms at VCC=2.7 V for M28C64-xxW
■
Enhanced Write Detection and Monitoring:
– Ready/Busy Open Drain Output
28
– Data Polling
1
– Toggle Bit
– Page Load Timer Status
■
JEDEC Approved Bytewide Pin-Out
■
Software Data Protection
■
100000 Erase/Write Cycles (minimum)
■
Data Retention (minimum):
– 40 Years for M28C64 and M28C64-xxW
– 10 Years for M28C64-A
SO28 (MS)
300 mil width
TSOP28 (NS)
8 x 13.4 mm
Figure 1. Logic Diagram
VCC
Table 1. Signal Names
13
A0-A12
Address Input
DQ0-DQ7
Data Input / Output
W
Write Enable
W
E
Chip Enable
E
G
Output Enable
G
RB
Ready / Busy
VCC
Supply Voltage
VSS
Ground
8
A0-A12
DQ0-DQ7
M28C64
RB
June 2000
VSS
AI01350C
1/24
M28C64
Figure 2C. SO Connections
Figure 2A. DIP Connections
RB
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
VSS
VCC
W
NC
A8
A9
A11
G
A10
E
DQ7
DQ6
DQ5
DQ4
DQ3
1
28
2
27
3
26
4
25
5
24
6
23
7
22
M28C64
8
21
9
20
10
19
11
18
12
17
13
16
14
15
RB
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
VSS
1
2
3
4
5
6
7
M28C64
8
9
10
11
12
13
14
AI01351C
28
27
26
25
24
23
22
21
20
19
18
17
16
15
AI01353C
Figure 2B. PLLC Connections
Figure 2D. TSOP Connections
RB
DU
VCC
W
NC
Note: 1. NC = Not Connected
A7
A12
Note: 1. NC = Not Connected
1 32
A6
A5
A4
A3
A2
A1
A0
NC
DQ0
9
M28C64
VCC
W
NC
A8
A9
A11
G
A10
E
DQ7
DQ6
DQ5
DQ4
DQ3
25
A8
A9
A11
NC
G
A10
E
DQ7
DQ6
DQ1
DQ2
VSS
DU
DQ3
DQ4
DQ5
17
G
A11
A9
A8
NC
W
VCC
RB
A12
A7
A6
A5
A4
A3
22
28
1
21
M28C64
7
15
14
8
A10
E
DQ7
DQ6
DQ5
DQ4
DQ3
VSS
DQ2
DQ1
DQ0
A0
A1
A2
AI01354C
AI01352D
Note: 1. NC = Not Connected
2. DU = Do Not Use
Note: 1. NC = Not Connected
DESCRIPTION
The M28C64 devices consist of 8192x8 bits of low
power, parallel EEPROM, fabricated with
STMicroelectronics’ proprietary single polysilicon
CMOS technology. The devices offer fast access
time, with low power dissipation, and require a
single voltage supply (5V or 3V, depending on the
option chosen).
The device has been designed to offer a flexible
microcontroller interface, featuring both hardware
and software handshaking, with Ready/Busy,
Data Polling and Toggle Bit. The device supports
a 64 byte Page Write operation. Software Data
Protection (SDP) is also supported, using the
standard JEDEC algorithm.
2/24
M28C64
Table 2. Absolute Maximum Ratings 1
Symbol
Value
Unit
Ambient Operating Temperature
-40 to 125
°C
T STG
Storage Temperature
-65 to 150
°C
VCC
Supply Voltage
-0.3 to VCC+1
V
VIO
Input or Output Voltage
-0.6 to VCC+0.6
V
VI
Input Voltage
-0.3 to 6.5
V
4000
V
TA
VESD
Parameter
Electrostatic Discharge Voltage (Human Body model) 2
Note: 1. Except for the rating “Operating Temperature Range”, stresses above those listed in the Table “Absolute Maximum Ratings” may
cause permanent damage to the device. These are stress ratings only, and operation of the device at these or any other conditions
above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the ST SURE Program and other relevant quality documents.
2. MIL-STD-883C, 3015.7 (100 pF, 1500 Ω)
Figure 3. Block Diagram
RB
A6-A12
(Page Address)
A0-A5
RESET
ADDRESS
LATCH
X DECODE
VPP GEN
E
G
W
CONTROL LOGIC
64K ARRAY
ADDRESS
LATCH
Y DECODE
SENSE AND DATA LATCH
I/O BUFFERS
PAGE LOAD
TIMER STATUS
TOGGLE BIT
DATA POLLING
DQ0-DQ7
AI01355
3/24
M28C64
Table 3. Operating Modes 1
Mode
E
G
W
DQ0-DQ7
Stand-by
1
X
X
Hi-Z
Output Disable
X
1
X
Hi-Z
Write Disable
X
X
1
Hi-Z
Read
0
0
1
Data Out
Write
0
1
0
Data In
Chip Erase
0
V
0
Hi-Z
Note: 1. 0=VIL; 1=VIH; X = VIH or VIL; V=12V ± 5%.
SIGNAL DESCRIPTION
The external connections to the device are
summarized in Table 1, and their use in Table 3.
Addresses (A0-A12). The address inputs are
used to select one byte from the memory array
during a read or write operation.
Data In/Out (DQ0-DQ7). The contents of the data
byte are written to, or read from, the memory array
through the Data I/O pins.
Chip Enable (E). The chip enable input must be
held low to enable read and write operations.
When Chip Enable is high, power consumption is
reduced.
Output Enable (G). The Output Enable input
controls the data output buffers, and is used to
initiate read operations.
Write Enable (W). The Write Enable input controls
whether the addressed location is to be read, from
or written to.
Ready/Busy (RB). Ready/Busy is an open drain
output that can be used to detect the end of the
internal write cycle.
DEVICE OPERATION
In order to prevent data corruption and inadvertent
write operations, an internal V CC comparator
inhibits the Write operations if the VCC voltage is
lower than VWI (see Table 4A and Table 4B). Once
the voltage applied on the V CC pin goes over the
VWI threshold (VCC>VWI), write access to the
memory is allowed after a time-out tPUW, as
specified in Table 4A and Table 4B.
Further protection against data corruption is
offered by the E and W low pass filters: any glitch,
on the E and W inputs, with a pulse width less than
10 ns (typical) is internally filtered out to prevent
inadvertent write operations to the memory.
Table 4A. Power-Up Timing1 for M28C64 (5V range)
(TA = 0 to 70 °C or –40 to 85 °C or –40 to 125 °C; VCC = 4.5 to 5.5 V)
Symbol
Parameter
Min.
Max.
Unit
tPUR
Time Delay to Read Operation
1
µs
tPUW
Time Delay to Write Operation (once VCC ≥ VWI)
10
ms
3.0
4.2
V
Min.
Max.
Unit
VWI
Write Inhibit Threshold
Note: 1. Sampled only, not 100% tested.
Table 4B. Power-Up Timing1 for M28C64-xxW (3V range)
(TA = 0 to 70 °C or –40 to 85 °C; VCC = 2.7 to 3.6 V)
Symbol
Parameter
tPUR
Time Delay to Read Operation
1
µs
tPUW
Time Delay to Write Operation (once VCC ≥ VWI)
15
ms
2.5
V
VWI
Write Inhibit Threshold
Note: 1. Sampled only, not 100% tested.
4/24
1.5
M28C64
Read
The device is accessed like a static RAM. When E
and G are low, and W is high, the contents of the
addressed location are presented on the I/O pins.
Otherwise, when either G or E is high, the I/O pins
revert to their high impedance state.
Write
Write operations are initiated when both W and E
are low and G is high. The device supports both
W-controlled and E-controlled write cycles (as
shown in Figure 11 and Figure 12). The address is
latched during the falling edge of W or E (which
ever occurs later) and the data is latched on the
rising edge of W or E (which ever occurs first).
After a delay, t WLQ5H, that cannot be shorter than
the value specified in Table 10A to Table 10C, the
internal write cycle starts. It continues, under
internal timing control, until the write operation is
complete. The commencement of this period can
be detected by reading the Page Load Timer
Status on DQ5. The end of the cycle can be
detected by reading the status of the Data Polling
and the Toggle Bit functions on DQ7 and DQ6.
Page Write
The Page Write mode allows up to 64 bytes to be
written on a single page in a single go. This is
achieved through a series of successive Write
operations, no two of which are separated by more
than the t WLQ5H value (as specified in Table 10A
to Table 10C).
All bytes must be located on the same page
address (A12-A6 must be the same for all bytes).
The internal write cycle can start at any instant
after t WLQ5H. Once initiated, the write operation is
internally timed, and continues, uninterrupted,
until completion.
As with the single byte Write operation, described
above, the DQ5, DQ6 and DQ7 lines can be used
to detect the beginning and end of the internally
controlled phase of the Page Write cycle.
Software Data Protection (SDP)
The device offers a software-controlled writeprotection mechanism that allows the user to
inhibit all write operations to the device. This can
be useful for protecting the memory from
inadvertent write cycles that may occur during
periods of instability (uncontrolled bus conditions
when excessive noise is detected, or when power
supply levels are outside their specified values).
By default, the device is shipped in the
“unprotected” state: the memory contents can be
freely changed by the user. Once the Software
Data Protection Mode is enabled, all write
commands are ignored, and have no effect on the
memory contents.
The device remains in this mode until a valid
Software Data Protection disable sequence is
received. The device reverts to its “unprotected”
state.
The status of the Software Data Protection
(enabled or disabled) is represented by a non-
Figure 4. Software Data Protection Enable Algorithm and Memory Write
Write AAh in
Address 1555h
Page Write
Timing
(see note 1)
Write 55h in
Address 0AAAh
Write AAh in
Address 1555h
Page Write
Timing
(see note 1)
Write A0h in
Address 1555h
SDP is set
SDP Enable Algorithm
Write 55h in
Address 0AAAh
Write A0h in
Address 1555h
Write
is enabled
Physical
Page Write
Instruction
Page Write
(1 up to 64 bytes)
Write to Memory
When SDP is SET
AI01356C
Note: 1. The most significant address bits (A12 to A6) differ during these specific Page Write operations.
5/24
M28C64
Figure 5. Software Data Protection Disable Algorithm
Write AAh in
Address 1555h
Write 55h in
Address 0AAAh
Page Write
Timing
Write 80h in
Address 1555h
Write AAh in
Address 1555h
Write 55h in
Address 0AAAh
Write 20h in
Address 1555h
Unprotected State
AI01357B
volatile latch, and is remembered across periods
of the power being off.
The Software Data Protection Enable command
consists of the writing of three specific data bytes
to three specific memory locations (each location
being on a different page), as shown in Figure 4.
Similarly to disable the Software Data Protection,
the user has to write specific data bytes into six
different locations, as shown in Figure 5. This
complex series of operations protects against the
chance of inadvertent enabling or disabling of the
Software Data Protection mechanism.
When SDP is enabled, the memory array can still
have data written to it, but the sequence is more
complex (and hence better protected from
inadvertent use). The sequence is as shown in
Figure 4. This consists of an unlock key, to enable
the write action, at the end of which the SDP
continues to be enabled. This allows the SDP to
be enabled, and data to be written, within a single
Write cycle (tWC).
Software Chip Erase
Using this function, available on the M28C64 but
not on the M28C64-A or M28C64-xxW, the
contents of the entire memory are erased (set to
FFh) by holding Chip Enable (E) low, and holding
Output Enable (G) at VCC+7.0V. The chip is
cleared when a 10 ms low pulse is applied to the
Write Enable (W) signal (see Figure 7 and Table 5
for details).
6/24
Status Bits
The devices provide three status bits (DQ7, DQ6
and DQ5), and one output pin (RB), for use during
write operations. These allow the application to
use the write time latency of the device for getting
on with other work. These signals are available on
the I/O port bits DQ7, DQ6 and DQ5 (but only
during programming cycle, once a byte or more
has been latched into the memory) or continuously
on the RB output pin.
Data Polling bit (DQ7). The internally timed write
cycle starts after tWLQ5H (defined in Table 10A to
Table 10C) has elapsed since the previous byte
was latched in to the memory. The value of the
DQ7 bit of this last byte, is used as a signal
Figure 6. Status Bit Assignment
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
DP
TB
PLTS
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
DP
TB
PLTS
Hi-Z
= Data Polling
= Toggle Bit
= Page Load Timer Status
= High impedance
AI02815
M28C64
Figure 7. Chip Erase AC Waveforms (M28C64 and M28C64-xxW)
tWHEH
E
G
tGLWH
W
tELWL
tWLWH2
tWHRH
AI01484B
throughout this write operation: it is inverted while
the internal write operation is underway, and is
inverted back to its original value once the
operation is complete.
Toggle bit (DQ6). The device offers another way
for determining when the internal write cycle is
completed. During the internal Erase/Write cycle,
DQ6 toggles from ’0’ to ’1’ and ’1’ to ’0’ (the first
read value being ’0’) on subsequent attempts to
read any byte of the memory. When the internal
write cycle is complete, the toggling is stopped,
and the values read on DQ7-DQ0 are those of the
addressed memory byte. This indicates that the
device is again available for new Read and Write
operations.
Page Load Timer Status bit (DQ5). An internal
timer is used to measure the period between
successive Write operations, up to tWLQ5H
(defined in Table 10A to Table 10C). The DQ5 line
is held low to show when this timer is running
(hence showing that the device has received one
write operation, and is waiting for the next). The
DQ5 line is held high when the counter has
overflowed (hence showing that the device is now
starting the internal write to the memory array).
Ready/Busy pin. The RB pin is an open drain
output that is held low during the erase/write cycle,
and that is released (allowed to float) at the
completion of the programming cycle.
Table 5. Chip Erase AC Characteristics1 for M28C64 and M28C64-xxW
(TA = 0 to 70 °C or –40 to 85 °C or –40 to 125 °C; VCC = 4.5 to 5.5 V)
(TA = 0 to 70 °C or –40 to 85 °C; VCC = 2.7 to 3.6 V)
Symbol
Parameter
Test Condition
Min.
Max.
Unit
tELWL
Chip Enable Low to Write Enable Low
G = VCC + 7V
1
µs
tWHEH
Write Enable High to Chip Enable High
G = VCC + 7V
0
ns
tWLWH2
Write Enable Low to Write Enable High
G = VCC + 7V
10
ms
tGLWH
Output Enable Low to Write Enable High
G = VCC + 7V
1
µs
tWHRH
Write Enable High to Write Enable Low
G = VCC + 7V
3
ms
Note: 1. Sampled only, not 100% tested.
7/24
M28C64
Table 6A. Read Mode DC Characteristics for M28C64 and M28C64-A (5V range)
(TA = 0 to 70 °C or –40 to 85 °C or –40 to 125 °C; VCC = 4.5 to 5.5 V)
Symbol
Parameter
Test Condi tion
ILI
Input Leakage Current
ILO
Output Leakage Current
Max.
Unit
0 V ≤ VIN ≤ VCC
10
µA
0 V ≤ VOUT ≤ VCC
10
µA
Supply Current (TTL inputs)
E = VIL, G = VIL , f = 5 MHz
30
mA
Supply Current (CMOS inputs)
E = VIL, G = VIL , f = 5 MHz
25
mA
ICC1 1
Supply Current (Stand-by) TTL
E = VIH
1
mA
ICC2 1
Supply Current (Stand-by) CMOS
E > VCC - 0.3V
100
µA
ICC 1
Min.
V IL
Input Low Voltage
-0.3
0.8
V
V IH
Input High Voltage
2
VCC + 0.5
V
VOL
Output Low Voltage
IOL = 2.1 mA
0.4
V
VOH
Output High Voltage
IOH = -400 µA
2.4
V
Note: 1. All inputs and outputs open circuit.
Table 6B. Read Mode DC Characteristics for M28C64-xxW (3V range)
(TA = 0 to 70 °C or –40 to 85 °C; VCC = 2.7 to 3.6 V)
Symbol
Parameter
Test Condi tion
ILI
Input Leakage Current
ILO
Output Leakage Current
ICC 1
Supply Current (CMOS inputs)
ICC2 1
Supply Current (Stand-by) CMOS
Min.
Max.
Unit
0 V ≤ VIN ≤ VCC
10
µA
0 V ≤ VOUT ≤ VCC
10
µA
E = VIL, G = VIL , f = 5 MHz, VCC = 3.3V
8
mA
E = VIL, G = VIL , f = 5 MHz, VCC = 3.6V
10
mA
E > VCC - 0.3V
20
µA
V IL
Input Low Voltage
-0.3
0.6
V
V IH
Input High Voltage
2
VCC + 0.5
V
VOL
Output Low Voltage
IOL = 1.6 mA
0.2 VCC
V
VOH
Output High Voltage
IOH = -400 µA
Note: 1. All inputs and outputs open circuit.
8/24
0.8 VCC
V
M28C64
Table 7. Input and Output Parameters1 (TA = 25 °C, f = 1 MHz)
Symbol
C IN
C OUT
Parameter
Test Condition
Input Capacitance
Output Capacitance
Min.
Max.
Unit
V IN = 0 V
6
pF
VOUT = 0 V
12
pF
Note: 1. Sampled only, not 100% tested.
Table 8. AC Measurement Conditions
≤ 20 ns
Input Rise and Fall Times
Input Pulse Voltages (M28C64, M28C64-A)
0.4 V to 2.4 V
0 V to VCC-0.3V
Input Pulse Voltages (M28C64-xxW)
Input and Output Timing Reference Voltages (M28C64, M28C64-A)
0.8 V to 2.0 V
Input and Output Timing Reference Voltages (M28C64-xxW)
Figure 8. AC Testing Input Output Waveforms
0.5 VCC
Figure 9. AC Testing Equivalent Load Circuit
4.5V to 5.5V Operating Voltage
2.4V
0.4V
2.0V
0.8V
IOL
DEVICE
UNDER
TEST
2.7V to 3.6V Operating Voltage
OUT
IOH
VCC – 0.3V
CL = 100pF
0.5 VCC
0V
AI02101B
CL includes JIG capacitance
AI02102B
9/24
M28C64
Table 9A. Read Mode AC Characteristics for M28C64 and M28C64-A (5V range)
(TA = 0 to 70 °C or –40 to 85 °C; VCC = 4.5 to 5.5 V)
Symbol
Alt.
Parameter
Test
Condi t
ion
M28C64
-90
Min
-12
Max
Min
-15
Max
Min
Unit
Max
tAVQV
tACC
Address Valid to Output Valid
E = VIL,
G = VIL
90
120
150
ns
tELQV
tCE
Chip Enable Low to Output Valid
G = VIL
90
120
150
ns
tGLQV
tOE
Output Enable Low to Output Valid
E = VIL
40
45
50
ns
tEHQZ1
tDF
Chip Enable High to Output Hi-Z
G = VIL
0
40
0
45
0
50
ns
tGHQZ1
tDF
Output Enable High to Output Hi-Z
E = VIL
0
40
0
45
0
50
ns
tAXQX
tOH
Address Transition to Output
Transition
E = VIL,
G = VIL
0
0
0
ns
Note: 1. Output Hi-Z is defined as the point at which data is no longer driven.
Table 9B. Read Mode AC Characteristics for M28C64 (5V range)
(TA = –40 to 125 °C; VCC = 4.5 to 5.5 V)
Symbol
Alt.
Parameter
Test
Condi t
ion
M28C64
-12
Min
Unit
Max
tAVQV
tACC
Address Valid to Output Valid
E = VIL,
G = VIL
120
ns
tELQV
tCE
Chip Enable Low to Output Valid
G = VIL
120
ns
tGLQV
tOE
Output Enable Low to Output Valid
E = VIL
45
ns
tEHQZ1
tDF
Chip Enable High to Output Hi-Z
G = VIL
0
65
ns
tGHQZ1
tDF
Output Enable High to Output Hi-Z
E = VIL
0
65
ns
tAXQX
tOH
Address Transition to Output
Transition
E = VIL,
G = VIL
0
Note: 1. Output Hi-Z is defined as the point at which data is no longer driven.
10/24
ns
M28C64
Table 9C. Read Mode AC Characteristics for M28C64-xxW (3V range)
(TA = 0 to 70 °C or –40 to 85 °C; VCC = 2.7 to 3.6 V)
Symbol
Alt.
Parameter
Test
Condit
ion
M28C64-xxW
-12
Min
-15
-20
-25
-30
Max Min
Max Min
Max
Min Max
Min
Unit
Max
tAVQV
tACC
Address Valid to
Output Valid
E =VIL,
G = VIL
120
150
200
250
300
ns
tELQV
tCE
Chip Enable Low to
Output Valid
G = VIL
120
150
200
250
300
ns
tGLQV
tOE
Output Enable Low
to Output Valid
E = VIL
80
80
100
150
150
ns
tEHQZ1
tDF
Chip Enable High to
Output Hi-Z
G = VIL
0
45
0
50
0
55
0
60
0
60
ns
tGHQZ1
tDF
Output Enable High
to Output Hi-Z
E = VIL
0
45
0
50
0
55
0
60
0
60
ns
tAXQX
tOH
Address Transition
to Output Transition
E =VIL,
G = VIL
0
0
0
0
0
ns
Note: 1. Output Hi-Z is defined as the point at which data is no longer driven.
Figure 10. Read Mode AC Waveforms (with Write Enable, W, high)
A0-A12
VALID
tAVQV
tAXQX
E
tGLQV
tEHQZ
G
tELQV
DQ0-DQ7
tGHQZ
DATA OUT
Hi-Z
AI00749B
Note: 1. Write Enable (W) = VIH
11/24
M28C64
Table 10A. Write Mode AC Characteristics for M28C64 and M28C64-A (5V range)
(TA = 0 to 70 °C or –40 to 85 °C; VCC = 4.5 to 5.5 V)
M28C64
Symbol
Alt.
Parameter
Test Condit ion
Unit
Min
Max
tAVWL
tAS
Address Valid to Write Enable Low
E = VIL, G = VIH
0
ns
tAVEL
tAS
Address Valid to Chip Enable Low
G = VIH, W = VIL
0
ns
tELWL
tCES
Chip Enable Low to Write Enable Low
G = VIH
0
ns
tGHWL
tOES
Output Enable High to Write Enable Low
E = VIL
0
ns
tGHEL
tOES
Output Enable High to Chip Enable Low
W = VIL
0
ns
tWLEL
tWES
Write Enable Low to Chip Enable Low
G = VIH
0
ns
tWLAX
tAH
Write Enable Low to Address Transition
50
ns
tELAX
tAH
Chip Enable Low to Address Transition
50
ns
tWLDV
tDV
Write Enable Low to Input Valid
E = VIL, G = VIH
1
µs
tELDV
tDV
Chip Enable Low to Input Valid
G = VIH, W = VIL
1
µs
tELEH
tWP
Chip Enable Low to Chip Enable High
50
ns
tWHEH
tCEH
Write Enable High to Chip Enable High
0
ns
tWHGL
tOEH
Write Enable High to Output Enable Low
0
ns
tEHGL
tOEH
Chip Enable High to Output Enable Low
0
ns
tEHWH
tWEH
Chip Enable High to Write Enable High
0
ns
tWHDX
tDH
Write Enable High to Input Transition
0
ns
tEHDX
tDH
Chip Enable High to Input Transition
0
ns
tWHWL
tWPH
Write Enable High to Write Enable Low
50
tWLWH
tWP
Write Enable Low to Write Enable High
50
ns
tWLQ5H
tBLC
Time-out after last byte write (M28C64)
100
µs
Time-out after last byte write (M28C64-A)
20
µs
tQ5HQ5X
tWC
tWHRL
tDB
Write Enable High to Ready/Busy Low
tEHRL
tDB
Chip Enable High to Ready/Busy Low
tDVWH
tDS
Data Valid before Write Enable High
50
ns
tDVEH
tDS
Data Valid before Chip Enable High
50
ns
ns
Write Cycle Time (M28C64)
3
ms
Write Cycle Time (M28C64-A)
1
ms
Note 1
150
ns
Note 1
150
ns
Note: 1. With a 3.3 kΩ pull-up resistor.
12/24
1000
M28C64
Table 10B. Write Mode AC Characteristics for M28C64 (5V range)
(TA = –40 to 125 °C; VCC = 4.5 to 5.5 V)
M28C64
Symbol
Alt.
Parameter
Test Condit ion
Unit
Min
Max
tAVWL
tAS
Address Valid to Write Enable Low
E = VIL, G = VIH
0
ns
tAVEL
tAS
Address Valid to Chip Enable Low
G = VIH, W = VIL
0
ns
tELWL
tCES
Chip Enable Low to Write Enable Low
G = VIH
0
ns
tGHWL
tOES
Output Enable High to Write Enable Low
E = VIL
0
ns
tGHEL
tOES
Output Enable High to Chip Enable Low
W = VIL
0
ns
tWLEL
tWES
Write Enable Low to Chip Enable Low
G = VIH
0
ns
tWLAX
tAH
Write Enable Low to Address Transition
75
ns
tELAX
tAH
Chip Enable Low to Address Transition
75
ns
tWLDV
tDV
Write Enable Low to Input Valid
E = VIL, G = VIH
1
µs
tELDV
tDV
Chip Enable Low to Input Valid
G = VIH, W = VIL
1
µs
tELEH
tWP
Chip Enable Low to Chip Enable High
50
ns
tWHEH
tCEH
Write Enable High to Chip Enable High
0
ns
tWHGL
tOEH
Write Enable High to Output Enable Low
0
ns
tEHGL
tOEH
Chip Enable High to Output Enable Low
0
ns
tEHWH
tWEH
Chip Enable High to Write Enable High
0
ns
tWHDX
tDH
Write Enable High to Input Transition
0
ns
tEHDX
tDH
Chip Enable High to Input Transition
0
ns
tWHWL
tWPH
Write Enable High to Write Enable Low
50
tWLWH
tWP
Write Enable Low to Write Enable High
50
ns
tWLQ5H
tBLC
Time-out after last byte write (M28C64)
100
µs
Time-out after last byte write (M28C64-A)
20
µs
tQ5HQ5X
tWC
tWHRL
tDB
Write Enable High to Ready/Busy Low
tEHRL
tDB
Chip Enable High to Ready/Busy Low
tDVWH
tDS
Data Valid before Write Enable High
50
ns
tDVEH
tDS
Data Valid before Chip Enable High
50
ns
1000
ns
Write Cycle Time (M28C64)
3
ms
Write Cycle Time (M28C64-A)
1
ms
Note 1
150
ns
Note 1
150
ns
13/24
M28C64
Table 10C. Write Mode AC Characteristics for M28C64-xxW (3V range)
(TA = 0 to 70 °C or –40 to 85 °C; VCC = 2.7 to 3.6 V)
M28C64-xxW
Symbol
Alt.
Parameter
Test Condit ion
Unit
Min
Max
tAVWL
tAS
Address Valid to Write Enable Low
E = VIL, G = VIH
0
ns
tAVEL
tAS
Address Valid to Chip Enable Low
G = VIH, W = VIL
0
ns
tELWL
tCES
Chip Enable Low to Write Enable Low
G = VIH
0
ns
tGHWL
tOES
Output Enable High to Write Enable Low
E = VIL
0
ns
tGHEL
tOES
Output Enable High to Chip Enable Low
W = VIL
0
ns
tWLEL
tWES
Write Enable Low to Chip Enable Low
G = VIH
0
ns
tWLAX
tAH
Write Enable Low to Address Transition
100
ns
tELAX
tAH
Chip Enable Low to Address Transition
100
ns
tWLDV
tDV
Write Enable Low to Input Valid
E = VIL, G = VIH
1
µs
tELDV
tDV
Chip Enable Low to Input Valid
G = VIH, W = VIL
1
µs
tELEH
tWP
Chip Enable Low to Chip Enable High
100
1000
ns
tWHEH
tCEH
Write Enable High to Chip Enable High
0
ns
tWHGL
tOEH
Write Enable High to Output Enable Low
0
ns
tEHGL
tOEH
Chip Enable High to Output Enable Low
0
ns
tEHWH
tWEH
Chip Enable High to Write Enable High
0
ns
tWHDX
tDH
Write Enable High to Input Transition
0
ns
tEHDX
tDH
Chip Enable High to Input Transition
0
ns
tWHWL
tWPH
Write Enable High to Write Enable Low
50
tWLWH
tWP
Write Enable Low to Write Enable High
100
ns
tWLQ5H
tBLC
Time-out after the last byte write
100
µs
tQ5HQ5X
tWC
Write Cycle Time
tWHRL
tDB
Write Enable High to Ready/Busy Low
tEHRL
tDB
Chip Enable High to Ready/Busy Low
tDVWH
tDS
Data Valid before Write Enable High
50
ns
tDVEH
tDS
Data Valid before Chip Enable High
50
ns
Note: 1. With a 3.3 kΩ pull-up resistor.
14/24
1000
ns
5
ms
Note 1
150
ns
Note 1
150
ns
M28C64
Figure 11. Write Mode AC Waveforms (Write Enable, W, controlled)
A0-A12
VALID
tAVWL
tWLAX
E
tELWL
tWHEH
G
tGHWL
tWLWH
tWHGL
W
tWLDV
tWHWL
DATA IN
DQ0-DQ7
tDVWH
tWHDX
RB
tWHRL
AI01126
Figure 12. Write Mode AC Waveforms (Chip Enable, E, controlled)
A0-A12
VALID
tAVEL
tELAX
E
tGHEL
tELEH
G
tWLEL
tEHGL
W
tELDV
DQ0-DQ7
tEHWH
DATA IN
tDVEH
tEHDX
RB
tEHRL
AI00751
15/24
M28C64
Figure 13. Page Write Mode AC Waveforms (Write Enable, W, controlled)
A0-A12
Addr 0
Addr 1
Addr 2
Addr n
E
G
tWHWL
W
tWLWH
Byte 0
DQ0-DQ7 (in)
Byte 1
Byte 2
Byte n
DQ5 (out)
tWHRL
tWLQ5H
tQ5HQ5X
RB
AI00752D
Figure 14. Software Protected Write Cycle Waveforms
G
E
tWLWH
tWHWL
W
tAVEL
tWLAX
A0-A5
Byte Address
tWHDX
A6-A12
1555h
0AAAh
1555h
Page Address
tDVWH
DQ0-DQ7
AAh
55h
A0h
Byte 0
Byte 62
Byte 63
AI01358B
Note: 1. A12 to A6 must specify the same page address during each high-to-low transition of W (or E). G must be high only when W and E
are both low.
16/24
M28C64
Figure 15. Data Polling Sequence Waveforms
A0-A12
Address of the last byte of the Page Write instruction
E
G
W
DQ7
DQ7
LAST WRITE
DQ7
DQ7
DQ7
INTERNAL WRITE SEQUENCE
DQ7
READY
AI00753C
Figure 16. Toggle Bit Sequence Waveforms
A0-A12
E
G
W
DQ6
(1)
LAST WRITE
TOGGLE
INTERNAL WRITE SEQUENCE
READY
AI00754D
Note: 1. The Toggle Bit is first set to ‘0’.
17/24
M28C64
Table 11. Ordering Information Scheme
Example:
M28C64
–
A
12
BS
6
T
Write Time
blank
tWC = 3 ms at 4.5V to 5.5V;
tWC = 5 ms at 2.7V to 3.6V
A1
tWC = 1 ms at 4.5V to 5.5V
Option
T
Speed
Tape and Reel Packing
Temperature Range
90 ns
1
0 °C to 70 °C
12
120 ns
6
–40 °C to 85 °C
15
150 ns
3
–40 °C to 125 °C5
20 3
200 ns
25 3
250 ns
30 3
300 ns
90
2
Operating Voltage
Package
BS
PDIP28
KA
PLCC32
blank 4.5 V to 5.5 V
MS
SO28 (300 mil width)
W4
NS
TSOP28 (8 x 13.4 mm)
Note: 1.
2.
3.
4.
5.
2.7 V to 3.6 V
Available only with 120 ns speed (-12), 5V operating range (-blank), and -40 to 85 °C temperature range (-6).
Available for the M28C64 only.
Available for the 3V range (-xxW) only.
Not available for the 1 ms write time option (-A).
Available only for the “M28C64 - 12 MS 3” (5V range, SO28 package)
ORDERING INFORMATION
Devices are shipped from the factory with the
memory content set at all ‘1’s (FFh).
The notation used for the device number is as
shown in Table 11. For a list of available options
(speed, package, etc.) or for further information on
any aspect of this device, please contact your
nearest ST Sales Office.
18/24
M28C64
Table 12. PDIP28 - 28 pin Plastic DIP, 600 mils width
mm
inches
Symb.
Typ.
Min.
Max.
A
3.94
A1
Min.
Max.
5.08
0.155
0.200
0.38
1.78
0.015
0.070
A2
3.56
4.06
0.140
0.160
B
0.38
0.56
0.015
0.021
B1
1.14
1.78
0.045
0.070
C
0.20
0.30
0.008
0.012
D
34.70
37.34
1.366
1.470
E
14.80
16.26
0.583
0.640
E1
12.50
13.97
0.492
0.550
–
–
–
–
eA
15.20
17.78
0.598
0.700
L
3.05
3.82
0.120
0.150
S
1.02
2.29
0.040
0.090
α
0°
15°
0°
15°
N
28
e1
2.54
Typ.
0.100
28
Figure 17. PDIP28 (BS)
A2
A1
B1
B
A
L
e1
α
eA
D2
C
eB
D
S
N
E1
E
1
PDIP
Note: 1. Drawing is not to scale.
19/24
M28C64
Table 13. PLCC32 - 32 lead Plastic Leaded Chip Carrier, rectangular
mm
Symbol
Typ.
inches
Min.
Max.
A
2.54
A1
Typ.
Min.
Max.
3.56
0.100
0.140
1.52
2.41
0.060
0.095
A2
–
0.38
–
0.015
B
0.33
0.53
0.013
0.021
B1
0.66
0.81
0.026
0.032
D
12.32
12.57
0.485
0.495
D1
11.35
11.56
0.447
0.455
D2
9.91
10.92
0.390
0.430
E
14.86
15.11
0.585
0.595
E1
13.89
14.10
0.547
0.555
E2
12.45
13.46
0.490
0.530
–
–
–
–
0.00
0.25
0.000
0.010
–
–
–
–
e
1.27
F
R
0.89
0.050
0.035
N
32
32
Nd
7
7
Ne
9
9
CP
0.10
0.004
Figure 18. PLCC (KA)
D
D1
A1
A2
1 N
B1
E1 E
Ne
e
D2/E2
F
B
0.51 (.020)
1.14 (.045)
A
Nd
R
PLCC
Note: 1. Drawing is not to scale.
20/24
CP
M28C64
Table 14. SO28 - 28 lead Plastic Small Outline, 300 mils body width
mm
inches
Symb.
Typ.
Min.
Max.
A
2.46
A1
Min.
Max.
2.64
0.097
0.104
0.13
0.29
0.005
0.011
A2
2.29
2.39
0.090
0.094
B
0.35
0.48
0.014
0.019
C
0.23
0.32
0.009
0.013
D
17.81
18.06
0.701
0.711
E
7.42
7.59
0.292
0.299
–
–
–
–
H
10.16
10.41
0.400
0.410
L
0.61
1.02
0.024
0.040
α
0°
8°
0°
8°
N
28
e
1.27
Typ.
0.050
28
CP
0.10
0.004
Figure 19. SO28 wide (MS)
A2
A
C
B
CP
e
D
N
E
H
1
A1
α
L
SO-b
Note: 1. Drawing is not to scale.
21/24
M28C64
Table 15. TSOP28 - 28 lead Plastic Thin Small Outline, 8 x 13.4 mm
mm
inches
Symb.
Typ.
Min.
Max.
Typ.
Min.
A
1.25
0.049
A1
0.20
0.008
A2
0.95
1.15
0.037
0.045
B
0.17
0.27
0.007
0.011
C
0.10
0.21
0.004
0.008
D
13.20
13.60
0.520
0.535
D1
11.70
11.90
0.461
0.469
E
7.90
8.10
0.311
0.319
–
–
–
–
L
0.50
0.70
0.020
0.028
α
0°
5°
0°
5°
N
28
e
0.55
0.022
28
CP
0.10
0.004
Figure 20. TSOP28 (NS)
A2
1
N
e
E
B
N/2
D1
A
CP
D
DIE
C
TSOP-a
Note: 1. Drawing is not to scale.
22/24
Max.
A1
α
L
M28C64
Table 16. Revision History
Date
Description of Revision
31-Mar-2000
–40 to 125°C temperature range added to timing and characteristics tables, and order info
19-Jun-2000
Paragraph on behaviour, following an out-of-bounds page write operation, corrected
23/24
M28C64
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by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
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authorized for use as critical components in life support devices or systems without express writt en approval of STMicroelectronics.
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24/24