CXA1166K
8-bit 250 MSPS Flash A/D Converter
Description
The CXA1166K is an 8-bit ultrahigh-speed flash
A/D converter IC capable of digitizing analog signals
at a maximum rate of 250 MSPS. The digital I/O
level of this A/D converter is compatible with the
ECL 100K/10KH/10K.
This IC is pin-compatible with the conventional
CXA1076AK/CXA1176K/CXA1176AK,
and
can
replace the conventional models easily. Compared
with the conventional models, the CXA1166K has a
greatly improved performance because of the new
circuit design and carefully considered layout.
Features
• Differential linearity error: ±0.5 LSB or less
• Integral linearity error: ±0.5 LSB or less
• Built-in integral linearity compensation circuit
• Ultrahigh-speed operation with maximum conversion rate of 250 MSPS
• Low input capacitance: 18pF
• Wide analog input bandwidth: 250MHz (full-scale
input, standard)
• Single power supply: –5.2V
• Low power consumption: 1.4W (Typ.)
• Low error rate
• Good temperature characteristics
• Capable of driving 50Ω loads
68 pin LCC (Ceramic)
Structure
Bipolar silicon monolithic IC
Applications
• Digital oscilloscopes
• Other apparatus requiring ultrahigh-speed A/D
conversion
AGND
VIN1
VIN1
AGND
VRM
AGND
VIN2
VIN2
AGND
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
AVEE
Pin Configuration (Top View)
Pins without name are NC pins (not connected internally).
AGND
AVEE
VRT
VRTS
AVEE
AVEE
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
AGND
AVEE
VRB
VRBS
AVEE
AVEE
CLK
CLK
MINV
D7
D7
D6
D6
DVEE
D2
D2
D3
D3
DGND2
DGND2
DGND1
D4
D4
D5
D5
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
LINV
OR
OR
D0
D0
D1
D1
DVEE
61
62
63
64
65
66
67
68
1
2
3
4
5
6
7
8
9
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E90406-ST
CXA1166K
Absolute Maximum Ratings (Ta = 25°C)
• Supply voltage
AVEE, DVEE
• Analog input voltage
VIN
• Reference input voltage
VRT, VRB, VRM
| VRT – VRB |
• Digital input voltage
MINV, LINV, CLK, CLK
| CLK – CLK |
• VRM pin input current
IVRM
• Digital output current
ID0 to ID7, IOR, ID0 to ID7, IOR
• Storage temperature
Tstg
Operating Conditions
• Supply voltage
• Reference input voltage
• Analog input voltage
• Operating temperature
AVEE, DVEE
AVEE – DVEE
AGND – DGND
VRT
VRB
VIN
Tc
Min.
–5.5
–0.05
–0.05
–0.1
–2.2
VRB
–20
–2–
–7 to +0.5
–2.7 to +0.5
–2.7 to +0.5
2.5
–4 to +0.5
2.7
–3 to +3
–30 to 0
–65 to +150
Typ.
–5.2
0
0
0
–2.0
Max.
–4.95
0.05
0.05
0.1
–1.8
VRT
100
V
V
V
V
V
V
mA
mA
°C
Unit
V
V
V
V
V
°C
CXA1166K
Block Diagram
MINV
33
r1
VRT 64
r/2
Comparator
r2
VRTS 65
r
r
0
2 OR
1
3 OR
r
VIN1 54
r
2
•
•
•
63
31 D7 (MSB)
32 D7
29 D6
64
55
30 D6
r
r3
r
VRM 52
r
r
r
127
128
22 D5
OUTPUT
r
21 D5
ENCODE LOGIC
r
65
•
•
•
126
r
r4
VRBS 39
r5
r
r/2
13 D2
129
•
•
•
191
6 D1
7 D1
4 D0 (LSB)
5 D0
193
•
•
•
254
255
VRB 40
CLK 35
CLK 34
14 D3
12 D2
r
50
20 D4
15 D3
192
VIN2 49
19 D4
CLOCK
DRIVER
1
LINV
–3–
CXA1166K
Pin Description
Pin
No.
Symbol
I/O
Standard
voltage level
Equivalent circuit
Description
DGND1
Polarity selection other than
MSB and overrange.
(Refer to the table of input
voltage vs. Digital output)
Low level is maintained with
left open.
18
1
LINV
I
ECL
r
LINV
r
1
r
or
33
MINV
33
MINV
I
–1.3V
DVEE
ECL
r
8
28
64
VRT
I
0V
VRT 64
Reference voltage
(Top) (0V typ.)
r1
r2
Polarity selection for MSB
(Refer to the table of input
voltage vs. Digital output)
Low level is maintained with
left open.
VRTS 65
r⁄2
65
VRTS
O
0V
52
VRM
I
VRB/2
39
VRBS
O
–2V
Reference voltage sense
(Top)
r
r3
r
VRM 25
To
Comparator
Reference voltage sense
(Bottom)
r
r4
Reference voltage mid-point.
Can be used for linearity
compensation.
r ⁄2
VRBS 39
40
VRB
I
–2V
r5
43, 48, 51, 53, 56, 61
AGND
VIN1
54
55
54
VIN1
I
49
50
VIN2
35
CLK
Reference voltage (Bottom)
VRB 40
VRTS
to
VRBS
55
To Comp
0 to 127
49
128 to 255
50
VIN2
Analog input.
Pins 49, 50 and Pins 54, 55
should be connected
externally.
DGND1
I
ECL
CLK input
18
r
r
r
CLK
35
r
CLK
34
34
CLK
I
ECL
DVEE
8
r
r
28
–4–
Complementary CLK input.
ECL threshold potential
(–1.3V) is maintained with
left open.
The complementary input is
recommended for stable
operation at high speed
though the operation only
with the CLK input is
possible when the CLK
input is left open.
CXA1166K
Pin
No.
Symbol
I/O
Standard
voltage level
Equivalent circuit
Description
MSB and complementary
MSB output
31
32
D7
D7
O
29
30
D6
D6
O
21
22
D5
D5
O
17
19
20
D4
D4
O
Di
14
15
D3
D3
O
Di
12
13
D2
D2
O
6
7
D1
D1
O
4
5
D0
D0
O
LSB and complementary
LSB output
O
Overrange output;
Low level for overrange.
Overrange complementary
output;
High level for overrange.
2
3
OR
OR
DGND2
16
D1 to D6: Output
D1 to D6: Complementary
output
ECL
8
DVEE
28
AGND
37, 38,
42, 58,
AVEE∗
62, 66,
67
–5.2V
43, 48,
51, 53, AGND∗
56, 61
0V
61 48 53
DGND1
43 51 56
18
Internal
Analog
Circuit
8
28
DVEE∗
18
DGND1
0V
62 38 66
16
17
DGND2∗
0V
AVEE
DGND2
16 17
Analog ground.
Separated from DGND.
Internal
Digital
Circuit
–5.2V
4 to 6Ω
42 37 58
67
8 28
DVEE
Analog supply.
Internally connected with
DVEE (resistance: 4 to 6Ω).
Di
Di
Digital supply.
Internally connected with
AVEE (resistance: 4 to 6Ω).
Digital ground
Digital ground for output
drive
41, 44,
45, 46,
47, 57, NC
59, 60,
63
—
No connected.
It is recommended to connect
these pins to AGND.
9, 10,
11, 23,
24, 25, NC
26, 27,
36, 68
—
No connected.
It is recommended to connect
these pins to DGND.
∗ For stable operation, all of these pins must be connected on the corresponding PCB pattern.
–5–
CXA1166K
Electrical Characteristics
Item
(AVEE = DVEE = –5.2V, VRT, VRTS = 0V, VRB, VRBS = –2V, Ta = 25°C)
Symbol
Condition
Min.
Resolution
EIL
EDL
Analog input
Analog input capacitance
Analog input resistance
Input bias current
CIN
RIN
IIN
Reference inputs
Reference resistance
Residual resistance∗1 r1
r2
r3
r4
r5
RREF
r1
r2
r3
r4
r5
VIH
VIL
IIH
IIL
Fc
Taj
Tds
Tdo
TPW1
TPW0
Digital output
Logic High level
Logic Low level
Output rise time
Output fall time
VOH
VOL
Tr
Tf
Dynamic characteristics
Input bandwidth
SNR
SNR
Error rate
Power supply
Supply current
Power consumption∗3
∗1 See Block Diagram.
∗2 TPS: Times Per Sample
2
∗3 Pd = IEE • VEE + (VRT – VRB)
RREF
VIN = –1V + 0.07Vrms
VIN = –1V
VIN = –1V
50
20
83
0.1
300
0.5
300
0.1
±0.5
±0.5
LSB
LSB
450
pF
kΩ
µA
182
2.0
700
5.0
700
2.0
Ω
Ω
Ω
Ω
Ω
Ω
–1.50
70
50
V
V
µA
µA
pF
9
1.4
2.5
2.4
3.2
MSPS
ps
ns
ns
ns
ns
0.6
0.6
–1.60
1.5
1.5
18
120
125
0.6
500
2.0
500
0.6
–1.13
VIH = –0.8V
VIL = –1.6V
0
–50
250
RL = 50Ω to –2V
}T
PW1
+ TPW0 = 4.0ns
RL = 50Ω to –2V
RL = 50Ω to –2V
RL = 50Ω to –2V
RL = 50Ω to –2V
VIN=2Vp-p
Input = 1kHz, FS
Clock = 250MHz
Input = 62.499MHz, FS
Clock = 250MHz
Input = 49.999MHz, FS
Error > 16LSB
Clock = 200MHz
Input = 62.499MHz, FS
Error > 16LSB
Clock = 250MHz
NTSC 40IRE mod.
ramp, Fc = 250MSPS
{
{
0.4
1.8
1.8
1.8
–1.00
46
MHz
dB
30
35
dB
10–8
–360
–6–
10–9
TPS∗2
10–6
TPS∗2
1.0
0.5
}
IEE
Pd
V
V
ns
ns
200
44
{
{
DG
DP
Unit
bits
4
Switching characteristics
Maximum conversion rate
Aperture jitter
Sampling delay
Output delay
Clock High pulse width
Clock Low pulse width
Differential gain error
Differential phase error
Max.
8
DC characteristics
Integral linearity error
Differential linearity error
Digital inputs
Logic High level
Logic Low level
Logic High current
Logic Low current
Input capacitance
Typ.
–270
1.4
%
deg
1.9
mA
W
CXA1166K
Input Voltage vs. Digital Output
VIN∗
MINV
LINV
Step
1
1
OR D7
1
0
D0 OR D7
0
0
D0 OR D7
D0 OR D7
D0
0
0 0 0 …… 0 0
0
1 0 0 …… 0 0
0
0 1 1 …… 1 1
0
1 1 1 …… 1 1
0
1
1
1
1
1
1
1
:
:
1
1
1
1
:
:
1
1
0 1 1 …… 1 1
0 1 1 …… 1 0
:
:
0 0 0 …… 0 0
1 1 1 …… 1 1
:
:
1 0 0 …… 0 1
1 0 0 …… 0 0
1
1
1
1
:
:
1
1
1 0 0 …… 0 0
1 0 0 …… 0 1
:
:
1 1 1 …… 1 1
0 0 0 …… 0 0
:
:
0 1 1 …… 1 0
0 1 1 …… 1 1
1
1
127
128
0 0 0 …… 0 0
0 0 0 …… 0 1
:
:
0 1 1 …… 1 1
1 0 0 …… 0 0
:
:
1 1 1 …… 1 0
1 1 1 …… 1 1
1
1
:
:
1
1
1 1 1 …… 1 1
1 1 1 …… 1 0
:
:
1 0 0 …… 0 0
0 1 1 …… 1 1
:
:
0 0 0 …… 0 1
0 0 0 …… 0 0
1
1 1 1 …… 1 1
1
0 1 1 …… 1 1
1
1 0 0 …… 0 0
1
0 0 0 …… 0 0
0V
–1V
0
1
254
255
–2V
∗ VRT = VRTS = 0V, VRM = –1V or Open, VRB = VRBS = –2V
Timing Diagram
Tds
N
N+1
Analog input
N+2
Tpw1
Tpw0
CLK
CLK
N–1
Digital output
20%
Td
80%
Tr
–7–
N
80%
N+1
20%
Tf
CXA1166K
Electrical Characteristics Measurement Circuit
Integral Linearity Error Measurement Circuit
Differential Linearity Error Measurement Circuit
+V
S2
S1
S1:ON when A<B
S2: ON when A>B
–V
A<B A>B
Comparator
VIN
DUT
CXA1166K
8
A8
to
A1
B8
to
B1
A0
B0
“0”
8
Buffer
“1 ”
DVM
000•••00
to
111•••10
Controller
Sampling Delay Measurement circuit
Aperture Jitter Measurement circuit
Aperture Jitter Measurement Method
0V
VIN
–1V
–2V
60MHz
Amp
CLK
OSC1
φ:Variable
VIN
fr
8
CXA1166K
∆υ
∆t
Logic
Analizer
VIN
CLK
1024
samples
OSC2
CLK
ECL
Buffer
60MHz
t
129
128
127
126
125
σ (LSB)
Sampling timing fluctuation
( = aperture jitter)
When the distribution of the output codes is σ (unit: LSB) If
the maximum slew rate point is sampled with the clock signal
having the same frequency as that of the analog input signal,
Aperture jitter (Taj) is defined as follows:
Taj = σ/
–8–
256
∆υ
= σ/ (
× 2πf )
∆t
2
CXA1166K
Error Rate Measurement Circuit
Vin
Signal
Source
fCLK – 1kHz
4
2Vp – p Sine Wave
CXA1166K
CLK
8
A
ECL
Latch
B
CLK
Comparator
A<B
Pulse
Counter
ECL
Latch
+
DATA 16
Signal
Source
1⁄16
fCLK
Differential Gain Error Measurement Circuit
Differential Phase Error Measurement Circuit
(CX20202A – 1)
NTSC
Signal
Source
DUT
CXA1166K
Amp
CLK
8
ECL
Latch
8
10bit
D⁄A
CLK
SG (CW)
Vector
Scope
Decimator
50
VBB
Power Supply Current Measurement Circuit
Analog Input Bias Current Measurement Circuit
IIN
A
60
61
– 1V
44
43
– 2V
1
9
CXA1166K
27
26
10
A IEE
– 5.2V
–9–
CXA1166K
Notes on Operation
• The CXA1166K is an ultra-high speed A/D converter featuring ECL level of input/output for the logic block. In
order to derive the most from its high-speed performance, the characteristic impedance should be matched
properly.
• The outputs are designed to drive a load terminated to –2V at 50Ω. An excellent transmission characteristic
can be yielded by designing the printed circuit board with a 50Ω characteristic impedance.
Yielding its top performance is difficult on the printed circuit board with a characteristic impedance of 100Ω or
more.
• The power supply and ground pattern greatly affect the characteristics of the converter. The higher the
frequency, the more important these connections become. The general precautions are as follows.
– Make the pattern of the power supply and ground as wide as possible. Using a ground plane inner layer by
using a multilayer printed circuit board is recommended.
– lsolate the AGND, DGND pins and the AVEE, DVEE from one another on the pattern in order to safeguard
against interaction. Connect the AGND and DGND pins at one place using a ferrite-bead filter to prevent
DC offset. The same processing is requited for the AVEE and DVEE pins.
• When mounting the A/D converter on the socket, use the one of shortest leads. The QFP socket, the type
name IC61-0684-048, manufactured by YAMAICHI ELECTRONICS CO., LTD. is recommended.
• The VIN analog input pins have somewhat large input capacitance (approximately 18pF) for high-frequency
circuits. In order to drive them with an excellent frequency response, it is necessary to safeguard against any
deterioration in performance resulting from parasitic capacitance and parasitic inductance by using a highcapacity drive circuit, keeping the wiring as short as possible, and using chip parts as resistors and
capacitors, for instance. The drive circuit shown in the Application Circuit has a virtually flat frequency
response up to approximately 170MHz. C89, R11 and C15 have been inserted mainly to expand the
bandwidth, while R10 has been inserted mainly to suppress operational amplifier oscillation and block
peaking of the frequency response. Since the optimal values of these elements differ depending on the
printed circuit board pattern and mounting condition of the A/D converter socket used, they must be
determined on the basis of experimentation.
• Connect all four VIN pins directly and as short as possible. Unlike the CXA1176, it is not necessary to insert
resistance of several ohms for each pin.
• The voltage at the VRT and VRB reference voltage pins and the reference voltage inside these pins differ
slightly due to residual resistance. VRTS and VRBS are provided to detect the reference voltage inside the pins.
The overrange reference voltage is 1/2 LSB down from VRTS; the lowest input voltage at which the output
code changes is 1/2 LSB up from VRBS.
• Provide adequate by-pass capacitors for VRT and VRB to protect them from high-frequency noise. Normally,
VRT is connected to AGND of an inner layer of the printed circuit board. Using a chip capacitor (approximately
0.1µF), make the by-pass from VRB to AGND as short as possible. C22 (1µF), in the Application Circuit is for
suppressing the oscillation of the reference voltage generation circuit.
– 10 –
CXA1166K
• Unlike the CXA1176, VRTS and VRBS are connected to the reference resistors via resistors of approximately
500Ω. Since these resistors may be eliminated in the future improved versions of this converter, use a
reference voltage generation circuit which is adaptable to their elimination. The reference voltage generation
circuit (the section composed of IC12_2, etc.) in the Application Circuit is recommended.
• Although VRM is provided to compensate for the integral linearity error, there is no need for such
compensation. It is recommended that it is kept open.
• OR and OR are output pins for indicating that the input is over range. They are not inverted by MINV or LINV.
• Noise in MINV and LINV results in misoperation, the cause of which is extremely difficult to track down. Keep
these pins open in cases where low level setting voltage alone is sufficient. When high level voltage input is
required, provide the shortest possible by-pass from them to DGND using chip capacitors (approximately
0.1µF). Input voltages of –0.5V to –1.0V for high level and –1.6V to –2.5V for low level are recommend. Do
not make the direct connection to DGND when high level voltage is input.
• Inputting differential signals is recommended for the CLK and CLK clock input pins. Although operation is
possible by driving only the CLK pin, doing so involves the risk that the characteristics may become unstable
near the maximum speed. This is because the internal operation of the A/D converter depends on both clock
rise and fall.
• When the CLK pin is not used, by-pass it to DGND using a capacitor (approximately 0.1µF). At this time,
approximately –1.3V voltage will be generated at this pin. However, the driving capacity is too weak for this to
be used as the VBB threshold voltage. It cannot drive even one ECL input load.
• This converter is designed to be used at the clock duty cycle of 50%. The deviation from this condition will
subtly affect the performance of the A/D converter but the degree of the affection is not so great as to require
adjustment. The “Error rate vs. Clock duty cycle characteristics” graph shows an example of these changes
in the converter’s performance.
• Increasing chip temperature will cause the supply current and also the error rate to rise. Adding to these
reasons, in order to prolong the converter’s service life, provide an adequate means of cooling. See the
“Maximum conversion frequency vs. Temperature characteristics” and “Supply current vs. Temperature
characteristics” graphs. The reference data for thermal resistance is shown in the “Thermal resistance of the
converter mounted on a board” graph. Note that the actual thermal resistance will differ greatly depending on
the mounting conditions.
• Since the CXA1166K is a high-speed IC, take adequate measures to prevent electrostatic breakdown. For
further details on these measures, refer to “Precautions for IC Application” in Sony’s Data book.
• Sony’s SPECL series is used as the logic ICs in the Application Circuit to investigate the maximum
performance of the CXA1166K. For normal applications, lower speed logic ICs can be used according to the
applied frequency.
– 11 –
CXA1166K
Example of Representative Characteristics
VIN pin input capacitance vs.
Voltage characteristics
Thermal resistance at on-board condition
25
Socket for YAMAICHI
ELECTRONICS IC61-0684-048
Socket for AMP173061-5
(without heat sink)
Socket for AMP173257-3
(with heat sink)
40
CIN — Input capacitance [pF]
θ ja — Thermal resistance [°C/W]
50
30
0
1.0
2.0
20
15
10
3.0
–2
Air velocity [m/s]
–1
–0.5
0
VIN — Input voltage [V]
VIN pin input resistance vs.
Voltage characteristics
VIN pin input current vs.
Voltage characteristics
200
150
125
IIN [µA]
Analog input resistance [kΩ]
–1.5
100
100
0
–2.0
–1.5
–1.0
–0.5
VIN — Input voltage [V]
–2.0
–1.5
–1.0
–0.5
0
VIN — Input voltage [V]
– 12 –
0
CXA1166K
VIN pin input current vs. Temperature characteristics
VIN — Input current [µA]
200
150
100
50
0
–50
0
50
100
150
Tc — Case temperature [°C]
Resistor string current vs. Temperature characteristics
–12
Resistor string current [mA]
–14
–16
–18
–20
–22
–24
–50
0
50
100
150
Tc — Case temperature [°C]
CLK open voltage vs. Temperature characteristics
–1.25
CLK open voltage [V]
–1.3
–1.35
–1.4
–1.45
–50
0
50
Tc — Case temperature [°C]
– 13 –
100
150
CXA1166K
VOH vs. Temperature characteristics
–0.7
VOH [V]
–0.8
–0.9
–1.0
–1.1
–50
50
0
100
150
Tc — Case temperature [°C]
VOL vs. Temperature characteristics
–1.7
VOL [V]
–1.8
–1.9
–2.0
–2.1
–50
50
0
100
Tc — Case temperature [°C]
SNR vs. Input frequency response characteristics
50
SNR [dB]
45
40
35
30
25
1
10
Input frequency [MHz]
– 14 –
100
150
CXA1166K
Harmonic distortion vs. Input frequency response characteristics
Clock frequency : 250MHz
–30
–40
–50
–60
–70
–80
0.1
10
1
100
Input frequency [MHz]
Maximum conversion rate vs.
Temperature characteristics
300
250
CLK [MHz]
Harmonic distortion [dB]
2nd harmonic distortion
3rd harmonic distortion
200
150
Error rate = 10–8TPS
Input frequency = CLK frequency/4 – 1kHz
16LSB or more error
–25
25
75
125
Ta — Ambient temperature [°C]
– 15 –
1000
CXA1166K
Error rate vs. Conversion rate
Error rate vs. Clock duty cycle
Input frequency = CLK frequency/4–1kHz
16LSB or more error
Error rate [TPS]
10–7
10–8
10–8
10–9
Input frequency = 125MHz, full-scale
Clock frequency = 250MHz
16LSB or more error
10–10
250
200
300
10–9
CLK frequency [MHz]
25
30
35
40
45
50
55
CLK duty cycle [%]
Supply current vs. Temperature characteristics
–200
Supply current [mA]
Error rate [TPS]
10–7
–250
–300
–350
–50
0
50
Tc — Case temperature [°C]
– 16 –
100
150
60
65
70
CXA1166K
8-bit, 250 MSPS ADC Evaluation Board
The CXA1166K PCB is a tool for customers to evaluate the performance of the CXA1166K (8-bit, 250MHz,
high-speed A/D converter). In addition to indispensable features such as the reference voltage generator, this
tool equips the input voltage offset generator, clock decimator, output date latches, 10-bit high-speed DAC,
and 20-pin cable connector for digital outputs. This evaluation board is designed to facilitate evaluation.
Features
• Resolution: 8 bits
• Maximum conversion rate: 250 MSPS
• Supply voltage: –5.2V, –4.5V, –2.0V, +5.0V
• Clock level converter: Sine wave to ECL level signal
• Reference voltage adjustment circuit for A/D converter
• Built-in clock frequency decimation circuit: 1/1 to 1/128
Fig. 1. Block Diagram
VR2
(2k)
VRB
– 2V
VR1
(2k)
Vin
OFFSET
H
VR3
(2k)
SW4
VIN
CXA1166K
CLK
X
(– 2)
53
DIGITAL OUT
(CONNECTOR)
SW5
LINV MINV
VRB
J1
AMP.IN
L
8 (D7 to D0)
8 (D7 to D0)
DATA
8 (D7 to D0) LATCH
CLK
2 (CLK.CLK)
8 (D7 to D0)
SW2
DELAY
SW1
D/A OUT
D/A
CONVERTER
0.1µ
H
DECIMATOR
CLK
CLK
51
SW3
+ 5V (A)
– 5.2V (A)
INV
L
SW6
1/1 to 1/128
AGND
DGND
– 17 –
– 5.2V (D)
– 2V (D)
– 4.5V (D)
CXA1166K
Supply Current
Item
Min.
–5.2V
+5.0V
–4.5V
–2.0
Typ.
Max.
Unit
0.65
17
0.9
0.7
0.9
40
1.1
0.9
A
mA
A
A
Typ.
Max.
Unit
0
V
Ω
Analog Input (AMP. IN)
Item
Min.
Input voltage
(AMP.IN) ∗
Input impedance
–2.0
50
(∗ Adjustable with VR1)
Clock input (CLK)
Item
Min.
Input voltage
(Peak to Peak)
Input impedance
Typ.
Max.
Unit
2.0
Vp-p
50
Ω
Digital output (Digital OUT)
ECL level
Output Code Table
VIN
1: ECL High level, 0: ECL Low level
MINV (SW5)
LINV (SW4)
0
0
0
1
1
0
1
1
0V
:
:
:
:
:
:
:
:
–2V
1 1 1 …… 1 1
1 1 1 …… 1 0
:
:
1 0 0 …… 0 0
0 1 1 …… 1 1
:
:
0 0 0 …… 0 1
0 0 0 …… 0 0
1 0 0 …… 0 0
1 0 0 …… 0 1
:
:
1 1 1 …… 1 1
0 0 0 …… 0 0
:
:
0 1 1 …… 1 0
0 1 1 …… 1 1
0 1 1 …… 1 1
0 1 1 …… 1 0
:
:
0 0 0 …… 0 0
1 1 1 …… 1 1
:
:
1 0 0 …… 0 1
1 0 0 …… 0 0
0 0 0 …… 0 0
0 0 0 …… 0 1
:
:
0 1 1 …… 1 1
1 0 0 …… 0 0
:
:
1 1 1 …… 1 0
1 1 1 …… 1 1
– 18 –
CXA1166K
Fig. 2. Timing Diagram
N
A/D input pin
(AMP. IN)
Vin
N+2
N+1
PCB input pin
CLK
CLK
A/D clock
CLK
D7 to D0
A/D output
N –1
N
N –2
N –1
D7 to D0
PCB output pin
(For 1/1 decimation)
D7 to D0
N
Tdh
1.8ns
(Typ)
CLKN
PCB output pin
(For 1/1 decimation)
PCB output pin
(For 1/2 decimation)
CLK
D7 to D0
N –4
N –2
N
Tdh
1.8ns
(Typ)
CLKN
PCB output pin
(For 1/2 decimation)
CLK
Adjustment Methods and Notes on Operation
1) VIN Offset (VR1)
The volume to adjust the AMP. IN signal range (0V center assumed) with the A/D converter input range.
2) A/D Full Scale (VR2)
The volume to adjust A/D converter VRB voltage (–2V typ.).
3) Linearity (VR3)
The volume to adjust the VRM (linearity) voltage by shorting the J1.
– 19 –
CXA1166K
4) D/A Full Scale (VR4)
The volume to adjust the bottom of D/A output full scale voltage (–1V typ.)
5) SW1 and SW2
Selection switches to adjust the clock delay. These switches enable clock delay to be stepped to any one of
128 settings (binary code of “0000000” to “1111111”) through binary input. Approximately 163ps is delayed
per one step. Normal evaluation requires the binary code of “0000000” (all of OFF), so that these switches
are not mounted for shipment.
6) SW3 (Decimation)
The switch to select clock frequency decimation. Selection settings are as follows.
SW3
3
2
Decimation
ratio
1
L
L
L
1/1
L
L
H
1/2
L
H
L
1/4
L
H
H
1/8
H
L
L
1/16
H
L
H
1/32
H
H
L
1/64
H
H
H
1/128
∗ H = ECL High level ; L = ECL Low level
7) SW4
The switch for LINV High/Low.
8) SW5
The switch for MINV High/Low.
9) SW6 (D/A INV)
The switch for D/A converter output inversion.
– 20 –
CXA1166K
10) The waveform monitoring pins P6 through P39 are designed to make connection to GND easily in order to
reduce distortion when monitoring the waveform with an oscilloscope. As shown in the diagram below, the
distance between the measuring point and GND is 300mil, and each is equipped with a through hole of
1.2mm. When a Tektronix ground chip (part No. 013-1185-00) is mounted on the tip of a probe, the
signal – GND positions match.
φ1.2mm
GND
Monitoring point
Fig. 3.
11) D/A converter (IC9) input data (waveform monitoring pins P28 to P35) are the negative logic signals of the
decimated A/D converter outputs. Those are inverted again in the D/A converter so that the direction
(rise/fall) of reproduced waveform can agree with the A/D input signal's.
12) In order to maintain the accuracy of the reproduced waveform (waveform from A/D to D/A), set the
decimator such that the clock frequency of the D/A converter (IC9: CX20201A-1) is less than 100MHz.
13) The input bandwidth weighs with the design of this PCB analog input circuit. Therefore, the SNR (signal-tonoise ratio) should be less significant. The input circuit example to improve the SNR is shown in Fig.4. See
the measured data in Fig.s 6 to 8 for the SNR and the input circuit characteristics.
14) The part number of the digital output connector mounted on the PCB is KEL 8830E-020-170S. A
corresponding connector and cable assembly is JUNKOSHA KB0020MCG50B1.
– 21 –
CXA1166K
From offset circuit
5pF
560Ω
VIN2
VIN2
240Ω
2
AMP. IN
CLC409
3pF
30Ω
6
3
68Ω
120Ω
VIN1
VIN1
AGND
AGND
VRB (– 2V)
Fig. 4. Example of SNR Improvement Circuit
– 22 –
CLK
AMP. IN
21 22
∗ C4
0.1µ
C5
0.1µ
∗
– 4.5V DGND
(D)
10
IC5
CXB1103Q
R6
1.3k
8
1
R8
51
17
18
15
IC1_2
16
7
IC1_1
1
– 2V
(D)
8
2
R7
240
C9
0.1µ
4
8
Q1
2SA970
TL4558
IC12_2
7
2
3
6
∗C12
0.1µ
R11
10
GND
J1
16
21 RBIAS
∗
C17 19 DOUTP
0.01µ
20 CBIAS
IC3
CXB1159Q
12
13
14
15
26 27
11 10
31
∗ C24
0.1µ
30
12
IC2
CXB1136Q
30
R23 ∗C26
51 0.1µ
∗
C25
0.1µ
28 29
32
11 10
– 5.2V
(D) DGND
13
L1
FERRITE
BEAD
C27
0.1µ
∗
32
31
CIMN 1
Q0 2
Q1 3
Q2 4
Q3 5
Q4 6
Q5 7
Q6 8
Q7 9
F2 1
F3 2
F4 3
F5 4
C0 5
C1 6
C2 7
C3 8
C4 9
DGND
28 29
DGND
15 14
26 27
16
P2
AGND
– 2V GND – 4.5V DGND GND
(D)
(D)
R22
51
25 D0
24 D1
23 D2
22 D3
21 D4
20 D5
19 D6
18 D7
17 NC
25 DINPB
24 DINP
23 SW
22 MR
60 NC
IC6
CXA1166K
3
R28
51
5
ORN
R27
P11 51
4
4
∗
C70
0.1µ
∗C28
0.1µ
11
D4 19
D4N 20
D5 21
D5N 22
NC 23
NC 24
NC 26
NC 25
8
∗
C36
0.1µ
26
DGND
∗ C29
0.1µ
R26
51
25 DOA
24 DOB
23 DOC
22 DOD
21 DOE
20 DOF
19 DOG
18 DOH
17 MR
16
SW4 SW5
LINV MINV
DGND
15
27
14
NORM
INV
13
– 5.2V
(D)
P9
DGND
∗
C38
0.1µ
DGND
– 2V (D)
9
C37
1µ
NC 10
NC 11
D2 12
D2N 13
D3 14
D3N 15
DGND2 16
DGND2 17
DGND1 18
R14
51
R15
51
R16
51
R17
51
R18
51
R19
51
R20
51
∗C26
0.1µ
∗C35
0.1µ
7
R21
51
IC1_4
24 12
23
R25
51
∗C30
0.1µ
∗C32
0.1µ
– 2V GND
(D)
R24
51
5
6
3
IC1_3
DGND
– 2V
(D)
DGND
∗ C33
0.1µ
SW1
DELAY ADJ.
6
DGND
SW2
DELAY ADJ.
OR
P10
2
DGND
61 62 63 64 65 66 67 68 1
∗
C34
∗ C19
0.1µ
0.1µ
18 DOUTPB
17 CAP
59 NC
58 AVEE
57 NC
56 AGND
55 VIN1
54 VIN1
53 AGND
52 VRM
51 AGND
50 VIN2
49 VIN2
48 AGND
47 NC
46 NC
45 NC
C18
1µ
FERRITE
BEAD
R12
51
GND – 2V
(D)
L2
43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27
C22
1µ
∗C23
0.1µ
AGND AGND
44 NC
∗
C21
0.1µ
P4
AVEE
– 5.2V
– 5.2V AGND
(A)
VRT
P1
∗
C16
1000p
Linearity
∗C15
10p
GND
∗C14
0.1µ
– 5.2V AGND AGND
(A)
C13
1µ
R10
4
CLC404AJP 24
IC11
7
R9
560
C11
1µ
AGND
VR3
1k
+ 5.2V
(A) AGND AGND
AGND
C89
3P
C8
3.3µ
R8
1k
AGND – 5.2V
(A)
AGND AGND
∗C7
0.1µ
– 5.2V AGND
R4 (A)
22k
4
TL4558
IC12_1
∗ C1
0.1µ
∗ C2
0.1µ
– 4.5V DGND
(D)
∗ C3
0.1µ
21 22
10
9
9
IC1
CXB1103Q
∗: CHIP CAPACITOR
DGND
CXA1166K EVALUATION BOARD
AGND
R1
68
2
3
R2
11k
AGND
AGND
R5
240
5
NC
NC
6
CLK
LINV
Full Scale
P7
MINV
ORN
VR2
2k
P6
CLK CLKN
R13
51
D6N
D1
R3
510
∗
C39
0.1µ
D7
D0N
Offset
P5
VRBS
D7N
D0
IC13
TL431CP
DIN
D6
D1N
VR1
2k
DOUT
DINB
NC
MR
VCC
VCC
DGND
CN
VBB
VBB
GND
VBB
VEE
VEE
NC
NC
VEE
VCCA
VCCA
VCCA
VRB
C6
NC
CLKN
OR
DVEE
NC
DVEE
AVEE
AGND
AVEE
GND
VCC
DOUTB
VRBS
VRTS
VRT
C5
COUT
VREF
AVEE
F1
DVEE
30
31 32
∗C31
0.1µ
SW3
DECIMATION
– 4.5V DGND
(D)
DIA 1
DIB 2
DIC 3
DID 4
DIE 5
DIF 6
DIG 7
9
LEN1
DIH 8
GND
12 11 10
IC4
CXB1144Q
28 29
P8
– 5.2V
(D)
4
5
IC5_5
3
6
11
12
IC5_1
R53
51
R54
51
INV
20
19
18
17
SW6
CLK P36
C52
0.1µ
∗
D1
P14
P19
D3N
P23
D5N
DGND
CLKA
R57 R58
51 51
P15
D1N
DGND
22 VCCA
11 NC
14 CLK
13 CLKN
12 NC
5
IC5_4
8
7
AGND
DGND
6
– 5.2V
(A)
VR4
2k
R63
1k
∗ C43
0.1µ
– 5.2V
(D)
C54
1µ
DGND DGND
DGND
∗ C55
0.1µ
Q3 8
VCC 9
Q3M 7
– 2V DGND
(D)
4
Q2 12
Q2M 11
VCCA 10
∗ C57 ∗ C58 C59
0.1µ 0.1µ 1µ
∗ C53
0.1µ
DVEE 15
INV 16
DGND 17
AGND 18
NC 19
OUT 20
NC 21
NC 22
NC 23
NC 24
VREF 27
AGND 28
2
1
R60
51
∗ C49
0.1µ
5 D5
9 D9
3
R44
51
IC8
CXB1109Q
R42 R43
51 51
2
– 2V DGND
(D)
R41
51
1
24 MR
23 VBB
∗C42
0.1µ
– 2V DGND
(D)
6
13
NC 25
8 D8
5
14
21 VEE
IC9
CXA20201
4
Q3M 7
Q3 8
VCC 9
VCCA 10
Q2M 11
Q2 12
13
16 15
AVEE 26
7 D7
3
R37 R38 R39 R40
51 51 51 51
3 D3
6 D6
IC7
CXB1109Q
14
17
20 CB
R59
51
2
16 15
18
19 CA
CLKB
DGND
17
R33 R34 R35 R36
51 51 51 51
1
24 MR
23 VBB
22 VCCA
21 VEE
∗ C41
0.1µ
P39
18
20 CB
19 CA
∗C40
0.1µ
– 2V DGND
(D)
R29 R30 R31 R32
51 51 51 51
4 D4
2 D2
1 D1
10 LSB
IC5_3
14
13
16
15
IC5_2
C60
0.1µ
CLKN P37
NORM
INV
DGND
– 2V DGND
(D)
R65
51
R66
51
DGND
DGND
∗C51
0.1µ
∗C50
0.1µ
– 2V
(D)
D7 P28
D6 P29
D5 P30
D4 P31
P18
D3
P22
D5
∗C48 R55 R56
0.1µ 51 51
R45
51
R46
51
R47
51
R48
51
R49
51
R50
51
R51
51
R52
51
23
24
D3 P32
D2 P33
D0N
P13
– 2V DGND
(D)
D1 P34
D0 P35
P17
P16
D0
D7N
P27
R61
51
– 2V
(D) ∗
C46
0.1µ
– 4.5V
DGND
(D) ∗
C47
0.1µ
D2N
P21
P20
D2
D4N
D4
P12
D7
P26
R62 P38
51
– 2V
(D) ∗
C44
0.1µ
– 4.5V
DGND
(D) ∗
C45
0.1µ
D6N
P25
D6
P24
D2N
D3
AVEE
COUTN
D2
D3N
∗C10
0.1µ
QON
D1N
Q4N
– 5V
(A) AGND
QO
S1
S0
F0
C
QIN
VEE
VEE
VCCA
S2
VCCA
VCCA
VCC
VEE
D2
D3N
D1
D4
AVEE
S1
LEN2
NC
Q1
Q4N
Q1
Q4
AVEE
S2
QI
NC
– 23 –
VCCA
D2N
D3
D1N
D4
Q1N
Q4
D1
D4N
Q1N
D4N
Fig. 5. Schematic Diagram
TL431CP
IC10
R64
270
AGND
DGND
DGND
VTT P40
DVEE P41
( – 4.5)
+ 5V P42
D4
9
AGND
DGND
DGND
C61
33µ
C62
33µ
DGND
DGND
C63
33µ
AGND
C64
33µ
AGND
AGND
C65
33µ
CLKN DGND
19
DGND
DGND
CLK
D7
15
DGND
DGND
DGND
DGND
DGND
17
D6
13
D5
D3
7
11
D2
5
DGND
D1
3
Digital OUT
D0
DGND
(LSB)
1
DGND
D/A OUT
– 2V (D)
– 4.5V (D)
DGND
– 5.2V (D)
– 5.2V (A)
AGND
+ 5V (A)
20
18
16
14
12
10
8
6
4
2
CXA1166K
CXA1166K
Characteristics
Fig.6. Gain vs. Input frequency
2
0
Gain [dB]
–2
–4
–6
–8
Fig.5. CXA1166K PCB Schematic Diagram
Fig.4. Example of SNR Improvement Circuit
– 10
– 12
5
10
100
300
Input frequency [MHz]
Fig.7. SNR vs. Input frequency
50
SNR [dB]
45
40
35
Fig.5. CXA1166K PCB Schematic Diagram
Fig.4. Example of SNR Improvement Circuit
30
25
1
10
100
200
Input frequency [MHz]
2nd, 3rd Harmonic distortion [dB]
– 20
– 30
– 40
Fig.8. 2nd, 3rd Harmonic distortion vs. Input frequency
Fig.5. Schematic Diagram
(2nd Harmonic distortion)
Fig.5. Schematic Diagram
(3rd Harmonic distortion)
Fig.4. Example of SNR Improvement
Circuit (2nd Harmonic distortion)
Fig.4. Example of SNR Improvement
Circuit (3rd Harmonic distortion)
– 50
– 60
– 70
– 80
1
10
Input frequency [MHz]
– 24 –
100
200
CXA1166K
Parts Layout
Component side
Soldering side
– 25 –
CXA1166K
Printed Pattern
Component side
Soldering side
– 26 –
CXA1166K
GND layer (inner layer)
VEE layer (inner layer)
– 27 –
CXA1166K
Unit: mm
68PIN LCC (CERAMIC)
1.27 ± 0.2
1.27 ± 0.1
C
1
1.9 ± 0.25
20.32 ± 0.1
21.59 ± 0.2
+ 0.38
24.13 – 0.25
1.27
0.915 ± 0.07
1.65 ± 0.18
0.3
15.85 ± 0.2
1.95 ± 0.25
Package Outline
R0.2
PIN NO.1
INDEX
2.16 ± 0.25
PACKAGE STRUCTURE
PACKAGE MATERIAL
CERAMIC
SONY CODE
LCC-68C-01
LEAD TREATMENT
GOLD PLATING
EIAJ CODE
∗QFN068-C-S950-A
LEAD MATERIAL
JEDEC CODE
PACKAGE WEIGHT
– 28 –
3.7g