Maxim MAX1273CPA Fault-protected, 12-bit adcs with software-selectable input range Datasheet

19-2921; Rev 1; 12/03
Fault-Protected, 12-Bit ADCs
with Software-Selectable Input Range
The MAX1272/MAX1273 are available in 8-pin PDIP
and µMAX packages. Both devices are available in the
commercial (0°C to +70°C) or extended (-40°C to
+85°C) temperature range.
Features
♦ Four Software-Selectable Input Ranges
MAX1272: 0 to 10V, 0 to 5V, ±10V, ±5V
MAX1273: 0 to VREF, 0 to VREF / 2, ±VREF,
±VREF / 2
♦ 12-Bit Resolution, No Missing Codes
♦ 5V Single-Supply Operation
♦ SPI/QSPI/MICROWIRE-Compatible 3-Wire
Interface
♦ 87ksps Sampling Rate
♦ ±12V Fault-Protected Analog Input (MAX1272)
♦ Internal (4.096V) or External (2.4V to 4.18V)
Reference
♦ Low Power
1.5mA at 87ksps
0.4mA at 10ksps
0.2mA at 1ksps
♦ Four Power-Down Modes
♦ 8-Pin µMAX and PDIP Packages
Ordering Information
PART
TEMP
RANGE
MAX1272CPA
0°C to +70°C
8 Plastic DIP
±1
MAX1272CUA
0°C to +70°C
8 µMAX
±1
Data-Acquisition Systems
MAX1272EPA
-40°C to +85°C
8 Plastic DIP
±1
Robotics
MAX1272EUA
-40°C to +85°C
8 µMAX
±1
MAX1273CPA
0°C to +70°C
8 Plastic DIP
±1
MAX1273CUA
0°C to +70°C
8 µMAX
±1
MAX1273EPA
-40°C to +85°C
8 Plastic DIP
±1
MAX1273EUA
-40°C to +85°C
8 µMAX
±1
Applications
Industrial Control Systems
Automatic Testing
Battery-Powered Instruments
Medical Instruments
PINPACKAGE
INL
(LSB)
Pin Configuration
TOP VIEW
Typical Application Circuit appears at end of data sheet.
SCLK
1
DIN
2
VDD
3
MAX1272
MAX1273
GND 4
8
DOUT
7
CS
6
REF
5
AIN
SPI and QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor Corp.
PDIP/µMAX
________________________________________________________________ Maxim Integrated Products
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
1
MAX1272/MAX1273
General Description
The MAX1272/MAX1273 multirange 12-bit data-acquisition systems (DAS) operate with a single 5V supply. The
software-programmable analog input accepts a variety
of voltage ranges: ±10V, ±5V, 0 to 10V, 0 to 5V for the
MAX1272; ±VREF, ±VREF / 2, 0 to VREF, 0 to VREF / 2 for
the MAX1273. The software-selectable extended analog
input range increases the effective dynamic range to 14
bits and provides the flexibility to interface 4–20mA powered sensors directly to a single 5V system. In addition,
the MAX1272 provides fault protection to ±12V. Other
features include a 5MHz track/hold (T/H) bandwidth,
87ksps throughput rate, and internal (4.096V) or external
(2.40V to 4.18V) reference.
The MAX1272/MAX1273 serial interfaces connect
directly to SPI™/QSPI™/MICROWIRE™-compatible
devices without any external logic.
Four software-programmable power-down modes
(delayed standby, immediate standby, delayed full powerdown, and immediate full power-down) provide low-current shutdown between conversions. In standby mode, the
internal reference buffer remains active, thus eliminating
startup delay.
MAX1272/MAX1273
Fault-Protected, 12-Bit ADCs
with Software-Selectable Input Range
ABSOLUTE MAXIMUM RATINGS
VDD to GND ..............................................................-0.3V to +6V
AIN to GND (MAX1272) ...................................................... ±12V
AIN to GND (MAX1273) ........................................................ ±6V
DOUT, CS, DIN, SCLK, REF to GND..........-0.3V to (VDD + 0.3V)
Maximum Current into Any Pin............................................50mA
Continuous Power Dissipation (TA = +70°C)
8-Pin Plastic DIP (derate 9.1mW/°C above +70°C) ......727mW
8-Pin µMAX (derate 4.5mW/°C above +70°C) ..............362mW
Operating Temperature Ranges
MAX127_ C_ _ .....................................................0°C to +70°C
MAX127_ E_ _...................................................-40°C to +85°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10s) ................................+300°C
Junction Temperature .....................................................+150°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VDD = 4.75V to 5.25V, unipolar/bipolar input range, external reference mode, VREF = 4.096V, CREF = 1.0µF, fSCLK = 1.4MHz,
50% duty cycle, CLOAD = 50pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETERS
SYMBOL
CONDITIONS
ACCURACY (Note 1)
Resolution
MIN
TYP
MAX
UNITS
12
Integral Nonlinearity
INL
Differential Nonlinearity
DNL
Offset Error
Gain Error (Note 2)
Gain Error Temperature
Coefficient (Note 2)
No missing codes over temperature
Bits
±0.3
±1.0
LSB
±0.35
±1.00
LSB
Unipolar
±5
Bipolar
±10
Unipolar
±10
Bipolar
±10
Unipolar
±3
Bipolar
±5
LSB
LSB
ppm/°C
DYNAMIC SPECIFICATIONS (10kHz sine-wave input, ±10VP-P (MAX1272), or ±4.096VP-P (MAX1273), fSAMPLE = 87ksps)
Signal-to-Noise + Distortion Ratio
SINAD
Total Harmonic Distortion
THD
Spurious-Free Dynamic Range
SFDR
69
Up to the 5th harmonic
72
-87
80
dB
-78
88
dB
dB
Aperture Delay
tAD
15
ns
Aperture Jitter
tAJ
<50
ps
ANALOG INPUT
T/H Acquisition Time
2
tACQ
_______________________________________________________________________________________
2.85
µs
Fault-Protected, 12-Bit ADCs
with Software-Selectable Input Range
(VDD = 4.75V to 5.25V, unipolar/bipolar input range, external reference mode, VREF = 4.096V, CREF = 1.0µF, fSCLK = 1.4MHz,
50% duty cycle, CLOAD = 50pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETERS
SYMBOL
CONDITIONS
MIN
±10V (MAX1272) or ±VREF (MAX1273)
range
Small-Signal Bandwidth
BW-3dB
2.5
0 to 10V (MAX1272) or 0 to VREF (MAX1273)
range
2.5
UNITS
0 to 5V (MAX1272) or 0 to VREF / 2
(MAX1273) range
1.25
MHz
Unipolar
MAX1273
VIN
MAX1272
Bipolar
MAX1273
MAX1272
Unipolar
MAX1273
Input Current
MAX
5
±5V (MAX1272) or ±VREF / 2 (MAX1273)
range
MAX1272
Input Voltage Range
(Tables 2, 3)
TYP
IIN
MAX1272
Bipolar
MAX1273
RNG = 1
0
10
RNG = 0
0
5
RNG = 1
0
VREF
RNG = 0
0
VREF / 2
RNG = 1
-10
+10
RNG = 0
-5
+5
RNG = 1
-VREF
+VREF
RNG = 0
-VREF / 2
+VREF / 2
0 to 10V range
-10
+860
+430
0 to 5V range
-10
0 to VREF range
-10
+10
0 to VREF / 2 range
-10
+10
-1400
+860
±10V range
±5V range
-720
+430
±VREF range
-1400
+10
±VREF / 2 range
-720
Input Capacitance
V
µA
+10
40
pF
INTERNAL REFERENCE
REF Output Voltage
REF Output Tempco
VREF
TC VREF
4.036
4.096
MAX127_ C
±15
MAX127_ E
±30
Output Short-Circuit Current
REF shorted to GND
40
Load Regulation
0 to 0.5mA output current
0.7
Capacitive Bypass at REF
REFERENCE INPUT (Reference buffer disabled, reference input applied to REF)
Input Voltage Range
4.156
ppm/°C
mA
10
1
2.40
V
mV
µF
4.18
V
_______________________________________________________________________________________
3
MAX1272/MAX1273
ELECTRICAL CHARACTERISTICS (continued)
MAX1272/MAX1273
Fault-Protected, 12-Bit ADCs
with Software-Selectable Input Range
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 4.75V to 5.25V, unipolar/bipolar input range, external reference mode, VREF = 4.096V, CREF = 1.0µF, fSCLK = 1.4MHz,
50% duty cycle, CLOAD = 50pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETERS
SYMBOL
Input Current
CONDITIONS
Converting
VREF = 4.096V
MIN
Standby power-down
mode
TYP
400
MAX
850
UNITS
5
10
µA
Full power-down mode
POWER REQUIREMENTS
Supply Voltage
VDD
4.75
Converting
Supply Current
(Internal Reference Mode)
IDD
1
5
5.25
Bipolar
2.4
4
Unipolar
2.2
3
400
700
Standby power-down mode
Full power-down mode
Converting
Supply Current
(External Reference Mode)
IDD
1
Bipolar
1.5
2.5
Unipolar
1.2
2.0
200
450
Standby power-down mode
Full power-down mode
Power-Supply Rejection
Ratio (Note 3)
PSRR
External reference = 4.096V
1
±0.3
Internal reference
±1.0
±0.5
V
mA
µA
mA
µA
LSB
TIMING
Clock Frequency Range
fSCLK
T/H Acquisition Time
tACQ
(Note 4)
2.85
µs
Conversion Time
tCONV
(Note 4)
8.57
µs
0.1
1.4
Throughput Rate
87.5
MHz
ksps
Internal Reference Settling Time
REF bypass capacitor initially discharged
2
ms
Device Power-Up Time
External reference mode
10
µs
DIGITAL INPUTS (DIN, SCLK, and CS)
Input High-Threshold Voltage
VIH
Input Low-Threshold Voltage
VIL
Input Hysteresis
2.4
0.8
VHYS
Input Leakage Current
IIN
Input Capacitance
CIN
V
0.2
VIN = 0 to VDD
V
-10
V
+10
15
µA
pF
DIGITAL OUTPUT (DOUT)
Output Voltage Low
VOL
Output Voltage High
VOH
Three-State Leakage Current
Three-State Output Capacitance
4
ISINK = 10mA
0.4
ISINK = 16mA
0.6
ISOURCE = 0.5mA
VDD
- 0.5
IL
CS = VDD
-10
COUT
CS = VDD
V
V
+10
15
_______________________________________________________________________________________
µA
pF
Fault-Protected, 12-Bit ADCs
with Software-Selectable Input Range
(VDD = 4.75V to 5.25V, unipolar/bipolar input range, external reference mode, VREF = 4.096V, CREF = 1.0µF, fSCLK = 1.4MHz,
50% duty cycle, CLOAD = 50pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Figures 1 and 4)
PARAMETERS
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
0
ns
250
ns
ns
DIN to SCLK Setup
tDS
DIN to SCLK Hold
tDH
100
ns
SCLK Fall to Output Data Valid
tDO
CS Fall to Output Enable
tDV
100
CS Rise to Output Disable
tTR
100
20
ns
CS to SCLK Rise Setup
tCSS
100
ns
CS to SCLK Rise Hold
tCSH
0
ns
SCLK Pulse Width High
tCH
200
ns
SCLK Pulse Width Low
tCL
200
ns
Note 1: Accuracy specifications tested at VDD = 5V. Performance at power-supply tolerance limit is guaranteed by power-supply
rejection test.
Note 2: Offset error nulled. The ideal last-code transition is (FS - 1.5 LSB).
Note 3: PSRR measured at full scale. Tested at ±10V (MAX1272) and ±4.096V (MAX1273) input ranges.
Note 4: Acquisition and conversion times are dependent on the clock speed.
Typical Operating Characteristics
(Typical operating circuit, BIP = RNG = 1, VDD = 5V, external reference mode, VREF = 4.096V, CREF = 1.0µF, fSCLK = 1.4MHz,
50% duty cycle, 87ksps, TA = +25°C, unless otherwise noted.)
3.0
2.5
INTERNAL
REFERENCE
2.0
1.5
1.0
4.0
EXTERNAL
REFERENCE
3.5
3.0
2.5
2.0
1.5
0.5
0
0
SUPPLY VOLTAGE (V)
EXTERNAL
REFERENCE
1.0
0.5
4.75 4.80 4.85 4.90 4.95 5.00 5.05 5.10 5.15 5.20 5.25
INTERNAL
REFERENCE
1.0
VAIN = 0
0.9
STANDBY SUPPLY CURRENT (mA)
3.5
VAIN = 0
4.5
SUPPLY CURRENT (mA)
SUPPLY CURRENT (mA)
4.0
5.0
STANDBY SUPPLY CURRENT
vs. TEMPERATURE
MAX1272/73 toc02
VAIN = 0
4.5
MAX1272/73 toc01
5.0
CONVERTING SUPPLY CURRENT
vs. TEMPERATURE
0.8
MAX1272/73 toc03
CONVERTING SUPPLY CURRENT
vs. SUPPLY VOLTAGE
0.7
0.6
INTERNAL
REFERENCE
0.5
0.4
EXTERNAL
REFERENCE
0.3
0.2
0.1
0
-40
-15
10
35
TEMPERATURE (°C)
60
85
-40
-15
10
35
60
85
TEMPERATURE (°C)
_______________________________________________________________________________________
5
MAX1272/MAX1273
TIMING CHARACTERISTICS
Typical Operating Characteristics (continued)
(Typical operating circuit, BIP = RNG = 1, VDD = 5V, external reference mode, VREF = 4.096V, CREF = 1.0µF, fSCLK = 1.4MHz,
50% duty cycle, 87ksps, TA = +25°C, unless otherwise noted.)
0.6
0.5
0.4
8
INTERNAL
REFERENCE
0.3
0.2
7
6
5
4
3
INTERNAL/EXTERNAL
REFERENCE
2
EXTERNAL
REFERENCE
0.1
1
0
-15
5
4
3
INTERNAL/EXTERNAL
REFERENCE
10
35
85
60
4.75 4.80 4.85 4.90 4.95 5.00 5.05 5.10 5.15 5.20 5.25
SUPPLY VOLTAGE (V)
0.9995
0.9990
0.9985
0.9980
0.9975
0.9970
0.9965
10
35
60
85
1.0010
MAX1272/73 toc08
1.0000
NORMALIZED INTERNAL REFERENCE VOLTAGE
NORMALIZED INTERNAL REFERENCE
VOLTAGE vs. SUPPLY VOLTAGE
MAX1272/73 toc07
NORMALIZED INTERNAL REFERENCE VOLTAGE
1.0005
1.0008
1.0006
1.0004
1.0002
1.0000
0.9998
0.9996
0.9994
0.9992
0.9990
4.75 4.80 4.85 4.90 4.95 5.00 5.05 5.10 5.15 5.20 5.25
TEMPERATURE (°C)
SUPPLY VOLTAGE (V)
INL vs. CODE
DNL vs. CODE
0.8
0.6
0.8
0.6
0.4
0.2
0.2
INL (LSB)
0.4
0
-0.2
MAX1272/73 toc10
1.0
MAX1272/73 toc09
1.0
DNL (LSB)
6
TEMPERATURE (°C)
0.9960
0
-0.2
-0.4
-0.4
-0.6
-0.6
-0.8
-0.8
-1.0
-1.0
0
512 1024 1536 2048 2560 3072 3584 4096
CODE
6
7
1
NORMALIZED INTERNAL REFERENCE
VOLTAGE vs. TEMPERATURE
-15
8
0
-40
SUPPLY VOLTAGE (V)
-40
VAIN = 0
9
2
0
4.75 4.80 4.85 4.90 4.95 5.00 5.05 5.10 5.15 5.20 5.25
10
SUPPLY CURRENT (µA)
0.7
VAIN = 0
9
SUPPLY CURRENT (µA)
0.8
10
FULL POWER-DOWN SUPPLY CURRENT
vs. SUPPLY VOLTAGE
MAX1272/73 toc05
VAIN = 0
0.9
MAX1272/73 toc04
1.0
FULL POWER-DOWN
SUPPLY CURRENT vs. TEMPERATURE
MAX1272/73 toc06
STANDBY SUPPLY CURRENT
vs. SUPPLY VOLTAGE
SUPPLY CURRENT (mA)
MAX1272/MAX1273
Fault-Protected, 12-Bit ADCs
with Software-Selectable Input Range
0
512 1024 1536 2048 2560 3072 3584 4096
CODE
_______________________________________________________________________________________
Fault-Protected, 12-Bit ADCs
with Software-Selectable Input Range
SUPPLY CURRENT
vs. CONVERSION RATE
FFT PLOT
-60
-80
-100
-120
VAIN = 0
STANDBY POWER-DOWN MODE
BETWEEN CONVERSIONS
2000
SUPPLY CURRENT (µA)
AMPLITUDE (dB)
-40
2500
MAX1272/73 toc12
fAIN = 10kHz
-20
MAX1272/73 toc11
0
1500
EXTERNAL REFERENCE
1000
INTERNAL REFERENCE
500
-140
-160
0
20
30
40
50
0.1
FREQUENCY (kHz)
OFFSET ERROR vs. TEMPERATURE
8
OFFSET ERROR vs. SUPPLY VOLTAGE
RNG = 1, BIP = 1
2
0
RNG = 0, BIP = 1
-4
8
6
OFFSET ERROR (LSB)
OFFSET ERROR (LSB)
6
-2
RNG = 0, BIP = 0
RNG = 1, BIP = 0
-6
2
0
-2
RNG = 0, BIP = 0
-6
-8
-10
10
RNG = 1, BIP = 0
-4
-8
-15
35
60
85
4.50
TEMPERATURE (°C)
GAIN ERROR vs. TEMPERATURE
GAIN ERROR (LSB)
RNG = 0, BIP = 1
2
RNG = 1, BIP = 0
RNG = 1, BIP = 1
-2
2
0
-2
-6
-8
-8
-10
-10
10
35
60
85
RNG = 0, BIP = 1
4
-4
TEMPERATURE (°C)
RNG = 0, BIP = 0
6
-6
-15
5.50
8
-4
-40
5.25
GAIN ERROR vs. SUPPLY VOLTAGE
GAIN ERROR (LSB)
RNG = 0, BIP = 0
0
5.00
10
MAX1272/73 toc15
8
4
4.75
SUPPLY VOLTAGE (V)
10
6
RNG = 1, BIP = 1
RNG = 0, BIP = 1
4
-10
-40
100
10
MAX1272/73 toc13
10
4
10
1
CONVERSION RATE (ksps)
MAX1272/73 toc14
10
MAX1272/73 toc16
0
RNG = 1, BIP = 1
4.50
4.75
5.00
RNG = 1, BIP = 0
5.25
5.50
SUPPLY VOLTAGE (V)
_______________________________________________________________________________________
7
MAX1272/MAX1273
Typical Operating Characteristics (continued)
(Typical operating circuit, BIP = RNG = 1, VDD = 5V, external reference mode, VREF = 4.096V, CREF = 1.0µF, fSCLK = 1.4MHz,
50% duty cycle, 87ksps, TA = +25°C, unless otherwise noted.)
Fault-Protected, 12-Bit ADCs
with Software-Selectable Input Range
MAX1272/MAX1273
Pin Description
PIN
NAME
1
SCLK
FUNCTION
2
DIN
Serial Data Input. Data clocks in on the rising edge of SCLK.
3
VDD
5V Supply. Bypass with a 0.1µF capacitor to GND.
4
GND
Ground
5
AIN
Analog Input
6
REF
Reference Buffer Output/Reference Input. Bypass REF with a 1µF capacitor to GND. In internal
reference mode, the reference buffer provides a 4.096V nominal output. For external reference mode,
disable the internal reference buffer through the serial interface and apply an external reference to REF.
7
CS
Active-Low Chip-Select Input. Drive CS low to clock data into the MAX1272/MAX1273. See the Input
Data Format section.
8
DOUT
Serial Clock Input. Clocks data in and out of serial interface. SCLK sets the conversion speed.
Serial Data Output. Data clocks out on the falling edge of SCLK. DOUT is high impedance when CS is
high.
DOUT
CLOAD
to convert an analog signal to a 12-bit digital output.
Figure 2 shows a block diagram of the MAX1272/
MAX1273.
Analog-Input Track/Hold
1kΩ
A) TEST CIRCUIT FOR VOH
DOUT
CLOAD
1kΩ
Input Bandwidth
5V
B) TEST CIRCUIT FOR VOL
fSCLK = 1.4MHz, CLOAD = 50pF
Figure 1. Output Load Circuit for Timing Characteristics
Detailed Description
Converter Operation
The MAX1272/MAX1273 multirange ADCs use successive approximation and internal track/hold (T/H) circuitry
8
The T/H tracking/acquisition mode begins on the falling
edge of the fourth clock cycle in the 8-bit input control
word and enters hold/conversion mode on the falling
edge of the eighth clock cycle.
The MAX1272/MAX1273 input architecture includes a
resistor-divider and a T/H system (Figure 3). When
operating in bipolar or unipolar mode, the resistordivider network formed by R1, R2, and R3 scales the
signal applied at the input channel. Use a low source
impedance (<4Ω) to minimize gain error.
The ADC’s small-signal input bandwidth depends on
the selected input range and varies from 1.25MHz to
5MHz (see the Electrical Characteristics). The maximum sampling rate for the MAX1272/MAX1273 is
87ksps (16 clocks per conversion). Use undersampling
techniques to digitize high-speed transient events and
measure periodic signals with bandwidths exceeding
the ADC’s sampling rate.
Use anti-alias filtering to avoid the aliasing of high-frequency signals into the frequency band of interest. An
anti-aliasing filter must limit the input bandwidth to no
more than one half of the sampling frequency.
_______________________________________________________________________________________
Fault-Protected, 12-Bit ADCs
with Software-Selectable Input Range
CS
SCLK
SERIAL INTERFACE
LOGIC
VDD
MAX1272
MAX1273
GND
AIN
DOUT
MAX1272/MAX1273
DIN
SIGNAL
CONDITIONING
OUT
T/H
IN
12-BIT
SAR ADC
CLK
REF
REF
4.096V
REFERENCE
Figure 2. Simplified Block Diagram
Table 1. Control-Byte Format
BIT 7
(MSB)
BIT 6
BIT 5
BIT 4
Bit 3
BIT 2
BIT 1
BIT 0
(LSB)
START
RNG
BIP
PD
MODE1
MODE0
RESERVED
REF
BIT
NAME
7 (MSB)
START
DESCRIPTION
6
RNG
5
BIP
Selects unipolar or bipolar conversion mode (Tables 2, 3)
4
PD
Selects normal operation (PD = 1) or power-down (PD = 0) mode
3
MODE1
Selects standby power-down (STBYPD) or full power-down (FULLPD) mode (Table 4)
2
MODE0
Selects delayed or immediate power-down mode (Table 4)
1
RESERVED
0 (LSB)
REF
Write a logic 1 (see the Input Data Format section)
Selects the full-scale input voltage range (Tables 2, 3)
Write a logic 0
Selects external (REF = 0, default) or internal (REF = 1) reference mode
Input Range and Protection
The MAX1272/MAX1273 provide software-selectable
analog input voltage ranges. Program the analog input
to one of four ranges by setting the appropriate control
bits (RNG, BIP) in the control byte (Table 1). The
MAX1272 has selectable input voltage ranges extending to ±10V (±VREF ✕ 2.4414), while the MAX1273 has
selectable input voltage ranges extending to ±VREF.
Figure 3 shows the equivalent input circuit.
Overvoltage circuitry at the analog input provides ±12V
fault protection for the MAX1272. This circuit limits the
current going into or out of the device to less than 2mA,
providing an added layer of protection from momentary
over/undervoltages at the analog input. The overvoltage
protection activates when the device enters powerdown mode or if VDD = 0.
_______________________________________________________________________________________
9
MAX1272/MAX1273
Fault-Protected, 12-Bit ADCs
with Software-Selectable Input Range
Table 2. Input Range and Polarity Selection for MAX1272
NEGATIVE
FULL SCALE
ZERO SCALE
FULL SCALE
0
—
0
VREF × 1.2207
1
-VREF × 1.2207
0
VREF × 1.2207
1
0
—
0
VREF × 2.4414
1
1
-VREF × 2.4414
0
VREF × 2.4414
NEGATIVE
FULL SCALE
ZERO SCALE
FULL SCALE
INPUT RANGE
RNG
BIP
0 to 5V
0
±5V
0
0 to 10V
±10V
Table 3. Input Range and Polarity Selection for MAX1273
INPUT RANGE
RNG
BIP
0 to VREF / 2
0
0
—
0
VREF / 2
±VREF / 2
0
1
-VREF / 2
0
VREF / 2
0 to VREF
1
0
—
0
VREF
±VREF
1
1
-VREF
0
VREF
Table 4. Power-Down Selection
PD
MODE1
MODE0
1
X
X
Normal operation (ADCs always active). Automatically enters delayed
standby power-down mode between conversions.
0
Delayed standby power-down mode.
0
0
1
MODE
1
Immediate standby power-down mode.
0
Delayed full power-down mode.
1
Immediate full power-down mode.
Input Data Format
BIPOLAR
VOLTAGE
REFERENCE
S1
UNIPOLAR
R3
4.8kΩ
OFF
R1
CHOLD
AIN
S2
T/H
OUT
ON
R2
S3
HOLD
S1 = BIPOLAR/UNIPOLAR SWITCH
S2 = INPUT MUX SWITCH
S3, S4 = T/H SWITCH
HOLD
TRACK
TRACK
S4
R1 = 11.3kΩ (MAX1272)
or 4.8kΩ (MAX1273)
R2 = 7.8kΩ (MAX1272)
or ∞ (OPEN) (MAX1273)
Input data (control byte) clocks in at DIN on the rising
edge of SCLK. CS enables communication with the
MAX1272/MAX1273. After CS falls, the first arriving 1
represents the start bit (MSB) of the input control byte.
The start bit is defined as follows:
1) The first high bit clocked into DIN with CS low any
time the converter is idle (e.g., after applying VDD).
2) The first high bit clocked into DIN after bit 4 (D4) of a
conversion in progress clocks out on DOUT.
See Table 1 for programming the control byte. Figure 4
shows the detailed serial interface timing.
Output Data Format
Output data (DOUT) clocks out MSB first on the falling
edge of SCLK. The unipolar mode provides a straight
binary output. The bipolar mode provides a two’s complement binary output. For output binary codes, see the
Transfer Function section.
Figure 3. Equivalent Input Circuit
10
______________________________________________________________________________________
Fault-Protected, 12-Bit ADCs
with Software-Selectable Input Range
MAX1272/MAX1273
•••
CS
tCSS
tCH
tCL
tCSH
tCSH
SCLK
•••
tDS
tDH
•••
DIN
tDO
tDV
tTR
•••
DOUT
Figure 4. Detailed Serial Interface Timing
ACQUISITION
4 SCLKs
CONVERSION
12 SCLKs
HI-Z
32
24
D1
D3
D2
D5
D4
D7
D9
D6
16
1
SCLK
8
DOUT
LSB
D8
D11
MSB
D10
HI-Z
D0
RESERVED
REF
MODE0
PD
MODE1
BIP
START
DIN
RNG
CS
AUTO STANDBY
Figure 5. Conversion Timing, 21 Clocks/Conversion
______________________________________________________________________________________
11
CS
ACQUISITION
4 SCLKs
CONVERSION
12 SCLKs
PD
BIP
MODE1
D0
D1
D2
D3
D4
D5
D6
32
D8
D7
D9
D10
D11
LSB
RESULT 1
24
ACQUISITION
4 SCLKs
RNG
START
REF
RESERVED
MODE0
PD
BIP
MODE1
D0
D1
D2
D3
D4
D5
MSB
16
D6
D8
D7
D9
8
DOUT
LSB
RESULT 0
D10
D11
MSB
RNG
START
REF
HI-Z
SCLK
CONTROL BYTE 2
CONTROL BYTE 1
RESERVED
MODE0
MODE1
PD
BIP
DIN
RNG
START
CONTROL BYTE 0
1
MAX1272/MAX1273
Fault-Protected, 12-Bit ADCs
with Software-Selectable Input Range
CONVERSION
12 SCLKs
Figure 6. Conversion Timing, 16 Clocks/Conversion
Starting a Conversion
The MAX1272/MAX1273 use the serial clock to complete
an acquisition. The falling edge of CS does not start a
conversion on the MAX1272/MAX1273. Each conversion
requires a control byte. Programming the fourth bit in the
control byte starts the acquisition sequence. Conversion
starts on the falling edge of the eighth clock cycle after
the start bit.
Keep CS low during successive conversions. If a start bit
is received after CS transitions from high to low, but before
the output bit 4 (D4) becomes available, the current conversion terminates and a new conversion begins. DOUT
enters high-impedance state when CS transitions high.
SCLK shifts data in and out of the MAX1272/MAX1273
and controls both acquisition and conversion timing.
Conversion begins immediately after the end of the
acquisition cycle. Successive-approximation bit decisions appear at DOUT on each of the following 12 clock
falling edges (Figure 5). Additional clock falling edges
result in trailing zeros at DOUT.
The maximum running rate of the MAX1272/MAX1273 is
16 clocks per conversion. A clock speed of 1.4MHz
allows for a maximum sampling rate of 87ksps (Figure 6).
12
To achieve the maximum throughput, keep CS low, and
start the control byte after bit 4 (D4) of the conversion in
progress clocks out on DOUT.
If CS is low and SCLK is continuous, guarantee a start
bit by first clocking in 16 zeros.
Applications Information
Power-On Reset
The MAX1272/MAX1273 power-up in normal operating
mode (all internal circuitry active), and external reference
mode. The MAX1272/MAX1273 require a start bit to initiate a conversion. The contents of the output data register
clear during power-up.
Internal or External Reference
Operate the MAX1272/MAX1273 with an internal or an
external reference. Configure REF as an internal reference output or an external reference input using the
serial interface. When changing from external reference
mode to internal reference mode, allow 2ms (CREF =
1µF) for the reference to stabilize before taking any
measurement.
Internal Reference
The internally trimmed reference provides 4.096V at REF.
Bypass REF to GND with a 1.0µF capacitor (Figure 7a).
______________________________________________________________________________________
Fault-Protected, 12-Bit ADCs
with Software-Selectable Input Range
IN
MAX6064
REF
CREF
MAX1272
MAX1273
1.0µF
OUT
REF
MAX1272
MAX1273
1.0µF
CREF
GND
Figure 7a. Internal Reference Configuration
Figure 7b. External Reference Configuration
External Reference
To use an external reference, disable the internal buffer
by setting the REF bit in the 8-bit control word to zero
(see Table 1), and apply a reference voltage to REF. Use
an external reference voltage ranging from 2.40V to
4.18V. External reference voltages less than 4.096V
increase the ratio of RMS noise to the LSB value (full
scale / 4096) resulting in performance degradation (loss
of effective bits—ENOB).
The REF input impedance is a minimum of 4.8kΩ for
DC currents; therefore, the external reference must be
able to source 850µA during conversions and have an
output impedance of less than 10Ω. Bypass REF with a
1µF capacitor to GND as close to REF as possible
(Figure 7b).
serial clock cycle and no conversion takes place
(Figure 9). In all power-down modes, the interface
remains active with the conversion results available at
DOUT. Additionally, the input overvoltage protection
remains active in all power-down modes (MAX1272).
Power-Down Modes
To save power, configure the ADC for a low-current
shutdown mode by setting the PD bit in the control
byte. The MAX1272/MAX1273 features four programmable power-down modes: delayed standby powerdown, immediate standby power-down, delayed full
power-down, and immediate full power-down. Select
standby or full power-down by programming MODE1 in
the input control byte (Table 4). Select delayed or
immediate power-down by programming MODE0 in the
input control byte. Use the MODE0 bit to choose when
the part enters the power-down state. For example,
when MODE0 of the control byte is 0, the device
remains powered up until after the current conversion
ends (Figure 8). On the other hand, if MODE0 = 1, the
device powers down on the falling edge of the eighth
The first high bit on DIN after CS falls (start condition)
powers up the MAX1272/MAX1273 from any softwareselected power-down condition. With external reference mode, device power-up time from full powerdown is typically 10µs. Send a control byte and allow
10µs for the device to wake up from full power-down.
The next received control byte initiates a conversion.
When in internal reference mode, full power-down
mode disables the internal reference and reference
buffer. Only the interface circuitry remains active for
reading conversion results. Send a control byte and
allow 2ms (CREF = 1µF) for the internal reference to settle and the MAX1272/MAX1273 to wake up from full
power-down mode. The next received control byte initiates a conversion.
AutoShutdown™
The MAX1272/MAX1273 automatically enter standby
power-down mode after each conversion without requiring any startup time on the next conversion.
Digital Interface
The MAX1272/MAX1273 feature a fully compatible
SPI/QSPI and MICROWIRE serial interface. For SPI and
QSPI, clear CPOL and CPHA in the microcontroller’s
SPI control registers.
AutoShutdown is a trademark of Maxim Integrated Products, Inc.
______________________________________________________________________________________
13
MAX1272/MAX1273
5V
MAX1272/MAX1273
Fault-Protected, 12-Bit ADCs
with Software-Selectable Input Range
ACQUISITION
4 SCLKs
RESERVED
REF
MODE0
PD
MODE1
BIP
RNG
START
D1
D2
D4
D3
24
32
D5
D6
D8
D7
HI-Z
16
SCLK
8
1
D11
DOUT
LSB
D9
MSB
D10
HI-Z
D0
RESERVED
REF
MODE1
0
0
RNG
DIN
BIP
START
CS
CONVERSION
12 SCLKs
POWERED UP
POWERED UP
POWERED DOWN
Figure 8. Delayed Power-Down Timing
REF
RESERVED
MODE0
MODE1
PD
BIP
START
RNG
RESERVED
REF
1
MODE1
0
RNG
DIN
BIP
START
CS
HI-Z
HI-Z
32
24
8
1
SCLK
16
DOUT
ACQUISITION
4 SCLKs
POWERED UP
POWERED DOWN
POWERED UP
Figure 9. Immediate Power-Down Timing
SPI and MICROWIRE Interface
When using the SPI (Figure 10a) or MICROWIRE (Figure
10b) interfaces, set CPOL = 0 and CPHA = 0 in the SPI
master. Conversion begins with a falling edge on CS.
Three consecutive 8-bit readings are necessary to
obtain the entire 12-bit result from the ADC. DOUT data
transitions on the serial clock’s falling edge. The first 814
bit data stream contains all leading zeros. The second
8-bit data stream contains a leading zero followed by
the MSB through D5. The third 8-bit data stream contains D4–D0 followed by trailing zeros.
______________________________________________________________________________________
Fault-Protected, 12-Bit ADCs
with Software-Selectable Input Range
PIC16 with SSP Module and
PIC17 Interface
The MAX1272/MAX1273 are compatible with a
PIC16/PIC17 controller (µC) using the synchronous serial-port (SSP) module.
To establish SPI communication, connect the controller
as shown in Figure 12 and configure the PIC16/PIC17
as system master by initializing its synchronous serialport control register (SSPCON) and synchronous serialport status register (SSPSTAT) to the bit patterns shown
in Tables 5 and 6.
In SPI mode, the PIC16/PIC17 µCs allow 8 bits of data
to be transmitted and received simultaneously. Three
consecutive 8-bit readings are necessary to obtain the
entire 12-bit result from the ADC. DOUT data transitions
on the serial clock’s falling edge and is clocked into the
I/O
µC on SCLK’s rising edge. The first 8-bit data stream
contains all zeros. The second 8-bit data stream contains a leading zero followed by the MSB through D5.
The third 8-bit data stream contains bits D4–D0 followed by trailing zeros.
Transfer Function
Output data coding for the MAX1272/MAX1273 is binary in unipolar mode with:
FS
1LSB =
4096
and two’s complement binary in bipolar mode with:
2 × | FS |
1LSB =
4096
Code transitions occur halfway between successive
integer LSB values. Figures 13a and 13b show the
input/output transfer functions for uni-polar and bipolar
operations, respectively. For full-scale (FS) values, see
Tables 2 and 3.
CS
I/O
CS
SCK
SCLK
SCK
SCLK
MISO
DOUT
SI
DOUT
SPI
MICROWIRE
VDD
MAX1272
MAX1273
SS
Figure 10a. SPI Connections
MAX1272
MAX1273
Figure 10b. MICROWIRE Connections
VDD
VDD
CS
SCLK
SCK
SCK
SCLK
DOUT
SDI
MISO
DOUT
CS
I/O
CS
QSPI
VDD
MAX1272
MAX1273
SS
MAX1272
MAX1273
PIC16/PIC17
GND
Figure 11. QSPI Connections
Figure 12. SPI Interface Connection for a PIC16/PIC17
______________________________________________________________________________________
15
MAX1272/MAX1273
QSPI Interface
Using the high-speed QSPI interface with CPOL = 0
and CPHA = 0, the MAX1272/MAX1273 support a maximum fSCLK of 1.4MHz. Figure 11 shows the MAX1272/
MAX1273 connected to a QSPI master.
MAX1272/MAX1273
Fault-Protected, 12-Bit ADCs
with Software-Selectable Input Range
Table 5. Detailed SSPCON Register Contents—PIC16/PIC17
CONTROL BIT
SYNCHRONOUS SERIAL-PORT CONTROL REGISTER (SSPCON)
WCOL
BIT7
X
Write Collision Detection Bit
SSPOV
BIT6
X
Receive Overflow Detection Bit
SSPEN
BIT5
1
Synchronous Serial-Port Enable Bit:
0: Disables serial port and configures these pins as I/O port pins.
1: Enables serial port and configures SCK, SDO, and SCI pins as serial port pins.
Clock Polarity Select Bit. CKP = 0 for SPI master mode section.
CKP
BIT4
0
SSPM3
SSPM2
BIT3
BIT2
0
0
SSPM1
BIT1
0
SSPM0
BIT0
1
Synchronous Serial-Port Mode-Select Bit. Sets SPI master mode and selects fCLK = fOSC / 16.
X = Don’t care.
Table 6. Detailed SSPSTAT Register Contents—PIC16/PIC17
CONTROL BIT
SYNCHRONOUS SERIAL-PORT STATUS REGISTER (SSPSTAT)
SMP
BIT7
0
SPI Data Input Sample Phase. Input data is sampled at the middle of the data output
time.
CKE
BIT6
1
SPI Clock Edge-Select Bit. Data is transmitted on the rising edge of the serial clock.
D/A
BIT5
X
Data Address Bit
P
BIT4
X
Stop Bit
S
BIT3
X
Start Bit
R/W
BIT2
X
Read/Write Bit Information
UA
BIT1
X
Update Address
BF
BIT0
X
Buffer Full Status Bit
X = Don’t care.
1 LSB = FS
4096
OUTPUT CODE
1 LSB = 2FS
4096
OUTPUT CODE
(TWO’S COMPLEMENT)
1…111
1…110
0…111
0…110
1…101
0…101
1…100
0…100
0…001
0…000
1…111
0…011
1…011
0…010
0…001
0…000
1…010
1…001
1…000
-2048 -2046
0 1
2
3
4092
INPUT VOLTAGE (LSB)
Figure 13a. Unipolar Transfer Function
16
4094
FS
-1 0 +1
INPUT VOLTAGE (LSB)
+2045 +2047
Figure 13b. Bipolar Transfer Function
______________________________________________________________________________________
Fault-Protected, 12-Bit ADCs
with Software-Selectable Input Range
Definitions
Integral Nonlinearity
Integral nonlinearity (INL) is the deviation of the values
on an actual transfer function from a straight line. This
straight line can be either a best-straight-line fit or a line
drawn between the endpoints of the transfer function,
once offset and gain errors have been nullified. The
static linearity parameters for the MAX1272/MAX1273
are measured using the endpoint method.
Differential Nonlinearity
Differential nonlinearity (DNL) is the difference between
an actual step-width and the ideal value of 1 LSB. A
DNL error specification of 1 LSB guarantees no missing
codes and a monotonic transfer function.
Aperture Definitions
Aperture jitter (tAJ) is the sample-to-sample variation in
the time between samples. Aperture delay (tAD) is the
time between the falling edge of the sampling clock
and the instant when the actual sample is taken.
Signal-to-Noise Ratio
For a waveform perfectly reconstructed from digital
samples, signal-to-noise ratio (SNR) is the ratio of the
full-scale analog input (RMS value) to the RMS quantization error (residual error).
The ideal, theoretical minimum analog-to-digital noise is
caused by quantization noise error only and results
directly from the ADC’s resolution (N-bits):
SNR = (6.02 ✕ N + 1.76) dB
In reality, there are other noise sources besides quantization noise: thermal noise, reference noise, clock jitter,
etc. SNR is computed by taking the ratio of the RMS
signal to the RMS noise, which includes all spectral
components minus the fundamental, the first five harmonics, and the DC offset.
Signal-to-Noise Plus Distortion
Signal-to-noise plus distortion (SINAD) is the ratio of the
fundamental input frequency’s RMS amplitude to the
RMS equivalent of all the other ADC output signals:
SINAD (dB) = 20 ✕ log [SignalRMS / (Noise +
Distortion)RMS]
Effective Number of Bits
Effective number of bits (ENOB) indicates the global
accuracy of an ADC at a specific input frequency and
sampling rate. An ideal ADC’s error consists of quantization noise only. With an input range equal to the fullscale range of the ADC, calculate the effective number
of bits as follows:
ENOB = (SINAD - 1.76) / 6.02
Total Harmonic Distortion
Total harmonic distortion (THD) is the ratio of the RMS
sum of the first five harmonics of the input signal to the
fundamental itself. This is expressed as:
  2
2
2
2
  V2 + V3 + V4 + V5 
THD = 20 × log 

V1








where V1 is the fundamental amplitude and V2 through
V5 are the 2nd- through 5th-order harmonics.
Spurious-Free Dynamic Range
Spurious-free dynamic range (SFDR) is the ratio of the
RMS amplitude of the fundamental (maximum signal
component) to the RMS value of the next largest frequency component, excluding DC offset.
______________________________________________________________________________________
17
MAX1272/MAX1273
Layout, Grounding, and Bypassing
For best performance, use printed circuit (PC) boards.
Wire-wrap configurations are not recommended since
the layout should ensure proper separation of analog
and digital traces. Do not run analog and digital lines
parallel to each other, and do not lay out digital signal
paths underneath the ADC package. Use separate
analog and digital PC board ground sections with only
one star point (Figure 14), connecting the two ground
systems (analog and digital). For lowest-noise operation, ensure that the ground return to the star ground’s
power supply is low impedance and as short as possible. Route digital signals far away from sensitive analog
and reference inputs.
High-frequency noise in the power supply (VDD) can
degrade the performance of the ADC’s fast comparator. Bypass VDD to the star ground with a 0.1µF capacitor located as close as possible to the MAX1272/
MAX1273’s power-supply input. Minimize capacitor lead
length for best supply-noise rejection. Add an attenuation resistor (5Ω) to extremely noisy power supplies.
MAX1272/MAX1273
Fault-Protected, 12-Bit ADCs
with Software-Selectable Input Range
Typical Operating Circuit
5V
SUPPLIES
0.1µF
5V
VLOGIC = 5V
GND
VDD
AIN
CS
R* = 5Ω
SCLK
0.1µF
VDD
MAX1272
MAX1273
GND
5V
DGND
REF
1.0µF
MAX1272
MAX1273
I/O
SCK
DIN
MOSI
DOUT
MISO
µP
GND
DIGITAL
CIRCUITRY
*OPTIONAL
Figure 14. Power-Supply Grounding Connections
Chip Information
TRANSISTOR COUNT: 6146
PROCESS: BiCMOS
18
______________________________________________________________________________________
Fault-Protected, 12-Bit ADCs
with Software-Selectable Input Range
PDIPN.EPS
______________________________________________________________________________________
19
MAX1272/MAX1273
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
4X S
8
8
INCHES
DIM
A
A1
A2
b
E
ÿ 0.50±0.1
H
c
D
e
E
H
0.6±0.1
L
1
1
α
0.6±0.1
S
BOTTOM VIEW
D
MIN
0.002
0.030
MAX
0.043
0.006
0.037
0.014
0.010
0.007
0.005
0.120
0.116
0.0256 BSC
0.120
0.116
0.198
0.188
0.026
0.016
6∞
0∞
0.0207 BSC
8LUMAXD.EPS
MAX1272/MAX1273
Fault-Protected, 12-Bit ADCs
with Software-Selectable Input Range
MILLIMETERS
MAX
MIN
0.05
0.75
1.10
0.15
0.95
0.25
0.36
0.13
0.18
2.95
3.05
0.65 BSC
2.95
3.05
4.78
5.03
0.41
0.66
0∞
6∞
0.5250 BSC
TOP VIEW
A1
A2
A
α
c
e
b
L
SIDE VIEW
FRONT VIEW
PROPRIETARY INFORMATION
TITLE:
PACKAGE OUTLINE, 8L uMAX/uSOP
APPROVAL
DOCUMENT CONTROL NO.
21-0036
REV.
J
1
1
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
20 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2003 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.