LINER LTC2923CMS Power supply tracking controller Datasheet

LTC2923
Power Supply
Tracking Controller
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FEATURES
DESCRIPTIO
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The LTC®2923 provides a simple solution to power supply
tracking and sequencing requirements. By selecting a few
resistors, the supplies can be configured to ramp-up and
ramp-down together or with voltage offsets, time delays
or different ramp rates.
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■
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Flexible Power Supply Tracking
Tracks Both Up and Down
Power Supply Sequencing
Supply Stability is Not Affected
Controls Two Supplies Without Series FETs
Controls a Third Supply With a Series FET
Adjustable Ramp Rates
Electronic Circuit Breaker
Available in 10-Lead MS and 12-Lead
(4mm × 3mm) DFN Packages
By introducing currents into the feedback nodes of two
independent switching regulators, the LTC2923 causes
their outputs to track without inserting any pass element
losses. Because the currents are controlled in an openloop manner, the LTC2923 does not affect the transient
response or stability of the supplies. Furthermore, it
presents a high impedance when power-up is complete,
effectively removing it from the DC/DC circuit.
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APPLICATIO S
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VCORE and VI/O Supply Tracking
Microprocessor, DSP and FPGA Supplies
Servers
Communication Systems
For systems that require a third supply, one supply can be
controlled with a series FET. This optional series FET can
also control a supply that does not allow direct access to
its feedback resistors (e.g., a power module) or a supply
whose output cannot be forced to ground (e.g., a 3-terminal linear regulator). When the FET is used, an electronic
circuit breaker provides protection from short-circuit
conditions.
, LTC and LT are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
Patents Pending.
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TYPICAL APPLICATIO
Q1
VIN
3.3V
3.3V
2.5V
1.8V
3.3V
1V/DIV
10nF
VIN
138k
VCC
GATE
ON
100k
RAMP
FB1
IN
DC/DC
FB = 1.235V
35.7k
2923 TA02
16.5k
STATUS
VIN
16.5k
TRACK1
SDO
TRACK2
FB2
887k
412k
1ms/DIV
1.8V
LTC2923
RAMPBUF
13k
OUT
IN
DC/DC
FB = 0.8V
3.3V
2.5V
1.8V
OUT
1V/DIV
2.5V
GND
887k
412k
2923 TA01
1ms/DIV
2923 F08b
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LTC2923
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ABSOLUTE
RATI GS (Note 1)
Supply Voltage (VCC) ................................ – 0.3V to 10V
Input Voltages
ON ........................................................ – 0.3V to 10V
TRACK1, TRACK2 ...................... – 0.3V to VCC + 0.3V
RAMP ........................................... – 0.3V to VCC + 1V
Output Voltages
FB1, FB2, SDO, STATUS ........................– 0.3V to 10V
RAMPBUF ................................. – 0.3V to VCC + 0.3V
GATE (Note 2) ................................... – 0.3V to 11.5V
Average Current
TRACK1, TRACK2 .............................................. 5mA
FB1, FB2 ............................................................ 5mA
RAMPBUF ......................................................... 5mA
Operating Temperature Range
LTC2923C ............................................... 0°C to 70°C
LTC2923I ............................................ – 40°C to 85°C
Storage Temperature Range ................ – 65°C to 150°C
Lead Temperature (Soldering, 10 sec)
MS Package .................................................... 300°C
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PACKAGE/ORDER I FOR ATIO
ORDER PART
NUMBER
TOP VIEW
VCC
ON
TRACK1
TRACK2
RAMPBUF
1
2
3
4
5
10
9
8
7
6
RAMP
GATE
FB1
FB2
GND
MS PACKAGE
10-LEAD PLASTIC MSOP
TJMAX = 125°C, θJA = 120°C/W
LTC2923CMS
LTC2923IMS
VCC
1
12 RAMP
ON
2
11 GATE
TRACK1
3
LTC2923CDE
LTC2923IDE
10 STATUS
13
MS PART
MARKING
LTAED
LTAEE
ORDER PART
NUMBER
TOP VIEW
TRACK2
4
9
SDO
RAMPBUF
5
8
FB1
GND
6
7
FB2
DE PART
MARKING
DE12 PACKAGE
12-LEAD (4mm × 3mm) PLASTIC DFN
2923
TJMAX = 125°C, θJA = 43°C/W
EXPOSED PAD (PIN 13) INTERNALLY CONNECTED TO GND
(PCB CONNECTION OPTIONAL)
Consult LTC Marketing for parts specified with wider operating temperature ranges.
ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. 2.9V < VCC < 5.5V unless otherwise noted (Note 3).
SYMBOL
PARAMETER
VCC
Input Supply Range
ICC
Input Supply Current
CONDITIONS
MIN
TYP
MAX
UNITS
5.5
V
mA
mA
●
2.9
IFBx = 0, ITRACKx = 0
IFBx = –1mA, ITRACKx = –1mA,
IRAMPBUF = –2mA
●
●
5
1.3
7
3
10
VCC Rising
●
2.2
2.5
2.7
VCC(UVL)
Input Supply Undervoltage Lockout
∆VCC(UVLHYST)
Input Supply Undervoltage Lockout Hysteresis
∆VGATE
External N-Channel Gate Drive (VGATE – VCC)
IGATE = –1µA
●
5
5.5
6
IGATE
GATE Pin Current
Gate On, VGATE = 0V, No Faults
Gate Off, VGATE = 5V, No Faults
Gate Off, VGATE = 5V,
Short-Circuit Fault
●
●
●
–7
7
5
–10
10
20
–13
13
50
VON(TH)
ON Pin Threshold Voltage
VON Rising
●
1.212
1.230
1.248
∆VON(HYST)
ON Pin Hysteresis
●
30
75
150
25
V
mV
V
µA
µA
mA
V
mV
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LTC2923
ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. 2.9V < VCC < 5.5V unless otherwise noted (Note 3).
SYMBOL
PARAMETER
CONDITIONS
VON(FC)
ON Pin Fault Clear Threshold Voltage
ION
ON Pin Input Current
∆VDS(TH)
FET Drain-Source Overcurrent Voltage Threshold
(VCC – VRAMP)
IRAMP
RAMP Pin Input Current
0V < RAMP < VCC, VCC = 5.5V
●
0
±1
µA
VRAMPBUF(OL)
RAMPBUF Low Voltage
IRAMPBUF = 2mA
●
90
150
mV
VRAMPBUF(OH)
RAMPBUF High Voltage (VCC – VRAMPBUF)
IRAMPBUF = –2mA
●
100
200
mV
VOS
Ramp Buffer Offset (VRAMPBUF – VRAMP)
VRAMPBUF = VCC/2, IRAMPBUF = 0A
0
30
mV
IERROR(%)
IFBx to ITRACKx Current Mismatch
IERROR(%) = (IFBx – ITRACKx)/ITRACKx
ITRACKx = –10µA
ITRACKx = –1mA
●
●
0
0
±5
±5
%
%
VTRACKx
TRACK Pin Voltage
ITRACKx = –10µA
ITRACKx = –1mA
●
●
0.8
0.8
0.824
0.824
V
V
IFB(LEAK)
IFB Leakage Current
VFB = 1.5V, VCC = 5.5V
●
±1
±100
nA
VFB(CLAMP)
VFB Clamp Voltage
1µA < IFB < 1mA
●
1.7
2
V
VSDO(OL)
SDO Output Low Voltage
ISDO = 3mA
●
0.2
0.4
V
VSTATUS(OL)
STATUS Output Low Voltage
ISTATUS = 3mA
●
0.2
0.4
V
tPSC
Short-Circuit Propagation Delay VDS High
to GATE Low
VDS = VCC, VCC = 2.9V
10
20
µs
●
TYP
MAX
0.3
0.4
0.5
0
±100
nA
160
200
240
mV
●
VON = 1.2V, VCC = 5.5V
●
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: The GATE pin is internally limited to a minimum of 11.5V. Driving
this pin to voltages beyond the clamp may damage the part.
MIN
–30
0.776
0.776
1.5
UNITS
V
Note 3: All currents into the device pins are positive; all currents out of
device pins are negative. All voltages are referenced to ground unless
otherwise specified.
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TYPICAL PERFOR A CE CHARACTERISTICS
Specifications are at TA = 25°C unless otherwise noted.
VGATE vs VCC
VGATE vs IGATE
12
IGATE vs VCC Fast Pull-Down
15
30
VGATE = 5V
25
VCC = 5.5V
11
10
IGATE (mA)
20
VGATE (V)
VGATE (V)
10
VCC = 2.9V
5
15
10
9
5
0
8
2
3
4
VCC (V)
5
6
0
5
10
0
15
IGATE (µA)
2923 G01
2923 G02
0
1
2
3
VCC (V)
4
5
6
2923 G03
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LTC2923
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TYPICAL PERFOR A CE CHARACTERISTICS
Specifications are at TA = 25°C unless otherwise noted.
IGATE Fast Pull-Down
vs Temperature
ICC vs VCC
ITRACKx = IFBx = –1mA
IRAMPBUF = –2mA
ITRACKx = IFBx = 0mA
IRAMPBUF = 0mA
35
VCC = 5.5V
ICC vs VCC
8.0
1.5
40
1.4
7.9
1.3
7.8
ICC (mA)
IGATE (mA)
25
20
VCC = 2.9V
15
10
ICC (mA)
30
1.2
7.7
7.6
1.1
5
–25
0
50
25
TEMPERATURE (°C)
75
1.0
2.5
100
3
3.5
4.5
4
5
VTRACKx vs Temperature
VTRACKx (V)
VRAMPBUF(OL) (mV)
VCC = 5.5V
ITRACKx = 10µA
0.795
0.790
VCC = 2.9V
ITRACKx = 10µA
0.785
–50
–25
VCC = 2.9V
ITRACKx = 1mA
75
0
25
50
TEMPERATURE (°C)
130
110
120
100
VCC = 2.9V
90
VCC = 5.5V
80
110
VCC = 2.9V
100
90
VCC = 5.5V
80
70
60
–50
100
–25
0
25
50
TEMPERATURE (°C)
75
60
–50
100
VSDO(OL) vs VCC
16
Tracking Cell Error vs ITRACKx
VTRACKx = 0V
ERROR =
I
VTRACKx
• FBx – 1
0.8V
ITRACKx
4
14
13
ERROR (%)
ITRACKx (mA)
VSDO(OL) (V)
0.8
100
5
15
ISDO = 5mA
75
2923 G09
ITRACKx vs VCC
0.2
50
25
0
TEMPERATURE (°C)
–25
2923 G08
2923 G07
1.0
5.5
VRAMPBUF(OH) vs Temperature
120
70
0.6
5
2923 G06
VRAMPBUF(OL) vs Temperature
VCC = 5.5V
ITRACKx = 1mA
4.5
4
VCC (V)
2923 G05
0.810
0.800
3.5
3
VCC (V)
2923 G04
0.805
7.5
2.5
5.5
VRAMPBUF(OH) (mV)
0
–50
12
11
3
2
EXACTLY 2%
10
1
0.2
9
0
ISDO = 10µA
0
1
2
3
VCC (V)
4
5
2923 G11
8
3
3.5
4
4.5
VCC (V)
5
5.5
2923 G10
0
0
1
3
2
ITRACKx (mA)
4
5
2923 G12
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LTC2923
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PI FU CTIO S
MS/DE Packages
VCC (Pin 1): Positive Supply Input Pin. The operating
supply input range is 2.9V to 5.5V. An undervoltage
lockout circuit resets the part when the supply is below
2.5V. VCC should be bypassed to GND with a 0.1µF
capacitor.
ON (Pin 2): On Control Input. The ON pin has a threshold
of 1.23V with 75mV of hysteresis. An active high will cause
10µA to flow from the GATE pin, ramping up the supplies.
An active low pulls 10µA from the GATE pin, ramping the
supplies down. Pulling the ON pin below 0.4V resets the
electronic circuit breaker in the LTC2923. If a resistive
divider connected to VCC drives the ON pin, the supplies
will automatically start up when VCC is fully powered.
TRACK1, TRACK2 (Pins 3, 4): Tracking Control Input. A
resistive voltage divider between RAMPBUF and TRACKx
determines the tracking profile of a slave supply (see
Applications Information). TRACKx pulls up to 0.8V and
the current supplied at TRACKx is mirrored at FBx. TRACKx
is capable of supplying at least 1mA when VCC = 2.9V.
Because a TRACKx pin is capable of supplying up to 30mA
under short-circuit conditions, avoid connecting TRACKx
to GND for extended periods. Limit the capacitance at each
TRACKx pin to less than 25pF. Float the TRACKx pins if
unused.
RAMPBUF (Pin 5): Ramp Buffer Output. Provides a low
impedance buffered version of the signal on the RAMP pin.
This buffered output drives the resistive dividers that
connect to the TRACKx pins. Limit the capacitance at the
RAMPBUF pin to less than 100pF.
GND (Pins 6, 13): Circuit Ground.
FB1, FB2 (Pins 8, 7): Feedback Control Output. FBx pulls
up on the feedback node of slave supplies. Tracking is
achieved by mirroring the current from TRACKx into FBx.
If the appropriate resistive divider connects RAMPBUF
and TRACKx, the FBx current will force OUTx to track
RAMP. To prevent damage to the slave supply, the FBx pin
will not force the slave’s feedback node above 1.7V. In
addition, it will not actively sink current from this node
even when the LTC2923 is unpowered. Float the FB pins if
unused.
GATE (Pin 9/Pin 11): Gate Drive for External N-Channel
FET. When the ON pin is high, an internal 10µA current
source charges the gate of the external N-channel MOSFET. A capacitor connected from GATE to GND sets the
ramp rate. An internal charge pump guarantees that GATE
will pull up to 5V above VCC ensuring that logic level
N-channel FETs are fully enhanced. When the ON pin is
pulled low, the GATE pin is pulled to GND with a 10µA
current source. Under a short-circuit condition, the electronic circuit breaker in the LTC2923 pulls the GATE low
immediately with 20mA. Tie GATE to GND if unused. It is
a good practice to add a 10Ω resistor between this
capacitor and the FET’s gate to prevent high frequency FET
oscillations.
RAMP (Pin 10/Pin 12): Ramp Buffer Input. When the
RAMP pin is connected to the source of the external
N-channel FET, the slave supplies track the FET’s source
as it ramps up and down. If the GATE is fully enhanced
(GATE > RAMP + 4.9V) and (VCC – RAMP > 200mV)
indicates a shorted output, then the electronic circuit
breaker trips and GATE quickly pulls low with 20mA. The
GATE will not ramp up again until ON is pulled below 0.4V
and then above 1.23V. Alternatively, when no external FET
is used, the RAMP pin can be tied directly to the GATE pin.
In this configuration, the supplies track the capacitor on
the GATE pin as it is charged and discharged by the 10µA
current source controlled by the ON pin. RAMP must not
be driven above VCC (except by the GATE pin).
SDO (Pin 9, DE Package Only): Slave Supply Shutdown
Output. SDO is an open-drain output that holds the shutdown (RUN/SS) pins of the slave supplies low until the ON
pin is pulled above 1.23V. If the slave supply is capable of
operating with an input supply that is lower than the
LTC2923’s minimum operating voltage of 2.9V, the SDO
pin can be used to hold off the slave supplies. SDO will be
pulled low again when RAMP < 100mV and ON < 1.23V.
STATUS (Pin 10, DE Package Only): Power Good Status
Indicator. The STATUS pin is an open-drain output that
pulls low until GATE has been fully charged at which time
all supplies will have reached their final operating voltage.
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LTC2923
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FU CTIO AL BLOCK DIAGRA
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VCC
CHARGE
PUMP
10µA
2
ON
1.2V
0.4V
10
+
–
–
+
GATE
11 (9)
SHORT-CIRCUIT
FAULT LATCH
R
Q
S
Q
ONSIG
10µA
STATUS
GATE > RAMP + 4.9V
4.9V
GATE
RAMP > VCC
VCC
RAMP
12 (10)
+
–
VCC – RAMP > 200mV
0.2V
VCC
RAMP < 100mV
+
–
9
SDO
ONSIG
VCC < 2.6V
–
+
5
RAMPBUF
0.1V
VCC
2.6V
1×
VCC
3
TRACK1
+
–
0.8V
FB1
8
VCC
4
TRACK2
+
–
6
0.8V
FB2
GND
7
2923 FBD
PIN NUMBERS IN PARENTHESES CORRESPOND
TO THE 10-LEAD MSOP PACKAGE
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LTC2923
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APPLICATIO S I FOR ATIO
Power Supply Tracking and Sequencing
The LTC2923 handles a variety of power-up profiles to
satisfy the requirements of digital logic circuits including
FPGAs, PLDs, DSPs and microprocessors. These requirements fall into one of the four general categories illustrated in Figures 1 to 4.
Some applications require that the potential difference
between two power supplies must never exceed a specified voltage. This requirement applies during power-up
and power-down as well as during steady-state operation,
often to prevent destructive latch-up in a dual supply ASIC.
Typically, this is achieved by ramping the supplies up and
down together (Figure 1). In other applications it is desirable to have the supplies ramp up and down with fixed
voltage offsets between them (Figure 2) or to have them
ramp up and down ratiometrically (Figure 3).
Certain applications require one supply to come up after
another. For example, a system clock may need to start
before a block of logic. In this case, the supplies are
sequenced as in Figure 4 where the 2.5V supply ramps up
after the 1.8V supply is completely powered.
Operation
The LTC2923 provides a simple solution to all of the power
supply tracking and sequencing profiles shown in Figures
1 to 4. A single LTC2923 controls up to three supplies with
two “slave” supplies that track a “master” signal. With just
two resistors, a slave supply is configured to ramp up as
a function of the master signal. This master signal can be
a third supply that is ramped up through an external FET,
whose ramp rate is set with a single capacitor, or it can be
a signal generated by tying the GATE and RAMP pins to an
external capacitor.
MASTER
SLAVE1
SLAVE2
1V/DIV
1ms/DIV
MASTER
SLAVE1
SLAVE2
1V/DIV
1ms/DIV
2923 F01
Figure 1. Coincident Tracking
2923 F02
Figure 2. Offset Tracking
MASTER
SLAVE1
SLAVE1
1V/DIV
SLAVE2
1ms/DIV
Figure 3. Ratiometric Tracking
2923 F03
1V/DIV
SLAVE2
1ms/DIV
2923 F04
Figure 4. Supply Sequencing
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LTC2923
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APPLICATIO S I FOR ATIO
Tracking Cell
In a properly designed system, when the master signal has
reached its maximum voltage the current from the TRACKx
pin is zero. In this case, there is no current from the FBx pin
and the LTC2923 has no effect on the output voltage
accuracy, transient response or stability of the slave
supply.
The LTC2923’s operation is based on the tracking cell
shown in Figure 5, which uses a proprietary wide-range
current mirror. The tracking cell shown in Figure 5 servos
the TRACK pin at 0.8V. The current supplied by the TRACK
pin is mirrored at the FB pin to establish a voltage at the
output of the slave supply. The slave output voltage varies
with the master signal, enabling the slave supply to be
controlled as a function of the master signal with terms set
by RTA and RTB. By selecting appropriate values of RTA and
RTB, it is possible to generate any of the profiles in
Figures 1 to 4.
When the ON pin falls below VON(TH) – ∆VON(HYST), typically 1.225V, the GATE pin pulls down with 10µA and the
master signal and the slave supplies will fall at the same
rate as they rose previously.
The ON pin can be controlled by a digital I/O pin or it can
be used to monitor an input supply. By connecting a
resistive divider from an input supply to the ON pin, the
supplies will ramp up only after the monitored supply has
reached a preset voltage.
Controlling the Ramp-Up and Ramp-Down Behavior
The operation of the LTC2923 is most easily understood
by referring to the simplified functional diagram in Figure 6. When the ON pin is low, the GATE pin is pulled to
ground causing the master signal to remain low. Since the
currents through RTB1 and RTB2 are at their maximum
when the master signal is low, the currents from FB1 and
FB2 are also at their maximum. These currents drive the
slaves’ outputs to their minimum voltages.
Optional External FET
The Coincident Tracking Example (Figures 8 and 9) illustrates how an optional external N-channel FET can ramp
up a single supply that becomes the master signal. When
used, the FET’s gate is charged by the GATE pin and its
source is tied to the RAMP pin. Under normal operation,
the GATE pin sources or sinks 10µA to ramp the FET’s gate
up or down at a rate set by the external capacitor connected to the GATE pin. It is a good practice to add 10Ω
between the FET’s gate and the external capacitor to
prevent high frequency oscillations.
When the ON pin rises above 1.23V, the master signal
rises and the slave supplies track the master signal. The
ramp rate is set by an external capacitor driven by a 10µA
current source from an internal charge pump. If no external FET is used, the ramp rate is set by tying the RAMP and
GATE pins together at one terminal of the external capacitor (see the Ratiometric Tracking Example).
VCC
+
+
–
MASTER
0.8V
–
RTB
TRACK
DC/DC
FB
FB OUT
SLAVE
RTA
RFA
RFB
2923 F05
Figure 5. Simplified Tracking Cell
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LTC2923
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APPLICATIO S I FOR ATIO
VCC
RONB
ON
10µA
+
GATE
RONA
1.2V
–
CGATE
10µA
VCC
+–
Q1
+
200mV
–
RAMPBUF
RAMP
1×
MASTER
VCC
+
0.8V
–
RTB1
FB1
TRACK1
VCC
RTA1
DC/DC
RFA1
+
SLAVE1
RFB1
0.8V
–
RTB2
FB2
TRACK2
DC/DC
SLAVE2
RTA2
RFA2
RFB2
2923 F06
Figure 6. Simplified Functional Diagram
The LTC2923 features an electronic circuit breaker function that protects the optional series FET against short
circuits. When the FET is fully enhanced (GATE > RAMP +
4.9V), the electronic circuit breaker is enabled. Then, if the
voltage across the FET (VDS) exceeds 200mV as measured
from VCC to the RAMP pin for more than about 10µs the
gate of the FET is pulled down with 20mA, turning it off.
Because the slaved supplies track the RAMP pin, they are
pulled low by the tracking circuit when a short-circuit fault
occurs. Following a short-circuit fault, the FET is latched
off until the fault is cleared by pulling the ON pin below
0.4V.
Ramp Buffer
The RAMPBUF pin provides a buffered version of the
RAMP pin voltage that drives the resistive dividers on the
TRACKx pins. When there is no external FET, it provides up
to 2mA to drive the resistors even though the GATE pin
only supplies 10µA. The RAMPBUF pin also proves useful
in systems with an external FET. Since the track cell in the
simplified functional diagram above drives 0.8V on the
TRACKx pins, if RTBx is connected directly to the FET’s
source, the TRACKx pin could potentially pull up the FET’s
source towards 0.8V when the FET is off. RAMPBUF
blocks this path.
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LTC2923
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APPLICATIO S I FOR ATIO
Shutdown Output
In some applications it might be necessary to control the
shutdown or RUN/SS pins of the slave supplies using the
12-lead LTC2923CDE or LTC2923IDE. The LTC2923 may
not be able to supply the rated 1mA of current from the FB1
and FB2 pins when VCC is below 2.9V. If the slave power
supplies are capable of operating at low input voltages,
use the open-drain SDO output to drive the SHDN or
RUN/SS pins of the slave supplies (see Figure 7). This will
hold the slave supplies’ outputs low until the ON pin is
above 1.23V, VCC is above the 2.6V undervoltage lockout
condition and there are no short-circuit faults latched. It
pulls low again when the ON pin is pulled below 1.23V and
the RAMP pin is below about 100mV. When two supplies
Q1
VIN
3.3V
must have their RUN/SS or SHDN pins controlled independently, tie a Schottky diode between each pin and the SDO
output (see Figure 8).
Status Output
The STATUS pin provides an indication that the supplies
are finished ramping up. This pin is an open-drain output
that pulls low until the GATE has been fully charged. Since
the GATE pin drives the gate of the external FET, or the
RAMP pin directly when no FET is used, the supplies are
completely ramped up when the GATE pin is fully charged.
It will go low again when the GATE pin is pulled low, either
because of a short-circuit fault or because the ON pin has
been pulled low.
Q1
VIN
3.3V
3.3V
3.3V
0.1µF
0.1µF
10Ω
CGATE
10nF
10Ω
VIN
CGATE
10nF
VIN
RSTATUS
10k
RONB
138k
VCC
GATE
RAMP
RONA
100k
FB1
RONB
138k
VIN
STATUS
ON
RSTATUS
10k
RUN/SS IN
DC/DC
FB = 1.235V
VCC
OUT
RTA1
13k
1.8V
RFA1
35.7k
FB1
RFB1
16.5k
SDO
FB2
TRACK2
RTA2
412k
RUN/SS IN
DC/DC
FB = 1.235V
RUN/SS IN
DC/DC
FB = 0.8V
OUT
2.5V
RTA1
13k
OUT
1.8V
OUT
2.5V
RFA2
412k
RTB2
887k
TRACK1
SDO
FB2
TRACK2
RUN/SS IN
DC/DC
FB = 0.8V
GND
RFB2
887k
RFA2
412k
2923 F07
Figure 7
RFB1
16.5k
VIN
RTA2
412k
GND
RFA1
35.7k
RAMPBUF
RTB1
16.5k
VIN
RTB2
887k
VIN
LTC2923
RAMPBUF
TRACK1
RAMP
STATUS
RONA
100k
LTC2923
RTB1
16.5k
GATE
ON
RFB2
887k
2923 F08
Figure 8
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3-Step Design Procedure
The following 3-step procedure allows one to complete a
design for any of the tracking or sequencing profiles
shown in Figures 1 to 4. A basic three supply application
circuit is shown in Figure 9.
Note that large ratios of slave ramp rate to master ramp
rate, SS/SM, may result in negative values for RTA′. If
sufficiently large delay is used in step 3, RTA will be
positive, otherwise SS/SM must be reduced.
3. Choose RTA to obtain the desired delay.
1. Set the ramp rate of the master signal.
If no delay is required, such as in coincident and
ratiometric tracking, then simply set RTA = RTA′. If a
delay is desired, as in offset tracking and supply sequencing, calculate RTA′′ to determine the value of RTA
where tD is the desired delay in seconds.
Solve for the value of CGATE, the capacitor on the GATE
pin, based on the desired ramp rate (V/s) of the master
supply, SM.
CGATE =
IGATE
where IGATE ≈ 10µA
SM
(1)
RTA ′′ =
If the external FET has a gate capacitance comparable to
CGATE, then the external capacitor’s value should be
reduced to compensate for the FET’s gate capacitance.
If no external FET is used, tie the GATE and RAMP pins
together.
2. Solve for the pair of resistors that provide the desired
ramp rate of the slave supply, assuming no delay.
Choose a ramp rate for the slave supply, SS. If the slave
supply ramps up coincident with the master supply or
with a fixed voltage offset, then the ramp rate equals the
master supply’s ramp rate. Be sure to use a fast enough
ramp rate for the slave supply so that it will finish
ramping before the master supply has reached its final
supply value. If not, the slave supply will be held below
the intended regulation value by the master supply. Use
the following formulas to determine the resistor values
for the desired ramp rate, where RFB and RFA are the
feedback resistors in the slave supply and VFB is the
feedback reference voltage of the slave supply:
S
RTB = RFB • M
SS
(4)
RTA = RTA′||RTA′′
(5)
the parallel combination of RTA′ and RTA′′
As noted in step 2, small delays and large ratios of slave
ramp rate to master ramp rate (usually only seen in
sequencing) may result in solutions with negative values
for RTA. In such cases, either the delay must be increased
or the ratio of slave ramp rate to master ramp rate must be
reduced.
Q1
VIN
MASTER
0.1µF
10Ω
CGATE
VIN
RONB
VCC
GATE
ON
RONA
IN
DC/DC
RAMP
FB1
FB
OUT
SLAVE1
OUT
SLAVE2
LTC2923
RFA1
RAMPBUF
RFB1
VIN
RTB1
TRACK1
RTA1
(2)
VTRACK • RTB
tD • SM
IN
DC/DC
RTB2
TRACK2
RTA2
FB2
FB
GND
RFB2
RTA ′ =
VFB
RFB
VTRACK
V
V
+ FB – TRACK
RFA
RTB
RFA2
(3)
2923 F09
Figure 9. Three Supply Application
where VTRACK ≈ 0.8V.
2923fa
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APPLICATIO S I FOR ATIO
Coincident Tracking Example
MASTER
SLAVE2
SLAVE1
1V/DIV
1ms/DIV
1V/DIV
1ms/DIV
2923 F10a
2923 F10b
Figure 10. Coincident Tracking (from Figure 11)
A typical three supply application is shown in Figure 11. The
master signal is a 3.3V module. The slave 1 supply is a 1.8V
switching power supply and the slave 2 supply is a 2.5V
switching power supply. Both slave supplies track coincidently with the 3.3V supply that is controlled with an external FET. The ramp rate of the supplies is 1000V/s. The
3-step design procedure detailed previously can be used
to determine component values. Only the slave 1 supply is
considered here as the procedure is the same for the slave 2
supply.
1. Set the ramp rate of the master signal.
10µA
= 10nF
1000 V/s
2. Solve for the pair of resistors that provide the desired
slave supply behavior, assuming no delay.
From Equation 2:
RTB = 16.5kΩ •
1000 V/s
= 16.5kΩ
1000 V/s
From Equation 3:
RTA ′ =
0.8 V
≈ 13kΩ
1.235V 1.235V
0.8 V
+
–
16.5kΩ 35.7kΩ 16.5kΩ
3. Choose RTA to obtain the desired delay.
Since no delay is desired, RTA = RTA′
12
3.3V
MASTER
0.1µF
10Ω
CGATE
10nF
3.3V
RONB
138k
RONA
100k
RTB1
16.5k
RTA1
13k
VCC
GATE
ON
RAMP
FB1
RTB2
887k
IN
DC/DC
FB = 1.235V OUT
1.8V
SLAVE1
LTC2923
RFA1 RFB1 16.5k
35.7k 3.3V
RAMPBUF
TRACK1
FB2
IN
DC/DC
FB = 0.8V
OUT
TRACK2
RTA2
412k
From Equation 1:
CGATE =
Q1
3.3V
GND
RFA2
412k
2.5V
SLAVE2
RFB2
887k
2923 F11
Figure 11. Coincident Tracking Example
In this example, all supplies remain low while the ON pin
is held below 1.23V. When the ON pin rises above 1.23V,
10µA pulls up CGATE and the gate of the FET at 1000V/s. As
the gate of the FET rises, the source follows and pulls up
the output to 3.3V at 1000V/s. This output serves as the
master signal and is buffered from the RAMP pin to the
RAMPBUF pin. As this output and the RAMPBUF pin rise,
the current from the TRACK pins is reduced. Consequently, the voltage at the slave supply’s outputs increases, and the slave supplies track the master supply.
When the ON pin is again pulled below 1.23V, 10µA will
pull down CGATE and the gate of the FET at 1000V/s. If the
loads on the outputs are sufficient, all outputs will track
down coincidently at 1000V/s.
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Ratiometric Tracking Example
SLAVE2
SLAVE1
1V/DIV
1ms/DIV
1V/DIV
1ms/DIV
2923 F12a
2923 F12b
Figure 12. Ratiometric Tracking (from Figure 13)
This example converts the coincident tracking example to
the ratiometric tracking profile shown in Figure 12, using
two supplies without an external FET. The ramp rate of the
master signal remains unchanged (Step 1) and there is no
delay in ratiometric tracking (Step 3), so only the result of
step 2 in the 3-step design procedure needs to be considered. In this example, the ramp rate of the 1.8V slave 1
supply ramps up at 600V/s and the 2.5V slave 2 supply
ramps up at 850V/s. Always verify that the chosen ramp
rate will allow the supplies to ramp-up completely before
RAMPBUF reaches VCC. If the 1.8V supply were to rampup at 500V/s it would only reach 1.65V because the
RAMPBUF signal would reach its final value of VCC = 3.3V
before the slave supply reached 1.8V.
2. Solve for the pair of resistors that provide the desired
slave supply behavior, assuming no delay.
From Equation 2:
1000 V/s
RTB = 16.5kΩ •
≈ 27.4kΩ
600 V/s
From Equation 3:
RTA ′ =
0.8 V
= 10kΩ
1.235V 1.235V
0.8 V
+
–
16.5kΩ 35.7kΩ 27.5kΩ
Step 3 is unnecessary because there is no delay, so
RTA = RTA′.
3.3V
CGATE
10nF
0.1µF
RONB
138k
VCC GATE
ON
RONA
100k
RAMP
FB1
IN
DC/DC
FB = 1.235V OUT
1.8V
SLAVE1
LTC2923
RFA1 RFB1
35.7k 16.5k
3.3V
RAMPBUF
RTB1
27.4k
RTA1
10k
3.3V
RTB2
1M
TRACK1
FB2
TRACK2
RTA2
383k
IN
DC/DC
FB = 0.8V
OUT
2.5V
SLAVE2
GND
RFA2
412k
RFB2
887k
2923 F13
Figure 13. Ratiometric Tracking Example
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Offset Tracking Example
MASTER
SLAVE2
SLAVE1
1V/DIV
1ms/DIV
1V/DIV
1ms/DIV
2923 F14a
2923 F14b
Figure 14. Offset Tracking (from Figure 15)
Converting the circuit in the coincident tracking example
to the offset tracking shown in Figure 14 is relatively
simple. Here the 1.8V slave 1 supply ramps up 1V below
the master. The ramp rate remains the same (1000V/s), so
there are no changes necessary to steps 1 and 2 of the
3-step design procedure. Only step 3 must be considered.
Be sure to verify that the chosen voltage offsets will allow
the slave supplies to ramp up completely. In this example,
if the voltage offset were 2V, the slave supply would only
ramp up to 3.3V – 2V = 1.3V.
3. Choose RTA to obtain the desired delay.
First, convert the desired voltage offset, VOS, to a delay,
tD, using the ramp rate:
tD =
VOS
1V
=
= 1ms
SS 1000 V/s
(6)
Q1
3.3V
MASTER
3.3V
0.1µF
10Ω
CGATE
10nF
3.3V
RONB
138k
RONA
100k
GATE
RAMP
FB1
RTB2
887k
1.8V
SLAVE1
RFA1 RFB1
35.7k 16.5k
3.3V
TRACK1
FB2
TRACK2
RTA2
316k
IN
DC/DC
FB = 1.235V OUT
LTC2923
RAMPBUF
RTB1
16.5k
RTA1
6.65k
VCC
ON
IN
DC/DC
FB = 0.8V
OUT
GND
RFA2
412k
2.5V
SLAVE2
RFB2
887k
2923 F15
Figure 15. Offset Tracking Example
From Equation 4:
RTA ′′ =
0.8 V • 16.5kΩ
= 13.2kΩ
1ms • 1000 V/s
From Equation 5:
RTA = 13.1kΩ||13.2kΩ ≈ 6.65kΩ
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Supply Sequencing Example
MASTER
SLAVE2
SLAVE1
1V/DIV
10ms/DIV
1V/DIV
10ms/DIV
2923 F16a
2923 F16b
Figure 16. Supply Sequencing (from Figure 17)
In Figure 16, the slave 1 supply and the slave 2 supply are
sequenced instead of tracking. The 3.3V supply ramps up
at 100V/s with an external FET and serves as the master
signal. The 1.8V slave 1 supply ramps up at 1000V/s
beginning 10ms after the master signal starts to ramp up.
The 2.5V slave 2 supply ramps up at 1000V/s beginning
25ms after the master signal begins to ramp up. Note that
not every combination of ramp rates and delays is possible. Small delays and large ratios of slave ramp rate to
master ramp rate may result in solutions that require
negative resistors. In such cases, either the delay must be
increased or the ratio of slave ramp rate to master ramp
rate must be reduced. In this example, solving for the
slave 1 supply yields:
1. Set the ramp rate of the master signal.
From Equation 3:
RTA ′ =
0.8 V
= –2.13kΩ
1.235V 1.235V
0.8 V
–
+
16.5kΩ 35.7kΩ 1.65kΩ
3. Choose RTA to obtain the desired delay.
From Equation 4:
RTA ′′ =
0.8 V • 1.65kΩ
= 1.32kΩ
10ms • 100 V/s
From Equation 5:
RTA = – 2.13kΩ||1.32kΩ = 3.48kΩ
Q1
From Equation 1:
0.1µF
10Ω
CGATE =
10µA
= 100nF
100 V/s
100 V/s
RTB = 16.5kΩ •
= 1.65kΩ
1000 V/s
CGATE
100nF
3.3V
RONB
138k
2. Solve for the pair of resistors that provide the desired
slave supply behavior, assuming no delay.
From Equation 2:
3.3V
MASTER
3.3V
RONA
100k
GATE
ON
RAMP
FB1
RTB2
88.7k
IN
DC/DC
FB = 1.235V OUT
RFA1 RFB1 16.5k
35.7k
3.3V
TRACK1
FB2
IN
DC/DC
FB = 0.8V
OUT
TRACK2
RTA2
36.5k
1.8V
SLAVE1
LTC2923
RAMPBUF
RTB1
1.65k
RTA1
3.48k
VCC
GND
2.5V
SLAVE2
2923 F17
RFA2
412k
RFB2
887k
Figure 17. Supply Sequencing Example
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Final Sanity Checks
The collection of equations below is useful for identifying
unrealizable solutions.
As stated in step 2, the slave supply must finish ramping
before the master signal has reached its final voltage. This
can be verified by the following equation:
⎛ R ⎞
VTRACK ⎜ 1 + TB ⎟ < VCC, where VTRACK = 0.8 V
⎝ RTA ⎠
It is possible to choose resistor values that require the
LTC2923 to supply more current than the Electrical Characteristics table guarantees. To avoid this condition, check
that ITRACKx does not exceed 1mA and IRAMPBUF does not
exceed ±2mA.
To confirm that ITRACKx < 1mA, the TRACKx pin’s maximum guaranteed current, verify that:
VTRACK
< 1mA
RTA RTB
Finally, check that the RAMPBUF pin will not be forced to
sink more then 2mA when it is at 0V or be forced to source
more than 2mA when it is at VCC.
VTRACK VTRACK
+
< 2mA and
RTB1
RTB2
VCC
VCC
+
< 2mA
RTA1 + RTB1 RTA2 + RTB2
Caution with Boost and Linear Regulators
Note that the LTC2923’s tracking cell is not able to control
the outputs of all types of power supplies. If it is necessary
to control one of these types of supplies, where the output
is not controllable through its feedback node, the series
FET can be used to control one supply’s output. For
example, boost regulators commonly contain an inductor
and diode between the input supply and the output supply
providing a DC current path when the output voltage falls
below the input voltage. Therefore, the LTC2923’s tracking cell will not effectively drive the supply’s output below
the input.
Special caution should be taken when considering the use
of linear regulators. Three-terminal linear regulators have
a reference voltage that is referred to the output supply
rather than to ground. In this case, driving current into the
regulator’s feedback node will cause its output to rise
rather than fall. Even linear regulators that have their
reference voltage referred to ground, including low dropout regulators (LDOs), may be problematic. Linear regulators commonly contain circuitry that prevents driving
their outputs below their reference voltage. This may not
be obvious from the data sheets, so lab testing is recommended whenever the LTC2923’s tracking cell is used to
control linear regulators.
Load Requirements
When the supplies are ramped down quickly, either the
load or the supply itself must be capable of sinking enough
current to support the ramp rate. For example, if there is
a large output capacitance on the supply and a weak
resistive load, supplies that do not sink current will have
their falling ramp rate limited by the RC time constant of
the load and the output capacitance. Figure 18 shows the
case when the 2.5V supply does not track the 1.8V and
3.3V supplies near ground.
Start-Up Delays
Often power supplies do not start-up immediately when
their input supplies are applied. If the LTC2923 tries to
ramp-up these power supplies as soon as the input supply
is present, the start-up of the outputs may be delayed,
defeating the tracking circuit (Figure 19). Often this delay
is intentionally configured by a soft-start capacitor. This
can be remedied either by reducing the soft-start capacitor
on the slave supply or by including a capacitor in the ON
pin’s resistive divider to delay the ramp up. See Figure 20.
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Layout Considerations
MASTER
SLAVE2
1V/DIV
SLAVE1
1ms/DIV
2923 F18
Figure 18. Weak Resistive Load
MASTER
SLAVE1
1V/DIV
SLAVE2
Be sure to place a 0.1µF bypass capacitor as near as
possible to the supply pin of the LTC2923. A 10Ω resistor
located near the FET and connected between the FET’s
gate and the external CGATE capacitor is recommended.
This will almost assuredly eliminate the troublesome high
frequency oscillations that can occur due to the FET
interacting with PCB parasitics.
To minimize the noise on the slave supplies’ outputs, keep
the traces connecting the FBx pins of the LTC2923 and the
feedback nodes of the slave supplies as short as possible.
In addition, do not route those traces next to signals with
fast transition times. In some circumstances it might be
advantageous to add a resistor near the feedback node of
the slave supply in series with the FBx pin of the LTC2923.
This resistor must not exceed:
1.5V – VFB ⎛ 1.5V ⎞
– 1⎟ (RFA || RFB)
=⎜
⎝ VFB
⎠
IMAX
This resistor is most effective if there is already a capacitor
at the feedback node of the slave supply (often a compensation component). Increasing the capacitance on a slave
supply’s feedback node will further improve the noise
immunity, but could affect the stability and transient
response of the supply.
RSERIES =
ON
1ms/DIV
2923 F19
Figure 19. Power Supply Start-Ups Delayed
10Ω
MASTER
FET
VCC
CGATE
OUT
SLAVE1
1V/DIV
SLAVE2
LTC2923
RAMP
VCC
GATE
RSERIES
FB1
GND
ON
MINIMIZE
TRACE
LENGTH
DC/DC
FB
OUT
RFA
RFB
0.1µF
2923 F21
1ms/DIV
Figure 20. ON Pin Delayed
2923 F20
Figure 21. Layout Considerations
2923fa
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LTC2923
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PACKAGE DESCRIPTIO
MS Package
10-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1661)
0.889 ± 0.127
(.035 ± .005)
5.23
(.206)
MIN
3.20 – 3.45
(.126 – .136)
3.00 ± 0.102
(.118 ± .004)
(NOTE 3)
0.50
0.305 ± 0.038
(.0197)
(.0120 ± .0015)
BSC
TYP
RECOMMENDED SOLDER PAD LAYOUT
0.254
(.010)
10 9 8 7 6
3.00 ± 0.102
(.118 ± .004)
(NOTE 4)
4.90 ± 0.152
(.193 ± .006)
DETAIL “A”
0.497 ± 0.076
(.0196 ± .003)
REF
0° – 6° TYP
GAUGE PLANE
1 2 3 4 5
0.53 ± 0.152
(.021 ± .006)
DETAIL “A”
1.10
(.043)
MAX
0.86
(.034)
REF
0.18
(.007)
SEATING
PLANE
0.17 – 0.27
(.007 – .011)
TYP
0.50
(.0197)
NOTE:
BSC
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
0.127 ± 0.076
(.005 ± .003)
MSOP (MS) 0603
2923fa
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LTC2923
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PACKAGE DESCRIPTIO
DE Package
12-Lead Plastic DFN (4mm × 3mm)
(Reference LTC DWG # 05-08-1695)
0.65 ±0.05
3.50 ±0.05
1.70 ±0.05
2.20 ±0.05 (2 SIDES)
PACKAGE OUTLINE
0.25 ± 0.05
3.30 ±0.05
(2 SIDES)
0.50
BSC
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
4.00 ±0.10
(2 SIDES)
7
R = 0.115
TYP
0.38 ± 0.10
12
R = 0.20
TYP
PIN 1
TOP MARK
(NOTE 6)
3.00 ±0.10
(2 SIDES)
1.70 ± 0.10
(2 SIDES)
PIN 1
NOTCH
(UE12/DE12) DFN 0603
0.200 REF
0.75 ±0.05
0.00 – 0.05
6
0.25 ± 0.05
3.30 ±0.10
(2 SIDES)
1
0.50
BSC
BOTTOM VIEW—EXPOSED PAD
NOTE:
1. DRAWING PROPOSED TO BE A VARIATION OF VERSION
(WGED) IN JEDEC PACKAGE OUTLINE M0-229
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
2923fa
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
19
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TYPICAL APPLICATIO S
Daisy-Chained Application
High Voltage Supply Application
3.3V
3.3V
0.1µF
0.1µF
GATE
VCC
ON
FB1
IN
DC/DC
FB = 1.235V OUT
CGATE
10nF
3.3V
SLAVE1
RONB
138k
LTC2923
RFB1
RFA1
RAMPBUF
RONA
100k
VCC GATE
ON
RAMP
FB1
TRACK1
RTB2
FB2
TRACK2
GND
RTA2
IN
DC/DC
FB = 0.8V
OUT
RFA1
RAMPBUF
RAMP
TRACK1
RTA1
RTB2
FB2
TRACK2
RTA2
RFA2
IN
DC/DC
FB = 0.8V
OUT
RFA2
0.1µF
RAMP
ON
RFB2
2923 TA04
CGATE
10nF
RONA
100k
5V
SLAVE2
GND
3.3V
VCC GATE
RFB1
RTB1
2.5V
SLAVE2
RFB2
RONB
138k
12V
SLAVE1
LTC2923
RTB1
RTA1
IN
DC/DC
FB = 1.235V OUT
FB1
IN
DC/DC
FB = 1.235V OUT
1.8V
SLAVE1
LTC2923
RFB
RFA
RAMPBUF
RTB
TRACK1
RTA
RTB
FB2
TRACK2
RTA
IN
DC/DC
FB = 0.8V
OUT
1.5V
SLAVE2
GND
RFB
RFA
2923 TA03
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
TM
LTC1645
Dual Hot Swap Controller
Operates from 1.2V to 12V, Allows Supply Sequencing
LTC2920
Power Supply Margining Controller
Single or Dual Versions, Symmetric as Symmetric High and Low Margining
LTC2921/LTC2922
Power Supply Tracker with Input Monitors
Includes 3 (LTC2921) or 5 (LTC2922) Remote Sense Switches
LTC2925
Multiple Power Supply Tracking Controller
Up to 4 Supplies, Status and Fault Pins, Slave Supply Shutdown, Remote
Sense Switch
LT®4220
Dual Supply Hot Swap Controller
±2.7V to ±16.5V, Supply Tracking Mode
LTC4230
Triple Hot Swap Controller with Multifunction
Current Control
1.7V to 16.5V, Active Inrush Limiting, Fast Comparator
LTC4253
– 48V Hot Swap Controller and Supply Sequencer
Floating Supply from –15V, Active Current Limiting,
Enables Three DC/DC Converters
Hot Swap is a trademark of Linear Technology Corporation.
2923fa
20
Linear Technology Corporation
LT/TP 1104 1K REV A • PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507
●
www.linear.com
© LINEAR TECHNOLOGY CORPORATION 2003