FEDL228XX-05 Issue Date: Oct. 10, 2013 ML2282X-XXX/ML2286X-XXX Speech Synthesis LSI with Built-in P2ROM Including 2-Channel Mixing Function GENERAL DESCRIPTION ML2282X(ML22825/ML22824/ML22823-XXX) and ML2286X (ML22865/ML22864/ML22863-XXX) are voice synthesis LSIs with built-in P2ROM that stores speech data. These LSIs include edit ROM, ADPCM2 decoder, 16-bit DA converter, low pass filter and monaural speaker amplifier. Also, ML2282X supports the synchronous serial interface and ML22865/ML22864/ML22863 supports the I2C interface. By integrating all the functions required for voice output into a single chip, these LSIs can be more easily incorporated in compact portable devices. • Built-in memory capacity and maximum vocal reproduction time: (at the case of 4-bit ADPCM2 algorithm) Product name ROM capacity ML22825-XXX/ML22865 ML22824-XXX/ML22864 ML22823-XXX/ML22863 16 Mbits 8 Mbits 4 Mbits Maximum vocal reproduction time (sec) FS = 8.0 kHz FS = 16 kHz FS = 4.0 kHz 1,044 522 261 520 260 130 258 129 64 • Voice synthesis method: 4-bit ADPCM2 8-bit Nonlinear PCM 8-bit PCM , 16-bit PCM Can be specified for each phrase. • Sampling frequency(Fs): 4.0 / 5.3 / 6.4 / 8.0 / 10.6 / 12.0 / 12.8 / 16.0 / 21.3 / 24.0 / 25.6 / 32.0 / 48.0 kHz fs can be specified for each phrase. • Built-in low-pass filter and 16-bit DA converter • Speaker driving amplifier: 0.7 W (when 8Ω , DVDD=5 V, Ta=25°C) 2ch analog input (internal: 1ch; external: 1ch) • CPU command interface: 3-wired serial clock-synchronized (ML2282X) I2C interface (ML2286X) • Maximum number of phrases: 4,096 phrases from 000h to 3FFh (1024 phrases/bank) • Memory bank switching: Enabled between bank 1 and bank 4 using the SEL0 and SEL1 pins • Volume control: 32 levels (OFF is included) can be set by CVOL command. 50 levels (OFF is included) can be set by AVOL command • Repeat function: LOOP commands • 2-channel mixing function: Available except case using 32kHz as sampling frequencys • Source oscillation frequency: 4.096 MHz • Power supply voltage: 2.7 to 3.6V / 4.5 to 5.5 V • Operating temperature range: –40 to +85°C • Package: 30-pin plastic SSOP (SSOP30-P-56-0.65-K-MC) • Product name: ML22825-xxxMB, ML22824-xxxMB, ML22823-xxxMB ML22865-xxxMB, ML22864-xxxMB, ML22863-xxxMB (xxx: ROM code No.) 1/63 FEDL228XX-05 ML2282X-XXX/ ML2286X -XXX The following table shows the differences among the other speech synthesis LSIs. Parameter CPU interface Playback method ← ML22825/ML22824/ ML22823-XXX ← ML22865/ML22864/ ML22863-XXX I2C ← ← ← 1,024 (256/bank) 4,096 (1,024/bank) ← ← 4.0/5.3/6.4/8.0/ 10.6/12.0/12.8/ 16.0/21.3/24.0/ 25.6/32.0/48.0 ← ML2216 ML22800 series Serial 4-bit ADPCM2 8-bit nonlinear PCM 8-bit straight PCM 16-bit straight PCM 256 Maximum number of phrases 4.0/5.3/6.4/ 8.0/10.6/12.8 16.0 Sampling frequency (kHz) Clock frequency DA converter Low-pass filter Speaker driving amplifier Edit ROM function Simultaneous sound production function (mixing function) Volume control Silence insertion Repeat function Interval at which a seam is silent during continuous playback (Note) Memory bank switching Power supply voltage Package 4.096MHz (with a built-in crystal oscillator circuit) 12 bits 3rd order comb filter Built-in 0.3W (8Ω, DVDD = 5 V) Yes ← ← ← 12 bits 3rd order comb filter ← ← ← 16 bits FIR interpolation filter Built-in 0.7W (8Ω, DVDD = 5 V) ← No ← 2-channel ← 16 levels Yes 20 ms to 1024 ms (4 ms/step) Yes ← 32 levels ← ← ← ← ← ← ← No ← ← ← No Yes ← ← 2.7 V to 5.5 V 2.7 V to 3.6 V 44-pin QFP 30-pin SSOP 2.7 to 3.6V 4.5 to 5.5 V ← 2.7 to 3.6V 4.5 to 5.5 V ← No ← ← *1: Continuous playback as shown below is possible. 1 phrase 1 phrase No silence interval 2/63 FEDL228XX-05 ML2282X-XXX/ ML2286X -XXX BLOCK DIAGRAMS (ML22825/ML22824/ML22823-XXX : Synchronous serial interface) DVDD DGND Multiplexer Address Controller 16/8/4Mbit ROM VDDL VDDR CSB SCK SI SO CBUSYB DIPH SEL0 SEL1 TESTI0,1 TESTO RESETB XT XTB Phrase Address Latch ADPCM Synthesizer Address Counter PCM Synthesizer I/O Interface LPF Timing Controller 16bit DAC SP-AMP OSC PLL SPVDD SPGND SPM SPP AIN (ML22865/ML22864/ML22863-XXX : I2C interface) DVDD DGND Multiplexer Address Controller 16/8/4Mbit ROM VDDL VDDR Phrase Address Latch ADPCM Synthesizer Address Counter SDA2-0 SCL SDA CBUSYB SEL0 SEL1 TESTI0,1 TESTO RESETB XT XTB PCM Synthesizer I/O Interface LPF Timing Controller 16bit DAC SP-AMP OSC PLL SPVDD SPGND SPM SPP AIN 3/63 FEDL228XX-05 ML2282X-XXX/ ML2286X -XXX PIN CONFIGURATIONS (TOP VIEW) (ML22825/ML22824/ML22823-XXXMB : Synchronous serial interface) AIN TESTI0 RESETB TESTO DIPH SEL0 SEL1 DGND CSB SCK SI SO CBUSYB DGND XT 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SPM SPP SPGND SPVDD DGND SG TESTI1 VDDR DVDD VDDL NC DGND NC DVDD XTB NC: No Connection 30-Pin Plastic SSOP (ML22865/ML22864/ML22863-XXXMB : I2C interface) AIN TESTI0 RESETB TESTO SAD0 SEL0 SEL1 DGND SAD1 SCL SDA SAD2 CBUSYB DGND XT 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 SPM SPP SPGND SPVDD DGND SG TESTI1 VDDR DVDD VDDL NC DGND NC DVDD XTB NC: No Connection 30-Pin Plastic SSOP 4/63 FEDL228XX-05 ML2282X-XXX/ ML2286X -XXX PIN DESCRIPTION (COMMON TO ALL PRODUCTS) Initial value Description (*1) 0 Input pin for speaker amplifier. Input pin for testing. 0 Fix this pin to “L” level (DGND level). This pin has a pull-down resistor built in. Input pin for reset. At the “L” level, the LSI enters initial state. During reset, the entire circuitry stops and enters power down state. Input “L” level when power is 0 supplied. After the power supply voltage is stable, drive this pin to “H” (*2) level. Then the entire circuitry can be powered up. This pin has a pull-up resistor built in. Output pins for testing. Hi-Z Leave these pins open. Memory bank switching pins. 0 Fix these pins to “L” level when the memory bank function is not used. Pin Symbol I/O 1 AIN I 2 TESTI0 I 3 RESETB I 4 TESTO O 6, 7 SEL0 SEL1 I 8, 14, 19, 26 DGND — — 13 CBUSYB O 1 15 XT I 0 16 XTB O 1 17, 22 DVDD — — 18, 20 N.C — — 21 VDDL — 0 23 VDDR — 0 24 TESTI1 — 0 25 SG — 0 27 SPVDD — — 28 SPGND — — 29 SPP O 0 30 SPM O Hi-Z Digital ground pin. Also serves as a ground pin for the internal memory. Output pin for command processing status. This pin outputs “L” level during command processing. Any command should be entered when this pin is “H” level. Connect to the crystal or ceramic resonator. A feedback resistor around 1 MΩ is built in between this pin and the XTB pin. Use this pin if need to use an external clock. If the resonator is used, connect it as close to this pin as possible. Connect to the crystal or ceramic resonator. When to use an external clock, leave this pin open. If the resonator is used, connect it as close to this pin as possible. Power supply pins for logic circuitry. Connect a capacitor of 0.1μF or more between these pins and DGND pins. Non connected pins. Leave these pins open. Regulator output pin for internal logic circuitry. Connect a capacitor recommended between this pin and DGND pin. Regulator output pin for Built-in ROM. Connect a capacitor recommended between this pin and DGND pin. Test pin. Fix this pin to a DGND level. Reference voltage output pin for the speaker amplifier built-in. Connect a capacitor recommended between this pin and DGND pin. Power supply pin for the speaker amplifier. Connect a bypass capacitor of 0.1μF or more between this pin and SPGND pin. Ground pin for the speaker amplifier. Positive(+) output pin of the speaker amplifier built-in. Serves as the LINE output (*3), if built-in speaker amplifier is not used. Negative(-) output pin of the speaker amplifier built-in. *1: Indicates the initial value during reset input or power down. *2: “H” during power down. *3: Outputs a voice signal before amplified by the speaker amplifier built-in. 5/63 FEDL228XX-05 ML2282X-XXX/ ML2286X -XXX PIN DESCRIPTION (FOR ML2282X SYNCHRONOUS SERIAL INTERFACE) Pin Symbol I/O Initial value (*1) 5 DIPH I 0 9 CSB I 1 10 SCK I 0 11 SI I 0 12 SO O Hi-Z Description Set pin of the SCK clock edge. When this pin is “L” level, rising edge is available for input(SI) and falling edge is available for output(SO). When this pin is “H” level, falling edge is available for input(SI) and rising edge is available for output(SO). Chip select pin. At the “L” level, data input/output is available. Synchronous clock input pin for serial interface. Input pin of synchronous serial data. When the DIPH pin is “L” level, data is shifted in at the rising edges of the SCK clock pulses. When the DIPH pin is “H” level, data is shifted in at the falling edges of the SCK clock pulses. Output pin of synchronous serial data. When the DIPH pin is “L” level, data is output at the falling edges of the SCK clock pulses. When the DIPH pin is “H” level, data is output at the rising edges of the SCK clock pulses. When the CSB pin is “H” level, this pin is Hi-Z state. *1: Indicate the initial value during reset or power down. PIN DESCRIPTION (FOR ML2286X I2C INTERFACE) Pin Symbol I/O Initial value (*1) 5, 9, 12 SAD0 SAD1 SAD2 I 0 10 SCL I 1 11 SDA IO 1 Description Set pin of the slave address. Clock input pin for I2C serial interface. This pin should be connected to pull-up resistor. Input/output pin for I2C serial data. Use for setting the mode of write/read and writing address, writing data or reading data. This pin should be connected to pull-up resistor. (N-ch MOS) open drain, when output mode. High impedance(Hi-Z), when input mode. *1: Indicate the initial value during reset or power down. 6/63 FEDL228XX-05 ML2282X-XXX/ ML2286X -XXX ABSOLUTE MAXIMUM RATINGS Parameter Power supply voltage Input voltage Power dissipation Output short-circuit current Storage temperature Symbol DVDD, SPVDD VIN PD IOS TSTG Condition (DGND = SPGND = 0 V, Ta = 25°C) Rating Unit −0.3 to +7.0 — V −0.3 to DVDD+0.3 V 938 mW Applies to all pins except SPM, SPP, VDDL, and VDDR. 10 mA Applies to SPM and SPP pins. 300 mA 50 mA −55 to +150 °C — Applies to VDDL and VDDR pins. — RECOMMENDED OPERATING CONDITIONS Parameter (DGND = SPGND = 0 V) Unit Symbol Condition Range Power supply voltage DVDD, SPVDD — 2.7 to 3.6 4.5 to 5.5 Operating temperature TOP — Master clock frequency fOSC — External capacitors for crystal oscillator Cd, Cg — V −40 to +85 °C Min. Typ. Max. 3.5 4.096 4.5 15 30 45 MHz pF 7/63 FEDL228XX-05 ML2282X-XXX/ ML2286X -XXX ELECTRICAL CHARACTERISTICS DC Characteristics (for the 3V applications) Parameter “H” input voltage “L” input voltage “H” output voltage 1 “H” output voltage 2 (*1) “L” output voltage 1 “L” output voltage 2 (*1) “L” output voltage 3 (*2) “H” input current 1 “H” input current 2 (*3) “H” input current 3 (*4) “L” input current 1 “L” input current 2 (*3) “L” input current 3 (*5) “H” output leak current 3 (*6) “L” output leak current 3 (*6) Supply current during playback Power-down supply current Symbol VIH VIL VOH1 VOH2 VOL1 VOL2 VOL3 IIH1 IIH2 IIH3 IIL1 IIL2 IIL3 DVDD = SPVDD = 2.7 to 3.6 V, DGND = AGND = 0 V, Ta = −40 to +85°C Condition Min. Typ. Max. Unit — 0.86×DVDD — DVDD V — 0 — 0.14×DVDD V IOH = −1 mA DVDD−0.4 — — V IOH = −50 µA DVDD−0.4 — — V IOL = 2 mA — — 0.4 V IOL = 50 µA — — 0.4 V IOL = 3 mA — — 0.4 V VIH = DVDD — — 10 µA VIH = DVDD 0.3 2.0 15 µA VIH = DVDD 2 30 200 µA VIL = GND −10 — — µA VIL = GND −15 −2.0 −0.3 µA VIL = GND −200 −30 −2 µA IILOH VOH = DVDD — — 10 µA IILOL VOL = GND −10 — — µA — — 20 mA — — 1 1 10 20 µA µA IDD IDDS fOSC = 4.096 MHz No output load Ta = −40 to +40°C Ta = −40 to +85°C *1: Applies to the XTB pin. *2: Applies to the SCL, SDA pin. *3: Applies to the XT pin. *4: Applies to the TESTI0 pin. *5: Applies to the RESETB pin. *6: Applies to the TESTO pin. 8/63 FEDL228XX-05 ML2282X-XXX/ ML2286X -XXX DC Characteristics (for the 5V applications) Parameter “H” input voltage “L” input voltage “H” output voltage 1 “H” output voltage 2 (*1) “L” output voltage 1 “L” output voltage 2 (*1) “L” output voltage 3 (*2) “H” input current 1 “H” input current 2 (*3) “H” input current 3 (*4) “L” input current 1 “L” input current 2 (*3) “L” input current 3 (*5) “L” output leak current 2 (*6) “L” output leak current 3 (*6) Supply current during playback Power-down supply current Symbol VIH VIL VOH1 VOH2 VOL1 VOL2 VOL3 IIH1 IIH2 IIH3 IIL1 IIL2 IIL3 DVDD = SPVDD = 4.5 to 5.5 V, DGND = SPGND = 0 V, Ta = −40 to +85°C Condition Min. Typ. Max. Unit — 0.8×DVDD — DVDD V — 0 — 0.2×DVDD V IOH = −1 mA DVDD−0.4 — — V IOH = −50µA DVDD−0.4 — — V IOL = 2 mA — — 0.4 V IOL = 50 µA — — 0.4 V IOL = 3 mA — — 0.4 V VIH = DVDD — — 10 µA VIH = DVDD 0.8 5.0 20 µA VIH = DVDD 20 100 400 µA VIL = GND −10 — — µA VIL = GND −20 −5.0 −0.8 µA VIL = GND −400 −100 −20 µA IILOH VOH = DVDD — — 10 µA IILOL VOL = GND −10 — — µA — — 25 mA — — 1 1 15 30 µA µA IDD IDDS fOSC = 4.096 MHz No output load Ta = −20 to +40°C Ta = −20 to +85°C *1: Applies to the XTB pin. *2: Applies to the SCL and SDA pins. *3: Applies to the XT pin. *4: Applies to the TESTI0 pin. *5: Applies to the RESETB pin. *6: Applies to the TESTO pin. 9/63 FEDL228XX-05 ML2282X-XXX/ ML2286X -XXX Characteristics of Analog Circuitry (for the 3V applications) Parameter AIN input resistance AIN input voltage range LINE output load resistance LINE output voltage range SG output voltage SG output resistance SPM, SPP output load resistance Speaker amplifier output power Output offset voltage between SPM and SPP with no signal present Symbol RAIN VAIN DVDD = SPVDD = 2.7 to 3.6 V, DGND = SPGND = 0 V, Ta = −40 to +85°C Condition Min. Typ. Max. Unit ⎯ 15 20 25 kΩ ⎯ ⎯ DVDD×2/3 Vp-p RLA During 1/2 DVDD output 10 ⎯ ⎯ kΩ VAO No output load DVDD/6 ⎯ DVDD×5/6 V VSG RSG ⎯ During power down 0.95×VDDL/2 57 VDDL/2 96 1.05×VDDL/2 135 V kΩ RLSP ⎯ 8 ⎯ ⎯ Ω PSPO SPVDD = 3.3V, f = 1kHz RSPO = 8Ω, THD≥10% 100 300 ⎯ mW VOF SPIN–SPM gain = 0dB With a load of 8Ω −50 ⎯ +50 mV Characteristics of Analog Circuitry (for the 5V applications) Parameter AIN input resistance AIN input voltage range LINE output load resistance LINE output voltage range SG output voltage SG output resistance SPM, SPP output load resistance Symbol RAIN VAIN DVDD = SPVDD = 4.5 to 5.5 V, DGND = SPGND = 0 V, Ta = −20 to +85°C Condition Min. Typ. Max. Unit ⎯ 15 20 25 kΩ ⎯ ⎯ DVDD×2/3 Vp-p RLA During 1/2 DVDD output 10 ⎯ ⎯ kΩ VAO No output load DVDD/6 ⎯ DVDD×5/6 V VSG RSG ⎯ During power down 0.95×VDDL/2 57 VDDL/2 96 1.05×VDDL/2 135 V kΩ RLSP ⎯ 8 ⎯ ⎯ Ω Speaker amplifier output power PSPO SPVDD = 5.0V, f = 1kHz RSPO = 8Ω, THD≥10% Ta=25°C 500 700 ⎯ mW Output offset voltage between SPM and SPP with no signal present VOF SPIN–SPM gain = 0dB With a load of 8Ω −50 ⎯ +50 mV 10/63 FEDL228XX-05 ML2282X-XXX/ ML2286X -XXX AC Characteristics (Common to All Products) DVDD = SPVDD = 2.7 to 5.5 V, DGND = SPGND = 0 V, Ta = −40 to +85°C, Applicable Symbol Condition Min. Typ. Max. Unit Parameter command Master clock duty cycle fduty — 40 50 60 % RESETB input pulse width tRST — 100 — — μs Reset noise rejection pulse width tNRST — — — 0.1 μs STOP, SLOOP, CLOOP, CVOL, tINT 2 — — ms AVOL Command input interval time fOSC = 4.096 MHz PUP tINTP 10 — — ms Command input enable time RDSTAT (After status read) SLOOP Continuous play by PLAY/MUON tINTRD 500 — — μs tcm fOSC = 4.096 MHz — — 10 ms PUP tPUP1 fOSC = 4.096 MHz 2.0 2.5 3.0 ms PDWN tPD1 fOSC = 4.096 MHz — — 20 μs tPOPA1 fOSC = 4.096 MHz 58 60 62 ms tPOPA2 fOSC = 4.096 MHz 90 93 95 ms tPDA1 fOSC = 4.096 MHz 108 110 112 ms tPDA2 fOSC = 4.096 MHz 140 142 144 ms tCB1 fOSC = 4.096 MHz — — 2 ms 2nd byte of AMODE (POP = “0” DAEN or SPEN = “0” →”1”) 2nd byte of AMODE (POP = “1” DAEN = “0” →”1” CBUSYB “L” level output time SPEN = “0”) 2nd byte of AMODE (POP = “0” DAEN or SPEN = “1” →”0”) 2nd byte of AMODE (POP = “1” DAEN = “1” →”0” SPEN = “0”) ) (*1) Note: Output pin load capacitance = 45 pF *1: Applies to cases where a command is input except after a PUP, PDWN, or 2nd byte of AMODE command input. 11/63 FEDL228XX-05 ML2282X-XXX/ ML2286X -XXX AC Characteristics of Synchronous Serial Command Interface (Applied to ML2282X) DVDD = SPVDD = 2.7 to 5.5 V, DGND = SPGND = 0 V, Ta = −40 to +85°C Applicable Symbol Condition Min. Typ. Max. Unit Parameter command SCK input enable time from CSB fall edge tESCK — 100 — — ns SCK hold time from CSB rise edge tCSH — 100 — — ns Data floating time from CSB rise edge tDOZ RL = 3 kΩ — — 100 ns Data setup time from SCK rise edge tDIS1 DIPH = “0” 50 — — ns Data hold time from SCK rise edge tDIH1 DIPH = “0” 50 — — ns Data output delay time from SCK fall edge tDOD1 RL = 3 kΩ — — 80 ns Data setup time from SCK fall edge tDIS2 DIPH = “1” 50 — — ns Data hold time from SCK fall edge tDIH2 DIPH = “1” 50 — — ns Data output delay time from SCK rise edge tDOD2 RL = 3 kΩ — — 80 ns SCK “H” level pulse width tSCKH — 100 — — ns SCK “L” level pulse width tSCKL — 100 — — ns CBUSYB output delay time from SCK rise edge tDBSY1 DIPH = “0” — — 150 ns CBUSYB output delay time from SCK fall edge tDBSY2 DIPH = “1” — — 150 ns Note: Output pin load capacitance = 45 pF 12/63 FEDL228XX-05 ML2282X-XXX/ ML2286X -XXX AC Characteristics of I2C Command Interface (Applied to ML2286X) DVDD = SPVDD = 2.7 to 5.5 V, DGND = SPGND = 0 V, Ta = −40 to +85°C (High-speed mode) Parameter Symbol Unit Min. Max. SCL clock frequence tSCL 0 400 kHz Hold time (repeated) START condition tHD;STA 0.6 — μs After this period, the first clock pulse is generated. SCL “L” level pulse width tLOW 1.3 — μs SCL “H” level pulse width tHIGH 0.6 — μs Setup time for repeated START condition tSU;STA 0.6 — μs Data hold time: For I2C bus devices tHD;DAT 0 0.9 μs Data setup time tSU;DAT 100 — ns SDA and SCL signal rise time tr 20 300 ns SDA and SCL signal fall time tf 20 300 ns STOP condition setup time tSU;STO 0.6 — μs Bus free time between STOP condition and START condition tBUF 1.3 — μs Capacitive load for each bus line Cb — 400 PF 0.1× Noise margin at a “L” level in each device connected (including VnL — V DVDD hysteresis) 0.1× Noise margin at a “H” level in each device connected (including VnH — V DVDD hysteresis) Pulse width of spikes which must be suppressed by the input filter tsp 0 50 ns Note: Output pin load capacitance = 45 pF 13/63 FEDL228XX-05 ML2282X-XXX/ ML2286X -XXX TIMING DIAGRAMS ( 3-WIRED SERIAL CLOCK-SYNCHRONIZED (ML2282X) ) Power-On Timing 5V SPVDD 5V DVDD t RST RESETB VIH VIL Performing a reset Status Power-down Oscillation is stopped after power-on. Power-Up Timing CSB SCK SI tPUP1 CBUSYB VOH VO L NCR (internal) VOH BUSYB (internal) VOH XTxXTB Status VO L VO L Oscillation stopped Power-down Oscillating Oscillation stabili zed Command is being processed Awaiting comman d 14/63 FEDL228XX-05 ML2282X-XXX/ ML2286X -XXX Power-Down Timing (At the PDWN command Input) CSB SCK SI tPD1 CBUSYB VOH VOL NCR (internal) VOH BUSYB (internal) VOH VOL VOL XT•XTB Status Oscillation stopped Oscillating Awaiting command Command is being processed Power-down Power-Down Timing (At the RESETB Input) RESETB tRST XTxXTB Oscillating Oscillation stopped VDDLxSG GND SPM Hi-Z GND SPP Status Playing Power-down Note: The same timing is applied in the case that the RESETB signal is input during command waiting. 15/63 FEDL228XX-05 ML2282X-XXX/ ML2286X -XXX Playback Start Timing by the PLAY Command PLAY command 2 nd byte PLAY command 1 st byte CSB SCK SI tC B1 CBUSYB tCB1 VOH VOL NCR (internal) BUSYB (internal) VOH VOL (*1) VOH VOL 1/2SPV DD SPM 1/2SPVDD SPP Status Command standby Awaiting command Address is being controlled Playing Awaiting command Command is being processed Note: The length of the “L” interval of BUSYB is tCB1 + voice reproduction time. Playback Stop Timing STOP command CSB SCK SI tCB1 CBUSYB VOH VOL NCR (internal) VOH BUSYB (internal) VOH VOL VOL 1/2SPV DD SPM 1/2SPVDD SPP Status Playing Awaiting command Command is being processed 16/63 FEDL228XX-05 ML2282X-XXX/ ML2286X -XXX Continuous Playback Timing by the PLAY Command PLAY command 2nd byte PLAY command PLAY command 1 st byte 2nd byte CSB SCK tcm SI tCB1 tCB1 CBUSYB VOH VOL NCR VOH VOL (internal) (*1) BUSYB (internal) 1/2SPVDD SPM 1/2SPVDD SPP Status Playing phrase 1 Awaiting command Address is being controlled *1: Playing phrase 2 Address is being controlled The time length of “L” level of the NCR signal during playback varies depending on the input timing of command. Silence Insertion Timing by the MUON Command PLAY command nd 2 MUON command MUON command st byte 1 byte 2 nd PLAY command PLAY command st byte nd 1 byte 2 byte CSB SCK tcm SI tCB1 CBUSYB tC B1 t CB1 tCB1 VOH VOL NCR (internal) VOH (*1) VOL (*1) BUSYB (internal) SPM SPP Status 1/2SPVDD 1/2SPVDD Awaiting command Address is being controlled *1: Playing Silence is being inserted Playing Waiting for silence insertion to be finished The time length of “L” level of the NCR signal during playback or silence insertion varies depending on the input timing of command. 17/63 FEDL228XX-05 ML2282X-XXX/ ML2286X -XXX Repeat Playback Set/Release Timing by the SLOOP and CLOOP Commands SLOOP command PLAY command VIH CSB 2 nd CLOOP command byte VIL tINT SCK SI tcm t CB1 CBUSYB t CB1 tCB1 VOH VOL NCR VO H VOL BUSYB (internal) 1/2SPVDD SPM 1/2SPVDD SPP Status Awaiting command Address is being controlled Playing Playing Address is being controlled Awaiting command Command is being processed Timing of Volume Change by the CVOL Command CVOL command 1st byte CVOL command nd 2 byte CSB SCK SI tCB1 tCB1 CBUSYB VOH VOL NCR VOH (internal) VOL BUSYB VOH (internal) VOL Status Awaiting command Command is being processed Awaiting command Awaiting command Command is being processed 18/63 FEDL228XX-05 ML2282X-XXX/ ML2286X -XXX TIMING DIAGRAMS ( I2C INTERFACE (ML2286X) ) Power-On Timing 5V SPVDD 5V DVDD t RST RESETB VIH VIL Performing a reset Status Power-down Oscillation is stopped after power-on. Power-Up Timing SCL A A A 6 5 4 SDA WA A tPUP1 CBUSYB VOH VOL NCR (internal) VOH BUSYB (internal) VOH XT・XTB Status VOL VOL Oscillation stopped Power-down Oscillationg Oscilla tio n sta bilized C ommand is being processed Awaiting command 19/63 FEDL228XX-05 ML2282X-XXX/ ML2286X -XXX Power-Down Timing (At the PDWN command Input) SCL A A A 6 5 4 SDA W A A tPD1 CBUSYB VOH VO L NCR VOH (internal) VO L BUSYB VOH (internal) VO L XT・XTB Oscillating Status Awaiting command Oscillation stopped C ommand is being pr ocessed Power-down Power-Down Timing (At the RESETB Input) RESETB tRST XT・XTB Oscillating Oscillation stopped VDDL・SG GND SPM Hi-Z GND SPP Status Playing Power-down Note: The same timing is applied in the case that the RESETB signal is input during command waiting. 20/63 FEDL228XX-05 ML2282X-XXX/ ML2286X -XXX Playback Start Timing by the PLAY Command PLAY command nd 2 byte PLAYcommand st 1 byte SCL A A A 6 5 4 SDA WA A A tCB1 tCB1 CBUSYB VOH VOL NCR (internal) VOH BUSYB (internal) VOH VOL (注) VOL 1/2SPVDD SPM 1/2SPVDD SPP Status Command standby Playing Awaiting command Awaiting command Address is being contorolled Command is being processed Note: The length of the “L” interval of BUSYB is tCB1 + voice reproduction time. Playback Stop Timing STOP command SCL SDA A A A 6 5 4 WA A tCB1 CBUSYB VO H V OL NCR (internal) VO H BUSY (internal) VO H V OL V OL 1/2SPVDD SPM 1/2SPVDD SPP Status Playing Awaiting command C ommand is being processed 21/63 FEDL228XX-05 ML2282X-XXX/ ML2286X -XXX Continuous Playback Timing by the PLAY Command PLAYcommand nd 2 byte PLAYcom mand st 1 byte PLAYcommand nd 2 byte SCL SDA A A A 6 5 4 A W A A A tCM tCB1 tCB1 CBUSYB VOH VOL NCR VOH VOL (internal) （*1） BUSYB (internal) SPM SPP Status 1/2SPVDD 1/2SPVDD Awaiting command Address is being controlled *1: Playing phrase1 Playing phrase2 Addre ss is being controlled The time length of “L” level of the NCR signal during playback varies depending on the input timing of command. 22/63 FEDL228XX-05 ML2282X-XXX/ ML2286X -XXX Silence Insertion Timing by the MUON Command MUONcommand st 1 byte PLAYcommand nd 2 byte MUONcommand nd 2 byte SCL SDA A A A 6 5 4 A WA A A tCM tCB1 tCB1 CBUSYB VOH VOL NCR VOH VOL (internal) （*1） BUSYB (internal) SPM SPP Status 1/2SPVDD 1/2SPVDD Playing Awaiting command Silence is being inserted Address is being controlled PLAYcommand st 1 byte PLAYcommand nd 2 byte SCL A A A 6 5 4 SDA WA A A tCB1 CBUSYB VOH VOL NCR (internal) VOH BUSYB (internal) VOH SPM SPP Status （*1） VOL VOL 1/2SPVDD 1/2SPVDD Silence is being insserted Playing Waiting for silence insertion to be finished *1: The time length of “L” level of the NCR signal during playback or silence insertion varies depending on the input timing of command. 23/63 FEDL228XX-05 ML2282X-XXX/ ML2286X -XXX Repeat Playback Set/Release Timing by the SLOOP and CLOOP Commands PLAYcommand nd 2 byte SLOOPcommand SCL SDA A A A 6 5 4 A A tCM tCB1 CBUSYB WA tCB1 VOH VOL NCR (internal) VOH VOL BUSYB (internal) SPM SPP Status 1/2SPVDD 1/2SPVDD Playing Awaiting command Playing Address is being controlled Command is being processed CLOOP command SCL A A A 6 5 4 SDA W A A tCB1 CBUSYB VOH VOL NCR V OH (internal) VOL BUSYB (internal) 1/2SPVDD SPM SPP Status 1/2SPVDD Playing Playing Awaiting command Command is being processed 24/63 FEDL228XX-05 ML2282X-XXX/ ML2286X -XXX Timing of Volume Change by the CVOL Command CVOLcommand st 1 byte CVOLcommand nd 2 byte SCL A A A 6 5 4 SDA WA A A tCB1 CBUSYB tCB1 VOH VOL NCR (internal) VOH BUSYB (internal) VOH Status VOL VOL Awaiting command Command is being processed Awaiting command Awaiting command Command is being processed 25/63 FEDL228XX-05 ML2282X-XXX/ ML2286X -XXX Serial Command Interface Timing when DIPH pin is “L” level (Rise edge for input, fall edge for output) VIH CSB VIL tESCK tCSH tSCKH VIH SCK VIL tDIS1 tDIH1 tSCKL VIH SI VIL tDOD1 tDOZ VIH SO VIL tDBSY1 CBUSYB VOH VOL Serial Command Interface Timing when DIPH pin is “H” level (Fall edge for input, rise edge for output) VIH CSB VIL tESCK tCSH tSCKL VIH SCK VIL tDIS2 tDIH2 tSCKH VIH SI VIL tDOD2 tDOZ VIH SO VIL tDBSY2 CBUSYB VOH VOL I2C Command Interface Timing (Applied to ML2286X) 26/63 FEDL228XX-05 ML2282X-XXX/ ML2286X -XXX FUNCTIONAL DESCRIPTION Synchronous Serial Command Interface The CSB, SCK, SI, and SO pins are used to input the command data or to read the status. Driving the CSB pin to “L” level enables the serial CPU interface. After the CSB pin is driven to “L” level, the command data are input through the SI pin from the MSB synchronized with the SCK clock. The command data shifts in through the SI pin at the rising or falling edge of the SCK clock pulse. Then, a command is executed at the rising or falling edge of the eighth pulse of the SCK clock. As for status reading, status is output from the SO pin, synchronized with the SCK clock after the CSB pin is driven to “L” level. The SCK clock edge is specified by the input level of the DIPH pin. - When the DIPH pin is “L” level, rising edge is available for input from SI pin and falling edge is available for output from SO pin. - When the DIPH pin is “H” level, falling edge is available for input from SI pin and rising edge is available for output from SO pin. It is possible to input command data, even if the CSB pin is fixed by “L” level. However, if unexpected pulses caused by noise are induced through the SCK pin, SCK clock pulses are incorrectly counted, causing a failure in normal recognition of command. Then it is recommended that the CSB pin is “L” level only for command input. The count of the SCK clock pulse is initialized when the CSB pin goes to “H” level. Command Data Input or Status Read Timing • When DIPH pin is “L” level CSB SCK SI D7 D6 D5 D4 D3 D2 D1 ( MSB ) SO D7 D0 (LSB) D6 D5 D4 D3 D2 D1 D6 D5 D4 D3 D2 D1 D0 • When DIPH pin is “H” level CSB SCK SI D7 ( MSB ) SO D7 D0 (LSB) D6 D5 D4 D3 D2 D1 D0 27/63 FEDL228XX-05 ML2282X-XXX/ ML2286X -XXX The following table shows the contents of each data output at a status read. Output status signal MSB ⎯ 7SB ⎯ 6SB Channel 2 BUSYB output (BUSYB1) 5SB Channel 1 BUSYB output (BUSYB0) 4SB ⎯ 3SB ⎯ 2SB Channel 2 NCR output (NCR1) LSB Channel 1 NCR output (NCR0) The BUSYB output is “L” level when a command is being processed or the playback of a particular channel is going on. In other states, the BUSYB output is “H” level. The NCR output is “L” level when a command is being processed or particular channel is in standby for playback. In other states, the NCR output is “H” level. 28/63 FEDL228XX-05 ML2282X-XXX/ ML2286X -XXX I2C Command Interface (Applies to ML2286X) The I2C Interface built-in is an serial interface (: slave side) that is compliant with I2C bus specification. It supports Fast mode and enables data transmission/reception at 400 kbps. The SCL and SDA pins are used to input the command data or to read the status. Pins (:SAD0, 1 and 2) are used to set the slave address. Pull-up resister should be connected to SCL pin and SDA pin. For the master on the I2C bus to communicate with this device (: slave), input the slave address with the first seven bits after setting the start condition. The upper three bits of the slave address can be set using the SAD0 to 2 pins. The eighth bit of slave address is used to set the direction (: write or read) of communication. If the eighth bit is “0” level, it is write mode from master to slave. And, if the eighth bit is “1” level, it is read mode from master. The communication is made in the unit of byte. And acknowledge is needed for each byte. The protocol of I2C communication is shown below. − Command flow at data write( 1byte command ) START condition Slave address +W (0) Write address (ex. 1st byte of a command) STOP condition y Data write timing( 1byte command ) SCL SDA A6 A5 A4 A3 A2 A1 A0 W A D7 D6D5 D4 D3D2D1 D0 A S Slave Address A 1st Command Data A P CBUSYB − Command flow at data write( 2byte command ) START condition Slave address +W (0) Write address (ex. 1st byte of a command) Write data (ex. 2nd byte of a command) STOP condition y Data write timing( 2byte command ) SCL SDA A6 A5 A4 A3 A2 A1 A0 W A D7 D6D5 D4 D3D2D1 D0 A D7 D6D5 D4 D3D2 D1 D0 A S Slave Address A 1st Command Data A 2nd Command Data A P 29/63 FEDL228XX-05 ML2282X-XXX/ ML2286X -XXX − Command flow at data read Start condition Slave address +W(0) Write address (RDSTAT command) STOP condition Start condition Slave address +R(1) Read data (ex. Status read) STOP condition y Data read timing SCL SDA A6 A5 A4 A3 A2 A1 A0 W A D7 D6D5 D4 D3D2D1 D0 A S Slave Address A RDSTAT Command A P CBUSYB SCL SDA A6 A5 A4 A3 A2 A1 A0 R A D7 D6D5 D4 D3 D2 D1 D0 A S Slave Address A Read Data A P CBUSYB 30/63 FEDL228XX-05 ML2282X-XXX/ ML2286X -XXX Setting of the slave address using the SAD0 to 2 pins SAD2 SAD1 SAD0 Lower 4 bits 0 0 0 0101 0 0 1 0101 0 1 0 0101 0 1 1 0101 1 0 0 0101 1 0 1 0101 1 1 0 0101 1 1 1 0101 The following table shows the contents of each data output at a status read. Status is updated by the RDSTAT command; therefore, be sure to input the RDSTAT command in order to read status. Output status signal MSB 7SB 6SB Channel 2 BUSYB output (BUSYB1) 5SB Channel 1 BUSYB output (BUSYB0) 4SB 3SB 2SB Channel 2 NCR output (NCR1) LSB Channel 1 NCR output (NCR0) The BUSYB signal is “L” level when either a command is being processed or the playback of a particular channel is going on. In other states, the BUSYB signal is “H” level. The NCR signal is “L” level when either a command is being processed or a particular channel is in standby for playback. In other states, the NCR signal is “H” level. 31/63 FEDL228XX-05 ML2282X-XXX/ ML2286X -XXX Command List Each command is configured by the unit of byte (8-bit). The following commands, AMODE, AVOL FADR, PLAY, MUON, and CVOL, use two bytes. Command D7 D6 D5 D4 D3 D2 D1 D0 PUP 0 0 0 0 0 0 S1 S0 PDWN 0 0 1 0 0 0 0 0 RDSTAT 1 0 1 1 0 0 0 0 0 0 0 0 0 1 0 0 AMODE FAD DAG1 DAG0 AIG1 AIG0 DAEN SPEN POP Description Power-up command. Shifts from the power down state to the command waiting state. Also, sets the number of memory banks. Power-down command. Shifts form the command waiting state to the power down state. Status read command. Reads the command status on each channel. Control command of analog circuitry. Setoperation of power-up/dpwn and input/output. Playback start command. Use the data of the 2nd byte to specify a phrase number. Can be specified for each channel. Playback stop command. Can be set for each channel. Set command of playback phrase. Can be set for each channel. Use START command to start. Playback start command without phrase spec. Use FADR command to set phrase.Can start playback on multiple channels simultaneously. After played back by PLAY command, the same phrase can be played back with this command. Silence insertion command. Set the silent time length for each channel using M7 to M0 bits in the 2nd byte. Set command of repeat playback. Setting is enabled during playback. Can be specified for each channel. Stop command of repeat playback. Can be specified for each channel. Also, repeat playback is released by STOP command automatically. 0 1 0 0 F9 F8 0 CH F7 F6 F5 F4 F3 F2 F1 F0 0 1 1 0 0 0 CH1 CH0 0 0 1 1 F9 F8 0 CH F7 F6 F5 F4 F3 F2 F1 F0 0 1 0 1 0 0 CH1 CH0 0 1 1 1 0 0 CH1 CH0 M7 M6 M5 M4 M3 M2 M1 M0 SLOOP 1 0 0 0 0 0 CH1 CH0 CLOOP 1 0 0 1 0 0 CH1 CH0 1 0 1 0 0 0 CH1 0 0 0 CV4 CV3 CV2 CV1 CH0 Volume control command. Set volume for each channel using CV0 CV4 to CV0 bits in the 2nd byte. 0 0 0 0 1 0 0 0 0 AV5 AV4 AV3 AV2 AV1 PLAY STOP FADR START MUON CVOL AVOL Analog volume control command. Set volume after channel mixing AV0 using AV5 to AV0 bits. 0 32/63 FEDL228XX-05 ML2282X-XXX/ ML2286X -XXX Voice Synthesis Algorithm Four types of voice synthesis algorithm are supported. They are 4-bit ADPCM2, 8-bit non-linear PCM, 8-bit straight PCM and 16-bit straight PCM. Select the best one according to the characteristics of playback voice. The following table shows key features of each algorithm. Voice synthesis algorithm Applied waveform 4-bit ADPCM2 Normal voice waveform 8-bit Nonlinear PCM Waveform including high frequency signals (sound effect, etc.) 8-bit straight PCM 16-bit straight PCM Feature Up version of LAPIS Semiconductor’s specific voice synthesis algorithm (: 4-bit ADPCM). Voice quality is improved. Algorithm, which plays back mid-range of waveform as 10-bit equivalent voice quality. Normal 8-bit PCM algorithm Normal 16-bit PCM algorithm 33/63 FEDL228XX-05 ML2282X-XXX/ ML2286X -XXX Memory Allocation and Creating Voice Data The ROM is partitioned into four data areas: voice (i.e., phrase) control area, test area, voice area, and edit ROM area. The voice control area manages the voice data in the ROM. It contains data for controlling the start/stop addresses of voice data for 1,024 phrases, use/non-use of the edit ROM function and so on. The test area contains data for testing. The voice area contains actual waveform data. The edit ROM area contains data for effective use of voice data. For the details, refer to the section of “Edit ROM Function.” The edit ROM area is not available if the edit ROM is not used. The ROM data is created using a dedicated tool. Configuration of ROM data 0x00000 Voice control area (Fixed 64 Kbits) 0x01FFF 0x02000 Test area 0x0205F 0x02060 Voice area max: 0x1FFFFF Edit ROM area Depends on creation of ROM data. max: 0x1FFFFF Playback Time and Memory Capacity The playback time depends on the memory capacity, sampling frequency, and playback method. The equation to know the playback time is shown below. But this is not applied if the edit ROM function is used. Playback time [sec] = 1.024 × (Memory capacity – 64.75 [Kbits] Sampling frequency [kHz] × Bit length (Bit length is 4 at the 4-bit ADPCM2 and 8/16 at the PCM.) Example) In the case that the sampling frequency is 16 kHz, algorithm is 4-bit ADPCM2 and ROM capacity is 16 Mbits, the playback time is approx. 261 seconds, as shown below. Playback time = 1.024×(16834 – 64.75) [Kbits] ≅ 261 [sec] 16 [kHz] × 4 [bits] 34/63 FEDL228XX-05 ML2282X-XXX/ ML2286X -XXX Edit ROM Function The edit ROM function makes it possible to play back multiple phrases in succession. The following functions are set using the edit ROM function: x Continuous playback: x Silence insertion function: There is no limit to set the number of times of continuous playback. It depends on the memory capacity only. 20ms to 1,024 ms It is possible to use voice ROM effectively to use the edit ROM function. Below is an example of the ROM structure, case of using the edit ROM function. Example 1) Phrases using the Edit ROM Function Phrase 1 A B D Phrase 2 A C D Phrase 3 E B D Phrase 4 E C D Phrase 5 A B D Silence E C D Example 2) Structure of the ROM that contents of Example 1 are stored Address control area A B C D E Editing area Mixing Function It is possible to perform mixing of two channels simultaneously. And also, it is possible to specify PLAY, STOP, and CVOL commands for each channel respectively. The mixing function is available if the sampling frequency (FS) is 32 kHz or less. - Precautions for Waveform Clamp Adjust the volume of each channel using the CVOL command, if the waveform clamp is increased by channel mixing. 35/63 FEDL228XX-05 ML2282X-XXX/ ML2286X -XXX Memory Bank Switching Function The memory bank switching function enables the the built-in ROM area that is divivided into up to four banks to be used. When four banks are used, the maximum number of phrases per bank is 1,024 so that up to 4096 phrases can be played back. Using this function, multiple ROM codes can be grouped into one code. The settings of SEL1 pin and SEL0 pin determines which memory bank is used. To playback phrases, the number of memory banks must be specified in PUP. When using a memory bank switching function, data must be divided and saved in the specified areas at ROM data creation. − When the number of memory banks is 1 SEL1 SEL0 ML22825 ML22865 ML22824 ML22864 ML22823 ML22863 0 0 00000h – 1FFFFFh 00000h – FFFFFh 00000h -7FFFFh ML22824 ML22864 ML22823 ML22863 − When the number of memory banks is 2 SEL1 SEL0 ML22825 ML22865 0 0 00000h – FFFFFh 00000h – 7FFFFh 00000h – 3FFFFh 0 1 100000h – 1FFFFFh 80000h – FFFFFh 40000h – 7FFFFh − When the number of memory banks is 4 SEL1 SEL0 ML22825 ML22865 ML22824 ML22864 ML22823 ML22863 0 0 00000h – 7FFFFh 00000h – 3FFFFh 00000h – 1FFFFh 0 1 80000h – FFFFFh 40000h – 7FFFFh 20000h – 3FFFFh 1 0 100000h – 17FFFFh 80000h – BFFFFh 40000h – 5FFFFh 1 1 180000h – 1FFFFFh C0000h – FFFFFh 60000h – 7FFFFh The memory (16 Mbits) in the ML22825 is divided as shown below. 0-7FFFFh Bank 1 Capacity: 16 Mbits Max. Phrase count: 1024 Bank 1 Capacity: 8 Mbits Max. Phrase count: 1024 Bank 1 Capacity: 4 Mbits Max. Phrase count: 1024 Bank 2 Capacity: 4 Mbits Max. Phrase count: 1024 80000-FFFFFh Bank 2 Capacity: 8 Mbits Max. Phrase count: 1024 100000-17FFFFh Bank 3 Capacity: 4 Mbits Max. Phrase count: 1024 Bank 4 Capacity: 4 Mbits Max. Phrase count: 1024 180000-1FFFFFh Memory divide count: 1 16 Mbits × 1 area Memory divide count: 2 8 Mbits × 2 areas Memory divide count: 4 4 Mbits × 4 areas 36/63 FEDL228XX-05 ML2282X-XXX/ ML2286X -XXX Description of Command Functions 1. PUP command x command 0 0 0 0 0 0 S1 S0 The PUP command is used to shift from the power down state to the command waiting state. This command is only available at the power down state . Conditions are as follows to enter the power down state. 1) When power is turned on 2) When the RESETB input is “L” level (: rest input). 3) When CBUSYB pin goes to “H” level after inputting the power down command(:PDWN). The relationship between S1/S0 and the memory banks is as follows: S1 0 S0 0 0 1 1 0 1 1 Overall memory area is used. The internal memory is divided into 2 areas. The 2 memory areas are switched with the SEL0 pin. The internal memory is divided into 4 areas. The 4 memory areas are switched with the SEL1 and SEL0 pins. Prohibited (The operation is the same as above.) CSB SCK tINT P SI TPUP1 CBUSYB XT•XTB Oscillation stopped Status Power-down Oscillating Awaiting command Oscillation stabilized / Command is being processed The regulator output starts operating after the PUP command is entered. Any command will be ignored if entered while oscillation is stabilized. However, if a “L” level is input to the RESETB pin, the LSI enters a power down state immediately. The built-in amplifier is not powered up by this command. It is powered up by the AMODE command. 37/63 FEDL228XX-05 ML2282X-XXX/ ML2286X -XXX 2. PDWN command x command 0 0 1 0 0 0 0 0 The PDWN command is used to shift from the command waiting state (:both NCR and BUSYB are “H” level) to the power down state. Any setting is initialized by this command, so it is necessary to set again after power up. This command is not available during playback. To resume playback after the entering power down state, input the AMODE and the PLAY command after input the PUP command. CSB SCK SI CBUSYB NCR (internal) BUSYB (internal) XT•XTB Oscillating Status Awaiting command Oscillation stopped Command is being proc es sed Power down The regulator and the speaker amplifier stop operation after a lapse of command processing time after the PDWN command is input. At this time, the SPM output of the speaker amplifier goes to a Hi-Z state to prevent troubles by pop noise. Initial stauts at reset input and status during power down The status of each output pin is as follows: Analog output pin State VDDL VDDR SG SPM SPP GND GND GND HiZ GND 38/63 FEDL228XX-05 ML2282X-XXX/ ML2286X -XXX 3. RDSTAT command x command 1 0 1 1 0 0 0 0 The RDSTAT command is used to read the NCR and BUSYB signals that indicate the status of internal operation. The NCR signal is “L” level while command are processed, and goes to “H” level at the command waiting state. The BUSYB signal is “L” level during playback voices. The command interval time ( : tINTRD) is needed to input the next command after reading status using this command. The following table shows the contents of each bit of data output. Output status signal MSB ⎯ 7SB ⎯ 6SB Channel 2 BUSYB output (BUSYB1) 5SB Channel 1 BUSYB output (BUSYB0) 4SB ⎯ 3SB ⎯ 2SB Channel 2 NCR output (NCR1) LSB Channel 1 NCR output (NCR0) RDSTAT command CSB SCK tINTRD SI SO tCB1 CBUSYB VOH VO L NCR (internal) VO L 39/63 FEDL228XX-05 ML2282X-XXX/ ML2286X -XXX 4. AMODE command x command 0 FAD 0 DAG1 0 DAG0 0 AIG1 0 AIG0 1 DAEN 0 SPEN 0 POP 1st byte 2nd byte The AMODE command uses 2 bytes. This command is used to perform various settings for analog circuitry. This command is not available during power-down state, transition to power-up state, transition to power down state or playback state. In the case of performing power down using PDWN command during power up of analog circuitry, the setting of power up by AMODE command is retained. Use the AMODE command to perform power down, if need to use different conditions from power up of analog circuitry. In the case of power up of analog circuitry, input the AMODE command after setting the CVOL command to “00h” (: initial value). The settings of each bit is shown below. The setting is initialized by reset release or power-up. The FAD bit specifies whether to perform fade-out processing when the STOP command is input. If the bit is set to “1”, fade-out processing is performed during a period of approx. 3 ms after the STOP command is input. The BUSYB signal goes to “H” level after fade-out processing. FAD 0 1 Fade-out processing Not available (initial value) Available The DAG1, 0 bits are used to set the gain of the internal DAC signal. The AIG1, 0 bits are used to set the gain of an analog input signal from the AIN pin. They are available only when using the speaker amplifier. DAG1 0 0 1 1 DAG0 0 1 0 1 Volume Input OFF Input ON (–6 dB) Input ON (0 dB) (initial value) Prohibited (input ON (0 dB)) AIG1 0 0 1 1 AIG0 0 1 0 1 Volume Input OFF (initial value) Input ON (–6 dB) Input ON (0 dB) Prohibited (input ON (0 dB)) The DAEN bit controls power-up and power-down of the DAC circuitry. DAEN 0 1 Status of the DAC section Power-down state (initial value) Power-up state 40/63 FEDL228XX-05 ML2282X-XXX/ ML2286X -XXX The SPEN bit takes power-up and power-down of the speaker circuitry. When the SPEN bit is “0”, SPP pin is the LINE output. SPEN 0 1 Status of the speaker circuitry Power-down state (initial value) Power-up state The POP bit sets whether to suppress the “pop” noise of the LINE output. − In the case of setting the POP bit to “0” If the DAEN bit is “1”, LINE output rises from the GND level to the SG level during a period of the specified time (:tPOPA1) . If the DAEN bit is “0”, LINE output falls from the SG level to the GND level during a period of the specified time (:tPDA1). − In the case of setting the POP bit to “1” If the DAEN bit is “1”, LINE output rises from the GND level to the SG level during a period of the specified time (:tPOPA2). If the DAEN bit is “0”, LINE output falls from the SG level to the GND level during a period of the specified time (:tPDA2). POP 0 1 Pop noise suppression Not available (initial value) Available 41/63 FEDL228XX-05 ML2282X-XXX/ ML2286X -XXX • When POP bit is “0” and DAEN or SPEN bits goes to “1” AMODE command 1st byte AMODE command 2nd byte CSB SCK SI tCB1 CBUSYB tPOPA1 VOH VO L NCR (internal) VOH BUSYB (internal) VOH VO L VO L AOUT (internal) GND 1/2SPVDD SPM Hi-Z SPP GND 1/2SPV DD Status Awaiting command Await ing command Command is being processed Awaiting command C ommand is being processed • When POP bit is “1”, SPEN bit is “0” and DAEN bit goes to “1” AMODE command 1st byte AMODE command 2nd byte CSB SCK SI t CB1 CBUSYB t POPA2 VO H VOL NCR (internal) VO H BUSYB (internal) VO H VOL VOL 1V SPP (LINE output) Status GND Awaiting command Command is being process ed Awaiting c ommand POP nois e suppressed Await ing c ommand Command is being processed 42/63 FEDL228XX-05 ML2282X-XXX/ ML2286X -XXX • When POP bit is “0” and DAEN or SPEN bit goes to “0” AMODE command 1st byte AMODE command 2nd byte CSB SCK SI t CB1 CBUSYB tPDA1 VOH VOL NCR (internal) VOH BUSYB (internal) VOH VOL VOL 1V AOUT (internal) GN D 1/2SPVDD Hi-Z SPM 1/2SPVDD SPP GN D Status Awaiting command Awaiting command Command is being proc es sed Awaiting command Command is being process ed • When POP bit is “1”, SPEN bit is “0” and DAEN bit goes to “0” AMODE command 1st byte AMODE command 2nd byte CSB SCK SI t CB1 CBUSYB t PDA2 VOH VOL NCR (internal) VOH BUSYB (internal) VOH VOL VOL 1V SPP (LINE output) Status G ND Awaiting command Command is being process ed Awaiting c ommand POP nois e suppressed Await ing c ommand Command is being processed 43/63 FEDL228XX-05 ML2282X-XXX/ ML2286X -XXX 5. PLAY command x command 0 F7 1 F6 0 F5 0 F4 F9 F3 F8 F2 0 F1 CH F0 1st byte 2nd byte The PLAY command uses 2 bytes. This command is used to start playback phrase. This command is able to input by each channel when the NCR signal is “H” level. The channel to be played back is specified by the CH bit. For the phrase to be played back, set the phrase address of voice data in the ROM using the F9 to F0 bits. The following figure shows the timing of playback phrase (F9 to F0 is 01h) . PLAY command st 1 byte PLAY command nd 2 byte CSB SCK SI CBUSYB NCR (internal) BUSYB (internal) SPM SPP Status 1/2SPVDD 1/2SPVDD Awaiting command Awaiting command Address is being controlled Playing Awaiting command Command is being processed When the 1st byte of the PLAY command is input, the device enters a state awaiting input of the 2nd byte of the PLAY command after a lapse of command processing time. When the 2nd byte of PLAY command is input, the device starts reading the external ROM to get the address information of the phrase to be played back after a lapse of command processing time. Thereafter, playback starts and the playback is performed up to the specified ROM address, then the playback stops automatically. The NCR1 signal is “L” level during address control, and goes “H” level when the address control is completed. Then it is possible to input the PLAY command for the next playback phrase. The BUSYB signal is “L” level during address control and playback, and goes to “H” level when playback is completed. Then it is possible to knowwhether the playback is going on by the BUSYB signal. - Channel settings mothod CH 0 1 Channel Channel 1 Channel 2 44/63 FEDL228XX-05 ML2282X-XXX/ ML2286X -XXX The PLAY Command Input Timing for Continuous Playback In the case of continuous playback, input the PLAY command for the next phrase within the command input enable time (:tcm) after NCR goes to “H” level. Then it is possible to start playback the next phrase without any silent interval between phrases. PLAY command 2nd byte PLAY command PLAY command 1st byte 2nd byte CSB SCK tcm SI CBUSYB NCR (internal) BUSYB (internal) SPM SPP Status 1/2SPVDD 1/2SPVDD Awaiting command Address is being controlled Playing phrase 1 Playing phrase 2 Address is being controlled As shown in the diagram above, if continuous playback is carried out, input the PLAY command for the second phrase (tcm) after NCR goes “H”. This will make it possible to start playing the second phrase immediately after the playback of the first phrase finishes. Phrases can thus be played continuously without inserting silence between phrases. 45/63 FEDL228XX-05 ML2282X-XXX/ ML2286X -XXX 6. STOP command x command 0 1 1 0 0 0 CH1 CH0 The STOP command is used to stop playback for each channel. This command can be set to each channel and also to multiple channels simultaneously. The channels are specified by setting CH0 to CH1 bits to “1” state respectively. If the playback is stopped, the NCR and BUSYB signals go to “H” level. Although it is possible to input this command regardless of the status of NCR during playback, a prescribed command interval time (:tINT) is needed. The STOP command is not available during power down, transition to power-up or transition to power-down. The playback related command (:PLAY, START or MUON) is not available during STOP command processing. STOP command CSB SCK SI CBUSYB NCR (internal) BUSYB (internal) 1/2SPV DD SPM 1/2SPVDD SPP Status Playing Awaiting command Command is being processed - Channel settings method CH0 CH1 Channel Channel 1 Channel 2 The playback related command (:PLAY, START or MUON), used on the same channel after the STOP command, should be input after confirming the completion (: NCRn is “H” and BUSYBn is “H”, n is the related number of channel concerned) of this command processing by the RDSTAT command, or waiting for 12ms from transition of the CBUSYB to “H” level. 46/63 FEDL228XX-05 ML2282X-XXX/ ML2286X -XXX 7. FADR command x command 0 F7 0 F6 1 F5 1 F4 F9 F3 F8 F2 0 F1 CH F0 1st byte 2nd byte The FADR command used 2 bytes. This command is used to specify phrase to be played. The channel and phrase to be played back are set by this command. The channel for playback is specified by CH bit. Playback will be started by START command after the phrase for each channel is specified. For the phrase to be played back, set the phrase address of voice data in the ROM using the F9 to F0 bits. The setting values of the FADR command are initialized at power-down. - Channel settings method CH 0 1 Channel Channel 1 Channel 2 47/63 FEDL228XX-05 ML2282X-XXX/ ML2286X -XXX 8. START command x command 0 1 0 1 0 0 CH1 CH0 The START command is used to start playback on the channel specified. It is necessary to specify a playback phrase using the FADR command before inputting this command. Usually, use this command when starting playback on multiple channels simultaneously. The channels to be player back are specified by setting CH0 to CH1 bits to “1” starts respectively. The following figure shows the timing when starting playback on channel 1 and channel 2 simultaneously. CSB SCK SI tCB1 CBUSYB NCR0,1 (internal) BUSYB0,1 (internal) SPP output 1/2SPVDD SPM output 1/2SPVDD Awaiting command Status Address is being controlled Playing Awaiting command - Channel settings method CH 0 CH 1 Channel Channel 1 Channel 2 48/63 FEDL228XX-05 ML2282X-XXX/ ML2286X -XXX 9. MUON command x command 0 M7 1 M6 1 M5 1 M4 0 M3 0 M2 CH1 M1 CH0 M0 1st byte 2nd byte The MUON command uses 2 bytes. This command is used to insert the silence between two playback phrases. This command can be set to each channel and also to multiple channels simultaneously. The channels are specified by setting CH0 to CH1 bits to “1” state respectively. This command can be input when the NCR signal is “H” level. Set the silent time value after inputting this command. The silent time length to be specified by M7 to M0 bits is able to be set by 256 steps at 4 ms interval between 20 ms and 1,024 ms. The silent time length (tmu) is calculated by equation as below. The silent time length should be set to 04h or higher (:tmu is 20ms or more). tmu = (27×(M7) + 26×(M6) + 25×(M5) + 24×(M4) + 23×(M3) + 22×(M2) + 21×(M1) + 20×(M0) + 1) × 4ms The following figure shows the timing of inserting the silence of 20 ms between the repetitions of a phrase (F7 to F0 is 01h). PLAY command 2nd byte MUON command MUON command 2nd byte 1st byte PLAY command PLAY command 1st byte 2nd byte tcm tcm Playing Silence is being inserted CSB SCK SI CBUSYB NCR (internal) BUSYB (internal) SPM SPP Status 1/2SPVDD 1/2SPVDD Awaiting command Address is being controlled Waiting for playback to be finished Playing Waiting for silence insertion to be finished When the playback starts after the PLAY command is input and the address control of phrase-1 is over, the CBUSYB and NCR signals go to “H” level. Input the MUON command after this CBUSYB signal changes to “H” level. After the MUON command input, the NCR signal remains at “L” level until the end of phrase-1 playback. This status is the waiting for the phrase-1 playback to be finished. When the phrase-1 playback is finished, the silence playback starts and the NCR signal goes to “H” level. Then, input the PLAY command again to playback phrase-1. Then, the NCR signal goes to “L” level again and the device enters a state of the waiting for the end of silence playback. When the silence playback is finished and then the phrase-1 playback starts, the NCR signal goes to “H” level, and the device enters a status where it is possible to input the next PLAY or MUON command. The BUSYB signal remains “L” level until the end of a series of playback. 49/63 FEDL228XX-05 ML2282X-XXX/ ML2286X -XXX 10. SLOOP command x command 1 0 0 0 0 0 CH1 CH0 The SLOOP command is used to set the repeat playback mode for each channel. This command can be set to each channel and also to multiple channels simultaneously. The channels are specified by setting CH0 to CH1 bits to “1” state respectively. Use the CLOOP command to release repeat playback mode. Since the SLOOP command is only valid during playback, be sure to input the SLOOP command while the NCR signal is “H” level after the PLAY command is input. The NCR signal is “L” level during repeat playback mode. Once repeat playback mode is set, the current phrase is repeatedly played until the repeat playback setting is released by the CLOOP command or until playback is stopped by the STOP command. In the case of a phrase that was edited by the edit function, the edited phrase is repeatedly played. The repeat playback mode is released if playback is stopped by the STOP command, therefore input the SLOOP command again if need to repeat playback again. The following shows the SLOOP command input timing. PLAY command 2nd byte SLOOP command CLOOP command CSB SCK SI CBUSYB NCR (internal) tcm BUSYB (internal) SPM SPP Status 1/2SPVDD 1/2SPVDD Awaiting command Address is being controlled Playing Address is being controlled Playing Awaiting command Command is being processed Effective Range of SLOOP Command Input After the PLAY command is input, input the SLOOP command within the command input enable time (: tcm) after NCR goes “H”. Then, the SLOOP command is available to repeat playback. - Channel settings method Channel CH 0 CH 1 Channel 1 Channel 2 50/63 FEDL228XX-05 ML2282X-XXX/ ML2286X -XXX 11. CLOOP command x command 1 0 0 1 0 0 CH1 CH0 The CLOOP command is used to release the repeat playback mode for each channel. This command can be set to each channel and also to multiple channels simultaneously. The channels are specified by setting CH0 to CH1 bits to “1” state respectively. When the repeat playback mode is released, the NCR signal goes “H” level. It is possible to input this command regardless of the NCR signal status during playback, but a prescribed command interval time (:tINT) is needed. - Channel setting method CH 0 CH 1 Channel Channel 1 Channel 2 51/63 FEDL228XX-05 ML2282X-XXX/ ML2286X -XXX 12. CVOL command x command 1 0 0 0 1 0 0 CV4 0 CV3 0 CV2 CH1 CV1 CH0 CV0 1st byte 2nd byte The CVOL command uses 2bytes. This command is used to adjust the playback volume of each channel. This command can be set to each channel and also to multiple channels simultaneously. The channels are specified by setting CH0 to CH1 bits to “1” state respectively. It is possible to input this command regardless of the NCR status. This command is not available during power down, transition to the power-up state or transition to the power-down state. This command can adjust volume by 32-levels as shown in the table below. The initial value is set to 0 dB after the reset is released. Also, the setting of this command is initialized after the reset is released or during power-up, CV4-0 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F Volume 0dB (initial value) -0.28 -0.58 -0.88 -1.20 -1.53 -1.87 -2.22 -2.59 -2.98 -3.38 -3.81 -4.25 -4.72 -5.22 -5.74 CV4-0 10 Volume 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F -6.90 -7.55 -8.24 -9.00 -9.83 -10.74 -11.77 -12.93 -14.26 -15.85 -17.79 -20.28 -23.81 -29.83 OFF -6.31 - Channel setting method CH 0 CH 1 Channel Channel 1 Channel 2 52/63 FEDL228XX-05 ML2282X-XXX/ ML2286X -XXX 13. AVOL command x command 0 0 0 0 0 AV5 0 AV4 1 AV3 0 AV2 0 AV1 0 AV0 1st byte 2nd byte The AVOL command uses 2 bytes. This command is used to adjust the playback volume. It is possible to input this ommand regardless of the NCR status.. This command is not available during power down state, transition to power-up state or transition to power-down state. This command can adjust volume by 50-level as shown in the table below. The initial value is set to -4.0 dB after the released. When the STOP command is input, the value set by the AVOL command is retained. When powered down, the value set by the AVOL command is initialized. AV5-0 Volume(dB) AV5-0 Volume (dB) AV5-0 Volume (dB) AV5-0 Volume (dB) 3F 3E 3D 3C 3B 3A 39 38 37 36 35 34 +12.0 +11.5 +11.0 +10.5 +10.0 +9.5 +9.0 +8.5 +8.0 +7.5 +7.0 +6.5 2F 2E 2D 2C 2B 2A 29 28 27 26 25 24 1F 1E 1D 1C 1B 1A 19 18 17 16 15 14 -8.0 -9.0 -10.0 -11.0 -12.0 -13.0 -14.0 -16.0 -18.0 -20.0 -22.0 -24.0 0F 0E 0D 0C 0B 0A 09 08 07 06 05 04 -34.0 OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF 33 +6.0 23 13 -26.0 03 OFF 32 31 30 +5.5 +5.0 +4.5 22 21 20 +4.0 +3.5 +3.0 +2.5 +2.0 +1.5 +1.0 +0.5 +0.0 -1.0 -2.0 -3.0 -4.0 (initial value) -5.0 -6.0 -7.0 12 11 10 -28.0 -30.0 -32.0 02 01 00 OFF OFF OFF To know the volume controls more Three commands (: CVOL, AVOL and AMODE) can control volume. CVOL sets volume of each channel. AVOL sets volume of signal after mixing. And AMODE sets input gain of amplifier. CVOL setting DAG bits on AMODE AVOL setting Channel1 Ch2 MIXING Channel2 Ch3 DAC Filter GAIN AMP SPP AMP GAIN AMP SPM AIG bit on AMODE AIN 53/63 FEDL228XX-05 ML2282X-XXX/ ML2286X -XXX TERMINATION OF THE SG PIN The SG pin is the signal ground for the built-in speaker amplifier. Connect a capacitor between this pin and the analog ground (:DGND) pin to prevent the trouble caused by noise. Recommended capacitance value is shown below; however, it is important to evaluate and decide using the own board. Also, start playback after each output voltage is stabilized. Pin Recommended capacitance value Remarks SG 0.1 μF ±20% The time to stabilize voltage of the speaker output (:SPM and SPP) is longer, if use the larger capacitance. TERMINATION OF THE VDDL AND VDDR PINS The VDDL pin is the regulator output that is power supply pin for the internal logic circuits and the VDDL pin is the power supply pin for the P2ROM. Connect a capacitor between this pin and the ground in order to prevent noise generation and power fluctuation. The recommended capacitance value is shown below. However, it is important to evaluate and decide using the own board. Also, start the next operation after each output voltage is stabilized. Pin Recommended capacitance value Remarks VDDL, VDDR 10 μF ±20% The larger the connection capacitance, the longer the settling time. 54/63 FEDL228XX-05 ML2282X-XXX/ ML2286X -XXX POWER SUPPLY WIRING The power supplies of this LSI are divided into the following two: • Power supply for logic circuitry (: DVDD) • Power supply for speaker amplifier (: SPVDD) As shown in the figure below, supply DVDD and SPVDD from the same power supply, and separate them into analog and logic power supplies in the wiring. DVDD DGND 5V SPVDD SPGND 55/63 FEDL228XX-05 ML2282X-XXX/ ML2286X -XXX RECOMMENDED CERAMIC OSCILLATION Recommended ceramic resonators for oscillation and conditions are shown below for reference. KYOCERA Corporation Optimal load capacity Freq [Hz] Type 4.096M PBRC4.096MR50X000 C1 [pF] C2 [pF] 15(internal) Rf Rd Supply voltage [Ohm] [Ohm] Range [V] --- -- Rf [Ohm] C1 [pF] 30 (internal) --- --- 30 (internal) --- --- 2.7 to3.3 4.5 to5.5 Operating Temperature Range [°C] -20 to +85 Note: C1 and C2 are capacitors built-in resonator. Circuit diagram GND VDD C1 C2 TDK Corporation Optimal load capacity Freq [Hz] Type FCR4.0MXC5 4.000M FCR4.0MXC5 FCR4.09MXC5 4.096M FCR4.09MXC5 C1 [pF] CL2 [pF] Supply voltage Range [V] 2.7 to3.6 4.5 to5.5 2.7 to3.6 4.5 to5.5 Operating Temperature Range [°C] -40 to +85 -40 to +85 Note: C1 and C2 are capacitors built-in resonator. Circuit diagram GND VDD CL1 CL2 56/63 FEDL228XX-05 ML2282X-XXX/ ML2286X -XXX MURATA Corporation Freq [Hz] 4.000M 4.096M Type C1 [pF] C2 [pF] SMD CSTCR4M00G55-R0 39 (Built-in) Leaded CSTLS4M00G56-B0 47 (Built-in) SMD CSTCR4M00G55-R0 39 (Built-in) Leaded CSTLS4M00G56-B0 47 (Built-in) SMD CSTCR4M09G55-R0 39 (Built-in) Leaded CSTLS4M09G56-B0 47 (Built-in) SMD CSTCR4M09G55-R0 39 (Built-in) Leaded CSTLS 4M09G56-B0 47 (Built-in) Optimal load capacity Supply Rf Rd voltage [Ohm] [Ohm] Range [V] Operating Temperature Range [°C] 2.7 to 3.6 --- 0 4.5 to 5.5 -40 to +85* 2.7 to 3.6 --- 0 4.5 to 5.5 Note: C1 and C2 are capacitors built-in resonator. Circuit diagram GND VDD C1 C2 57/63 FEDL228XX-05 ML2282X-XXX/ ML2286X -XXX APPLICATION CIRCUIT (ML2282X: DVDD = SPVDD = 5V) MCU RESETB CSB SCK SI SO CBUSYB DIPH SPM SPP Speaker SG TESTI1 AIN 0.1μF 0.1μF TESTI0 33pF XT VDDL VDDR DVDD SPVDD 4.096MHz 10μF 0.1μF XTB 33pF 10μF 0.1μF 5V DGND SPGND APPLICATION CIRCUIT (ML2282X: DVDD = SPVDD = 3V) MCU RESETB CSB SCK SI SO CBUSYB DIPH TESTI1 SPM SPP Speaker SG 0.1μF AIN 0.1 μF TESTI0 33pF XT VDDL VDDR DVDD SPVDD 4.096MHz 0.1μF XTB 33pF 10μF DGND SPGND 0.1μF 0.1μF 3V 58/63 FEDL228XX-05 ML2282X-XXX/ ML2286X -XXX APPLICATION CIRCUIT (ML2286X: DVDD=SPVDD=5V) 7kΩ 7kΩ SCL SDA (CBUSYB) MCU SPM SPP Speaker SAD2-0 SG TESTI0 AIN 0.1μF 0.1μF TESTI1 33pF XT VDDL VDDR DVDD SPVDD 4.096MHz 10μF 0.1μF XTB 33pF 10μF 0.1μF 5V DGND SPGND APPLICATION CIRCUIT (ML2286X: DVDD=SPVDD=3V) 7kΩ 7kΩ SCL SDA (CBUSYB) MCU SPM SPP Speaker SAD2-0 SG TESTI0 AIN 0.1μF 0.1μF TESTI1 33pF XT VDDL VDDR DVDD SPVDD 4.096MHz 0.1μF XTB 33pF DGND SPGND 0.1μF 0.1μF 10μF 3V 59/63 FEDL228XX-05 ML2282X-XXX/ ML2286X -XXX PACKAGE DIMENSIONS (Unit: mm) Notes for Mounting the Surface Mount Type Package The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact ROHM’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 60/63 FEDL228XX-05 ML2282X-XXX/ ML2286X -XXX REVISION HISTORY Page Previous Current Edition Edition Document No. Date PEDL2282XFULL-01 Dec. 17, 2007 – – Preliminary edition 1 FEDL228XXFULL-01 Apr. 18, 2008 – – Final edition 1 FEDL228XXFULL-02 May. 29, 2008 – – Final edition 2 1 1 2-channel mixing function 48kHz-> 32kHz 2 2 Power supply voltage 2.7 to 5.5V -> 2.7 to 3.6V / 4.5 to 5.5 V 10 10 LINE output voltage range MAX. DVDD x 4/6 -> DVDD x 5/6 10 10 SG output resistance Min 52 -> Min 57 10 10 AIN input voltage range(for the 5V app..) Max. DVDD x 2/4 -> DVDD x 2/3 11 11 CBUSYB “L” level output time PUP: (Min= - /Typ= - /Max=10) -> (Min=2.0/Typ=2.5/Max=3.0) 11 11 CBUSYB “L” level output time tCB1: Max= 2μs -> Max= 2ms 13 13 (Ta = -40 to +70) -> (Ta = -40 to +85) 12,24,32, 33,34,35 12,24,32, 33,34,35 26 26 44, 45 44, 45 45 45 50,51 50,51 Modify application circuit 45 45 Correct value for AVOL 6 6 Modify SCL/SDA initial value.(0 -> 1) - 13 - 19-25 Add timing chart( I2C interface ) - 29-30 Add timing chart( I2C interface ) 53 53 FEDL228XXFULL-03 FEDL228XXFULL-04 Description Mar. 24, 2009 Jun. 20, 2011 PUP(AMODE) -> POP(AMODE) Correct ROM address and calculation Modify volume table Add volume setting information Add “Pulse width of spikes which must be suppressed by the input filter”. Modify AVOL table 61/63 FEDL228XX-05 ML2282X-XXX/ ML2286X -XXX Document No. Date FEDL228XX-05 Oct. 10, 2013 Page Previous Current Edition Edition 12 12 Description Modify tDOD1. ( SCK rise edge -> SCK fall edge ) 62/63 FEDL228XX-05 ML2282X-XXX/ ML2286X -XXX NOTES No copying or reproduction of this document, in part or in whole, is permitted without the consent of LAPIS Semiconductor Co., Ltd. The content specified herein is subject to change for improvement without notice. Examples of application circuits, circuit constants and any other information contained herein illustrate the standard usage and operations of the Products. The peripheral conditions must be taken into account when designing circuits for mass production. Great care was taken in ensuring the accuracy of the information specified in this document. However, should you incur any damage arising from any inaccuracy or misprint of such information, LAPIS Semiconductor shall bear no responsibility for such damage. The technical information specified herein is intended only to show the typical functions of and examples of application circuits for the Products. LAPIS Semiconductor does not grant you, explicitly or implicitly, any license to use or exercise intellectual property or other rights held by LAPIS Semiconductor and other parties. LAPIS Semiconductor shall bear no responsibility whatsoever for any dispute arising from the use of such technical information. The Products specified in this document are intended to be used with general-use electronic equipment or devices (such as audio visual equipment, office-automation equipment, communication devices, electronic appliances and amusement devices). The Products specified in this document are not designed to be radiation tolerant. While LAPIS Semiconductor always makes efforts to enhance the quality and reliability of its Products, a Product may fail or malfunction for a variety of reasons. Please be sure to implement in your equipment using the Products safety measures to guard against the possibility of physical injury, fire or any other damage caused in the event of the failure of any Product, such as derating, redundancy, fire control and fail-safe designs. LAPIS Semiconductor shall bear no responsibility whatsoever for your use of any Product outside of the prescribed scope or not in accordance with the instruction manual. The Products are not designed or manufactured to be used with any equipment, device or system which requires an extremely high level of reliability the failure or malfunction of which may result in a direct threat to human life or create a risk of human injury (such as a medical instrument, transportation equipment, aerospace machinery, nuclear-reactor controller, fuel-controller or other safety device). LAPIS Semiconductor shall bear no responsibility in any way for use of any of the Products for the above special purposes. If a Product is intended to be used for any such special purpose, please contact a ROHM sales representative before purchasing. If you intend to export or ship overseas any Product or technology specified herein that may be controlled under the Foreign Exchange and the Foreign Trade Law, you will be required to obtain a license or permit under the Law. Copyright 2007-2013 LAPIS Semiconductor Co., Ltd. 63/63