NB4L6254 2.5V / 3.3V Differential LVPECL 2x2 Clock Switch and Low Skew Fanout Buffer http://onsemi.com Description The NB4L6254 is a differential 2x2 clock switch and drives precisely aligned clock signals through its LVPECL fanout buffers. It employs a fully differential architecture with bipolar technology, offers superior digital signal characteristics, has very low clock output skew and supports clock frequencies from DC up to 3.0 GHz. The NB4L6254 is designed for the most demanding, skew critical differential clock distribution systems. Typical applications for the NB4L6254 are clock distribution, switching and data loopback systems of high−performance computer, networking and telecommunication systems, as well as on−board clocking of OC−3, OC−12 and OC−48 communication systems. In addition, the NB4L6254 can be configured as a single 1:6 or dual 1:3 LVPECL fanout buffer. The NB4L6254 can be operated from a single 3.3 V or 2.5 V power supply. MARKING DIAGRAM* NB4L 6254 AWLYYWWG LQFP−32 FA SUFFIX CASE 873A A WL YY WW G = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package *For additional marking information, refer to Application Note AND8002/D. Features • • • • • • • • • • • Maximum Clock Input Frequency, 3 GHz CLK0 Maximum Input Data Rate, 3 Gb/s CLK0 Differential LVPECL Inputs and Outputs Low Output Skew: 50 ps Maximum Output−to−Output Skew Synchronous Output Enable Eliminating Output Runt Pulse Generation and Metastability CLK1 Operating Range: Single 3.3 V or 2.5 V Supply CLK1 VCC = 2.375 V to 3.465 V LVCMOS Compatible Control Inputs SEL0 Packaged in LQFP−32 SEL1 Fully Differential Architecture −40°C to 85°C Ambient Operating Temperature OEA These are Pb−Free Devices* OEB VCC Bank A QA0 QA0 QA1 QA1 QA2 QA2 Bank B QB0 QB0 QB1 QB1 QB2 QB2 0 1 VCC 0 1 Figure 1. Functional Block Diagram *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. © Semiconductor Components Industries, LLC, 2006 August, 2006 − Rev. 1 1 ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 7 of this data sheet. Publication Order Number: NB4L6254/D NB4L6254 VCC 24 GND 23 OEA CLK0 CLK0 SEL0 GND 22 21 20 19 18 VCC 17 QA2 25 16 QB2 QA2 26 15 QB2 VCC 27 14 VCC QA1 28 13 QB1 12 QB1 LQFP−32 QA1 29 VCC 30 11 VCC QA0 31 10 QB0 QA0 32 9 QB0 1 VCC 2 3 4 5 6 GND SEL1 CLK1 CLK1 OEB 7 GND 8 VCC Figure 2. Pin Configuration (Top View) Table 1. PIN CONFIGURATION Pin Name I/O Description CLK0, CLK0 LVPECL Input Differential reference clock signal input 0. CLK1, CLK1 LVPECL Input Differential reference clock signal input 1. OEAb, OEB LVCMOS Input Output Enable SEL0, SEL1 LVCMOS Input Clock Switch Select QA[0−2], QA[0−2] QB[0−2], QB[0−2] LVPECL Output Differential LVPECL Clock Outputs, (banks A and B) Typically terminated with 50 W resistor to VCC – 2.0 V. GND Power Supply Negative Supply Voltage VCC Power Supply Positive supply voltage. All VCC pins must be connected to the positive power supply for correct DC and AC operation. Table 2. FUNCTION TABLE Control Default 0 1 OEA 0 QA[0−2], QA[0−2] are active. Deassertion of OEA can be asynchronous to the reference clock without generation of output runt pulses QA[0−2] = L, QA[0−2] = H (outputs disabled). Assertion of OE can be asynchronous to the reference clock without generation of output runt pulses OEB 0 QB[0−2], QB[0−2] are active. Deassertion of OEB can be asynchronous to the reference clock without generation of output runt pulses QB[0−2] = L, QB[0−2] = H (outputs disabled). Assertion of OE can be asynchronous to the reference clock without generation of output runt pulses SEL0, SEL1 00 Refer to Table 3 Refer to Table 3 Table 3. CLOCK SELECT CONTROL SEL0 SEL1 CLK0 Routed To CLK1 Routed to 0 0 QA[0:2] and QB[0:2] − 1:6 Fanout of CLK0 0 1 − QA[0:2] and QB[0:2] 1:6 Fanout of CLK1 1 0 QA[0:2] QB[0:2] Dual 1:3 Buffer 1 1 QB[0:2] QA[0:2] Dual 1:3 Buffer (Crossed) http://onsemi.com 2 Application Mode NB4L6254 Table 4. ATTRIBUTES Characteristics Value Internal Input Pullup Resistor 37.5 kW Internal Input Pulldown Resistor 75 kW ESD Protection Human Body Model Machine Model > 2000 V > 200 V Latchup Immunity >200 mA Cin, inputs 4.0 pF (TYP) Moisture Sensitivity (Note 1) LQFP−32 Flammability Rating Oxygen Index: 28 to 34 Level 2 UL 94 V−0 @ 0.125 in Transistor Count 336 Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional information, see Application Note AND8003/D. Table 5. MAXIMUM RATINGS (Note 2) Parameter Symbol Condition Condition Rating Unit VCC Positive Power Supply −0.3 v VCC v 3.6 V VIN DC Input Voltage −0.3 v VIN v VCC + 0.3 V VOUT DC Output Voltage −0.3 v VOUT v VCC + 0.3 V IIN DC Input Current $20 mA Iout LVPECL DC Output Current Continuous Surge $50 100 mA mA TA Operating Temperature Range LQFP−32 −40 to +85 °C Tstg Storage Temperature Range −65 to +150 °C qJA Thermal Resistance (Junction−to−Ambient) (Note 3) 0 lfpm 500 lfpm LQFP−32 LQFP−32 80 55 °C/W °C/W qJC Thermal Resistance (Junction−to−Case) 2S2P (Note 3) LQFP−32 12 to 17 °C/W Tsol Wave Solder 265 °C VTT Output Termination Voltage VCC – 2.0, TYP V Pb−Free Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 2. Maximum Ratings are those values beyond which device damage may occur. 3. JEDEC standard multilayer board − 2S2P (2 signal, 2 power); MIL−SPEC 883E Method 1012.1. http://onsemi.com 3 NB4L6254 Table 6. DC CHARACTERISTICS VCC = 2.375 V to 3.465 V, GND = 0 V, TA = −40°C to +85°C Symbol Characteristic Min Typ Max Unit 60 85 mA POWER SUPPLY CURRENT IGND Power Supply Current (Outputs Open) LVPECL CLOCK OUTPUTS VOH LVPECL Output HIGH Voltage (Notes 4, 5) VOL LVPECL Output LOW Voltage (Notes 4, 5) VCC = 3.3 V VCC = 2.5 V VCC − 1145 2155 1355 VCC − 1020 2280 1480 VCC – 895 2405 1605 mV VCC = 3.3 V VCC = 2.5 V VCC − 1945 1355 555 VCC − 1770 1530 730 VCC − 1600 1700 900 mV CLOCK INPUTS VPP Dynamic Differential Input Voltage (Clock Inputs) 0.1 1.3 V VCMR Differential Cross−point Voltage (Clock Inputs) 1.0 VCC − 0.3 V LVCMOS CONTROL INPUTS VIH Output HIGH Voltage (LVTTL/LVCMOS) VIL Output LOW Voltage (LVTTL/LVCMOS) IIH Input Current VIN = VCC or VIN = GND 2.0 −100 V 0.8 V +100 mA NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 4. LVPECL Outputs loaded with 50 W termination resistors to VTT = VCC – 2.0 V for proper operation. 5. LVPECL Output parameters vary 1:1 with VCC. http://onsemi.com 4 NB4L6254 Table 7. AC CHARACTERISTICS VCC = 2.375 V to 3.465 V, GND = 0 V, TA = −40°C to +85°C (Note 6) Symbol Max Unit VINPP Differential Input Voltage (Peak−to−Peak) Characteristic Min 0.3 1.3 V VCMR Differential Input Cross−Point Voltage (Clock Inputs) 1.2 VCC − 0.3 V fIN Clock Input Frequency 0 3.0 GHz VOUTPP Differential Output Output Voltage Amplitude (Peak−to−Peak) (Note 7) fO < 1.1 GHz fO < 2.5 GHz fO < 3.0 GHz fCLKOUT Output Clock Frequency Range tpd Propagation Delay CLKx to Qx (Differential Configuration) tskew Within Device Output−to−Output Skew (Differential Configuration) Device−to−Device Skew Output Pulse Skew (Duty Cycle Skew) (Note 8) DCO Output CLOCK Duty Cycle (DC Ref = 50%) (Note 9) tJIT CLOCK Random Jitter (RMS) (SEL0 0 SEL1) (Note 10) tr, tf Output Rise/Fall Times (Note 11) CLKx / CLKx tPDL Output Disable Time, T = CLK period 2.5 T + tPD tPLD Output Enable Time, T = CLK period 3 T + tPD 4 T + tPD ns 0.45 0.35 0.2 Typ 0 tREF <100 MHz tREF < 800 MHz 360 3.0 GHz 485 610 ps 25 30 10 50 250 60 ps 50.6 54.8 % 0.8 ps 300 ps 3.5 T + tPD ns 49.4 45.2 0.3 50 V 0.70 0.55 0.35 130 NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 6. LVPECL Outputs loaded with 50 W to VCC − 2.0V. 7. VOUTPP MIN = 0.1 V @ +85°C, fO < 3.0 GHz. 8. Output Pulse Skew is the absolute difference of the propagation delay times: |tPLH − tPHL| 9. DCOMIN/MAX = 43.2%/59.2% @ +85°C. 10. tJITMAX = 1.6 ps @ 85°C, 3.0 V 11. Measured 20% to 80% http://onsemi.com 5 NB4L6254 CLKX CLKX 50% OEX tPDL (OEX to QXn) tPLD (OEX to QXn) QXn Outputs Disabled QXn VOUTPP, OUTPUT VOLTAGE AMPLITUDE (TYP) Figure 3. Output Disable / Enable Timing 800 700 600 500 400 300 200 100 0 0 1 2 fOUT, CLOCK OUTPUT FREQUENCY (GHz) 3 Figure 4. Output Voltage Amplitude (VOUTPP) versus Clock Output Frequency at Ambient Temperature (Typical) Q Zo = 50 W D Receiver Device Driver Device Q D Zo = 50 W 50 W 50 W VTT VTT = VCC − 2.0 V Figure 5. Typical Termination for Output Driver and Device Evaluation (See Application Note AND8020/D − Termination of ECL Logic Devices.) http://onsemi.com 6 NB4L6254 Example Configurations CLK0 3 System A CLK1 3 SEL0 SEL1 SEL0 SEL1 Switch Configuration 0 0 System Loopback 0 1 Line Loopback 1 0 Transmit/Receive Operation 1 1 System and Line Loopback System B APPLICATIONS INFORMATION Figure 6. 2 x 2 Clock Switch Maintaining Lowest Device Skew SEL0 SEL1 0 0 CLK0 Clocks System A and System B 0 1 CLK1 Clocks System A and System B 1 0 CLK0 Clocks System A and CLK1 Clocks System B 1 1 CLK1 Clocks System B and CLK1 Clocks System A The NB4L6254 guarantees low output−output bank skew at 50 ps and a part−to−part skew of 250 ps. To ensure low skew clock signals in the application, both outputs of any differential output pair need to be terminated identically, even if only one output is used. When fewer than all nine output pairs are used, identical termination of all output pairs within the output bank is recommended. If an entire output bank is not used, it is recommended to leave all of these outputs open and unterminated. This will reduce the device power consumption while maintaining minimum output skew. Switch Configuration Power Supply Bypassing The NB4L6254 is a mixed analog/digital product. The differential architecture of the NB4L6254 supports low noise signal operation at high frequencies. In order to maintain its superior signal quality all VCC pins should be bypassed by high−frequency ceramic capacitors connected to GND. If the spectral frequencies of the internally generated switching noise on the supply pins cross the series resonant port of an individual bypass capacitor, its overall impedance begins to look inductive and thus increases with increasing frequency. The parallel capacitor combination shown ensures that a low impedance path to ground exists for frequencies well above the noise bandwidth. CLK0 CLK1 0 SEL0 0 SEL1 Figure 7. 1:6 Clock Fanout Buffer System−Tx CLK0 Transmitter QAn VCC VCC SEL0 33...100 nF SEL1 QBn System−Rx CLK1 Receiver 0.1 nF NB4L6254 Figure 9. VCC Power Supply Bypass Figure 8. Loopback Device ORDERING INFORMATION Package Shipping † NB4L6254FAG LQFP−32 (Pb−Free) 250 Units / Tray NB4L6254FAR2G LQFP−32 (Pb−Free) 2000 / Tape & Reel Device †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://onsemi.com 7 NB4L6254 PACKAGE DIMENSIONS 32 A1 A −T−, −U−, −Z− 32 LEAD LQFP CASE 873A−02 ISSUE C 4X 25 0.20 (0.008) AB T−U Z 1 AE −U− −T− B P V 17 8 BASE METAL DETAIL Y V1 AC T−U Z AE DETAIL Y ÉÉ ÉÉ ÉÉ 9 −Z− S1 4X 0.20 (0.008) AC T−U Z F S 8X M_ D DETAIL AD G −AB− SECTION AE−AE C E −AC− H W K X DETAIL AD NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DATUM PLANE −AB− IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 4. DATUMS −T−, −U−, AND −Z− TO BE DETERMINED AT DATUM PLANE −AB−. 5. DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE −AC−. 6. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.250 (0.010) PER SIDE. DIMENSIONS A AND B DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE −AB−. 7. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. DAMBAR PROTRUSION SHALL NOT CAUSE THE D DIMENSION TO EXCEED 0.520 (0.020). 8. MINIMUM SOLDER PLATE THICKNESS SHALL BE 0.0076 (0.0003). 9. EXACT SHAPE OF EACH CORNER MAY VARY FROM DEPICTION. DIM A A1 B B1 C D E F G H J K M N P Q R S S1 V V1 W X http://onsemi.com 8 MILLIMETERS MIN MAX 7.000 BSC 3.500 BSC 7.000 BSC 3.500 BSC 1.400 1.600 0.300 0.450 1.350 1.450 0.300 0.400 0.800 BSC 0.050 0.150 0.090 0.200 0.450 0.750 12_ REF 0.090 0.160 0.400 BSC 1_ 5_ 0.150 0.250 9.000 BSC 4.500 BSC 9.000 BSC 4.500 BSC 0.200 REF 1.000 REF INCHES MIN MAX 0.276 BSC 0.138 BSC 0.276 BSC 0.138 BSC 0.055 0.063 0.012 0.018 0.053 0.057 0.012 0.016 0.031 BSC 0.002 0.006 0.004 0.008 0.018 0.030 12_ REF 0.004 0.006 0.016 BSC 1_ 5_ 0.006 0.010 0.354 BSC 0.177 BSC 0.354 BSC 0.177 BSC 0.008 REF 0.039 REF Q_ 0.250 (0.010) 0.10 (0.004) AC GAUGE PLANE SEATING PLANE J R M N 9 0.20 (0.008) B1 NB4L6254 ECLinPS is a trademark of Semiconductor Components INdustries, LLC (SCILLC). ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. 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This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: N. American Technical Support: 800−282−9855 Toll Free Literature Distribution Center for ON Semiconductor USA/Canada P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Japan: ON Semiconductor, Japan Customer Focus Center 2−9−1 Kamimeguro, Meguro−ku, Tokyo, Japan 153−0051 Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Phone: 81−3−5773−3850 Email: [email protected] http://onsemi.com 9 ON Semiconductor Website: http://onsemi.com Order Literature: http://www.onsemi.com/litorder For additional information, please contact your local Sales Representative. NB4L6254/D