AD ADS1216 S1 216 www.ti.com SBAS171D – NOVEMBER 2000 – REVISED SEPTEMBER 2006 8-Channel, 24-Bit ANALOG-TO-DIGITAL CONVERTER FEATURES • • • • • • • • • • • • 24 BITS, NO MISSING CODES 0.0015% INL 22 BITS EFFECTIVE RESOLUTION (PGA = 1), 19 BITS (PGA = 128) PGA FROM 1 TO 128 SINGLE-CYCLE SETTLING MODE PROGRAMMABLE DATA OUTPUT RATES: up to 1kHz ON-CHIP 1.25V/2.5V REFERENCE EXTERNAL DIFFERENTIAL REFERENCE: 0.1V to 2.5V ON-CHIP CALIBRATION SPI™-COMPATIBLE 2.7V TO 5.25V < 1mW POWER CONSUMPTION APPLICATIONS • • • • • • • INDUSTRIAL PROCESS CONTROL LIQUID/GAS CHROMATOGRAPHY BLOOD ANALYSIS SMART TRANSMITTERS PORTABLE INSTRUMENTATION WEIGHT SCALES PRESSURE TRANSDUCERS DESCRIPTION The ADS1216 is a precision, wide dynamic range, delta-sigma, Analog-to-Digital (A/D) converter with 24-bit resolution operating from 2.7V to 5.25V supplies. The delta-sigma A/D converter provides up to 24 bits of no-missing-code performance and an effective resolution of 22 bits. The eight input channels are multiplexed. Internal buffering can be selected to provide a very high input impedance for direct connection to transducers or low-level voltage signals. Burnout current sources are provided that allow for the detection of an open or shorted sensor. An 8-bit Digital-to-Analog Converter (DAC) provides an offset correction with a range of 50% of the FSR (Full-Scale Range). The PGA (Programmable Gain Amplifier) provides selectable gains of 1 to 128 with an effective resolution of 19 bits at a gain of 128. The A/D conversion is accomplished with a second-order delta-sigma modulator and programmable sinc filter. The reference input is differential and can be used for ratiometric cancellation. The onboard current DACs operate independently with the maximum current set by an external resistor. The serial interface is SPI-compatible. Eight bits of digital I/O are also provided that can be used for input or output. The ADS1216 is designed for high-resolution measurement applications in smart transmitters, industrial process control, weight scales, chromatography, and portable instrumentation. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. SPI is a trademark of Motorola. All other trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2000–2006, Texas Instruments Incorporated ADS1216 www.ti.com SBAS171D – NOVEMBER 2000 – REVISED SEPTEMBER 2006 This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ORDERING INFORMATION For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. ABSOLUTE MAXIMUM RATINGS (1) AVDD to AGND DVDD to DGND Input Current Input Current AIN UNIT V –0.3 to +6 V 100, Momentary mA 10, Continuous mA GND – 0.5 to AVDD + 0.5 V AVDD to DVDD –6 to +6 V –0.3 to +0.3 V Digital Input Voltage to GND –0.3 to DVDD + 0.3 V Digital Output Voltage to GND –0.3 to DVDD + 0.3 V +150 °C Operating Temperature Range –40 to +85 °C Storage Temperature Range –60 to +100 °C AGND to DGND Maximum Junction Temperature (1) 2 ADS1216 –0.3 to +6 Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not implied. Submit Documentation Feedback ADS1216 www.ti.com SBAS171D – NOVEMBER 2000 – REVISED SEPTEMBER 2006 ELECTRICAL CHARACTERISTICS: AVDD = +5V All specifications at TMIN to TMAX, AVDD = +5V, DVDD = +2.7V to +5.25V, fMOD = 19.2kHz, PGA = 1, Buffer ON, RDAC = 150kΩ, fDATA = 10Hz, and VREF = +2.5V, unless otherwise specified. ADS1216 PARAMETER CONDITIONS MIN TYP Buffer OFF AGND – 0.1 Buffer ON AGND + 0.05 MAX UNIT AVDD + 0.1 V AVDD – 1.5 V ±VREF/PGA V ANALOG INPUT (AIN0 – AIN7, AINCOM) Analog input range Full-scale input voltage range (In+) – (In–); see Functional Block Diagram Differential input impedance Buffer OFF 5/PGA MΩ Input current Buffer ON 0.5 nA Fast-settling filter –3dB 0.469 × fDATA Hz Sinc2 filter –3dB 0.318 × fDATA Hz Sinc3 filter –3dB 0.262 × fDATA Bandwidth Programmable gain amplifier User-selectable gain ranges 1 Input capacitance Input leakage current Modulator OFF, TA = +25°C Burnout current sources Hz 128 9 pF 5 pA 2 µA OFFSET DAC ±VREF /(2 × PGA) Offset DAC range Offset DAC monotonicity V 8 Offset DAC gain error Offset DAC gain error drift Bits ±10 % 1 ppm/°C SYSTEM PERFORMANCE Resolution 24 No missing codes Integral nonlinearity Bits Sinc3 filter 24 Bits End-point fit ±0.0015 % of FS Offset error (1) 7.5 ppm of FS Offset drift (1) 0.02 ppm of FS/°C Gain error (1) 0.005 % 0.5 ppm/°C Gain error drift (1) Common-mode rejection Normal-mode rejection At DC 100 130 dB fCM = 50Hz, fDATA = 50Hz 120 dB fCM = 60Hz, fDATA = 60Hz 120 dB fSIG = 50Hz, fDATA = 50Hz 100 dB fSIG = 60Hz, fDATA = 60Hz 100 dB Output noise Power-supply rejection dB fCM = 60Hz, fDATA = 10Hz See Typical Characteristics At DC, dB = –20 log(∆VOUT/∆VDD) (2) 80 REF IN+, REF IN– AGND VREF ≡ (REF IN+) – (REF IN–) 0.1 95 dB VOLTAGE REFERENCE INPUT Reference input range VREF AVDD 2.5 2.6 V V Common-mode rejection at DC 120 dB Common-mode rejection fVREFCM = 60Hz, fDATA = 60Hz 120 dB VREF = 2.5V 1.3 µA Bias current (3) (1) (2) (3) Calibration can minimize these errors. ∆ VOUT is change in digital result. 12pF switched capacitor at fSAMP clock frequency. Submit Documentation Feedback 3 ADS1216 www.ti.com SBAS171D – NOVEMBER 2000 – REVISED SEPTEMBER 2006 ELECTRICAL CHARACTERISTICS: AVDD = +5V (continued) All specifications at TMIN to TMAX, AVDD = +5V, DVDD = +2.7V to +5.25V, fMOD = 19.2kHz, PGA = 1, Buffer ON, RDAC = 150kΩ, fDATA = 10Hz, and VREF = +2.5V, unless otherwise specified. ADS1216 PARAMETER CONDITIONS MIN REF HI = 1 2.4 TYP MAX UNIT 2.5 2.6 V ON-CHIP VOLTAGE REFERENCE Output voltage REF HI = 0 Short-circuit current source Short-circuit current sink Short-circuit duration Sink or source Output impedance V 8 mA 50 µA Indefinite Drift Noise 1.25 15 ppm/°C VRCAP = 0.1µF, BW = 0.1Hz to 100Hz 10 µVPP Sourcing 100µA 3 Ω 50 µs RDAC = 150kΩ, range = 1 0.5 mA RDAC = 150kΩ, range = 2 1 mA RDAC = 150kΩ, range = 3 2 mA mA Startup time IDAC Full-scale output current RDAC = 15kΩ, range = 3 20 Maximum short-circuit current duration RDAC = 10kΩ Indefinite Monotonicity RDAC = 150kΩ RDAC = 0kΩ 10 8 Compliance voltage Bits 0 Output impedance Minute AVDD – 1 V See Typical Characteristics Power-supply rejection ratio VOUT = AVDD/2 400 Absolute error Individual IDAC 5 ppm/V % Absolute drift Individual IDAC 75 ppm/°C Mismatch error Between IDACs, same range and code 0.25 % Mismatch drift Between IDACs, same range and code 15 ppm/°C POWER-SUPPLY REQUIREMENTS Power-supply voltage Analog current (IADC + IVREF + IDAC) ADC current (IADC) AVDD 4.75 1 Digital current Power dissipation V nA PGA = 1, buffer OFF 140 225 µA PGA = 128, buffer OFF 430 650 µA PGA = 1, buffer ON 180 275 µA PGA = 128, buffer ON 800 1250 µA 250 375 µA Excludes load current 480 675 µA Normal mode, DVDD = 5V 180 275 µA SLEEP mode, DVDD = 5V 150 µA Read data continuous mode, DVDD = 5V 230 µA PDWN 1 nA PGA = 1, buffer OFF, REFEN = 0, IDACS OFF, DVDD = 5V 1.6 VREF current (IVREF) IDAC current (IDAC) 5.25 PDWN = 0 or SLEEP 2.5 mW TEMPERATURE RANGE 4 Operating –40 +85 °C Storage –60 +100 °C Submit Documentation Feedback ADS1216 www.ti.com SBAS171D – NOVEMBER 2000 – REVISED SEPTEMBER 2006 ELECTRICAL CHARACTERISTICS: AVDD = +3V All specifications at TMIN to TMAX, AVDD = +3V, DVDD = +2.7V to +5.25V, fMOD = 19.2kHz, PGA = 1, Buffer ON, RDAC = 75kΩ, fDATA = 10Hz, and VREF = +1.25V, unless otherwise specified. ADS1216 PARAMETER CONDITIONS MIN TYP Buffer OFF AGND – 0.1 Buffer ON AGND + 0.05 MAX UNIT AVDD + 0.1 V AVDD – 1.5 V ±VREF/PGA V ANALOG INPUT (AIN0 – AIN7, AINCOM) Analog input range Full-scale input voltage range (In+) – (In–); see Functional Block Diagram Input impedance Buffer OFF 5/PGA MΩ Input current Buffer ON 0.5 nA Fast-settling filter –3dB 0.469 × fDATA Hz Sinc2 filter –3dB 0.318 × fDATA Hz Sinc3 filter –3dB 0.262 × fDATA Bandwidth Programmable gain amplifier User-selectable gain ranges 1 Input capacitance Input leakage current Modulator OFF, TA = +25°C Burnout current sources Hz 128 9 pF 5 pA 2 µA OFFSET DAC ±VREF /(2 × PGA) Offset DAC range Offset DAC monotonicity V 8 Offset DAC gain error Offset DAC gain error drift Bits ±10 % 2 ppm/°C SYSTEM PERFORMANCE Resolution 24 No missing codes Integral nonlinearity Bits Sinc3 filter 24 Bits End-point fit ±0.0015 % of FS Offset error (1) 15 ppm of FS Offset drift (1) 0.04 ppm of FS/°C Gain error (1) 0.010 % 1.0 ppm/°C Gain error drift (1) Common-mode rejection Normal-mode rejection At DC 100 130 dB fCM = 50Hz, fDATA = 50Hz 120 dB fCM = 60Hz, fDATA = 60Hz 120 dB fSIG = 50Hz, fDATA = 50Hz 100 dB fSIG = 60Hz, fDATA = 60Hz 100 dB Output noise Power-supply rejection dB fCM = 60Hz, fDATA = 10Hz See Typical Characteristics At DC, dB = –20 log(∆VOUT/∆VDD) (2) 75 90 dB VOLTAGE REFERENCE INPUT Reference input range VREF REF IN+, REF IN– 0 VREF ≡ (REF IN+) – (REF IN–) 0.1 Common-mode rejection at DC Common-mode rejection Bias current (3) (1) (2) (3) AVDD 1.25 1.3 V V 120 dB fVREFCM = 60Hz, fDATA = 60Hz 120 dB VREF = 1.25V 0.65 µA Calibration can minimize these errors. ∆ VOUT is change in digital result. 12pF switched capacitor at fSAMP clock frequency. Submit Documentation Feedback 5 ADS1216 www.ti.com SBAS171D – NOVEMBER 2000 – REVISED SEPTEMBER 2006 ELECTRICAL CHARACTERISTICS: AVDD = +3V (continued) All specifications at TMIN to TMAX, AVDD = +3V, DVDD = +2.7V to +5.25V, fMOD = 19.2kHz, PGA = 1, Buffer ON, RDAC = 75kΩ, fDATA = 10Hz, and VREF = +1.25V, unless otherwise specified. ADS1216 PARAMETER CONDITIONS MIN TYP MAX REF HI = 0 1.2 1.25 1.3 UNIT ON-CHIP VOLTAGE REFERENCE Output voltage Short-circuit current source Short-circuit current sink Short-circuit duration Sink or source Output impedance mA 50 µA Indefinite Drift Noise V 3 15 ppm/°C VRCAP = 0.1µF, BW = 0.1Hz to 100Hz 10 µVPP Sourcing 100µA 3 Ω 50 µs RDAC = 75kΩ, range = 1 0.5 mA RDAC = 75kΩ, range = 2 1 mA RDAC = 75kΩ, range = 3 2 mA RDAC = 15kΩ, range = 3 20 mA RDAC = 10kΩ Indefinite Startup time IDAC Full-scale output current Maximum short-circuit current duration RDAC = 0kΩ Monotonicity 10 RDAC = 75kΩ 8 Compliance voltage Bits 0 Output impedance Minute AVDD – 1 V See Typical Characteristics Power-supply rejection ratio VOUT = AVDD/2 600 Absolute error Individual IDAC 5 ppm/V % Absolute drift Individual IDAC 75 ppm/°C Mismatch error Between IDACs, same range and code 0.25 % Mismatch drift Between IDACs, same range and code 15 ppm/°C POWER-SUPPLY REQUIREMENTS Power-supply voltage Analog current (IADC + IVREF + IDAC) ADC current (IADC) AVDD 2.7 1 Digital current Power dissipation V nA PGA = 1, buffer OFF 120 200 µA PGA = 128, buffer OFF 370 600 µA PGA = 1, buffer ON 170 250 µA PGA = 128, buffer ON 750 1200 µA 250 375 µA Excludes load current 480 675 µA Normal mode, DVDD = 3V 90 200 µA VREF current (IVREF) IDAC current (IDAC) 3.3 PDWN = 0 or SLEEP SLEEP mode, DVDD = 3V 75 µA Read data continuous mode, DVDD = 3V 113 µA PDWN = 0 1 nA PGA = 1, buffer OFF, REFEN = 0, IDACS OFF, DVDD = 3V 0.6 1.2 mW TEMPERATURE RANGE 6 Operating –40 +85 °C Storage –60 +100 °C Submit Documentation Feedback ADS1216 www.ti.com SBAS171D – NOVEMBER 2000 – REVISED SEPTEMBER 2006 DIGITAL CHARACTERISTICS: TMIN to TMAX, DVDD +2.7V to +5.25V ADS1216 PARAMETER CONDITIONS MIN TYP MAX UNIT Digital input/output Logic family CMOS Logic level: VIH 0.8 × DVDD DVDD V Logic level: VIL DGND 0.2 × DVDD V Logic level: VOH IOH = 1mA DVDD – 0.4 Logic level: VOL IOL = 1mA DGND Input leakage: IIH VI = DVDD Input leakage: IIL VI = 0 V 10 µA 1 5 MHz 200 1000 ns µA –10 Master clock rate: fOSC Master clock period: tOSC V DGND + 0.4 1/fOSC FUNCTIONAL BLOCK DIAGRAM AGND RDAC AVDD VREFOUT VREF+ VRCAP VREF- XIN XOUT 8-Bit IDAC IDAC2 8-Bit IDAC IDAC1 AVDD 2m A Clock Generator 1.25V or 2.5V Reference Offset DAC AIN0 A = 1:128 AIN1 Registers IN+ AIN2 AIN3 MUX AIN4 IN- BUF + 2nd-Order Modulator PGA Programmable Digital Filter Controller RAM AIN5 AIN6 AIN7 AINCOM POL 2m A Serial Interface Digital I/O Interface AGND DVDD DGND SCLK DIN DOUT CS BUFEN D0 ... D7 PDWN Submit Documentation Feedback DSYNC RESET DRDY 7 ADS1216 www.ti.com SBAS171D – NOVEMBER 2000 – REVISED SEPTEMBER 2006 TIMING CHARACTERISTICS CS t3 t1 t2 t10 SCLK (POL = 0) SCLK (POL = 1) t4 DIN MSB t2 t6 t5 t11 LSB (Command or Command and Data) t7 DOUT t8 MSB t9 (1) LSB (1) NOTE: (1) Bit Order = 0. SPEC t1 DESCRIPTION MIN SCLK period t2 SCLK pulse width, HIGH and LOW t3 t4 t5 MAX UNITS 3 DRDY periods 4 tOSC periods 200 ns CS LOW to first SCLK edge; setup time 0 ns DIN valid to SCLK edge; setup time 50 ns Valid DIN to SCLK edge; hold time 50 ns RDATA, RDATAC, RREG, WREG, RRAM, WRAM 50 tOSC periods CSREG, CSRAMX, CSRAM 200 tOSC periods CSARAM, CSARAMX 1100 tOSC periods Delay between last SCLK edge for DIN and first SCLK edge for DOUT: t6 t7 SCLK edge to valid new DOUT t8 SCLK edge to DOUT, hold time 0 50 ns t9 Last SCLK edge to DOUT tri-state NOTE: DOUT goes tri-state immediately when CS goes HIGH. 6 t10 CS LOW time after final SCLK edge 16 tOSC periods 4 tOSC periods CREG, CRAM 220 tOSC periods CREGA 1600 tOSC periods SELFGCAL, SELFOCAL, SYSOCAL, SYSGCAL 7 DRDY periods SELFCAL 14 DRDY periods RESET (Command, SCLK or Pin), DSYNC 16 tOSC periods ns 10 tOSC periods Final SCLK edge of one op code until first edge SCLK of next command: RREG, WREG, RRAM, WRAM, CSRAMX, CSARAMX, CSRAM, CSARAM, CSREG, SLEEP, RDATA, RDATAC, STOPC t11 8 Submit Documentation Feedback ADS1216 www.ti.com SBAS171D – NOVEMBER 2000 – REVISED SEPTEMBER 2006 ADS1216 Resets On Falling Edge SCLK Reset Waveform t13 t13 SCLK t12 t14 t15 t16 t17A RESET, DSYNC, PDWN DRDY t17B SPEC DESCRIPTION t12 MIN MAX UNITS 300 500 tOSC periods t13 5 t14 550 750 tOSC periods t15 1050 1250 tOSC periods 4 tOSC periods DOR data not valid during this update period 4 tOSC periods DOR data not valid during this update period 12 tOSC periods SCLK CS DRDY DVDD DGND DSYNC POL PDWN XOUT XIN DEVICE INFORMATION DIN 36 35 34 33 32 31 30 29 28 27 26 25 D0 37 24 RESET D1 38 23 BUFEN D2 39 22 DGND D3 40 21 DGND D4 41 20 DGND D5 42 19 DGND ADS1216 D6 43 18 DGND D7 44 17 RDAC 2 3 4 5 6 7 8 9 10 11 12 AGND 1 AINCOM 13 AVDD AIN7 VREF- 48 AIN6 14 VRCAP AIN5 VREF+ 47 AIN4 15 IDAC1 AIN3 VREFOUT 46 AIN2 16 IDAC2 AIN1 AGND 45 AIN0 t17B AGND t17A DOUT Pulse width AVDD t16 tOSC periods Submit Documentation Feedback 9 ADS1216 www.ti.com SBAS171D – NOVEMBER 2000 – REVISED SEPTEMBER 2006 DEVICE INFORMATION (continued) TERMINAL FUNCTIONS PIN NUMBER 10 NAME DESCRIPTION 1, 13 AVDD Analog power supply 2, 12, 45 AGND Analog ground 3–10 AIN0–7 Analog input 0–7 11 AINCOM Analog input common 14 VRCAP VREF bypass capcitor 15 IDAC1 Current DAC1 output 16 IDAC2 Current DAC2 output 17 RDAC Current DAC resistor 18–22, 30 DGND Digital ground 23 BUFEN Buffer enable 24 RESET Active LOW; resets the entire chip. 25 XIN 26 XOUT 27 PDWN 28 POL 29 DSYNC Clock input Clock output, used with crystal or resonator. Active LOW; power down. The power-down function shuts down the analog and digital circuits. Serial clock polarity Active LOW; synchronization control 31 DVDD Digital power supply 32 DRDY Active LOW; data ready 33 CS Active LOW; chip select 34 SCLK Serial clock, Schmitt trigger 35 DIN 36 DOUT Serial data input, Schmitt trigger 37–44 D0–D7 46 VREFOUT 47 VREF+ Positive differential reference input 48 VREF– Negative differential reference input Serial data output Digital I/O 0–7 Voltage reference output Submit Documentation Feedback ADS1216 www.ti.com SBAS171D – NOVEMBER 2000 – REVISED SEPTEMBER 2006 TYPICAL CHARACTERISTICS At AVDD = +5V, DVDD = +5V, fOSC = 2.4576MHz, PGA = 1, RDAC = 150kΩ, fDATA = 10Hz, and VREF = +2.5V, unless otherwise specified. EFFECTIVE NUMBER OF BITS vs DECIMATION RATIO 22 22 PGA8 21 21 20 20 19 19 18 PGA16 17 PGA32 PGA64 ENOB (rms) ENOB (rms) PGA4 PGA2 PGA1 EFFECTIVE NUMBER OF BITS vs DECIMATION RATIO PGA128 16 18 17 14 PGA16 14 3 Sinc Filter 13 13 3 Sinc Filter, Buffer ON 12 12 0 500 1000 1500 0 2000 500 Decimation Ratio = fMOD/fDATA 22 1500 Figure 1. Figure 2. EFFECTIVE NUMBER OF BITS vs DECIMATION RATIO EFFECTIVE NUMBER OF BITS vs DECIMATION RATIO PGA2 PGA1 20 20 19 19 18 PGA32 PGA16 PGA4 PGA2 21 17 2000 22 PGA8 PGA4 21 16 1000 Decimation Ratio = fMOD/fDATA ENOB (rms) ENOB (rms) PGA128 PGA64 PGA32 16 15 15 PGA128 PGA64 PGA8 PGA1 18 17 16 PGA16 15 15 PGA32 PGA128 PGA64 14 14 13 13 3 Sinc Filter, VREF = 1.25V, BUFFER OFF 12 0 500 1000 1500 3 Sinc Filter, VREF = 1.25, BUFFER ON 12 0 2000 500 Decimation Ratio = fMOD/fDATA 1000 1500 2000 Decimation Ratio Figure 3. Figure 4. EFFECTIVE NUMBER OF BITS vs DECIMATION RATIO FAST-SETTLING FILTER EFFECTIVE NUMBER OF BITS vs DECIMATION RATIO 22 22 PGA2 21 PGA4 PGA8 21 PGA1 20 20 19 19 18 17 PGA32 PGA16 PGA64 PGA128 16 ENOB (rms) ENOB (rms) PGA8 PGA4 PGA2 PGA1 18 17 16 15 15 14 14 2 Sinc Filter 13 13 Fast-Settling Filter 12 12 0 500 1000 1500 2000 0 Decimation Ratio = fMOD/fDATA 500 1000 1500 2000 Decimation Ratio = fMOD/fDATA Figure 5. Figure 6. Submit Documentation Feedback 11 ADS1216 www.ti.com SBAS171D – NOVEMBER 2000 – REVISED SEPTEMBER 2006 TYPICAL CHARACTERISTICS (continued) At AVDD = +5V, DVDD = +5V, fOSC = 2.4576MHz, PGA = 1, RDAC = 150kΩ, fDATA = 10Hz, and VREF = +2.5V, unless otherwise specified. NOISE vs INPUT SIGNAL CMRR vs FREQUENCY 0.8 0.6 0.5 CMRR (dB) Noise (rms, ppm of FS) 0.7 0.4 0.3 0.2 0.1 0 -2.5 -1.5 0.5 -0.5 1.5 130 120 110 100 90 80 70 60 50 40 30 20 10 0 2.5 1 10 VIN (V) 100 Figure 7. 10k 100k Figure 8. PSRR vs FREQUENCY OFFSET vs TEMPERATURE 50 120 110 PGA16 PGA1 100 0 Offset (ppm of FS) 90 80 PSRR (dB) 1k Frequency of CM Signal (Hz) 70 60 50 40 30 -50 PGA64 -100 PGA128 -150 20 10 0 -200 1 10 100 1k 10k 100k -50 -30 Figure 9. 10 30 50 70 90 Figure 10. GAIN vs TEMPERATURE INTEGRAL NONLINEARITY vs INPUT SIGNAL 10 1.00010 8 1.00006 -40°C 6 INL (ppm of FS) Gain (Normalized) -10 Temperature (°C) Frequency of Power Supply (Hz) 1.00002 0.99998 0.99994 4 2 +85°C 0 -2 -4 +25°C -6 0.99990 -8 0.99986 -50 -30 -10 10 30 50 70 90 -10 -2.5 -2.0 -1.5 -1.0 -0.5 Figure 11. 12 0 0.5 VIN (V) Temperature (°C) Figure 12. Submit Documentation Feedback 1.0 1.5 2.0 2.5 ADS1216 www.ti.com SBAS171D – NOVEMBER 2000 – REVISED SEPTEMBER 2006 TYPICAL CHARACTERISTICS (continued) At AVDD = +5V, DVDD = +5V, fOSC = 2.4576MHz, PGA = 1, RDAC = 150kΩ, fDATA = 10Hz, and VREF = +2.5V, unless otherwise specified. CURRENT vs TEMPERATURE 250 ADC CURRENT vs PGA 900 IDIGITAL AVDD = 5V, Buffer = ON 800 Buffer = OFF 700 600 150 IADC (mA) Current (mA) 200 IANALOG 100 500 AVDD = 3V, Buffer = ON 400 Buffer = OFF 300 200 50 100 0 0 -50 -30 10 -10 30 50 70 90 0 1 4 8 16 PGA Setting Figure 13. Figure 14. DIGITAL CURRENT 32 64 128 HISTOGRAM OF OUTPUT DATA 400 4500 Normal 4.91MHz 300 Normal 2.45MHz 250 4000 Number of Occurrences 350 Current (mA) 2 Temperature (°C) SLEEP 4.91MHz 200 150 100 50 SLEEP 2.45MHz Power-Down 3500 3000 2500 2000 1500 1000 500 0 0 3.0 4.0 5.0 -2.0 -1.5 -1.0 -0.5 VDD (V) 0 0.5 1.0 1.5 2.0 ppm of FS Figure 15. Figure 16. VREFOUT vs LOAD CURRENT OFFSET DAC – OFFSET vs TEMPERATURE 200 2.55 170 Offset (ppm of FSR) VREFOUT (V) 140 2.50 110 80 50 20 -10 -40 -70 2.45 -0.5 -100 0 0.5 1.0 1.5 2.0 2.5 -50 -30 -10 10 30 50 70 90 Temperature (°C) VREFOUT Current Load (mA) Figure 17. Figure 18. Submit Documentation Feedback 13 ADS1216 www.ti.com SBAS171D – NOVEMBER 2000 – REVISED SEPTEMBER 2006 TYPICAL CHARACTERISTICS (continued) At AVDD = +5V, DVDD = +5V, fOSC = 2.4576MHz, PGA = 1, RDAC = 150kΩ, fDATA = 10Hz, and VREF = +2.5V, unless otherwise specified. OFFSET DAC – GAIN vs TEMPERATURE IDAC ROUT vs VOUT 1.00020 1.000 1.00016 +85°C 1.000 1.00008 IOUT (Normalized) Normalized Gain 1.00012 1.00004 1.00000 0.99996 0.99992 0.99988 +25°C 0.999 0.999 0.99984 -40°C 0.99980 0.99976 0.998 -50 -30 10 -10 30 50 70 90 0 1 2 3 Temperature (°C) VDD - VOUT (V) Figure 19. Figure 20. IDAC NORMALIZED vs TEMPERATURE 4 5 IDAC MATCHING vs TEMPERATURE 1.010 3000 2000 1000 IDAC Match (ppm) IOUT (Normalized) 1.005 1.000 0.995 0 -1000 -2000 -3000 -4000 0.990 -5000 0.985 -6000 -50 -30 10 -10 30 50 70 90 -50 -30 50 70 Figure 21. Figure 22. IDAC DIFFERENTIAL NONLINEARITY (Range = 1, RDAC = 150kΩ, VREF = 2.5V) IDAC INTEGRAL NONLINEARITY (Range = 1, RDAC = 150kΩ, VREF = 2.5V) 0.5 0.5 0.4 0.4 0.3 0.3 0.2 0.2 0.1 0.1 INL (LSB) DNL (LSB) 30 90 Temperature (°C) 0 -0.1 0 -0.1 -0.2 -0.2 -0.3 -0.3 -0.4 -0.4 -0.5 -0.5 0 14 10 -10 Temperature (°C) 32 64 96 128 160 192 224 255 0 32 64 96 128 160 IDAC Code IDAC Code Figure 23. Figure 24. Submit Documentation Feedback 192 224 255 ADS1216 www.ti.com SBAS171D – NOVEMBER 2000 – REVISED SEPTEMBER 2006 OVERVIEW INPUT MULTIPLEXER The input multiplexer provides for any combination of differential inputs to be selected on any of the input channels, as shown in Figure 25. If channel 1 is selected as the positive differential input channel, any other channel can be selected as the negative differential input channel. With this method, it is possible to have up to eight fully-differential input channels. In addition, current sources are supplied that will source or sink current to detect open or short circuits on the pins. AIN0 AIN1 AVDD Burnout Current Source On AIN2 of the diode is connected to the negative input of the A/D converter. The output of IDAC1 is connected to the anode to bias the diode and the cathode of the diode is also connected to ground to complete the circuit. In this mode, the output of IDAC1 is also connected to the output pin, so some current may flow into an external load from IDAC1, rather than the diode. See Application Report Measuring Temperature with the ADS1216, ADS1217, or ADS1216 (SBAA073), available for download at www.ti.com, for more information. BURNOUT CURRENT SOURCES When the Burnout bit is set in the ACR Configuration Register (see the Register Map section), two current sources are enabled. The current source on the positive input channel sources approximately 2µA of current. The current source on the negative input channel sinks approximately 2µA. This sinking allows for the detection of an open circuit (full-scale reading) or short circuit (0V differential reading) on the selected input differential pair. INPUT BUFFER AIN3 AIN4 AIN5 Burnout Current Source On AIN6 The input impedance of the ADS1216 without the buffer is 5MΩ/PGA. With the buffer enabled, the input voltage range is reduced and the analog power-supply current is higher. The buffer is controlled by ANDing the state of the buffer pin with the state of the BUFFER bit in the ACR Register (see the Register Map section). See Application Report Input Currents for High-Resolution ADCs (SBAA080), available for download at www.ti.com, for more information. AGND IDAC1 AIN7 AINCOM Figure 25. Input Multiplexer Configuration TEMPERATURE SENSOR An on-chip diode provides temperature sensing capability. When the configuration register for the input MUX is set to all 1s, the diode is connected to the input of the A/D converter. All other channels are open. The anode of the diode is connected to the positive input of the A/D converter, and the cathode IDAC1 AND IDAC2 The ADS1216 has two 8-bit current output DACs that can be controlled independently. The output current is set with RDAC, the range select bits in the ACR register, and the 8-bit digital value in the IDAC register. The output current equals VREF/(8 × RDAC)(2RANGE – 1)(DAC CODE). With VREFOUT = 2.5V and RDAC = 150kΩ, the full-scale output can be selected to be 0.5, 1, or 2mA. The compliance voltage range is 0 to within 1V of AVDD. When the internal voltage reference of the ADS1216 is used, it is the reference for the IDAC. An external reference may be used for the IDACs by disabling the internal reference and tying the external reference input to the VREFOUT pin. Submit Documentation Feedback 15 ADS1216 www.ti.com SBAS171D – NOVEMBER 2000 – REVISED SEPTEMBER 2006 PROGRAMMABLE GAIN AMPLIFIER (PGA) ON-CHIP VOLTAGE REFERENCE The PGA can be set to gains of 1, 2, 4, 8, 16, 32, 64, or 128. Using the PGA can improve the effective resolution of the A/D converter. For instance, with a PGA of 1 on a 5V full-scale range, the A/D converter can resolve to 1µV. With a PGA of 128 on a 40mV full-scale range, the A/D converter can resolve to 75nV. A selectable voltage reference (1.25V or 2.5V) is available for supplying the voltage reference input. To use, connect VREF– to AGND and VREF+ to VREFOUT. The enabling and voltage selection are controlled through bits REF EN and REF HI in the Setup Register (see the Register Map section). The 2.5V reference requires AVDD = +5V. When using the on-chip voltage reference, the VREFOUT pin should be bypassed with a 0.1µF capacitor to AGND. PGA OFFSET DAC The input to the PGA can be shifted by half the full-scale input range of the PGA by using the ODAC (Offset DAC) Register; see the Register Map section. The ODAC register is an 8-bit value; the MSB is the sign and the seven LSBs provide the magnitude of the offset. Using the ODAC does not reduce the performance of the A/D converter. See Application Report The Offset DAC (SBAA077), available for download at www.ti.com, for more information. VRCAP PIN This pin provides a bypass cap for noise filtering on internal VREF circuitry only. This pin is a sensitive pin; therefore place the capacitor as close as possible and avoid any resistive loading. The recommended capacitor is a 1000pF ceramic cap. If an external VREF is used, this pin can be left unconnected. CLOCK GENERATOR MODULATOR The modulator is a single-loop, second-order system. The modulator runs at a clock speed (fMOD) that is derived from the external clock (fOSC), as shown in Table 1. The frequency division is determined by the SPEED bit in the Setup Register (see the Register Map section). The clock source for the ADS1216 can be provided from a crystal, oscillator, or external clock. When the clock source is a crystal, external capacitors must be provided to ensure startup and a stable clock frequency; this configuration is shown in Figure 26 and Table 2. C1 Table 1. Modulator Speed XIN Crystal SPEED BIT fMOD 0 fOSC/128 1 fOSC/256 C2 Figure 26. Crystal Connection VOLTAGE REFERENCE INPUT The ADS1216 uses a differential voltage reference input. The input signal is measured against the differential voltage VREF ≡ (VREF+) – (VREF–). For AVDD = +5V, VREF is typically +2.5V. For AVDD = +3V, VREF is typically +1.25V. As a result of the sampling nature of the modulator, the reference input current increases with higher modulator clock frequency (fMOD) and higher PGA settings. 16 XOUT Table 2. Typical Clock Sources CLOCK SOURCE FREQUENCY C1 C2 PART NUMBER Crystal 2.4576 0–20pF 0–20pF ECS, ECSD 2.45 – 32 Crystal 4.9152 0–20pF 0–20pF ECS, ECSL 4.91 Crystal 4.9152 0–20pF 0–20pF ECS, ECSD 4.91 Crystal 4.9152 0–20pF 0–20pF CTS, MP 042 4M9182 Submit Documentation Feedback ADS1216 www.ti.com SBAS171D – NOVEMBER 2000 – REVISED SEPTEMBER 2006 CALIBRATION At the completion of calibration, the DRDY signal goes low, which indicates the calibration is finished and valid data is available. See Application Report Calibration Routine and Register Value Generation for the ADS121x Series (SBAA099), available for download at www.ti.com, for more information. The offset and gain errors in the ADS1216, or the complete system, can be reduced with calibration. Internal calibration of the ADS1216 is called self-calibration. Self-calibration is handled with three commands. One command does both offset and gain calibration. There is also a gain calibration command and an offset calibration command. Each calibration process takes seven tDATA periods to complete. It takes 14 tDATA periods to complete both an offset and gain calibration. Self-gain calibration is optimized for PGA gains less than 8. When using higher gains, system gain calibration is recommended. DIGITAL FILTER The Digital Filter can use either the Fast-Settling, Sinc2, or Sinc3 filter, as shown in Figure 27. In addition, the Auto mode changes the sinc filter after the input channel or PGA is changed. When switching to a new channel, it will use the Fast-Settling filter for the next two conversions, the first of which should be discarded. It will then use the Sinc2 followed by the Sinc3 filter. This architecture combines the low-noise advantage of the Sinc3 filter with the quick response of the Fast-Settling time filter. See Figure 28 for the frequency response of each filter. For system calibration, the appropriate signal must be applied to the inputs. The system offset command requires a zero differential input signal. It then computes an offset that will nullify offset in the system. The system gain command requires a positive full-scale differential input signal. It then computes a value to nullify gain errors in the system. Each of these calibrations will take seven tDATA periods to complete. When using the Fast-Settling filter, select a decimation value set by the DEC0 and M/DEC1 registers that is evenly divisible by four for the best gain accuracy. For example, choose 260 rather than 261. Calibration must be performed after power on, a change in decimation ratio, or a change of the PGA. For operation with a reference voltage greater than (AVDD – 1.5V), the buffer must also be turned off during calibration. Adjustable Digital Filter Sinc Modulator Output 3 Sinc 2 Data Out Fast-Settling AUTO MODE FILTER SELECTION FILTER SETTLING TIME FILTER 3 Sinc 2 Sinc Fast SETTLING TIME (Conversion Cycles) (1) 3 (1) 2 (1) 1 CONVERSION CYCLE 1 2 3 Discard Fast Sinc 4 2 Sinc 3 NOTE: (1) With Synchronized Channel Changes. Figure 27. Filter Step Responses Submit Documentation Feedback 17 ADS1216 www.ti.com SBAS171D – NOVEMBER 2000 – REVISED SEPTEMBER 2006 3 (1) 2 (1) SINC FILTER RESPONSE (-3dB = 0.318 ´ fDATA = 19.11Hz) 0 0 -20 -20 -40 -40 Gain (dB) Gain (dB) SINC FILTER RESPONSE (-3dB = 0.262 ´ fDATA = 15.76Hz) -60 -60 -80 -80 -100 -100 -120 -120 0 30 60 90 120 150 180 210 240 270 300 0 30 60 90 Frequency (Hz) 120 150 180 210 240 270 300 Frequency (Hz) FAST SETTLING FILTER RESPONSE (-3dB = 0.469 ´ fDATA = 28.125Hz) (1) 0 -20 Gain (dB) -40 -60 -80 -100 -120 0 30 60 90 120 150 180 210 240 270 300 Frequency (Hz) NOTE: (1) fDATA = 60Hz. Figure 28. Filter Frequency Responses DIGITAL I/O INTERFACE Chip Select (CS) The ADS1216 has eight pins dedicated for digital I/O. The default power-up condition for the digital I/O pins are as inputs. All of the digital I/O pins are individually configurable as inputs or outputs. They are configured through the DIR control register. The DIR register defines whether the pin is an input or output, and the DIO register defines the state of the digital output. When the digital I/O are configured as inputs, DIO is used to read the state of the pin. If the digital I/O are not used, either 1) configure as outputs; or 2) leave as inputs and tie to ground; this configuration prevents excess power dissipation. The chip select (CS) input of the ADS1216 must be externally asserted before a master device can exchange data with the ADS1216. CS must be low for the duration of the transaction. CS can be tied low. SERIAL PERIPHERAL INTERFACE (SPI) Serial Clock (SCLK) SCLK, a Schmitt-Trigger input, clocks data transfer on the DIN input and DOUT output. When transferring data to or from the ADS1216, multiple bits of data may be transferred back-to-back with no delay in SCLKs or toggling of CS. Make sure to avoid glitches on SCLK because they can cause extra shifting of the data. The SPI allows a controller to communicate synchronously with the ADS1216. The ADS1216 operates in slave-only mode. 18 Submit Documentation Feedback ADS1216 www.ti.com SBAS171D – NOVEMBER 2000 – REVISED SEPTEMBER 2006 Polarity (POL) The serial clock polarity is specified by the POL input. When SCLK is active high, set POL high. When SCLK is active low, set POL low. Configuration Registers 16 bytes DATA READY SETUP MUX ACR IDAC1 IDAC2 ODAC DIO DIR DEC0 M/DEC1 OCR0 OCR1 OCR2 FSR0 FSR1 FSR2 The DRDY output is used as a status signal to indicate when data is ready to be read from the ADS1216. DRDY goes low when new data is available. It is reset high when a read operation from the data register is complete. It also goes high prior to the updating of the output register to indicate when not to read from the device to ensure that a data read is not attempted while the register is being updated. RAM 128 Bytes Bank 0 16 bytes DSYNC OPERATION DSYNC is used to provide for synchronization of the A/D conversion with an external event. Synchronization can be achieved either through the DSYNC pin or the DSYNC command. When the DSYNC pin is used, the filter counter is reset on the falling edge of DSYNC. The modulator is held in reset until DSYNC is taken high. Synchronization occurs on the next rising edge of the system clock after DSYNC is taken high. Bank 2 16 bytes MEMORY Bank 7 16 bytes Two types of memory are used on the ADS1216: registers and RAM. 16 registers directly control the various functions (PGA, DAC value, Decimation Ratio, etc.) and can be directly read or written to. Collectively, the registers contain all the information needed to configure the part, such as data format, mux settings, calibration settings, decimation ratio, etc. Additional registers, such as conversion data, are accessed through dedicated instructions. Figure 29. Memory Organization REGISTER BANK The operation of the device is set up through individual registers. The set of the 16 registers required to configure the device is referred to as a Register Bank, as shown in Figure 29. Submit Documentation Feedback 19 ADS1216 www.ti.com SBAS171D – NOVEMBER 2000 – REVISED SEPTEMBER 2006 RAM Reads and Writes to Registers and RAM occur on a byte basis. However, copies between registers and RAM occur on a bank basis. The RAM is independent of the Registers; for example, the RAM can be used as general-purpose RAM. The ADS1216 supports any combination of eight analog inputs. With this flexibility, the device can easily support eight unique configurations—one per input channel. In order to facilitate this type of usage, eight separate register banks are available. Therefore, each configuration could be written once and recalled as needed without having to serially retransmit all the configuration data. Checksum commands are also included, which can be used to verify the integrity of RAM. The RAM provides eight banks, with a bank consisting of 16 bytes. The total size of the RAM is 128 bytes. Copies between the registers and RAM are performed on a bank basis. Also, the RAM can be directly read or written through the serial interface on power-up. The banks allow separate storage of settings for each input. 20 The RAM address space is linear; therefore, accessing RAM is done using an auto-incrementing pointer. Access to RAM in the entire memory map can be done consecutively without having to address each bank individually. For example, if you were currently accessing bank 0 at offset 0xF (the last location of bank 0), the next access would be bank 1 and offset 0x0. Any access after bank 7 and offset 0xF will wrap around to bank 0 and Offset 0x0. Although the Register Bank memory is linear, the concept of addressing the device can also be thought of in terms of bank and offset addressing. Looking at linear and bank addressing syntax, we have the following comparison: in the linear memory map, the address 0x14 is equivalent to bank 1 and offset 0x4. Simply stated, the most significant four bits represent the bank, and the least significant four bits represent the offset. The offset is equivalent to the register address for that bank of memory. Submit Documentation Feedback ADS1216 www.ti.com SBAS171D – NOVEMBER 2000 – REVISED SEPTEMBER 2006 REGISTER MAP Table 3. Registers ADDRESS REGISTER BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 00h SETUP ID ID ID SPEED REF EN REF HI BUF EN BIT ORDER 01h MUX PSEL3 PSEL2 PSEL1 PSEL0 NSEL3 NSEL2 NSEL1 NSEL0 02h ACR BOCS IDAC2R1 IDAC2R0 IDAC1R1 IDAC1R0 PGA2 PGA1 PGA0 03h IDAC1 IDAC1_7 IDAC1_6 IDAC1_5 IDAC1_4 IDAC1_3 IDAC1_2 IDAC1_1 IDAC1_0 04h IDAC2 IDAC2_7 IDAC2_6 IDAC2_5 IDAC2_4 IDAC2_3 IDAC2_2 IDAC2_1 IDAC2_0 05h ODAC SIGN OSET_6 OSET_5 OSET_4 OSET_3 OSET_2 OSET_1 OSET_0 06h DIO DIO_7 DIO_6 DIO_5 DIO_4 DIO_3 DIO_2 DIO_1 DIO_0 07h DIR DIR_7 DIR_6 DIR_5 DIR_4 DIR_3 DIR_2 DIR_1 DIR_0 08h DEC0 DEC07 DEC06 DEC05 DEC04 DEC03 DEC02 DEC01 DEC00 09h M/DEC1 DRDY U/B SMODE1 SMODE0 Reserved DEC10 DEC9 DEC8 0Ah OCR0 OCR07 OCR06 OCR05 OCR04 OCR03 OCR02 OCR01 OCR00 0Bh OCR1 OCR15 OCR14 OCR13 OCR12 OCR11 OCR10 OCR09 OCR08 0Ch OCR2 OCR23 OCR22 OCR21 OCR20 OCR19 OCR18 OCR17 OCR16 0Dh FSR0 FSR07 FSR06 FSR05 FSR04 FSR03 FSR02 FSR01 FSR00 0Eh FSR1 FSR15 FSR14 FSR13 FSR12 FSR11 FSR10 FSR09 FSR08 0Fh FSR2 FSR23 FSR22 FSR21 FSR20 FSR19 FSR18 FSR17 FSR16 DETAILED REGISTER DEFINITIONS SETUP (Address 00h) Setup Register Reset value = iii01110. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ID ID ID SPEED REF EN REF HI BUF EN BIT ORDER bits 7-5 Factory programmed bits bit 4 SPEED: modulator clock speed 0 : fMOD = fOSC/128 1 : fMOD = fOSC/256 bit 3 REF EN: Internal voltage reference enable 0 = Internal voltage reference disabled 1 = Internal voltage reference enabled bit 2 REF HI: internal reference voltage select 0 = Internal reference voltage = 1.25V 1 = Internal reference voltage = 2.5V bit 1 BUF EN: buffer enable 0 = Buffer disabled 1 = Buffer enabled bit 0 BIT ORDER: set order bits are transmitted 0 = Most significant bit transmitted first 1 = Least significant bit transmitted first data is always shifted into the part most significant bit first. Data is always shifted out of the part most significant byte first. This configuration bit only controls the bit order within the byte of data that is shifted out. Submit Documentation Feedback 21 ADS1216 www.ti.com SBAS171D – NOVEMBER 2000 – REVISED SEPTEMBER 2006 MUX (Address 01h) Multiplexer Control Register Reset value = 01h. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 PSEL3 PSEL2 PSEL1 PSEL0 NSEL3 NSEL2 NSEL1 NSEL0 bits 7-4 PSEL3: PSEL2: PSEL1: PSEL0: Positive channel select 0000 = 0001 = 0010 = 0011 = AIN0 AIN1 AIN2 AIN3 0100 0101 0110 0111 = = = = AIN4 AIN5 AIN6 AIN7 0100 0101 0110 0111 = = = = AIN4 AIN5 AIN6 AIN7 1xxx = AINCOM (except when all bits are 1s) 1111 = Temperature sensor diode bits 3-0 NSEL3: NSEL2: NSEL1: NSEL0: Negative channel select 0000 = 0001 = 0010 = 0011 = AIN0 AIN1 AIN2 AIN3 1xxx = AINCOM (except when all bits are 1s) 1111 = Temperature sensor diode ACR (Address 02h) Analog Control Register Reset value = 00h. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 BOCS IDAC2R1 IDAC2R0 IDAC1R1 IDAC1R0 PGA2 PGA1 PGA0 bit 7 BOCS: Burnout current source 0 = Disabled 1 = Enabled IDAC Current + ǒ8RV Ǔǒ2 REF RANGE*1 Ǔ(DAC CODE) DAC bits 6-5 IDAC2R1: IDAC2R0: Full-scale range select for IDAC2 00 = 01 = 10 = 11 = Off Range 1 Range 2 Range 3 bits 4-3 IDAC1R1: IDAC1R0: Full-scale range select for IDAC1 00 = 01 = 10 = 11 = Off Range 1 Range 2 Range 3 bits 2-0 PGA2: PGA1: PGA0: Programmable gain amplifier gain selection 000 = 001 = 010 = 011 = 22 1 2 4 8 100 = 101 = 110 = 111 = 16 32 64 128 Submit Documentation Feedback ADS1216 www.ti.com SBAS171D – NOVEMBER 2000 – REVISED SEPTEMBER 2006 IDAC1 (Address 03h) Current DAC 1 Reset value = 00h. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 IDAC1_7 IDAC1_6 IDAC1_5 IDAC1_4 IDAC1_3 IDAC1_2 IDAC1_1 IDAC1_0 The DAC code bits set the output of DAC1 from 0 to full-scale. The value of the full-scale current is set by this byte, VREF, RDAC, and the DAC1 range bits in the ACR register. IDAC2 (Address 04h) Current DAC 2 Reset value = 00h. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 IDAC2_7 IDAC2_6 IDAC2_5 IDAC2_4 IDAC2_3 IDAC2_2 IDAC2_1 IDAC2_0 The DAC code bits set the output of DAC2 from 0 to full-scale. The value of the full-scale current is set by this byte, VREF, RDAC, and the DAC2 range bits in the ACR register. ODAC (Address 05h) Offset DAC Setting Reset value = 00h. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 SIGN OSET6 OSET5 OSET4 OSET3 OSET2 OSET1 OSET0 bit 7 Offset sign 0 = Positive 1 = Negative bits 6-0 V REF 2PGA Offset + NOTE: ǒCode Ǔ 127 The offset must be used after calibration or the calibration will nullify the effects. DIO (Address 06h) Digital I/O Reset value = 00h. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 DIO7 DIO6 DIO5 DIO4 DIO3 DIO2 DIO1 DIO0 A value written to this register will appear on the digital I/O pins if the pin is configured as an output in the DIR register. Reading this register will return the value of the digital I/O pins. DIR (Address 07h) Direction control for digital I/O Reset value = FFh. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 DIR7 DIR6 DIR5 DIR4 DIR3 DIR2 DIR1 DIR0 Each bit controls whether the Digital I/O pin is an output (= 0) or input (= 1). The default power-up state is as inputs. Submit Documentation Feedback 23 ADS1216 www.ti.com SBAS171D – NOVEMBER 2000 – REVISED SEPTEMBER 2006 DEC0 (Address 08h) Decimation Register (least significant 8 bits) Reset value = 80h. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 DEC07 DEC06 DEC05 DEC04 DEC03 DEC02 DEC01 DEC00 The decimation value is defined with 11 bits for a range of 20 to 2047. This register is the least significant eight bits. The three most significant bits are contained in the M/DEC1 register. M/DEC1 (Address 09h) Mode and Decimation Register Reset value = 07h. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 DRDY U/B SMODE1 SMODE0 Reserved DEC10 DEC09 DEC08 bit 7 DRDY: Data ready (read-only) This bit duplicates the state of the DRDY pin. bit 6 U/B: Data format 0 = Bipolar 1 = Unipolar U/B ANALOG INPUT DIGITAL OUTPUT 0 +FS Zero –FS 0x7FFFFF 0x000000 0x800000 1 +FS Zero –FS 0xFFFFFF 0x000000 0x000000 bits 5-4 SMODE1: SMODE0: Settling mode 00 = 01 = 10 = 11 = bit 3 Auto Fast-Settling filter Sinc2 filter Sinc3 filter Reserved This bit is not used in the ADS1216 and it is recommended that it be set to 0. bits 2-0 DEC10: DEC09: DEC08: Most significant bits of the decimation value 24 Submit Documentation Feedback ADS1216 www.ti.com SBAS171D – NOVEMBER 2000 – REVISED SEPTEMBER 2006 OCR0 (Address 0Ah) Offset Calibration Coefficient (least significant byte) Reset value = 00h. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 OCR07 OCR06 OCR05 OCR04 OCR03 OCR02 OCR01 OCR00 OCR1 (Address 0Bh) Offset Calibration Coefficient (middle byte) Reset value = 00h. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 OCR15 OCR14 OCR13 OCR12 OCR11 OCR10 OCR09 OCR08 OCR2 (Address 0Ch) Offset Calibration Coefficient (most significant byte) Reset value = 00h. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 OCR23 OCR22 OCR21 OCR20 OCR19 OCR18 OCR17 OCR16 FSR0 (Address 0Dh) Full-Scale Register (least significant byte) Reset value = 24h. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 FSR07 FSR06 FSR05 FSR04 FSR03 FSR02 FSR01 FSR00 FSR1 (Address 0Eh) Full-Scale Register (middle byte) Reset value = 90h. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 FSR15 FSR14 FSR13 FSR12 FSR11 FSR10 FSR09 FSR08 FSR2 (Address 0Fh) Full-Scale Register (most significant byte) Reset value = 67h. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 FSR23 FSR22 FSR21 FSR20 FSR19 FSR18 FSR17 FSR16 Submit Documentation Feedback 25 ADS1216 www.ti.com SBAS171D – NOVEMBER 2000 – REVISED SEPTEMBER 2006 COMMAND DEFINITIONS The commands summarized in Table 4 control the operation of the ADS1216. All of the commands are stand-alone except for the register reads and writes (RREG, WREG) which require a second command byte plus data. Additional command and data bytes may be shifted in without delay after the first command byte. The ORDER bit in the STATUS register (see the Register map section) sets the order of the bits within the output data. CS must stay low during the entire command sequence. Table 4. Command Definitions (1) (1) 26 COMMAND DESCRIPTION 1ST COMMAND BYTE WAKEUP Completes SYNC and exits standby mode 0000 0000 (00h) RDATA Read data 0000 0001 (01h) 2ND COMMAND BYTE RDATAC Read data continuously 0000 0011 (03h) SDATAC Stop read data continuously 0000 1111 (0Fh) RREG Read from REG rrr 0001 rrrr (1xh) 0000 nnnn RRAM Read from RAM bank aaa 0010 0aaa (2xh) xnnn nnnn (number of bytes – 1) CREG Copy REG to RAM bank aaa 0100 0aaa (4xh) CREGA Copy REG to all RAM banks 0100 1000 (48h) WREG Write to REG rrr 0101 rrrr (5xh) 0000 nnnn xnnn nnnn (number of bytes – 1) WRAM Write to RAM bank aaa 0110 0aaa (6xh) CRAM Copy RAM bank aaa to REG 1100 0aaa (Cxh) CSRAMX Calculate RAM bank aaa checksum 1101 0aaa (Dxh) CSARAMX Calculate all RAM banks checksum 1101 1000 (D8h) CSREG Calculate REG checksum 1101 1111 (DFh) CSRAM Calculate RAM bank aaa checksum 1110 0aaa (Exh) CSARAM Calculate all RAM banks checksum 1110 1000 (E8h) SELFCAL Offset and gain self-calibration 1111 0000 (F0h) SELFOCAL Offset self-calibration 1111 0001 (F1h) SELFGCAL Gain self-calibration 1111 0010 (F2h) SYSOCAL System offset calibration 1111 0011 (F3h) SYSGCAL System gain calibration 1111 0100 (F4h) DSYNC Synchronize the A/D conversion 1111 1100 (FCh) SLEEP Begin sleep mode 1111 1101 (FDh) RESET Reset to power-up values 1111 1110 (FEh) WAKEUP Completes SYNC and exits standby mode 1111 1111 (FFh) n = number of registers to be read/written – 1. For example, to read/write three registers, set nnnn = 2 (0010). r = starting register address for read/write commands. Submit Documentation Feedback ADS1216 www.ti.com SBAS171D – NOVEMBER 2000 – REVISED SEPTEMBER 2006 RDATA Read Data Description: Issue this command after DRDY goes low to read a single conversion result. After all 24 bits have been shifted out on DOUT, DRDY goes high. It is not necessary to read back all 24 bits, but DRDY will then not return high until new data is being updated. See the Timing Characteristics for the required delay between the end of the RDATA command and the beginning of shifting data on DOUT: t6. DRDY DIN 0000 0001 MSB DOUT Mid-Byte LSB t6 SCLK ··· ··· Figure 30. RDATA Command Sequence RDATAC Read Data Continuous Description: Issue command after DRDY goes low to enter the Read Data Continuous mode. This mode enables the continuous output of new data on each DRDY without the need to issue subsequent read commands. After all 24 bits have been read, DRDY goes high. It is not necessary to read back all 24 bits, but DRDY will then not return high until new data is being updated. This mode may be terminated by the Stop Read Data Continuous command (STOPC). Because DIN is constantly being monitored during the Read Data Continuous mode for the STOPC or RESET command, do not use this mode if DIN and DOUT are connected together. See the Timing Characteristics for the required delay between the end of the RDATAC command and the beginning of shifting data on DOUT: t6. DRDY DIN 0000 0011 t6 24 Bits DOUT 24 Bits Figure 31. RDATAC Command Sequence On the following DRDY, shift out data by applying SCLKs. The Read Data Continuous mode terminates if input_data equals the STOPC or RESET command in any of the three bytes on DIN. DRDY DIN DOUT input_data input_data input_data MSB Mid-Byte LSB Figure 32. DIN and DOUT Command Sequence During Read Continuous mode Submit Documentation Feedback 27 ADS1216 www.ti.com SBAS171D – NOVEMBER 2000 – REVISED SEPTEMBER 2006 STOPC Stop Read Data Continuous Description: Ends the continuous data output mode; refer to RDATAC in the Command Definitions section. The command must be issued after DRDY goes low and completed before DRDY goes high. DRDY DIN 000 1111 Figure 33. STOPC Command Sequence RREG Read from Registers Description: Output the data from up to 16 registers starting with the register address specified as part of the command. The number of registers read will be one plus the second byte of the command. If the count exceeds the remaining registers, the addresses will wrap back to the beginning. 1st Command Byte: 0001 rrrr where rrrr is the address of the first register to read. 2nd Command Byte: 0000 nnnn where nnnn is the number of bytes to read – 1. See the Timing Characteristics for the required delay between the end of the RREG command and the beginning of shifting data on DOUT: t6. DIN 0001 0001 0000 0001 1st Command 2nd Command Byte Byte t6 DOUT MUX ADCON Data Byte Data Byte Figure 34. RREG Command Example: Read Two Registers Starting from Regiater 01h (multiplexer) RRAM Read from RAM Description:This command allows for the direct reading of the RAM contents. All reads begin at the specified starting RAM bank. More than one bank can be read out in a single read operation. The reads will wrap around to the first bank if there is more data to be retrieved when the last bank is completely read. See the Timing Characteristics for the required delay between the end of the RRAM command and the beginning of shifting data on DOUT: t6. 1st Command Byte: 0010 0aaa where aaa is the starting RAM bank for the read. 2nd Command Byte: 0nnn nnnn where nnn nnnn is the number of bytes to be read – 1. DIN 0010 0001 0000 1111 t6 DOUT Bank 1, Byte 0 Bank 1, Byte 1 RAM Data Figure 35. RRAM Command Example: Read 16 Bytes Starting from Bank 1 28 Submit Documentation Feedback ADS1216 www.ti.com SBAS171D – NOVEMBER 2000 – REVISED SEPTEMBER 2006 CREG Copy Registers to RAM Bank Description: This command copies the registers to the selected RAM bank. Do not issue additional commands while the copy operation is underway. 1st Command byte: 0100 0aaa where aaa is the RAM bank that will be updated with a copy of the registers. CREGA Copy Registers to All RAM Banks Description: This command copies the registers to all RAM banks. Do not issue additional commands while the copy operation is underway. WREG Write to Register Description: Write to the registers starting with the register specified as part of the command. The number of registers that will be written is one plus the value of the second byte in the command. 1st Command Byte: 0101 rrrr where rrrr is the address to the first register to be written. 2nd Command Byte: 0000 nnnn where nnnn is the number of bytes to be written – 1. Data Byte(s): data to be written to the registers. DIN 0101 0011 DRATE Data 0000 0001 1st Command 2nd Command Byte Byte Data Byte IO Data Data Byte Figure 36. WREG Command Example: Write Two Registers Starting from 03h (DRATE) WRAM Write to RAM Description: This command allows for direct writing to the RAM. All writes begin at the specified starting RAM bank. More than one bank can be written in a single write operation. The writes will wrap around to the first bank if there is more data to be written when the last bank is completely written. See the Timing Characteristics for the required delay between the end of the RRAM command and the beginning of shifting data on DOUT: t6. 1st Command Byte: 0010 0aaa where aaa is the starting RAM bank for the write. 2nd Command Byte: 0nnn nnnn where nnn nnnn is the number of bytes to be written – 1. DIN 0110 0001 Bank 1, Byte 0 0000 1111 Bank 1, Byte 1 tx RAM Data Figure 37. WRAM Command Example: Write 16 Bytes Starting at Bank 1 CRAM Copy Selected RAM Bank to Registers Description: This command copies the selected RAM bank to the registers. This action will overwrite all previous register settings. Do not issue additional commands while this copy operation is underway. 1st Command Byte: 1100 0aaa where aaa is the selected RAM bank. Submit Documentation Feedback 29 ADS1216 www.ti.com SBAS171D – NOVEMBER 2000 – REVISED SEPTEMBER 2006 CSRAM Calculate Checksum for Selected RAM Bank Description: This command calculates the checksum for the selected RAM bank. The checksum is calculated as the sum of all the bytes in the registers with the carry ignored. Do not issue any additional commands while the checksum is being calculated. CSRAMX Calculate Checksum for Selected RAM Bank, Ignoring Certain Bits Description: This command calculates the checksum of the selected RAM bank. The checksum is calculated as a sum of all the bytes in the RAM bank with the carry ignored. The ID, DRDY, and DIO bits are masked and are not included in the checksum calculation. Do not issue any additional commands while the checksum is being calculated. CSARAM Calculate Checksum for all RAM Banks Description: This command calculates the checksum for all RAM banks. The checksum is calculated as a sum of all the bytes in the RAM bank with the carry ignored. Do not issue any additional commands while the checksum is being calculated. Calculate Checksum for all RAM Banks, Ignoring Certain Bits CSARAMX Description: This command calculates the checksum for all RAM banks. The checksum is calculated as a sum of all the bytes in the RAM bank with the carry ignored. The ID, DRDY, and DIO bits are masked and are not included in the checksum calculation. Do not issue any additional commands while the checksum is being calculated. CSREG Calculate Checksum for the Registers Description: This command calculates the checksum for the registers. The checksum is calculated as a sum of all the bytes in the registers with the carry ignored. The ID, DRDY, and DIO bits are masked and are not included in the checksum calculation. Do not issue any additional commands while the checksum is being calculated. See the Timing Characteristics for the required delay between the end of the checksum commands and the beginning of shifting data on DOUT: t6. Note that this time is dependent on the specific checksum command used. DIN 0000 0011 t6 DOUT 24 Bits Figure 38. Checksum Command Sequence SYSOCAL System Offset Calibration Description: Performs a system offset calibration. The Offset Calibration Register (OFC) is updated after this operation. DRDY goes high at the beginning of the calibration. It goes low after the calibration completes and settled data is ready. Do not send additional commands after issuing this command until DRDY goes low indicating that the calibration is complete. 30 Submit Documentation Feedback ADS1216 www.ti.com SBAS171D – NOVEMBER 2000 – REVISED SEPTEMBER 2006 SYSGCAL System Gain Calibration Description: Performs a system gain calibration. The Full-Scale Calibration Register (FSC) is updated after this operation. DRDY goes high at the beginning of the calibration. It goes low after the calibration completes and settled data is ready. Do not send additional commands after issuing this command until DRDY goes low indicating that the calibration is complete. DSYNC Synchronize the A/D Conversion Description: This command synchronizes the A/D conversion. To use, first shift in the command. Then shift in the WAKEUP command. Synchronization occurs on the first CLKIN rising edge after the first SCLK used to shift in the WAKEUP command. DIN 1111 1100 (SYNC) SCLK ··· CLKIN 0000 0000 (WAKEUP) ··· ··· ··· Synchronization Occurs Here Figure 39. DSYNC Command Sequence SLEEP Sleep Mode Description: This command puts the ADS1216 into a Sleep mode. After issuing the SLEEP command, make sure there is no more activity on SCLK while CS is low because this will interrupt Sleep mode. If CS is high, SCLK activity is allowed during Sleep mode. To exit Sleep mode, issue the WAKEUP command. DIN 1111 1101 (SLEEP) 0000 0000 (WAKEUP) SCLK Normal Mode Sleep Mode Normal Mode Figure 40. SLEEP Command Sequence WAKEUP Complete Synchronization or Exit Sleep Mode Description: Used in conjunction with the SYNC and STANDBY commands. Two values (all zeros or all ones) are available for this command. RESET Reset Registers to Default Values Description: Returns all registers to their default values. This command will also stop the Read Data Continuous mode. While in the Read Data Continuous mode, the RESET command must be issued after DRDY goes low and complete before DRDY returns high. Submit Documentation Feedback 31 ADS1216 www.ti.com SBAS171D – NOVEMBER 2000 – REVISED SEPTEMBER 2006 DEFINITIONS Analog Input Voltage—the voltage at any one analog input relative to AGND. Analog Input Differential Voltage—given by the following equation: (AIN+) – (AIN–). Thus, a positive digital output is produced whenever the analog input differential voltage is positive, while a negative digital output is produced whenever the differential is negative. For example, when the converter is configured with a 2.5V reference and placed in a gain setting of 1, the positive full-scale output is produced when the analog input differential is 2.5V. The negative full-scale output is produced when the differential is –2.5V. In each case, the actual input voltages must remain within the AGND to AVDD range. Conversion Cycle—the term conversion cycle usually refers to a discrete A/D conversion operation, such as that performed by a successive approximation converter. As used here, a conversion cycle refers to the tDATA time period. However, each digital output is actually based on the modulator results from several tDATA time periods. FILTER SETTING MODULATOR RESULTS Fast Settling 1 tDATA Time Period Sinc2 2 tDATA Time Period Sinc3 3 tDATA Time Period Data Rate—the rate at which conversions are completed. See definition for fDATA. Decimation Ratio—defines the ratio between the output of the modulator and the output Data Rate. Valid values for the Decimation Ratio are from 20 to 2047. Larger Decimation Ratios will have lower noise. Effective Resolution—the effective resolution of the ADS1216 in a particular configuration can be expressed in two different units: bits rms (referenced to output) and VRMS (referenced to input). Computed directly from the converter output data, each is a statistical calculation. The conversion from one to the other is shown below. Effective number of bits (ENOB) or effective resolution is commonly used to define the usable resolution of the A/D converter. It is calculated from empirical data taken directly from the device. It is typically determined by applying a fixed known signal source to the analog input and computing the standard deviation of the data sample set. The rms noise defines the ±σ interval about the sample mean. 32 The data from the A/D converter is output as codes, which then can be easily converted to other units, such as ppm or volts. The equations and table below show the relationship between bits or codes, ppm, and volts. −20 log(ppm) ENOB + 6.02 BITS rms BIPOLAR VRMS ǒ Ǔ ǒ Ǔ 2V REF PGA 10ǒ UNIPOLAR VRMS V REF PGA Ǔ Ǔ 10ǒ6.02ER 20 24 298nV 149nV 22 1.19µV 597nV 20 4.77µV 2.39µV 18 19.1µV 9.55µV 16 76.4µV 38.2µV 14 505µV 152.7µV 12 1.22mV 610µV 6.02ER 20 fDATA—the frequency of the digital output data produced by the ADS1216. fDATA is also referred to as the data rate. f DATA + f f ǒDecimation Ǔ + ǒmfactor Decimation Ǔ Ratio Ratio MOD OSC fMOD—the frequency or speed at which the modulator of the ADS1216 is running. This rate depends on the SPEED bit as shown below: SPEED BIT fMOD 0 fOSC/128 1 fOSC/256 fOSC—the frequency of the crystal input signal at the XIN input of the ADS1216. fSAMP—the frequency, or switching speed, of the input sampling capacitor. The value is given by one of the following equations: PGA SETTING SAMPLING FREQUENCY 1, 2, 4, 8 f SAMP + f OSC mfactor 8 f SAMP + 2f OSC mfactor 16 f SAMP + 8f OSC mfactor 32 f SAMP + 16f OSC mfactor 64, 128 f SAMP + 16f OSC mfactor Submit Documentation Feedback ADS1216 www.ti.com SBAS171D – NOVEMBER 2000 – REVISED SEPTEMBER 2006 Filter Selection—the ADS1216 uses a (sinx/x) filter or sinc filter. There are three different sinc filters that can be selected. A Fast-Settling filter will settle in one tDATA cycle. The Sinc2 filter will settle in two cycles and have lower noise. The Sinc3 will achieve lowest noise and higher number of effective bits, but requires three cycles to settle. The ADS1216 will operate with any one of these filters, or it can operate in an auto mode, where it will first select the Fast-Settling filter after a new channel is selected for two readings and will then switch to Sinc2 for one reading, followed by Sinc3 from then on. Full-Scale Range (FSR)—as with most A/D converters, the full-scale range of the ADS1216 is defined as the input, which produces the positive full-scale digital output minus the input, which produces the negative full-scale digital output. The full-scale range changes with gain setting; see Table 5. For example, when the converter is configured with a 2.5V reference and is placed in a gain setting of 2, the full-scale range is: [1.25V (positive full-scale) – (–1.25V (negative full-scale))] = 2.5V. Least Significant Bit (LSB) Weight—this is the theoretical amount of voltage that the differential voltage at the analog input would have to change in order to observe a change in the output data of one least significant bit. It is computed as shown in Equation 1: Full−Scale Range LSB Weight + 2N (1) where N is the number of bits in the digital output. tDATA—the inverse of fDATA, or the period between each data output. Table 5. Full-Scale Range vs PGA Setting 5V SUPPLY ANALOG INPUT (1) GAIN SETTING (1) (2) FULL-SCALE RANGE DIFFERENTIAL INPUT VOLTAGES (2) PGA OFFSET RANGE 1 5V ±2.5V ±1.25V 2 2.5V ±1.25V ±0.625V 4 1.25V ±0.625V ±312.5mV 8 0.625V ±312.5mV ±156.25mV 16 312.5mV ±156.25mV ±78.125mV 34 156.25mV ±78.125mV ±39.0625mV 64 78.125mV ±39.0625mV ±19.531mV 128 39.0625mV ±19.531mV ±9.766mV GENERAL EQUATIONS FULL-SCALE RANGE DIFFERENTIAL INPUT VOLTAGES (2) PGA SHIFT RANGE 2V REF PGA " VREF PGA " VREF 2PGA With a 2.5V reference. The ADS1216 allows common-mode voltage as long as the absolute input voltage on AIN+ or AIN– does not go below AGND or above AVDD. Submit Documentation Feedback 33 ADS1216 www.ti.com SBAS171D – NOVEMBER 2000 – REVISED SEPTEMBER 2006 Changes from C Revision (May 2006) to D Revision ..................................................................................................... Page • • 34 Added title for Table 1......................................................................................................................................................... 16 Changed 11 registers to 16 registers in Description text of RREG section in Command Definitions. ............................... 28 Submit Documentation Feedback PACKAGE OPTION ADDENDUM www.ti.com 21-May-2010 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) ADS1216Y/250 ACTIVE TQFP PFB 48 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR ADS1216Y/250G4 ACTIVE TQFP PFB 48 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR ADS1216Y/2K ACTIVE TQFP PFB 48 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR ADS1216Y/2KG4 ACTIVE TQFP PFB 48 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Samples (Requires Login) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant ADS1216Y/250 TQFP PFB 48 250 330.0 16.4 9.6 9.6 1.5 12.0 16.0 Q2 ADS1216Y/2K TQFP PFB 48 2000 330.0 16.4 9.6 9.6 1.5 12.0 16.0 Q2 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) ADS1216Y/250 TQFP PFB ADS1216Y/2K TQFP PFB 48 250 367.0 367.0 38.0 48 2000 367.0 367.0 38.0 Pack Materials-Page 2 MECHANICAL DATA MTQF019A – JANUARY 1995 – REVISED JANUARY 1998 PFB (S-PQFP-G48) PLASTIC QUAD FLATPACK 0,27 0,17 0,50 36 0,08 M 25 37 24 48 13 0,13 NOM 1 12 5,50 TYP 7,20 SQ 6,80 9,20 SQ 8,80 Gage Plane 0,25 0,05 MIN 0°– 7° 1,05 0,95 Seating Plane 0,75 0,45 0,08 1,20 MAX 4073176 / B 10/96 NOTES: A. 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