NCP346 Overvoltage Protection IC The NCP346 Overvoltage Protection circuit (OVP) protects sensitive electronic circuitry from overvoltage transients and power supply faults when used in conjunction with an external P−channel FET. The device is designed to sense an overvoltage condition and quickly disconnect the input voltage supply from the load before any damage can occur. The OVP consists of a precise voltage reference, a comparator with hysteresis, control logic, and a MOSFET gate driver. The OVP is designed on a robust BiCMOS process and is intended to withstand voltage transients up to 30 V. The device is optimized for applications that have an external AC/DC adapter or car accessory charger to power the product and/or recharge the internal batteries. The nominal overvoltage thresholds are 4.45 and 5.5 V and can be adjusted upward with a resistor divider between the VCC, IN, and GND pins. It is suitable for single cell Li−Ion applications as well as 3/4 cell NiCD/NiMH applications. http://onsemi.com 1 PIN CONNECTIONS & MARKING DIAGRAM Overvoltage Turn−Off Time of Less Than 1.0 msec Accurate Voltage Threshold of 4.45 V and 5.5 V (Nominal) CNTRL Input Compatible with 1.8 V Logic Levels These are Pb−Free Devices 2 CNTRL 3 5 VCC 4 IN (Top View) xxx = SQZ for NCP346SN1 = SRD for NCP346SN2 A = Asembly Location Y = Year W = Work Week G = Pb−Free Package (Note: Microdot may be in either location) Typical Applications • • • • GND xxxAYWG G OUT 1 Features • • • • THIN SOT−23−5 SN SUFFIX CASE 483 5 Cellular Phones Digital Cameras Portable Computers and PDAs Portable CD and other Consumer Electronics ORDERING INFORMATION Device Shipping† Package NCP346SN1T1G SOT−23−5 (Pb−Free) NCP346SN2T1G 3000 / Tape & Reel (7 inch Reel) †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. P−CH AC/DC Adapter or Accessory Charger (optional) Schottky Diode VCC IN + − (optional) + Logic FET Driver C1 LOAD OUT Vref NCP346 GND CNTRL Microprocessor port Note: This device contains 89 active transistors Figure 1. Simplified Application Diagram © Semiconductor Components Industries, LLC, 2006 September, 2006 − Rev. 6 1 Publication Order Number: NCP346/D NCP346 VCC (5) IN (4) VCC V5 Pre−regulator R1 VCC + COMP − LOGIC BLOCK ON/OFF OUT DRIVER OUT (1) R2 Bandgap Reference CNTRL (3) GND (2) Figure 2. Detailed Block Diagram PIN FUNCTION DESCRIPTIONS Pin # Symbol Pin Description 1 OUT This signal drives the gate of a P−channel MOSFET. It is controlled by the voltage level on IN or the logic state of the CNTRL input. When an overvoltage event is detected, the OUT pin is driven to within 1.0 V of VCC in less than 1.0 msec provided that gate and stray capacitance is less than 12 nF. 2 GND Circuit Ground 3 CNTRL This logic signal is used to control the state of OUT and turn−on/off the P−channel MOSFET. A logic High results in the OUT signal being driven to within 1.0 V of VCC which disconnects the FET. The input is tied Low via an internal 50 kW pull−down resistor. It is recommended that the input be connected to GND if it is not used. 4 IN This pin senses an external voltage point. If the voltage on this input rises above the overvoltage threshold (Vth), the OUT pin will be driven to within 1.0 V of VCC, thus disconnecting the FET. The nominal threshold level can be increased with the addition of an external resistor divider between IN, VCC, and GND. 5 VCC Positive Voltage supply. OUT is guaranteed to be in low state (MOSFET ON) as long as VCC remains above 2.5 V, and below the overvoltage threshold. TRUTH TABLE IN CNTRL OUT <Vth L GND <Vth H VCC >Vth L VCC >Vth H VCC http://onsemi.com 2 NCP346 MAXIMUM RATINGS (TA = 25°C unless otherwise noted.) Rating Pin Symbol Min Max Unit OUT Voltage to GND 1 VO −0.3 30 V Input and CNTRL Pin Voltage to GND 4 3 Vinput VCNTRL −0.3 −0.3 30 13 V 4, 5 V(VCC, IN) −0.3 15 V VCC Maximum Range 5 VCC(max) −0.3 30 V Maximum Power Dissipation at TA = 85°C − PD − 0.216 W Thermal Resistance, Junction−to−Air − RqJA − 300 °C/W Junction Temperature − TJ − 150 °C Operating Ambient Temperature − TA −40 85 °C VCNTRL Operating Voltage 3 − 0 5.0 V Storage Temperature Range − Tstg −65 150 °C Input Pin Voltage to VCC Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. ATTRIBUTES Characteristic Value ESD Protection Human Body Model (HBM) per JEDEC Standard JESD22−A114 Machine Model (MM) per JEDEC Standard JESD22−A114 Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1) Transistor Count v 2.5 kV v 250 V Level 1 89 Latchup Current Maximum Rating per JEDEC Standard EIA/JESD78 1. For additional Moisture Sensitivity information, refer to Application Note AND8003/D. http://onsemi.com 3 v 150 mA NCP346 ELECTRICAL CHARACTERISTICS (NCP346SN1T1) (For typical values TA = 25°C, for min/max values TA = −40°C to +85°C unless otherwise noted.) Characteristic Pin Symbol Min Typ Max Unit 5 VCC(opt) 2.5 − 25 V Total Supply Current (IN Connected to VCC; ON Mode, VCC = 4.0 V, CNTRL Pin Floating, Steady State) 4,5 Icc on − 650 1200 mA Total Supply Current (IN Connected to VCC; OFF Mode Driven by CNTRL Pin, VCC = 4.0 V, VCNTRL = 1.5 V, Steady State) 4,5 Icc off CNTRL − 700 1200 mA Total Supply Current (IN Connected to VCC; OFF Mode Driven by Overvoltage, VCC = 5.0 V, CNTRL Pin Floating, Steady State) 4,5 Icc off IN − 750 1200 mA Input Threshold (IN Connected to VCC; VCC Increasing) 4 Vth (LH) 4.3 4.45 4.6 V Input Threshold (IN Connected to VCC; VCC Decreasing) 4 Vth (HL) 4.3 4.4 4.6 V Input Hysteresis (IN Connected to VCC) 4 Vhyst − 50 − mV Input Impedance of IN Pin 4 Rin 30 55 85 kW CNTRL Voltage High 3 VIH 1.5 − − V CNTRL Voltage Low 3 VIL − − 0.5 V CNTRL Current High (Vih = 5.0 V) 3 IIH − 90 200 mA CNTRL Current Low (Vil = 0.5 V) 3 IIL − 9.0 20 mA Output Voltage High (IN Connected to VCC, VCC = 5.0 V) Isource = 10 mA Isource = 0.25 mA Isource = 0 mA 1 Voh − − V Output Voltage Low (IN Connected to VCC, VCC = 4.0 V, CNTRL Pin Floating) Isink = 0 mA 1 Vol − − 0.1 V Output Sink Current (IN Connected to VCC, VCC = 4.0 V, CNTRL Pin Floating, VOUT = 1.0 V) 1 Isink 4.0 10 16 mA Turn ON Delay – Input (IN Connected to VCC; VCC Steps Down from 5.0 V to 4.0 V, Cload = 12 nF, Measured to Vout < 1.0 V) 1 ton IN − 1.8 3.5 msec Turn OFF Delay – Input (IN Connected to VCC; VCC Steps Up from 4.0 V to 5.0 V, Cload = 12 nF, Measured to VOUT > VCC − 1.0 V) 1 toff IN − 0.6 1.0 msec Turn OFF Delay – CNTRL (IN Connected to VCC; VCC = 4.0 V, VCNTRL Steps from 0.5 V to 2.0 V, Cload = 12 nF, Measured to VOUT > VCC − 1.0 V) 1 toff CNTRL − 0.5 1.0 msec VCC Operating Voltage Range VCC − 1.0 VCC − 0.25 VCC − 0.1 http://onsemi.com 4 NCP346 ELECTRICAL CHARACTERISTICS (NCP346SN2T1) (For typical values TA = 25°C, for min/max values TA = −40°C to +85°C unless otherwise noted.) Characteristic Pin Symbol Min Typ Max Unit 5 VCC(opt) 2.5 − 25 V Total Supply Current (IN Connected to VCC; ON Mode, VCC = 5.0 V, CNTRL Pin Floating, Steady State) 4, 5 Icc on − 650 1200 mA Total Supply Current (IN Connected to VCC; OFF Mode Driven by CNTRL Pin, VCC = 5.0 V, VCNTRL = 1.5 V, Steady State) 4, 5 Icc off CNTRL − 700 1200 mA Total Supply Current (IN Connected to VCC; OFF Mode Driven by Overvoltage, VCC = 6.0 V, CNTRL Pin Floating, Steady State) 4, 5 Icc off IN − 750 1200 mA Input Threshold (IN Connected to VCC; VCC Increasing) 4 Vth (LH) 5.3 5.5 5.7 V Input Threshold (IN Connected to VCC; VCC Decreasing) 4 Vth (HL) 5.3 5.45 5.7 V Input Hysteresis (IN Connected to VCC) 4 Vhyst − 50 − mV Input Impedance of IN Pin 4 Rin 30 60 100 kW CNTRL Voltage High 3 VIH 1.5 − − V CNTRL Voltage Low 3 VIL − − 0.5 V CNTRL Current High (Vih = 5.0 V) 3 IIH − 95 200 mA CNTRL Current Low (Vil = 0.5 V) 3 IIL − 9.0 20 mA Output Voltage High (IN Connected to VCC, VCC = 6.0 V) Isource = 10 mA Isource = 0.25 mA Isource = 0 mA 1 Voh − − V Output Voltage Low (IN Connected to VCC, VCC = 5.0 V, CNTRL Pin Floating) Isink = 0 mA 1 Vol − − 0.1 V Output Sink Current (IN Connected to VCC, VCC = 5.0 V, CNTRL Pin Floating, VOUT = 1.0 V) 1 Isink 4.0 10 16 mA Turn ON Delay – Input (IN Connected to VCC; VCC Steps Down from 6.0 V to 5.0 V, Cload = 12 nF, Measured to Vout < 1.0 V) 1 ton IN − 1.8 4.5 msec Turn OFF Delay – Input (IN Connected to VCC; VCC Steps Up from 5.0 V to 6.0 V, Cload = 12 nF, Measured to VOUT > VCC − 1.0 V) 1 toff IN − 0.5 1.0 msec Turn OFF Delay – CNTRL (VCNTRL Steps Up from 0.5 V to 2.0 V, VCC = 5.0 V, Cload = 12 nF, Measured to VOUT > VCC − 1.0 V) 1 toff ICNTRL − 0.6 1.0 msec VCC Operating Voltage Range VCC − 1.0 VCC − 0.25 VCC − 0.1 http://onsemi.com 5 NCP346 APPLICATION INFORMATION NTHS4101PT1 MBRM130LT1 P−CH AC/DC Adapter or Accessory Charger (optional) Schottky Diode VCC IN Zener Diode (optional) + − (opt.) FET Driver Logic Zener Diode OUT (optional) + C1 LOAD Vref NCP346 GND CNTRL Microprocessor port Figure 3. Introduction dV/dT rise that occurs during the brief time it takes to turn−off the MOSFET. For battery powered applications, a low−forward voltage Schottky diode such as the MBRM120LT3 can be placed in series with the MOSFET to block the body diode of the MOSFET and prevent shorting the battery out if the input is accidentally shorted to ground. This provides additional voltage margin at the load since there is a small forward drop across this diode that reduces the voltage at the load. When the protection circuit turns off the MOSFET, there can be a sudden rise in the input voltage of the device. This transient can be quite large depending on the impedance of the supply and the current being drawn from the supply at the time of an overvoltage event. This inductive spike can be clamped with a Zener diode from IN to ground. This diode breakdown voltage should be well above the worst case supply voltage provided from the AC/DC adapter or Cigarette Lighter Adapter (CLA), since the Zener is only intended to clamp the transient. The NCP346 is designed so that the IN and VCC pin can safely protect up to 25 V and withstand transients to 30 V. Since these spikes can be very narrow in duration, it is important to use a high bandwidth probe and oscilloscope when prototyping the product to verify the operation of the circuit under all the transient conditions. A similar problem can result due to contact bounce as the DC source is plugged into the product. For portable products it is normal to have a capacitor to ground in parallel with the battery. If the product has a battery pack that is easily removable during charging, this scenario should be analyzed. Under that situation, the charging current will go into the capacitor and the voltage may rise rapidly depending on the capacitor value, the charging current and the power supply response time. In many electronic products, an external AC/DC wall adapter is used to convert the AC line voltage into a regulated DC voltage or a current limited source. Line surges or faults in the adapter may result in overvoltage events that can damage sensitive electronic components within the product. This is becoming more critical as the operating voltages of many integrated circuits have been lowered due to advances in sub−micron silicon lithography. In addition, portable products with removable battery packs pose special problems since the pack can be removed at any time. If the user removes a pack in the middle of charging, a large transient voltage spike can occur which can damage the product. Finally, damage can result if the user plugs in the wrong adapter into the charging jack. The challenge of the product designer is to improve the robustness of the design and avoid situations where the product can be damaged due to unexpected, but unfortunately, likely events that will occur as the product is used. Circuit Overview To address these problems, the protection system above has been developed consisting of the NCP346 Overvoltage Protection IC and a P−channel MOSFET switch such as the MGSF3441. The NCP346 monitors the input voltage and will not turn on the MOSFET unless the input voltage is within a safe operating window that has an upper limit of the overvoltage detection threshold. A Zener diode can be placed in parallel to the load to provide for secondary protection during the brief time that it takes for the NCP346 to detect the overvoltage fault and disconnect the MOSFET. The decision to use this secondary diode is a function of the charging currents expected, load capacitance across the battery, and the desired protection voltage by analyzing the http://onsemi.com 6 NCP346 Normal Operation which equates to: Figure 1 illustrates a typical configuration. The external adapter provides power to the protection system so the circuitry is only active when the adapter is connected. The OVP monitors the voltage from the charger and if the voltage exceeds the overvoltage threshold, Vth, the OUT signal drives the gate of the MOSFET to within 1.0 V of VCC, thus turning off the FET and disconnecting the source from the load. The nominal time it takes to drive the gate to this state is 400 nsec (1.0 msec maximum for gate capacitance of < 12 nF). The CNTRL input can be used to interrupt charging and allow the microcontroller to measure the cell voltage under a normal condition to get a more accurate measure of the battery voltage. Once the overvoltage is removed, the NCP346 will turn on the MOSFET. The turn on circuitry is designed to turn on the MOSFET more gradually to limit the in−rush current. This characteristic is a function of the threshold of the MOSFET and will vary depending on the device characteristics such as the gate capacitance. There are two events that will cause the OVP to drive the gate of the FET to a HIGH state. • Voltage on IN Rises Above the Overvoltage Detection Threshold • CNTRL Input is Driven to a Logic HIGH VCC + Vx(1 ) R1ńR2 ) R1ńRin) So, as Rin approaches infinity: VCC + Vx(1 ) R1ńR2) Designing around the Maximum Voltage Rating Requirements, V(VCC, IN) The NCP346’s maximum breakdown voltage between pins VCC and IN is 15 V. Therefore, care must be taken that the design does not exceed this voltage. Normally, the designer shorts VCC to IN, V(VCC, IN) is shorted to 0 V, so there is no issue. However, one must take care when adjusting the overvoltage threshold. In Figure 4, the R1 resistor of the voltage divider divides the V(VCC, IN) voltage to a given voltage threshold equal to: (VCC, IN) + VCC * (R1ń(R1 ) (R2ńń Rin))) (eq. 4) V(VCC, IN) worst case equals 15 V, and VCC worst case equals 30 V, therefore, one must ensure that: R1ń(R1 ) (R2ńń Rin)) t 0.5 (eq. 5) Where 0.5 = V(VCC, IN)max/VCCmax Therefore, the NCP346 should only be adjusted to maximum overvoltage thresholds which are less than 15 V. If greater thresholds are desired than can be accommodated by the NCP346, ON Semiconductor offers the NCP345 which can withstand those voltages. The separate IN and VCC pins allow the user to adjust the overvoltage threshold, Vth, upwards by adding a resistor divider with the tap at the IN pin. However, Rin does play a significant role in the calculation since it is several 10’s of kW. The following equation shows the effects of Rin. (eq. 1) VCC R1 IN R2 (eq. 3) This shows that Rin shifts the Vth detection point in accordance to the ratio of R1 / Rin. However, if R1 << Rin, this shift can be minimized. The following steps show this procedure. Adjusting the Overvoltage Detection Point with External Resistors VCC + Vx(1 ) R1ń(R2ńńRin)) (eq. 2) Rin GND Figure 4. Voltage divider input to adjust overvoltage detection point http://onsemi.com 7 NCP346 Design Steps for Adjusting the Overvoltage Threshold The specification takes into account the hysteresis of the comparator, so the minimum input threshold voltage (Vth) is the falling voltage detection point and the maximum is the rising voltage detection point. One should design the input supply such that its maximum supply voltage in normal operation is less than the minimum desired overvoltage threshold. 8. Use worst case resistor tolerances to determine the maximum V(VCC,IN) 1. Use Typical Rin, and Vth Values from the Electrical Specifications 2. Minimize Rin Effect by Selecting R1 << Rin since: VOV + Vth(1 ) R1ńR2 ) R1ńRin). (eq. 6) 3. Let X = Rin / R1 = 100. 4. Identify Required Nominal Overvoltage Threshold. 5. Calculate nominal R1 and R2 from Nominal Values: R1 + RinńX V(VCC, IN) min + VCCmax * (R1minń(R1min ) R2max)) (eq. 12) (eq. 7) R1 R2 + (VOVńVth * R1ńRin * 1) (eq. 8) V(VCC, IN)typ + VCCmax * (R1typń(R1typ ) R2typ)) (eq. 13) 6. Pick Standard Resistor Values as Close as Possible to these Values V(VCC, IN) max + VCCmax * (R1maxń(R1max ) R2min)) (eq. 14) 7. Use min/max Data and Resistor Tolerances to Determine Overvoltage Detection Tolerance: This is shown empirically in Tables 2 through 4. The following tables show an example of obtaining a 6 V detection voltage from the NCP346SN2T2, which has a typical Vth of 5.5 V. VOVmin + Vthmin(1 ) R1min ń R2max ) R1min ń Rinmax) (eq. 9) VOVtyp + Vthtyp(1 ) R1typ ń R2typ ) R1typ ń Rintyp) (eq. 10) VOVmax + Vthmax(1 ) R1min R2max ) R1max ń Rinmin) (eq. 11) http://onsemi.com 8 NCP346 Table 1. Design Steps 1−5 Parameter Typical Design Steps IN Pin Input Impedance (IN) 54000 (1) Input Threshold (Vth) 5.5 (1) Ratio of Rin to R1 (X) 100 (2, 3) Desired Overvoltage Threshold (VOV) 6 (4) R1 540 (5) R2 6674 (5) Table 2. Design Steps 6−7 with 1% Resistors 1% Resistors Parameter Min Typical Max Design Steps R1 543.51 549 554.49 (6) R2 6583.5 6650 6716.5 (6) Vth 5.3 5.5 5.7 (6) Rin 30000 54000 100000 (6) VOV 5.76 6.01 6.29 (7) V(VCC, IN) @ VCCmax 2.25 2.29 2.33 (8) Table 3. Design Steps 6−7 with 5% Resistors 5% Resistors Parameter Min Typ Max Design Steps R1 532 560 588 (6) R2 6460 6800 7140 (6) Vth 5.3 5.5 5.7 (6) Rin 30000 54000 100000 (6) VOV 5.72 6.01 6.33 (7) V(VCC, IN) @ VCCmax 2.08 2.28 2.50 (8) Table 4. Design Steps 6−7 with 10% Resistors 10% Resistors Parameter Min Typ Max Design Steps R1 504 560 616 (6) R2 6120 6800 7480 (6) Vth 5.3 5.5 5.7 (6) Rin 30000 54000 100000 (6) VOV 5.68 6.01 6.39 (7) V(VCC, IN) @ VCCmax 1.89 2.28 2.74 (8) http://onsemi.com 9 NCP346 5.7 4.6 IN Shorted to VCC IN Shorted to VCC 5.65 4.55 Vth VOLTAGE (V) Vth VOLTAGE (V) 5.6 4.5 Vth (VCC Increasing) 4.45 Vth (VCC Decreasing) 4.4 5.55 Vth (VCC Increasing) 5.5 Vth (VCC Decreasing) 5.45 5.4 4.35 5.35 5.3 4.3 −40 −25 −10 5 20 35 50 65 AMBIENT TEMPERATURE (°C) 80 95 −40 Figure 5. Typical Vth Variation vs. Temperature (NCP346SN1) 80 95 900 800 SUPPLY CURRENT (mA) SUPPLY CURRENT (mA) −10 5 20 35 50 65 AMBIENT TEMPERATURE (°C) Figure 6. Typical Vth Variation vs. Temperature (NCP346SN2) 900 Overvoltage Tripped (VCC = 5 V) 700 Disabled by CNTRL Pin (VCC = 4 V) Normal Operation (VCC = 4 V) 600 500 −25 −10 5 20 35 50 65 80 Overvoltage Tripped (VCC = 6 V) 800 Disabled by CNTRL Pin (VCC = 5 V) 700 Normal Operation (VCC = 5 V) 600 500 −40 95 −40 −25 −10 5 20 35 50 65 80 AMBIENT TEMPERATURE (°C) AMBIENT TEMPERATURE (°C) Figure 7. Typical Supply Current (ICC + IIN) vs. Temperature (NCP346SN1) Figure 8. Typical Supply Current (ICC + IIN) vs. Temperature (NCP346SN2) 5.0 5.0 4.5 4.5 4.0 4.0 3.5 3.5 ICC + IIN (mA) SUPPLY CURRENT (mA) −25 3.0 2.5 2.0 3.0 2.5 2.0 1.5 1.5 1.0 1.0 0.5 0.5 0.0 95 0.0 0 2.5 5 7.5 10 12.5 15 17.5 20 22.5 25 27.5 30 0 2.5 5 7.5 10 12.5 15 17.5 20 22.5 25 27.530 VCC (V) VCC (V) Figure 9. Total Supply Current vs. VCC (NCP346SN1) Figure 10. Total Supply Current vs. VCC (NCP346SN2) http://onsemi.com 10 15 15 14 14 13 13 SUPPLY CURRENT (mA) SUPPLY CURRENT (mA) NCP346 12 11 10 9 8 7 6 12 11 10 9 8 7 6 5 5 −40 −25 −10 5 20 35 50 65 80 95 −40 −25 −10 5 20 35 50 65 80 AMBIENT TEMPERATURE (°C) AMBIENT TEMPERATURE (°C) Figure 11. Typical OUT Sink Current vs. Temperature (NCP346SN1) Figure 12. Typical OUT Sink Current vs. Temperature (NCP346SN2) http://onsemi.com 11 95 NCP346 MOSFET = NTHS4101PT1 C1= N/C Load = 50 W (See Figure 3) VCNTRL VLoad Figure 13. Typical Turn−off Time CNTRL (NCP346SN1) MOSFET = NTHS4101PT1 C1 = N/C Load = 50 W (See Figure 3) VCNTRL VLoad Figure 14. Typical Turn−off Time CNTRL (NCP346SN2) http://onsemi.com 12 NCP346 MOSFET = NTHS4101PT1 C1 = N/C Load = 50 W (See Figure 3) VCNTRL VLoad Figure 15. Typical Turn−on Time CNTRL (NCP346SN1) VCNTRL MOSFET = NTHS4101PT1 C1 =N/C Load = 50 W (See Figure 3) VLoad Figure 16. Typical Turn−on Time CNTRL (NCP346SN2) http://onsemi.com 13 NCP346 THIN SOT−23−5 POWER DISSIPATION The values for the equation are found in the maximum ratings table on the data sheet. Substituting these values into the equation for an ambient temperature TA of 25°C, one can calculate the power dissipation of the device which in this case is 400 milliwatts. The power dissipation of the Thin SOT−23−5 is a function of the pad size. This can vary from the minimum pad size for soldering to a pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by TJ(max), the maximum rated junction temperature of the die, RqJA, the thermal resistance from the device junction to ambient, and the operating temperature, TA. Using the values provided on the data sheet for the Thin SOT−23−5 package, PD can be calculated as follows: PD + P D + 150°C – 25°C + 417 milliwatts 300°CńW The 300°C/W for the Thin SOT−23−5 package assumes the use of the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 417mw. T J(max)–T A R qJA http://onsemi.com 14 NCP346 PACKAGE DIMENSIONS THIN SOT−23−5 SN SUFFIX CASE 483−02 ISSUE E NOTES: 1 DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2 CONTROLLING DIMENSION: MILLIMETER. 3 MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH THICKNESS. MINIMUM LEAD THICKNESS IS THE MINIMUM THICKNESS OF BASE MATERIAL. 4 A AND B DIMENSIONS DO NOT INCLUDE MOLD FLASH, PROTRUSIONS, OR GATE BURRS. D S 5 4 1 2 3 B L G DIM A B C D G H J K L M S A J C 0.05 (0.002) H M K MILLIMETERS MIN MAX 2.90 3.10 1.30 1.70 0.90 1.10 0.25 0.50 0.85 1.05 0.013 0.100 0.10 0.26 0.20 0.60 1.25 1.55 0_ 10 _ 2.50 3.00 INCHES MIN MAX 0.1142 0.1220 0.0512 0.0669 0.0354 0.0433 0.0098 0.0197 0.0335 0.0413 0.0005 0.0040 0.0040 0.0102 0.0079 0.0236 0.0493 0.0610 0_ 10 _ 0.0985 0.1181 SOLDERING FOOTPRINT* 0.95 0.037 1.9 0.074 2.4 0.094 1.0 0.039 0.7 0.028 SCALE 10:1 mm Ǔ ǒinches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Email: [email protected] N. American Technical Support: 800−282−9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81−3−5773−3850 http://onsemi.com 15 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative NCP346/D