MCNIX MX28F640C3BTTC-90 64m-bit [4m x16] cmos single voltage 3v only flash memory Datasheet

ADVANCED INFORMATION
MX28F640C3BT/B
64M-BIT [4M x16] CMOS SINGLE VOLTAGE
3V ONLY FLASH MEMORY
FEATURES
• Bit Organization: 4,194,304 x 16
• Single power supply operation
- 3.0V only operation for read, erase and program
operation
- VCC=VCCQ=2.7~3.6V
- Operating temperature:-40° C~85° C
• Fast access time : 90/120ns
• Low power consumption
- 9mA maximum active read current, f=5MHz (CMOS
input)
- 21mA program erase current maximum
(VPP=1.65~3.6V)
- 7uA typical standby current under power saving
mode
• Sector architecture
- Sector Erase (Sector structure : 4Kword x 2 (boot
sectors), 4Kword x 6 (parameter sectors), 32Kword x
127 (parameter sectors)
- Top/Bottom Boot
• Auto Erase (chip & sector) and Auto Program
- Automatically program and verify data at specified
address
• Automatic Suspend Enhance
- Word write suspend to read
- Sector erase suspend to word write
- Sector erase suspend to read register report
• Automatic sector erase, full chip erase, word write and
sector lock/unlock configuration
• Status Reply
- Detection of program and erase operation completion.
- Command User Interface (CUI)
- Status Register (SR)
• Data Protection Performance
- Include boot sectors and parameter and main sectors
to be block/unblock
• 100,000 minimum erase/program cycles
• Common Flash Interface (CFI)
• 128-bit Protection Register
- 64-bit Unique Device Identifier
- 64-bit User-Programmable
• Latch-up protected to 100mA from -1V to VCC+1V
• Package type:
- 48-pin TSOP (12mm x 20mm)
GENERAL DESCRIPTION
cessors without wait states.
The MX28F640C3BT/B is a 64-mega bit Flash memory
organized as 4M words of 16 bits. The 1M word of data
is arranged in eight 4Kword boot and parameter sectors,
and 127 32Kword main sector which are individually
erasable. MXIC's Flash memories offer the most costeffective and reliable read/write non-volatile random access memory. The MX28F640C3BT/B is packaged in
48-pin TSOP. It is designed to be reprogrammed and
erased in system or in standard EPROM programmers.
MXIC's Flash memories augment EPROM functionality
with in-circuit electrical erasure and programming. The
MX28F640C3BT/B uses a command register to manage this functionality. The command register allows for
100% TTL level control inputs and fixed power supply
levels during erase and programming, while maintaining
maximum EPROM compatibility.
MXIC Flash technology reliably stores memory contents
even after 100,000 erase and program cycles. The MXIC
cell is designed to optimize the erase and programming
mechanisms. In addition, the combination of advanced
The standard MX28F640C3BT/B offers access time as
fast as 90ns, allowing operation of high-speed micropro-
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1
MX28F640C3BT/B
tunnel oxide processing and low internal electric fields
for erase and program operations produces reliable cycling. The MX28F640C3BT/B uses a 2.7V~3.6V VCC
supply to perform the High Reliability Erase and auto
Program/Erase algorithms.
static mode (addresses not switching). In this mode, the
typical ICCS current is 7uA (CMOS) at 3.0V VCC.
As CE# and RESET# are at VCC, ICC CMOS standby
mode is enabled. When RESET# is at GND, the reset
mode is enabled which minimize power consumption and
provide data write protection.
The highest degree of latch-up protection is achieved
with MXIC's proprietary non-epi process. Latch-up protection is proved for stresses up to 100 milliamps on
address and data pin from -1V to VCC + 1V.
A reset time (tPHQV) is required from RESET# switching high until outputs are valid. Similarly, the device has
a wake time (tPHEL) from RESET#-high until writes to
the CUI are recognized. With RESET# at GND, the WSM
is reset and the status register is cleared.
The dedicated VPP pin gives complete data protection
when VPP< VPPLK.
A Command User Interface (CUI) serves as the interface between the system processor and internal operation of the device. A valid command sequence written to
the CUI initiates device automation. An internal Write
State Machine (WSM) automatically executes the algorithms and timings necessary for erase, full chip erase,
word write and sector lock/unlock configuration operations.
A sector erase operation erases one of the device's 32Kword sectors typically within 1.0s, 4K-word sectors typically within 0.5s independent of other sectors. Each sector can be independently erased minimum 100,000 times.
Sector erase suspend mode allows system software to
suspend sector erase to read or write data from any other
sector.
Writing memory data is performed in word increments of
the device's 32K-word sectors typically within 0.8s and
4K-word sectors typically within 0.1s. Word program suspend mode enables the system to read data or execute
code from any other memory array location.
MX28F640C3BT/B features with individual sectors locking by using a combination of bits thirty-nine sector lockbits and WP#, to lock and unlock sectors.
The status register indicates when the WSM's sector
erase, full chip erase, word program or lock configuration operation is done.
The access time is 90/120ns (tELQV) over the operating temperature range (-40° C to +80° C) and VCC supply
voltage range of 2.7V~3.6V.
MX28F640C3BT/B's power saving mode feature substantially reduces active current when the device is in
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MX28F640C3BT/B
BLOCK DIAGRAM
Q0~Q7
Output
Buffer
Input
Buffer
Identifier
Register
VCC
CE#
Data
Register
Output
Multiplexer
I/O
Logic
Status
Register
WE#
Command
User
Interface
OE#
RESET#
WP#
Data
Comparator
A0~A21
Input
Buffer
Y
Decoder
Write
State
Machine
Y-Gating
Program/Erase
Voltage Switch
VPP
Main Sector 126
32K-Word
Main Sector
x127
Main Sector 125
Main Sector 1
Main Sector 0
X
Decoder
.......
Address
Latch
Boot Sector 0
Boot Sector 1
Parameter Sector
Parameter Sector
Parameter Sector
Parameter Sector
Parameter Sector
Parameter Sector
0
1
2
3
4
5
VCC
GND
Address
Counter
.......
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MX28F640C3BT/B
PIN CONFIGURATIONS
48 TSOP (Standard Type) (12mm x 20mm)
A15
A14
A13
A12
A11
A10
A9
A8
A21
A20
WE#
RESET#
VPP
WP#
A19
A18
A17
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
MX28F640C3T/B
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A16
VCCQ
GND
Q15
Q7
Q14
Q6
Q13
Q5
Q12
Q4
VCC
Q11
Q3
Q10
Q2
Q9
Q1
Q8
Q0
OE#
GND
CE#
A0
Table 1. Pin Description
Symbol
A0-A21
Type
input
Q0-Q15 input/output
CE#
input
RESET#
input
WE#
input
VPP
input/supply
OE#
WP#
input
input
VCC
VCCQ
supply
input
GND
supply
Description and Function
Address inputs for memory address. Data pin float to high-impedance when the chip is
deselected or outputs are disable. Addresses are internally latched during a write or erase
cycle.
Data inputs/outputs: Inputs array data on the second CE# and WE# cycle during a program
command. Data is internally latched. Outputs array and configuration data. The data pin float
to tri-state when the chip is de-selected.
Activates the device's control logic, input buffers, and sense amplifiers. CE# high de-selects the memory device and reduce power consumption to standby level. CE# is active low.
Reset Deep Power Down: when RESET#=VIL, the device is in reset/deep power down
mode, which drives the outputs to High Z, resets the WSM and minimizes current level.
When RESET#=VIH, the device is normal operation. When RESET# transition the device
defaults to the read array mode.
Write Enable: to control write to CUI and array sector. WR#=VIL becomes active. The data
and address is latched WE# on the rising edge of the second WE# pulse.
Program/Erase Power Supply:(1.65V~3.6V or 11.4V~12.6V)
Lower VPP<VPPLK, to protect any contents against Program and Erase Command.
Set VPP=VCC for in-system Read, Program and Erase Operation.
Raise VPP to 12V±5% for faster program and erase in a production environment.
Output enable: gates the device's outputs during a real cycle.
Write protect: when WP# is VIL, the boot sectors cannot be written or erased. When WP# is
VIH, locked boot sectors cannot be written or erase. WP is not affected parameter and main
sectors.
Device power supply: (2.7V~3.6V).
I/O Power Supply: supplies for input/output buffers.
[2.7V~3.6V] This input should be tied directly to VCC.
Ground voltage: all the GND pin shall not be connected.
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MX28F640C3BT/B
SECTOR STRUCTURE (TOP)
Sector
Sector Size
Boot Sector 0
4K Word
Boot Sector 1
4K Word
Parameter Sector 0 4K Word
Parameter Sector 1 4K Word
Parameter Sector 2 4K Word
Parameter Sector 3 4K Word
Parameter Sector 4 4K Word
Parameter Sector 5 4K Word
Main Sector 0
32K Word
Main Sector 1
32K Word
Main Sector 2
32K Word
Main Sector 3
32K Word
Main Sector 4
32K Word
Main Sector 5
32K Word
Main Sector 6
32K Word
Main Sector 7
32K Word
Main Sector 8
32K Word
Main Sector 9
32K Word
Main Sector 10
32K Word
Main Sector 11
32K Word
Main Sector 12
32K Word
Main Sector 13
32K Word
Main Sector 14
32K Word
Main Sector 15
32K Word
Main Sector 16
32K Word
Main Sector 17
32K Word
Main Sector 18
32K Word
Main Sector 19
32K Word
Main Sector 20
32K Word
Main Sector 21
32K Word
Main Sector 22
32K Word
Main Sector 23
32K Word
Main Sector 24
32K Word
Main Sector 25
32K Word
Main Sector 26
32K Word
Main Sector 27
32K Word
Main Sector 28
32K Word
Main Sector 29
32K Word
Main Sector 30
32K Word
Address Range (h)
3FF000-3FFFFF
3FE000-3FEFFF
3FD000-3FDFFF
3FC000-3FCFFF
3FB000-3FBFFF
3FA000-3FAFFF
3F9000-3F9FFF
3F8000-3F8FFF
3F0000-3F7FFF
3E8000-3EFFFF
3E0000-3E7FFF
3D8000-3DFFFF
3D0000-3D7FFF
3C8000-3CFFFF
3C0000-3C7FFF
3B8000-3BFFFF
3B0000-3B7FFF
3A8000-3AFFFF
3A0000-3A7FFF
398000-39FFFF
390000-397FFF
388000-38FFFF
380000-387FFF
378000-37FFFF
370000-377FFF
368000-36FFFF
360000-367FFF
358000-35FFFF
350000-357FFF
348000-34FFFF
340000-347FFF
338000-33FFFF
330000-337FFF
328000-32FFFF
320000-327FFF
318000-31FFFF
310000-317FFF
308000-30FFFF
300000-307FFF
Sector
Main Sector 31
Main Sector 32
Main Sector 33
Main Sector 34
Main Sector 35
Main Sector 36
Main Sector 37
Main Sector 38
Main Sector 39
Main Sector 40
Main Sector 41
Main Sector 42
Main Sector 43
Main Sector 44
Main Sector 45
Main Sector 46
Main Sector 47
Main Sector 48
Main Sector 49
Main Sector 50
Main Sector 51
Main Sector 52
Main Sector 53
Main Sector 54
Main Sector 55
Main Sector 56
Main Sector 57
Main Sector 58
Main Sector 59
Main Sector 60
Main Sector 61
Main Sector 62
Main Sector 63
Main Sector 64
Main Sector 65
Main Sector 66
Sector Size
32K Word
32K Word
32K Word
32K Word
32K Word
32K Word
32K Word
32K Word
32K Word
32K Word
32K Word
32K Word
32K Word
32K Word
32K Word
32K Word
32K Word
32K Word
32K Word
32K Word
32K Word
32K Word
32K Word
32K Word
32K Word
32K Word
32K Word
32K Word
32K Word
32K Word
32K Word
32K Word
32K Word
32K Word
32K Word
32K Word
Main Sector 67
Main Sector 68
Main Sector 69
Main Sector 70
32K Word
32K Word
32K Word
32K Word
Address Range (h)
2F8000-2FFFFF
2F0000-2F7FFF
2E8000-2EFFFF
2E0000-2E7FFF
2D8000-2DFFFF
2D0000-2D7FFF
2C8000-2CFFFF
2C0000-2C7FFF
2B8000-2BFFFF
2B0000-2B7FFF
2A8000-2AFFFF
2A0000-2A7FFF
298000-29FFFF
290000-297FFF
288000-28FFFF
280000-287FFF
278000-27FFFF
270000-277FFF
268000-26FFFF
260000-267FFF
258000-25FFFF
250000-257FFF
248000-24FFFF
240000-247FFF
238000-23FFFF
230000-237FFF
228000-22FFFF
220000-227FFF
218000-21FFFF
210000-217FFF
208000-20FFFF
200000-207FFF
1F8000-1FFFFF
1F0000-1F7FFF
1E8000-1EFFFF
1E0000-1E7FFF
1D8000-1DFFFF
1D0000-1D7FFF
1C8000-1CFFFF
1C0000-1C7FFF
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MX28F640C3BT/B
Sector
Sector Size
Main Sector 71
32K Word
Main Sector 72
32K Word
Main Sector 73
32K Word
Main Sector 74
32K Word
Main Sector 75
32K Word
Main Sector 76
32K Word
Main Sector 77
32K Word
Main Sector 78
32K Word
Main Sector 79
32K Word
Main Sector 80
32K Word
Main Sector 81
32K Word
Main Sector 82
32K Word
Main Sector 83
32K Word
Main Sector 84
32K Word
Main Sector 85
32K Word
Main Sector 86
32K Word
Main Sector 87
32K Word
Main Sector 88
32K Word
Main Sector 89
32K Word
Main Sector 90
32K Word
Main Sector 91
32K Word
Main Sector 92
32K Word
Main Sector 93
32K Word
Main Sector 94
32K Word
Main Sector 95
32K Word
Main Sector 96
32K Word
Main Sector 97
32K Word
Main Sector 98
32K Word
Main Sector 99
32K Word
Main Sector 100
32K Word
Main Sector 101
32K Word
Main Sector 102
32K Word
Main Sector 103
32K Word
Main Sector 104
32K Word
Main Sector 105
32K Word
Main Sector 106
32K Word
Address Range (h)
1B8000-1BFFFF
1B0000-1B7FFF
1A8000-1AFFFF
1A0000-1A7FFF
198000-19FFFF
190000-197FFF
188000-18FFFF
180000-187FFF
178000-17FFFF
170000-177FFF
168000-16FFFF
160000-167FFF
158000-15FFFF
150000-157FFF
148000-14FFFF
140000-147FFF
138000-13FFFF
130000-137FFF
128000-12FFFF
120000-127FFF
118000-11FFFF
110000-117FFF
108000-10FFFF
100000-107FFF
0F0000-0FFFFF
0F0000-0F7FFF
0E8000-0EFFFF
0E0000-0E7FFF
0D8000-0DFFFF
0D0000-0D7FFF
0C8000-0CFFFF
0C0000-0C7FFF
0B8000-0BFFFF
0B0000-0B7FFF
0A8000-0AFFFF
0A0000-0A7FFF
Main Sector 107
Main Sector 108
Main Sector 109
Main Sector 110
098000-09FFFF
090000-097FFF
088000-08FFFF
080000-087FFF
32K Word
32K Word
32K Word
32K Word
Sector
Sector Size
Main Sector 111
32K Word
Main Sector 112
32K Word
Main Sector 113
32K Word
Main Sector 114
32K Word
Main Sector 115
32K Word
Main Sector 116
32K Word
Main Sector 117
32K Word
Main Sector 118
32K Word
Main Sector 119
32K Word
Main Sector 120
32K Word
Main Sector 121
32K Word
Main Sector 122
32K Word
Main Sector 123
32K Word
Main Sector 124
32K Word
Main Sector 125
32K Word
Main Sector 126
32K Word
Address Range (h)
078000-07FFFF
070000-077FFF
068000-06FFFF
060000-067FFF
058000-05FFFF
050000-057FFF
048000-04FFFF
040000-047FFF
038000-03FFFF
030000-037FFF
028000-02FFFF
020000-027FFF
018000-01FFFF
010000-017FFF
008000-00FFFF
000000-007FFF
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MX28F640C3BT/B
SECTOR STRUCTURE (BOTTOM)
Sector
Sector Size
Boot Sector 0
4K Word
Boot Sector 1
4K Word
Parameter Sector 0 4K Word
Parameter Sector 1 4K Word
Parameter Sector 2 4K Word
Parameter Sector 3 4K Word
Parameter Sector 4 4K Word
Parameter Sector 5 4K Word
Main Sector 0
32K Word
Main Sector 1
32K Word
Main Sector 2
32K Word
Main Sector 3
32K Word
Main Sector 4
32K Word
Main Sector 5
32K Word
Main Sector 6
32K Word
Main Sector 7
32K Word
Main Sector 8
32K Word
Main Sector 9
32K Word
Main Sector 10
32K Word
Main Sector 11
32K Word
Main Sector 12
32K Word
Main Sector 13
32K Word
Main Sector 14
32K Word
Main Sector 15
32K Word
Main Sector 16
32K Word
Main Sector 17
32K Word
Main Sector 18
32K Word
Main Sector 19
32K Word
Main Sector 20
32K Word
Main Sector 21
32K Word
Main Sector 22
32K Word
Main Sector 23
32K Word
Main Sector 24
32K Word
Main Sector 25
32K Word
Main Sector 26
32K Word
Main Sector 27
32K Word
Main Sector 28
32K Word
Main Sector 29
32K Word
Main Sector 30
32K Word
Address Range (h)
000000-000FFF
001000-001FFF
002000-002FFF
003000-003FFF
004000-004FFF
005000-005FFF
006000-006FFF
007000-007FFF
008000-00FFFF
010000-017FFF
018000-01FFFF
020000-027FFF
028000-02FFFF
030000-037FFF
038000-03FFFF
040000-047FFF
048000-04FFFF
050000-057FFF
058000-05FFFF
060000-067FFF
068000-06FFFF
070000-077FFF
078000-07FFFF
080000-087FFF
088000-08FFFF
090000-097FFF
098000-09FFFF
0A0000-0A7FFF
0A8000-0AFFFF
0B0000-0B7FFF
0B8000-0BFFFF
0C0000-0C7FFF
0C8000-0CFFFF
0D0000-0D7FFF
0D8000-0DFFFF
0E0000-0E7FFF
0E8000-0EFFFF
0F0000-0F7FFF
0F8000-0FFFFF
Sector
Main Sector 31
Main Sector 32
Main Sector 33
Main Sector 34
Main Sector 35
Main Sector 36
Main Sector 37
Main Sector 38
Main Sector 39
Main Sector 40
Main Sector 41
Main Sector 42
Main Sector 43
Main Sector 44
Main Sector 45
Main Sector 46
Main Sector 47
Main Sector 48
Main Sector 49
Main Sector 50
Main Sector 51
Main Sector 52
Main Sector 53
Main Sector 54
Main Sector 55
Main Sector 56
Main Sector 57
Main Sector 58
Main Sector 59
Main Sector 60
Main Sector 61
Main Sector 62
Main Sector 63
Main Sector 64
Main Sector 65
Main Sector 66
Sector Size
32K Word
32K Word
32K Word
32K Word
32K Word
32K Word
32K Word
32K Word
32K Word
32K Word
32K Word
32K Word
32K Word
32K Word
32K Word
32K Word
32K Word
32K Word
32K Word
32K Word
32K Word
32K Word
32K Word
32K Word
32K Word
32K Word
32K Word
32K Word
32K Word
32K Word
32K Word
32K Word
32K Word
32K Word
32K Word
32K Word
Main Sector 67
Main Sector 68
Main Sector 69
Main Sector 70
32K Word
32K Word
32K Word
32K Word
Address Range (h)
100000-107FFF
108000-10FFFF
110000-117FFF
118000-11FFFF
120000-127FFF
128000-12FFFF
130000-137FFF
138000-13FFFF
140000-147FFF
148000-14FFFF
150000-157FFF
158000-15FFFF
160000-167FFF
168000-16FFFF
170000-177FFF
178000-17FFFF
180000-187FFF
188000-18FFFF
190000-197FFF
198000-19FFFF
1A0000-1A7FFF
1A8000-1AFFFF
1B0000-1B7FFF
1B8000-1BFFFF
1C0000-1C7FFF
1C8000-1CFFFF
1D0000-1D7FFF
1D8000-1DFFFF
1E0000-1E7FFF
1E8000-1EFFFF
1F0000-1F7FFF
1F8000-1FFFFF
200000-207FFF
208000-20FFFF
210000-217FFF
218000-21FFFF
220000-227FFF
228000-22FFFF
230000-237FFF
238000-23FFFF
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MX28F640C3BT/B
Sector
Main Sector 71
Main Sector 72
Main Sector 73
Main Sector 74
Main Sector 75
Main Sector 76
Main Sector 77
Main Sector 78
Main Sector 79
Main Sector 80
Main Sector 81
Main Sector 82
Main Sector 83
Main Sector 84
Main Sector 85
Main Sector 86
Main Sector 87
Main Sector 88
Main Sector 89
Main Sector 90
Main Sector 91
Main Sector 92
Main Sector 93
Main Sector 94
Main Sector 95
Main Sector 96
Main Sector 97
Main Sector 98
Main Sector 99
Main Sector 100
Main Sector 101
Main Sector 102
Main Sector 103
Main Sector 104
Main Sector 105
Main Sector 106
Sector Size
32K Word
32K Word
32K Word
32K Word
32K Word
32K Word
32K Word
32K Word
32K Word
32K Word
32K Word
32K Word
32K Word
32K Word
32K Word
32K Word
32K Word
32K Word
32K Word
32K Word
32K Word
32K Word
32K Word
32K Word
32K Word
32K Word
32K Word
32K Word
32K Word
32K Word
32K Word
32K Word
32K Word
32K Word
32K Word
32K Word
Main Sector 107
Main Sector 108
Main Sector 109
Main Sector 110
32K Word
32K Word
32K Word
32K Word
Address Range (h)
240000-247FFF
248000-24FFFF
250000-257FFF
258000-25FFFF
260000-267FFF
268000-26FFFF
270000-277FFF
278000-27FFFF
280000-287FFF
288000-28FFFF
290000-297FFF
298000-29FFFF
2A0000-2A7FFF
2A8000-2AFFFF
2B0000-2B7FFF
2B8000-2BFFFF
2C0000-2C7FFF
2C8000-2CFFFF
2D0000-2D7FFF
2D8000-2DFFFF
2E0000-2E7FFF
2E8000-2EFFFF
2F0000-2F7FFF
2F8000-2FFFFF
300000-307FFF
308000-30FFFF
310000-317FFF
318000-31FFFF
320000-327FFF
328000-32FFFF
330000-337FFF
338000-33FFFF
340000-347FFF
348000-34FFFF
350000-357FFF
358000-35FFFF
Sector
Main Sector 111
Main Sector 112
Main Sector 113
Main Sector 114
Main Sector 115
Main Sector 116
Main Sector 117
Main Sector 118
Main Sector 119
Main Sector 120
Main Sector 121
Main Sector 122
Main Sector 123
Main Sector 124
Main Sector 125
Main Sector 126
Sector Size
32K Word
32K Word
32K Word
32K Word
32K Word
32K Word
32K Word
32K Word
32K Word
32K Word
32K Word
32K Word
32K Word
32K Word
32K Word
32K Word
Address Range (h)
380000-387FFF
388000-38FFFF
390000-397FFF
398000-39FFFF
3A0000-3A7FFF
3A8000-3AFFFF
3B0000-3B7FFF
3B8000-3BFFFF
3C0000-3C7FFF
3C8000-3CFFFF
3D0000-3D7FFF
3D8000-3DFFFF
3E0000-3E7FFF
3E8000-3EFFFF
3F0000-3F7FFF
3F8000-3FFFFF
360000-367FFF
368000-36FFFF
370000-377FFF
378000-37FFFF
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MX28F640C3BT/B
2 PRINCIPLES OF OPERATION
3 BUS OPERATION
The product includes an on-chip WSM to manage sector erase, word write and lock-bit configuration functions.
The local CPU reads and writes flash memory in-system. All bus cycles to or from the flash memory conform
to standard microprocessor bus cycles.
After initial device power-up or return from reset mode
(see section on Bus Operations), the device defaults to
read array mode. Manipulation of external memory control pins allow array read, standby and output disable
operations.
3.1 Read
Information can be read from any sector, configuration
codes or status register independent of the VPP voltage. RESET# can be at VIH.
Status register and identifier codes can be accessed
through the CUI independent of the VPP voltage. All
functions associated with altering memory contents-sector erase, word write, sector lock/unlock, status and identifier codes - are accessed via the CUI and verified
through the status register.
The first task is to write the appropriate read mode command (Read Array, Read Configuration, Read Query or
Read Status Register) to the CUI. Upon initial device
power-up or after exit from reset mode, the device automatically resets to read array mode. In order to read
data, control pins set for CE#, OE#, WE#, RESET# and
WP must be driven to active. CE# and OE# must be
active to obtain data at the outputs. CE# is the device
selection control. OE# is the data output (Q0-Q15) control and active drives the selected memory data onto the
I/O bus, WE# must be VIH, RESET# must be VIH, WP
must be at VIL or VIH.
Commands are written using standard microprocessor
write timings. The CUI contents serve as input to the
WSM, which controls the sector erase, word write and
sector lock/unlock. The internal algorithms are regulated
by the WSM, including pulse repetition, internal verification and margining of data. Addresses and data are internally latched during write cycles. Address is latched
at falling edge of CE# and data latched at rising edge of
WE#. Writing the appropriate command outputs array data,
accesses the identifier codes or outputs status register
data.
3.2 Output Disable
With OE# at a logic-high level (VIH), the device outputs
are disabled. Output pins (Q0-Q15) are placed in a highimpedance state.
Interface software that initiates and polls progress of
sector erase, full chip erase, word write and sector lock/
unlock can be stored in any sector. This code is copied
to and executed from system RAM during flash memory
updates. After successful completion, reads are again
possible via the Read Array command. Sector erase suspend allows system software to suspend a sector erase
to read/write data from/to sectors other than that which
is suspend. Word write suspend allows system software
to suspend a word write to read data from any other
flash memory array location.
3.3 Standby
CE# at a logic-high level (VIH) places the device in
standby mode which substantially reduces device power
consumption. Q0~Q15 outputs are placed in a high-impedance state independent of OE#. If deselected during
sector erase, word write or sector lock/unlock, the device continues functioning, and consuming active power
until the operation completes.
With the mechanism of sector lock, memory contents
cannot be altered due to noise or unwanted operation.
When RESET#=VIH and VCC<VLKO (lockout voltage),
any data write alteration can be failure. During read operation, if write VPP voltage is below VPPLK, then hardware level data protection is achieved. With CUI's twostep command sequence sector erase, word write or
sector lock/unlock, software level data protection is
achieved also.
3.4 Reset
As RESET#=VIL, it initiates the reset mode. The device
enters reset/deep power down mode. However, the data
stored in the memory has to be sustained at least 100ns
in the read mode before the device becomes deselected
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and output high impedance state.
vice or sector within the device (Sector Lock) to be locked.
The Clear Sector Lock-Bits command requires the command and address within the device.
In read modes, RESET#-low deselects the memory,
places output drivers in a high-impedance state and turns
off all internal circuits. RESET# must be held low for a
minimum of 100ns. Time tPHQV is required after return
from reset mode until initial memory access outputs are
valid. After this wake-up interval tPHEL or tPHWL, normal operation is restored. The CUI is reset to read array
mode and status register is set to 80H. Sector lock bit is
set at lock status.
The CUI does not occupy an addressable memory location. It is written when WE# and CE# are active (whichever goes high first). The address and data needed to
execute a command are latched on the rising edge of
WE# or CE#. Standard microprocessor write timings are
used.
During sector erase, word write or sector lock/unlock
modes, RESET#-low will abort the operation. Memory contents being altered are no longer valid; the data may be
partially erased or written.
In addition, CUI will go into either array read mode or
erase/write interrupted mode. When power is up and the
device reset subsequently, it is necessary to read status register in order to assure the status of the device.
Recognizing status register (SR.7~0) will assure if the
device goes back to normal reset and enters array read
mode.
3.5 Read Configuration Codes
The read configuration codes operation outputs the manufacturer code, device code, sector lock configuration
codes, and the protection register Using the manufacturer and device codes, the system CPU can automatically match the device with its proper algorithms. The
sector lock codes identify locked and unlocked sectors.
3.6 Write
Writing commands to the CUI enable reading of device
data and identifier codes. They also control inspection
and clearing of the status register. When VCC=2.7V-3.6V
and VPP=VPPH1/2, the CUI additionally controls sector erase, full chip erase, word write and sector lock/
unlock.
The Sector Erase command requires appropriate command data and an address within the sector to be erased.
The Full Chip Erase command requires appropriate command data and an address within the device. The Word
Write command requires the command and address of
the location to be written. Set Sector lock/unlock commands require the command and address within the de-
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4 COMMAND DEFINITIONS
When the VPP voltage < VPPLK, read operations from
the status register, identifier codes, or sectors are enabled. Placing VPP on VPPH1/2 enables successful
sector erase, full chip erase, word write and sector lock/
unlock.
Device operations are selected by writing specific commands into the CUI. Table 3 defines these commands.
Table 2. Bus Operation
1,2
Mode
Notes
RESET
CE#
OE#
WE#
Q0~Q15
Read
1,2
VIH
VIL
VIL
VIH
DOUT
Output Disable
2
VIH
VIL
VIH
VIH
High Z
Standby
2
VIH
VIH
X
X
High Z
Reset
2
VIL
X
X
X
High Z
Write
2,3,4,5
VIH
VIL
VIH
VIL
DIN
Notes:
1. Refer to DC Characteristics for VPPLK, VPP1, VPP2, VPP3 voltage.
2. X can be VIL or VIH for pin and addresses.
3. RESET# at GND±0.2 to ensure the lowest power consumption.
4. Refer to Table 3 for valid DIN during a write operation.
5. To program or erase the lockable sectors holds WP# at VIH.
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Table 3. Command Definition (1)
Command
Bus
Notes
Cycles
Read Array
Read Configuration
First Bus Cycle
Operation Address
Second Bus Cycle
Data
Required
(1)
(2)
(3)
1
Write
X
FFH
Write
X
Operation Address
Data
(1)
(2)
(3)
90H
Read
IA
ID
>2
3,4
Read Query
2
2,7
Write
X
98H
Read
QA
QD
Read Status Register
2
3
Write
X
70H
Read
X
SRD
Clear Status Register
1
3
Write
X
50H
Write
X
20H
Write
BA
D0H
5
Write
X
40H/10H
Write
WA
WD
Sector Erase/Confirm
2
Word Write
2
Program/Erase Suspend
1
Write
X
B0H
Program/Erase Resume
1
Write
X
D0H
Sector Lock
2
Write
X
60H
Write
BA
01H
Sector Unlock
2
Write
X
60H
Write
BA
D0H
Lock-Down Sector
2
Write
X
60H
Write
BA
2FH
Protection Program
2
Write
X
C0H
Write
PA
PPH
6
Notes:
1. Bus operation are defined in Table 2 and referred to AC Timing Waveform.
2. X=Any address within device
IA=ID-Code Address (refer to Table 4)
BA=Sector within the sector being erased
WA=Address of memory location to be written
QA=Query Address, QD=Query Data
3. Data is latched from the rising edge of WE# or CE# (whichever goes high first)
SRD=Data read from status register, see Table 6 for description of the status register bits.
WD=Data to be written at location WA. ID=Data read from identifier codes
4. Following the Read configuration codes command, read operation access manufacturer, device codes, sector
lock/unlock codes, see chapter 4.2.
5. Either 40H or 10H are recognized by the WSM as word write setup.
6. The sector unlock operation simultaneously clear all sector lock.
7. Read Query Command is read for CFI query information.
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4.1 Read Array Command
4.3 Read Status Register Command
Upon initial device power-up and after exit from reset
mode, the device defaults to read array mode. This operation is also initiated by writing the Read Array command. The device remains enabled for reads until another command is written. Once the internal WSM has
started a sector erase, word write or sector lock configuration the device will not recognize the Read Array
command until the WSM completes its operation unless
the WSM is suspended via a Sector Erase Suspend or
Word Write Suspend command. If RESET#=VIL device
is in read Read Array command mode, this read operation no longer requires VPP. The Read Array command
functions independently of the VPP voltage and RESET#
can be VIH.
CUI writes read status command (70H). The status register may be read to determine when a sector erase,
word write or lock-bit configuration is complete and
whether the operation completed successfully. (refer to
table 6) It may be read at any time by writing the Read
Status Register command. After writing this command,
all subsequent read operations output data from the status register until another valid command is written. The
status register contents are latched on the falling edge
of CE# or OE#, whichever occurs. CE# or OE# must
toggle to VIH before further reads to update the status
register latch. The Read Status Register command functions independently of the VPP voltage. RESET# can be
VIH.
4.2 Read Configuration Codes Command
4.4 Clear Status Register Command
The configuration code operation is initiated by writing
the Read Configuration Codes command (90H). To return to read array mode, write the Read Array Command
(FFH). Following the command write, read cycles from
addresses shown in Table 4 retrieve the manufacturer,
device, sector lock configuration codes (see Table 4 for
configuration code values). To terminate the operation,
write another valid command. Like the Read Array command, the Read Configuration Codes command functions independently of the VPP voltage and RESET# can
be VIH. Following the Read Configuration Codes command, the information is shown:
Status register bits SR.5, SR.4, SR.3 or SR.1 are set to
"1"s by the WSM and can only be reset by the Clear
Status Register command (50H). These bits indicate
various failure conditions (see Table 6). By allowing system software to reset these bits, several operations (such
as cumulatively erasing multiple sectors or writing several words in sequence) may be performed. The status
register may be polled to determine if an error occurred
during the sequence.
To clear the status register, the Clear Status Register
command (50H) is written on CUI. It functions independently of the applied VPP Voltage. RESET# can be VIH.
This command is not functional during sector erase or
word write suspend modes.
Table 4: ID Code
Code
Address
Data
(A19-A0)
(Q15-Q0)
Manufacturer Code
00000H
00C2H
Device Code
00001H
88CC/88CDH
Sector Lock Configuration XX002H
LocK
- Sector is unlocked
Q0=0
- Sector is locked
Q0=1
- Sector is locked-down
Q1=1
Protection Register Lock
80
PR-LK
Protection Register
81-88
PR
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should be checked. If word write error is detected, the
status register should be cleared. The internal WSM verify
only detects errors for "1"s that do not successfully write
to "0"s. The CUI remains in read status register mode
until it receives another command.
4.5 Sector Erase Command
Erase is executed one sector at a time and initiated by a
two-cycle command. A sector erase setup is first written (20H), followed by a sector erase confirm (D0H). This
command sequence requires appropriate sequencing and
an address within the sector to be erased. Sector preconditioning, erase, and verify are handled internally by
the WSM. After the two-cycle sector erase sequence is
written, the device automatically outputs status register
data when read (see Figure 8). The CPU can detect sector erase completion by analyzing the output data of the
status register bit SR.7.
Reliable word writes can only occur when
VCC=2.7V~3.6V and VPP=VPPH1/2. In the absence of
this high voltage, memory contents are protected against
word writes. If word write is attempted while
VPP<VPPLK, status register bits SR.3 and SR.4 will be
set to "1". Successful word write requires for boot sector
that WP# is VIH the corresponding sector lock-bit be
cleared. In parameter and main sectors case, it must be
cleared the corresponding sector lock-bit. If word write
is attempted when the excepting above sector being
clocked conditions, SR.1 and SR.4 will be set to "1".
Word write is not functional.
When the sector erase is complete, status register bit
SR.5 should be checked. If a sector erase error is detected, the status register should be cleared before system software attempts corrective actions. The CUI remains in read status register mode until a new command is issued.
4.7 Sector Erase Suspend Command
This two-step command sequence of set-up followed by
execution ensures that sector contents are not accidentally erased. An invalid sector Erase command sequence
will result in both status register bits SR.4 and SR.5
being set to "1". Also, reliable sector erasure can only
occur when 2.7V~3.6V and VPP=VPPH1/2. In the absence of this high voltage, sector contents are protected
against erasure. If sector erase is attempted while
VPP<VPPLK SR.3 and SR.5 will be set to "1". To successfully erase the boot sector, the corresponding sector lock-bit must be clear first. In parameter and sectors
case, it must be cleared the corresponding sector lockbit. If sector erase is attempted when the excepting
above sector being locked conditions, SR.1 and SR.5
will be set to "1". Sector erase is not functional.
The Sector Erase Suspend command (50H) allows sector-erase interruption to read or word write data in another sector of memory. Once the sector erase process
starts, writing the Sector Erase Suspend command requests that the WSM suspend the sector erase sequence
at a predetermined point in the algorithm. The device
outputs status register data when read after the Sector
Erase Suspend command is written. Polling status register bits SR.7 and SR.6 can determine when the sector
erase operation has been suspended (both will be set to
"1"). Specification tWHR12 defines the sector erase suspend latency.
When Sector Erase Suspend command write to the CUI,
if sector erase was finished, the device places read array mode. Therefore, after Sector Erase Suspend command write to the CUI, Read Status Register command
(70H) has to write to CUI, then status register bit SR.6
should be checked for placing the device in suspend
mode.
4.6 Word Write Command
Word write is executed by a two-cycle command sequence. Word write setup (standard 40H or alternate 10H)
is written, followed by a second write that specifies the
address and data. The WSM then takes over, controlling
the word write and write verify algorithms internally. After the word write sequence is written, the device automatically outputs status register data when read (see
Figure 6). The CPU can detect the completion of the
word write event by analyzing the status register bit SR.7.
At this point, a Read Array command can be written to
read data from sectors other than that which is suspended. A Word Write commands sequence can also be
issued during erase suspend to program data in other
sectors. Using the Word Write Suspend command (see
Section 4.9), a word write operation can also be suspended. During a word write operation with sector erase
suspended, status register bit SR.7 will return to "0".
When word write is complete, status register bit SR.4
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However, SR.6 will remain "1" to indicate sector erase
suspend status.
to the flash memory, the WSM will continue the Word
write process. Status register bits SR.2 and SR.7 will
automatically clear. After the Word Write Resume command is written, the device automatically outputs status
register data when read (see Figure 4). VPP must remain at VPPH1/2 while in word write suspend mode.
RESET# must also remain at VIL or VHH (the same
RESET# level used for word write).
The only other valid commands while sector erase is
suspended are Read Status Register and sector erase
Resume. After a Sector Erase Resume command is written to the flash memory, the WSM will continue the sector erase process. Status register bits SR.6 and SR.7
will automatically clear. After the Erase Resume command is written, the device automatically outputs status
register data when read (see Figure 4). VPP must remain at VPPH1/2 while sector erase is suspended. RESET# must also remain at VIL or VHH (the same RESET# level used for sector erase). WP must also remain
at VIL or VIH (the same WP level used for sector erase).
Sector cannot resume until word write operations initiated during sector erase suspend has completed.
If the time between writing the Word Write Resume command and writing the Word Write Suspend command is
short and both commands are written repeatedly, a longer
time is required than standard word write until the completion of the operation.
If the time between writing the Sector Erase Resume
command and writing the Sector Erase Suspend command is shorter than 15ms and both commands are written repeatedly, a longer time is required than standard
sector erase until the completion of the operation.
4.8 Word Write Suspend Command
The Word Write Suspend command allows word write
interruption to read data in other flash memory locations.
Once the word write process starts, writing the Word
Write Suspend command requests that the WSM suspend the Word write sequence at a predetermined point
in the algorithm. The device continues to output status
register data when read after the Word Write Suspend
command is written. Polling status register bits SR.7 and
SR.2 can determine when the word write operation has
been suspended (both will be set to "1"). Specification
tWHR11 defines the word write suspend latency.
When Word Write Suspend command write to the CUI, if
word write was finished, the device places read array
mode. Therefore, after Word Write Suspend command
write to the CUI, Read Status Register command (70H)
has to write to CUI, then status register bit SR.2 should
be checked for placing the device in suspend mode.
At this point, a Read Array command can be written to
read data from locations other than that which is suspended. The only other valid commands while word write
is suspended are Read Status Register and Word Write
Resume. After Word Write Resume command is written
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4.9 Sector Lock/Unlock /Lock-down Command
4.9.4 Read Sector Lock Status
4.9.1 Sector Locked State
The lock status of every sector can be read through
Read Configuration mode. To enter this mode first command write 90H to the device. The next sector reads at
address +00002 will output the lock status of this sector. The lock status can be read from the lowest two
output pins Q0 and Q1. Q0, Q0 indicates the sector lock/
unlock status and set by the lock command and cleared
by the unlock command. When entering lock-down, the
lock status is automatically set. Q1 indicates lock-down
status and is set by the lock-down command. It cannot
be further cleared by software, only by device reset or
power-down.
The default status of all sectors when power-up or reset
is locked. Any attempt on program or erase operations
will result in an error on bit SR.1 of a locked sector. The
status of a locked sector can be changed to unlocked or
lock-down using software commands. An unlocked sector can be locked by writing the sector lock command
sequence, 60H followed by 01H.
4.9.2 Sector Unlocked State
An unlocked sector can be programmed or erased. All
unlocked sector return to the locked state when the device is either reset or powered down. The status of an
unlocked sector can be changed to locked or lockeddown using software commands. A locked sector can
be unlocked by writing unlock command sequence, 60H
followed by D0H.
Sector Lock Configuration Table
Lock Status
Sector is unlocked
Sector is locked
Sector is locked-down
Data
Q0=0
Q0=1
Q1=1
4.9.3 Sector Locked-Down State
Sectors which are locked-down are protected from program and erase operation; however, the protection status of three sectors cannot be changed using software
commands alone. Any sector locked or unlocked can be
locked-down by writing the lock-down command sequence, 60H followed by 2FH. When the device is reset
or powered down, the locked-down sectors will revert to
the locked state.
The status of WP# will determine the function of sector
lock-down and is summarized is followed:
WP#
WP#=0
WP#=1
Sector Lock-down Description
- sectors are protected from program, erase,
and lock status changes
- the sector lock-down function is disabled
- an individual lock-down sector can be un
locked and relocked via software command.
Once WP# goes low, sectors that previously
locked-down returns to lock-down state
regardless of any changes when WP# was
high.
In addition, sector lock-down is cleared only when the
device is reset or powered down.
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sector is being placed in erase suspend, the locking status bits will be changed immediately, but when the erase
is resumed, the erase operation will complete.
4.9.5 Sector Locking while Erase Suspend
The sector lock status can be performed during an erase
suspend by using standard locking command sequences
to unlock, lock, or lock-down a sector.
Locking operation cannot be performed during a program
suspend.
In order to change sector locking during an erase operation, the write erase suspend command (B0H) is placed
first; then check the status register until it is shown that
the actual erase operation has been suspended. Subsequent writing the desired lock command sequence to a
sector and the lock status will be changed. When completing any desired lock, read or program operation, resume the erase operation with the Erase Resume Command (D0H).
4.9.6 Status Register Error Checking
The operation of locking system for this device can be
used the term "state (X,Y,Z)" to specify locking status,
where X=value of WP#, Y=bit Q1 of the sector lock status register, and Z=bit Q0 of the sector lock status register. Q0 indicates if a sector is locked (1) or unlocked (0).
Q1 indicates if a sector has been locked-down(1) or not
(0).
If a sector is locked or locked-down during the same
Table 5. Sector Locking State Transitions
WP#
Current State
Erase/Prog.
(X, Y, Z)=
Operation if
Lock Command Input Result (Next State)
(X, Y, Z)=
Q1
Q0
Name
Enable ?
Lock
Unlock
Lock-Down
0
0
0
Unlocked
Yes
(001)
Unchanged
(011)
0
0
1
Locked (Default)
No
Unchanged
(000)
(011)
0
1
1
Locked-Down
No
Unchanged
Unchanged
Unchanged
1
0
0
Unlocked
Yes
(101)
Unchanged
(111)
1
0
1
Locked
No
Unchanged
(100)
(111)
1
1
0
Lock-Down Disabled
Yes
(111)
Unchanged
(111)
1
1
1
Lock-Down Disabled
No
Unchanged
(110)
Unchanged
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Table 6. Status Register Definition
WSMS
BESS
ES
PS
VPPS
PSS
BLS
R
7
6
5
4
3
2
1
0
NOTES:
Check WSM bit first to determine word program or sector Erase completion, before checking Program or Erase
Status bits.
SR.7 = WRITE STATE MACHINE STATUS (WSMS)
1 = Ready
0 = Busy
When Erase Suspend is issued, WSM halts execution
and sets both WSMs and ESS bits to "1". ESS bit remains set to "1" until an Erase Resume command is
issued.
SR.6 = SECTOR ERASE SUSPEND STATUS (ESS)
1 = Sector ERASE Suspended
0 = Sector Erase in Progress/Completed
SR.5 = ERASE STATUS (ES)
1 = Error in Programming
0 = Successful Sector Erase or Clear Sector LockBits
When this bit (SR.5) is set to "1", it means WSM is
unable to verify successful sector erasure.
When this bit is set to "1", WSM has attempted but failed
to program a word.
SR.4 = PROGRAM STATUS (PS)
1 = Error in Programming
0 = Successful Programming
SR.3 bit is not guaranteed to report accurate feedback
between VPPLK and VPP min.
SR.3 = VPP STATUS (VPPS)
1 = VPP Low Detect, Operation Abort
0 = VPP OK
SR.2 = PROGRAM SUSPEND STATUS (PSS)
1 = Program Suspended
0 = Program in Progress/Completed
When program suspend is issued, WSM halts the execution and sets both WSMs and SR.2 bit to "1". SR.2
remains set to "1" until a Program Resume command is
issued.
SR.1 = SECTOR LOCK STATUS
1 =Program/Erase attempted an a locked sector;
operation aborted
0 = No operation to locked sectors
If a program or erase operation is attempted to one of
the locked sectors, this bit is set by the WSM. The operation specified is aborted and the device is returned to
read status mode.
SR.0 = RESERVED FOR FUTURE ENHANCEMENTS
(R)
SR. 0 is reserved for future use and should be masked
out when polling the status register.
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read cycles from addresses shown in Table 7 will retrieve the specified information. To return to read array
mode, write the Read Array Command (FFH).
5. 128-Bit Protection Register
The 128-bits of protection register are divided into two
64-bit segments. One of the segments is programmed
at MXIC side with unique 64-bit number; where changes
are forbidden. The other segment is left empty for customer to program. Once the customer segment is programmed, it can be locked to prevent further reprogramming.
Two-cycle Protection Program Command is used to program protection register bits. The 64-bit register is programmed 16-bits at a time. First write C0H protection
program setup. The next write to the device will latch in
address and data and program the specified location.
The allowable address are also show in Table 7. Refer to
Figure 6 for the Protection Register Programming Flowchart.
5.1 Protection Register Read & Programming
Any attempt to address Protection Program command
onto undefined protection register address space will
result in a Status Register error (SR.4 set to "1"). In
addition, attempting to program or to previously locked
protection register segment will result in a status register error (SR.4=1, SR.1=1).
The protection register is read in the configuration read
mode, which follows the stated Command Bus Definitions.
The device is switched to this read mode by writing the
Read Configuration command (90H). Once this mode,
Table 7. Word-Wide Protection Register Addressing
Word
Lock
0
1
2
3
4
5
6
7
User
Both
Factory
Factory
Factory
Factory
Customer
Customer
Customer
Customer
A7
1
1
1
1
1
1
1
1
1
A6
0
0
0
0
0
0
0
0
0
A5
0
0
0
0
0
0
0
0
0
A4
0
0
0
0
0
0
0
0
0
A3
0
0
0
0
0
0
0
0
1
A2
0
0
0
0
1
1
1
1
0
A1
0
0
1
1
0
0
1
1
0
A0
0
1
0
1
0
1
0
1
0
Notes: 1. Set address bit A21-A15=1 for TOP Boot device.
2. Set address bit A21-A15=0 for Bottom Boot device.
3. The address not specified in above are don't care.
Table 8. Protection Register Memory Map
5.2 Protection Register Locking
The user-programmable segment of the protection register is lockable by programming Bit 1 of the PR-Lock
location to 0. Bit 0 of this location is programmed to 0 at
MXIC to protect the unique device number. This bit is
set using the unique device number. This bit is set using
the protection program command to program "FFFD" to
PR-LOCK location. After these bits have been programmed, no further changes can be made to the value
stored in the protection register. Protection program command to a locked section will result in a status register
error (Program Error bit SR.4 and Lock Error bit SR.1
will be set to 1). Protection register lockout state is not
reversible.
Protection Register
Bit Address
88H~85H
84H~81H
80H(Bit0 & Bit1)
Purpose
4 word user program Register
4 word factory program
Register
Protection Register Lock
(PR-Lock)
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WARNING: Stressing the device beyond the "Absolute
Maximum Ratings" may cause permanent damage.
These are stress ratings only. Operation beyond the
"Operating Conditions" is not recommended and extended exposure beyond the "Operation Conditions" may
affect device reliability.
6 ELECTRICAL SPECIFICATIONS
6.1 ABSOLUTE MAXIMUM RATINGS
Operating Temperature
During Read, Sector Erase, Word
Write . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to +85oC
Storage Temperature . . . . . . . . . . . . . .-65oC to +125oC
Voltage on Any Pin (except VCC and
VPP with respect to GND) . . . . . . . . . . .-0.5 V to +5V(1)
VCC Supply Voltage . . . . . . . . . . . . .-0.2V to +4.6V(2)
VPP Supply Voltage (for sector erase and
VPP with respect to GND) . . . . . . . .-0.5V to +4.6V(1,2)
VCC and VCCQ Supply Voltage
with respect to GND. . . . . . . . . . . . . . . . .-0.2V to +3.6V(1)
Output Short Circuit Voltage . . . . . . . . . . . . .100mA
1. Minimum DC voltage is -0.5V on input pins. During
transitions, this level may undershoot to -2.0V for periods <20ns. Maximum DC voltage on input/output pins
to VCC+0.5V which during transition; may overshoot
to VCC+2.0V for periods <20ns.
2. Output shorted for no more than one second. No more
than one output shorted at a time.
6.2 Operating Conditions (Temperature and VCC Operating Conditions)
Symbol
Parameter
Min.
Max.
TA
Unit
Notes
Operating Temperature
-40
+85
o
VCC1
VCC Supply Voltage
2.7
3.6
V
1
VCCQ1
I/O Supply Voltage
2.7
3.6
V
1
VPP1
Supply Voltage
1.65
3.6
V
1
VPP2
Supply Voltage
11.4
12.6
V
1
Cycling
Sector Erase Cycling
C
100,000
2
NOTE:
1. VCC and VCCQ must share the same supply when they are in the VCC1 range.
2. Applying VPP=11.4~12.6V during a program/erase can only be done for a maximum of 1000 cycles on the main
sectors and 2500 cycles on the parameter sectors. VPP may be connected to 12V for a total of 80 hours maximum.
6.2.1 Capacitance (1) (TA=+25oC, f=1MHz)
Symbol
Parameter
Typ.
Max.
Unit
CIN
COUT
Test Condition
Input Capacitance
6
8
pF
VIN=0.0V
Output Capacitance
10
12
pF
VOUT=0.0V
NOTE:
1. Sampled, not 100% tested.
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6.2.2 AC Input/Output Test Conditions
VCCQ
TEST POINTS
Input VCCQ/2
VCCQ/2 Output
0.0
Note:AC test inputs are driven at VCCQ/2 for a Logic "1" and 0.0V for a Logic "0".
Figure 1. Transient Input/Output Reference Waveform
Figure 2. SWITCHING TEST CIRCUITS
TEST SPECIFICATIONS
Test Condition
90
120
Output Load
1 TTL gate
Output Load Capacitance, CL 30
100
(including jig capacitance)
Input Rise and Fall Times
5
Input Pulse Levels
0.0-3.0
Input timing measurement
1.5
reference levels
Output timing measurement
1.5
reference levels
2.7K ohm
DEVICE UNDER
TEST
3.3V
CL
6.2K ohm
DIODES=IN3064
OR EQUIVALENT
Unit
pF
ns
V
V
V
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6.2.3 AC Characteristic -- Read Only Operation (1)
-90
Notes
Min.
-110
Sym.
Parameter
Max.
tAVAV
Read Cycle Time
tAVQV
Address to Output Delay
tELQV
CE# to Output Delay
tGLQV
OE# to Output Delay
tPHQV
RESET# to Output Delay
tELQX
CE# to Output in Low Z
3
0
0
ns
tGLQX
OE# to Output in Low Z
3
0
0
ns
tEHQZ
CE# to Output in High Z
3
20
20
ns
tGHQZ
OE# to Output in High Z
3
20
20
ns
tOH
Output Hold from Address,
3
90
Min.
Max.
110
Unit
ns
90
110
ns
2
90
110
ns
2
30
30
ns
150
150
ns
0
0
ns
CE#, or OE# Change,
Whichever Occurs First
Notes:
1. See AC Waveform: Read Operations.
2. OE# may be delayed up to tELQV-tGLQV after the falling edge of CE# without impact on tELQV.
3. Sampled, but not 100% tested.
4. See test Configuration.
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Figure 3. READ-ONLY OPERATION AC WAVEFORM
Addresses(A)
Device and
Address Selection
VIH
Data
Valid
Standby
Address Stable
VIL
tAVAV
CE# (E)
VIH
VIL
tEHQZ
OE# (G)
VIH
VIL
tGHQZ
WE# (W)
VIH
tGLQV
VIL
tOH
tGLQX
tELQV
VOH
DATA (Q)
tELQX
High Z
Valid Output
VOL
High Z
tAVQV
RESET# (P)
VIH
tPHQV
VIL
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MX28F640C3BT/B
6.2.5 AC Characteristic -- Write Operation
Note
-90
-110
Min.
Min.
Unit
150
150
ns
0
0
ns
Sym.
Parameter
tPHWL/tPHEL
RESET# High Recovery to WE#(CE#) Going Low
tELWL/tWLEL
CE#(WE#) Setup to WE#(CE#) Going Low
tELEH/tWLWH
WE#(CE#) Pulse Width
4
50
70
ns
tDVWH/tDVEH
Data Setup to WE#(CE#) Going High
2
50
60
ns
tAVWH/tAVEH
Address Setup to WE#(CE#) Going High
2
50
70
ns
0
0
ns
tWHEH/tEHWH CE#(WE#) Hold Time from WE#(CE#) High
tWHDX/tEHDX
Data Hold Time from WE#(CE#) High
2
0
0
ns
tWHAX/tEHAX
Address Hold Time from WE#(CE#) High
2
0
0
ns
tWHWL/tEHEL
WE#(CE#) Pulse Width High
4
30
30
ns
tVPWH/tVPEH
VPP Setup to WE#(CE#) Going High
3
200
200
ns
tQVVL
VPP Hold from Valid SRD
3
0
0
ns
tBHWH/tBHEH
WP# Setup to WE#(CE#) Going High
3
0
0
ns
tQVBL
WP# Hold from Valid SRD
3
0
0
ns
tWHGL
WE# High to OE# Going Low
3
30
30
ns
Notes:
1. Write timing characteristics during erase suspend are the same as during write-only operations.
2. Refer to Table 5 for valid AIN or DIN.
3. Sampled, not 100% tested.
4. Write pulse width (tWP) is defined from CE# or WE# going low (whichever goes low last) to CE# or WE# going high
(whichever goes high first). Hence, tWP=tWLWH=tELEH=tELWH. Similarly, Write pulse width high (tWPH) is
defined from CE# or WE# going high (whichever goes high first) to CE# or WE# going low (whichever goes low first).
Hence, tWPH=tWHWL=tEHEL=tEHWL.
5. See Test Configuration.
6. Vcc Max = 3.3V.
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MX28F640C3BT/B
Figure 4. PROGRAM AND ERASE OPERATION AC WAVEFORM
A
Address (A)
B
C
AIN
AIN
D
E
F
VIH
VIL
tAVWH
(tAVEH)
tWHAX
(tEHAX)
(Note 1)
VIH
CE(WE#)[E(W)]
VIL
tELWL
(tWLEL)
tWHEH
(tEHWH)
VIH
OE#(G)
tWHWL
(tEHEL)
VIL
tWHGL
(Note 1)
Disable VIH
WE#,(CE#)[W(E)]
Enable VIL
tELEH
(tWLWH)
VIH High Z
DATA[Q]
tDVWH
(tEVEH)
tWHDX
(tEHDX)
DIN
DIN
VIL
Valid
SRD
DIN
tPHWL
(tPHEL)
VOH
RESET#[P]
VOL
tQVBL
tBHWH
(tBHEH)
VIH
WP#
VIL
tVPWH
(tVPEH)
tQVVL
VPPH2
VPPH1
VPP[V]
VPPLK
VIL
Notes:
1. CE# must be toggled low when reading Status Register Data. WE# must be inactive (high) when reading Status
Register Data.
A. VCC Power-Up and Standby.
B. Write Program or Erase Setup Command.
C. Write Valid Address and Data (for Program) or Erase Confirm Command.
D. Automated Program or Erase Delay.
E. Read Status Register Data (SRD): reflects completed program/erase operation.
F. Write Read Array Command.
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6.2.5 Erase and Program Timing (1)
Vpp
Symbol
Parameter
tBWPB
4-KW Parameter Sector
1.65V-3.6V
11.4V-12.6V
Note
Typ(1)
Max
Typ(1)
Max
Unit
2,3
0.10
0.30
0.03
0.12
s
2,3
0.8
2.4
0.24
1
s
Word Program Time
2,3
12
200
8
185
us
tWHQV2/
4-KW Parameter Sector
2,3
0.5
4
0.4
4.0
s
tEHQV2
Erase Time
tWHQV3/
32-KW Main Sector
2,3
1
5
0.6
5
s
tEHQV3
Erase Time
tWHRH1/
Program Suspend Latency
3
5
16
15
20
us
Erase Suspend Latency
3
5
20
15
20
us
Word Program Time(Word)
tBWMB
32-KW Main Sector
Word Program Time
tWHQV1/
tEHQV1
tEHRH1
tWHRH2/
tEHRH2
Notes:
1. Typical values measured at TA=+25° C and nominal voltage.
2. Excludes external system-level overhead.
3. Sampled, but not 100% tested.
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MX28F640C3BT/B
Figure 5. RESET# WAVEFORM
VIH
RESET# (P)
tPHQV
tPHWL
tPHEL
VIL
tPLPH
(A) Reset during Read Mode
tPLRH
RESET# (P)
tPHQV
tPHWL
tPHEL
Abort
Complete
VIH
VIL
tPLPH
(B) Reset during Program or Sector Erase, tPLPH < tPLRH
Abort
Complete
tPLRH
Deep
PowerDown
tPHQV
tPHWL
tPHEL
VIH
RESET# (P)
VIL
tPLPH
(C) Reset Program or Sector Erase, tPLPH > tPLRH
AC Characteristic -- Under Reset Operation
Sym.
Parameter
VCC=2.7V~3.6V
Min.
tPLPH
RESET# Low to Reset during Read
Unit
Notes
ns
2,4
Max.
100
(If RESET# is tied to VCC, this specification is applicable)
tPLRH1 RESET# Low to Reset during Sector Erase
22
us
3,4
tPLRH2 RESET# Low to Reset during Program
12
us
3,4
Notes:
1. See Section 3.4 for a full description of these conditions.
2. If tPLPH is < 100ns the device may still reset but this is not guaranteed.
3. If RESET# is asserted while a sector erase or word program operation is not executing, the reset will complete
within 100ns.
4. Sampled, but not 100% tested.
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6.2.6 DC Characteristics
VCC
Note
Sym.
Parameter
ILI
Input Load Current
1,2
ILO
1,2
ICCS
Output Leakage
Current
VCC Standby Current
ICCD
VCC Power-Down Current
ICCR
VCC Read Current
IPPD
ICCW
VPP Deep PowerDown Current
VCC Program Current
ICCE
VCC Erase Current
2.7V-3.6V
Typ.
Max.
Unit
Test Conditions
±1
uA
0.2
± 10
uA
1
7
15
uA
1,2
7
15
uA
1,2,3
9
18
mA
1
0.2
5
uA
1,4
18
55
mA
VCC=VCC Max., VCCQ=VCCQ Max.
VIN=VCCQ or GND
VCC=VCC Max., VCCQ=VCCQ Max.
VIN=VCCQ or GND
VCC=VCC Max., CE#=RESET#=VCCQ
or during Program/Erase Suspend
WP#=VCCQ or GND
VCC=VCC Max., VCCQ=VCCQ Max.
VIN=VCCQ or GND,RESET#=GND±0.2V
VCC=VCC Max.,VCCQ=VCCQ Max.
OE#=VIH, CE#=VIL
f=5MHz, IOUT=0mA, Inputs=VIL or VIH
RESET#=GND±0.2V
VPP < VCC
VPP=VPP1, Program in Progress
1,4
16
45
mA
VPP=VPP1, Erase in Progress
ICCES VCC Erase Suspend
Current
IPPR VPP Read Current
1,4
7
15
mA
1,4
2
±15
uA
CE#=VCC,
Erase Suspend in Progress
VPP < VCC
IPPW
VPP Program Current
1,4
0.05
0.1
mA
VPP=VPP1, Program in Progress
IPPE
VIL
VPP Erase Current
Input Low Voltage
1,4
0.05
-0.4
mA
V
VPP=VPP1, Program in Progress
VIH
Input High Voltage
2.0
VOL
Output Low Voltage
-0.1
0.1
VCC*
0.22V
VCCQ
+0.3V
0.1
VOH
Output High Voltage
VCCQ
-0.1V
VPPLK
VPP1
VPP2
VLKO
VLKO2
VPP Lock-Out Voltage
VPP during Program/
Erase Operations
VCC Prog/Erase Lock Voltage
VCCQ Prog/Erase
Lock Voltage
6
6
6,7
V
V
V
1.0
3.6
12.6
1.65
11.4
1.5
1.2
V
V
V
V
V
VCC=VCC Min, VCC=VCCQ Min
IOL=100uA
VCC=VCC Min, VCC=VCCQ Min
IOH=-100uA
Complete Write Protection
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Notes:
1. All currents are in RMS unless otherwise noted. Typical values at nominal VCC, TA=+25° C.
2. The test conditions VCC Max, VCCQ Max, VCC Min, and VCCQ Min refer to the maximum or minimum VCC or
VCCQ voltage listed at the top of each column. VCC Max=3.3V for 0.25um 32-Mbit devices.
3. Power Savings (Mode) reduces ICCR to approximately standby levels in static operation (CMOS inputs).
4. Sampled, but not 100% tested.
5. ICCES and ICCWS are specified with device de-selected. If device is read while in erase suspend, current draw is
sum of ICCES and ICCR. If the device is read while in program suspend, current draw is the sum of ICCWS and
ICCR.
6. Erase and Program are inhibited when VPP<VPPLK and not guaranteed outside the valid VPP ranges of and
VPP2.
7. Applying VPP=11.4~12.6V during program/erase can only be done for a maximum of 1000 cycles on the main
sectors and 2500 cycles on the parameter sectors. VPP may be connected to 12V for a total of 80 hours maximum.
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MX28F640C3BT/B
Figure 6. Automated Word Programming Flowchart
Bus
Command
Operation
Write
Program
Setup
Write
Program
Start
Write 40H
Data=40H
Data=Data to Program
Addr=Location to Program
Read
Status Register Data Toggle
CE# or OE# to Update
Status Register Data
Standby
Check SR.7
1=WSM Ready
0=WSM Busy
Repeat for subsequent programming operations.
SR full status check can be done after each program
or after a sequence of program operations.
Write FFH after the last program operation to reset
device to read array mode.
Program Address/Data
Read Status Register
SR.7=1 ?
Comments
No
Yes
Full Status
Check if Desired
Program Ccomplete
Bus
Command
Operation
Standby
FULL STATUS CHECK PROCEDURE
Check SR.3
1=VPP Low Detect
Standby
Check SR.4
1=VPP Program Detect
Standby
Check SR.11
1=Attempted Program to
Locked Sector-Program
Aborted
SR.3 MUST be cleared, if set during a program attempt, before further attempts are allowed by the Write
State Machine.
SR.4, SR.3, and SR.1 are only cleared by the Clear
Status Register Command, in cases where multiple
programmed before full status is checked.
If an error is detected, clear the status register before
attempting retry or other error recovery.
Read Status Register
Data(See Above)
SR.3=
1
VPP Range Error
0
SR.4=
1
Programming Error
0
SR.1=
1
Comments
Attempted Program to
Locked Block- Aborted
0
Program Successful
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Figure 7. Program Suspend/Resume Flowchart
Bus
Command
Operation
Write
Program
Suspend
Write
Read Status
Start
Write B0H
Write 70H
Read
Read
Status Register
SR.7=
0
Standby
1
Stanby
SR.2=
0
Program Completed
Write
1
Read Array
Write FFH
Read
Read Array Data
Write
Done Reading
Program
Resume
Comments
Data=B0H
Addr=X
Data=70H
Addr=X
Status Register Data Toggle
CE# or OE# to Update
Status Register Data
Addr=X
Check SR.7
1=WSM Ready
0=WSM Busy
Check SR.2
1=Program Suspended
0=Program Completed
Data=FFH
Addr=X
Read array data from
sector other than the one
being programmed.
Data=D0H
Addr=X
No
Yes
Write D0H
Write FFH
Program Write Resumed
Read Array Data
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Figure 8. Automated Sector Erase Flowchart
Bus
Command Comments
Operation
Write
Erase Setup Data=20H
Addr=Within Sector to Be
Erased
Write
Erase
Data=D0H
Confirm
Addr=Within Sector to Be
Erased
Read
Status Register Data Toggle
CE# or OE# to Update
Status Register Data
Standby
Check SR.7
1=WSM Ready
0=WSM Busy
Repeat for subsequent block erasures.
Full status check can be done after each sector erase
or after a sequence of sector erasures.
Write FFH after the last write operation to reset device
to read array mode.
Start
Write 20H
Write D0H and
Block Address
Read
Status Register
Suspend
Erase Loop
No
SR.7=
Yes
0
Suspend Erase
1
Full Status Check if Desired
Sector Erase Complete
Bus
Command
Operation
Standby
FULL STATUS CHECK PROCEDURE
Read Status Register
Data(See Above)
SR.3=
1
Check SR.3
1=VPP Low Detect
Standby
Check SR.4, 5
Both 1=Command
Sequence Error
Standby
Check SR.5
1=Sector Erase Error
Standby
Check SR.1
1=Attempted Erase of
Locked Sector- Erase
Aborted
SR.1 and SR.3 MUST be cleared, if set during an erase
attempt, before further attempts are allowed by the
Write State Machine.
SR.1,3,4,5 are only cleared by the Clear Status Register Command, in cases where multiple sectors are
erased before full status is checked.
If an error is detected, clear the status register before
attempting retry or other error recovery.
VPP Range Error
0
SR.4,5=
1
Command Sequence Error
0
SR.5=
1
Sector Erase Error
0
SR.1=
1
Comments
Attempted Erase of Locked
Sector - Aborted
0
Sector Erase Successful
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MX28F640C3BT/B
Figure 9. Erase Suspend/Resume Flowchart
Bus
Command
Operation
Write
Erase
Suspend
Write
Read Status
Start
Write B0H
Write 70H
Read
Read
Status Register
SR.7=
Standby
0
1
Stanby
SR.6=
0
Erase Completed
Write
1
Read Array
Write FFH
Read
Read Array Data
Write
Done Reading
Erase
Resume
Comments
Data=B0H
Addr=X
Data=70H
Addr=X
Status Register Data Toggle
CE# or OE# to Update
Status Register Data
Addr=X
Check SR.7
1=WSM Ready
0=WSM Busy
Check SR.6
1=Erase Suspended
0=Erase Completed
Data=FFH
Addr=X
Read array data from
sector other than the one
being erased.
Data=D0H
Addr=X
No
Yes
Write D0H
Write FFH
Erase Write Resumed
Read Array Data
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MX28F640C3BT/B
Figure 10. Locking Operations Flowchart
Bus
Command
Comments
Operation
Write
Config. Setup Data=60H
Addr=X
Write
Lock, unlock Data=01H (Sector Lock)
or Lockdown
D0H(Sector Unlock)
2FH(Sector Lockdown)
Addr=Within sector to lock
Write
Read
Data=90H
(Optional) Configuration Addr=X
Read
Sector Lock Sector Lock Status Data
(Optional)
Status
Addr=Second addr of
sector
Stanby
Confirm Locking Change
on Q1, Q0 (See Sector
Locking State Table for
valid combinations.)
Start
Write 60H
(Configuration Setup)
Write
01H, D0H, or 2FH
Write 90H
(Read Configuration)
Read Sector Lock Status
Locking Change
Confirmed ?
No
Yes
Write FFh (Read Array)
Locking Change
Complete
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MX28F640C3BT/B
Figure 11. Protection Register Programming Flowchart
Bus
Command
Operation
Write
Protection
Program
Setup
Write
Protection
Program
Read
Start
Write C0H
(Protection Reg. Program Setup)
Data=C0H
Data=Data to Program
Addr=Location to Program
Status Register Data Toggle
CE# or OE# to Update
Status Register Data
Standby
Check SR.7
1=WSM Ready
0=WSM Busy
Protection Program operations can only be addressed
within the protection register address space. Addresses
outside the defined space will return an error.
Repeat for subsequent programming operations.
SR Full Status Check can be done after each program
or after a sequence of program operations.
Write FFH after the last operation to reset device to
read array mode.
Write Protect. Register
Address/Data
Read Status Register
SR.7=1 ?
Comments
No
Yes
Full Status
Check if Desired
Program Ccomplete
FULL STATUS CHECK PROCEDURE
Read Status Register
Data(See Above)
SR.3, SR.4=
SR.1, SR.4=
SR.1, SR.4=
Bus
Command
Operation
Standby
1,1
SR.1, SR.3, SR.4
0
1
1 VPP Low
Standby
0
0
1 Prot. Reg.
Prog. Error
Stanby
1
0
1 Register
Locked:
Aborted
SR.3 MUST be cleared, if set during a program attempt, before further attempts are allowed by the Write
State Machine.
SR.1,3,4 are only cleared by the Clear Status Register Command, in cases of multiple protection register
program operations before full status is checked.
If an error is detected, clear the status register before
attempting retry or other error recovery.
VPP Range Error
0,1
Protection Register
programming Error
1,1
Attempted Program to
Locked Register Aborted
Comments
Program Successful
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7 VPP Program and Erase Voltage
When VPP is between 1.65V and 3.6V, all program and
erase current is drawn through the VCC pin. If VPP is
driven by a logic signal, VIH=1.65V. That is, VPP must
remain above 1.65V to perform in-system flash update/
modifications.
7.1 VPP Fast manufacturing Programming
When VPP is between 1.65V and 3.6V, all program and
erase current is drawn through the VCC pin. If VPP is
driven by a logic signal, VIH=1.65V. That is, VPP must
remain above 1.65V to perform in-system flash update/
modifications. When VPP is connected to a 12V power
supply, the device draws program and erase current directly from the VPP pin.
7.2 Protection Under VPP<VPPLK
VPP can off additional hardware write protection. The VPP
programming voltage can be kept low for the absolute
hardware protection of all sector in the flash device. As
VPP is below VPPLK, any program or erase operation
will result in a error, prompting the corresponding status
register bit (SR.3) to be set.
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The single cycle Query command is valid only when the
device is in the Read mode, including Erase Suspend,
Program Suspend, Standby mode, and Read ID mode;
however, it is ignored otherwise.
8. QUERY COMMAND AND COMMON FLASH
INTERFACE (CFI) MODE
MX28F640C3BT/B is capable of operating in the CFI
mode. This mode all the host system to determine the
manufacturer of the device such as operating parameters and configuration. Two commands are required in
CFI mode. Query command of CFI mode is placed first,
then the Reset command exits CFI mode. These are
described in Table X.
The Reset command exits from the CFI mode to the
Read mode, or Erase Suspend mode, Program Suspend
or read ID mode. The command is valid only when the
device is in the CFI mode.
Table 9-1. CFI mode: Identification Data Values
(All values in these tables are in hexadecimal)
Description
Address h
Data h
10
0051
11
0052
12
0059
13
0003
14
0000
15
0035
16
0000
17
0000
18
0000
19
0000
1A
0000
Address h
Data h
VCC supply, minimum (2.7V)
1B
0027
VCC supply, maximum (3.6V)
1C
0036
VPP supply, minimum (none)
1D
00B4
1E
00C6
Query-unique ASCII string "QRY"
Primary vendor command set and control interface ID code
Address for primary algorithm extended query table
Alternate vendor command set and control interface ID code (none)
Address for secondary algorithm extended query table (none)
Table 9-2. CFI Mode: System Interface Data Values
Description
VPP supply, maximum (none)
N
Typical timeout for single word write (2 us)
1F
0005
N
20
0000
Typical timeout for individual block erase (2 ms)
21
000A
22
0000
23
0004
24
0000
Maximum timeout for individual block erase times (2 X Typ)
25
0003
Maximum timeout for full chip erase times (not supported)
26
0000
Typical timeout for maximum size buffer write (2 us)
N
N
Typical timeout for full chip erase (2 ms)
N
Maximum timeout for single word write times (2 X Typ)
N
Maximum timeout for maximum size buffer write times (2 X Typ)
N
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Table 9-3. CFI Mode: Device Geometry Data Values
Description
Device size (2N bytes)
Flash device interface code (02=asynchronous x8/x16)
Maximum number of bytes in multi-byte write (not supported)
Number of erase block regions
Erase block region 1 information
[2E,2D] = # of blocks in region -1
[30, 2F] = size in multiples of 256-bytes
Erase Sector Region 2 information
[32,31] = number of same-size sectors in region 2-1
[34,33] = region erase sector size in multiples of 256-bytes
Address h
27
28
29
2A
2B
2C
2D
2E
2F
30
31
32
33
34
Data h
0017
0001
0000
0000
0000
0002
T
B
07
TE
00
00
20
00
00
01
07
7E
00
00
20
00
00
01
Table 9-4. CFI Mode: Primary Vendor-Specific Extended Query Data Values
Description
Query-unique ASCII string "PRI"
Major version number, ASCII
Minor version number, ASCII
Optional Feature & Command Support
bit 0 Chip Erase Supported (1=yes, 0=no)
bit 1 Suspend Erase Supported (1=yes, 0=no)
bit 2 Suspend Program Supported (1=yes, 0=no)
bit 3 Lock/Unlock Supported (1=yes, 0=no)
bit 4 Queued Erase Supported (1=yes, 0=no)
bits 5-31 revered for future use; undefined bits are "0"
Sector Lock Status
Define which bits in the sector status Register section of the Query are
implemented.
bit 0 sector Lock Status Register Lock/Unlock bit (bit 0) active; (1=yes, 0=no)
bit 1 sector Lock Status Register Lock/Unlock bit (bit 1) active; (1=yes, 0=no)
Bits 2-15 reserved for future use. Undefined bits are 0.
VCC Logic Supply Optimum Program/Erase Voltage (highest performance)
bits 7-4 BCD value in volts
bits 3-0 BCD value in 100mV
VPP (Programming) Supply Optimum Program/Erase Voltage
bits 7-4 HEX value in volts
bits 3-0 BCD value in 100mV
Address h
35
36
37
38
39
3A
3B
3C
3D
Data h
0050
0052
0049
0031
0030
66
00
00
00
3F
40
03
00
41
33
42
C0
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MX28F640C3BT/B
ORDER INFORMATION
PART NO.
ACCESS TIME
OPERATING
STANDBY
PACKAGE
(ns)
Current MAX.(mA)
Current MAX.(uA)
MX28F640C3BTTC-90
90
30
5
48 Pin TSOP
MX28F640C3BBTC-90
90
30
5
48 Pin TSOP
MX28F640C3BTTC-12
120
30
5
48 Pin TSOP
MX28F640C3BBTC-12
120
30
5
48 Pin TSOP
MX28F640C3BTTI-90
90
30
5
48 Pin TSOP
MX28F640C3BBTI-90
90
30
5
48 Pin TSOP
MX28F640C3BTTI-12
120
30
5
48 Pin TSOP
MX28F640C3BBTI-12
120
30
5
48 Pin TSOP
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MX28F640C3BT/B
PACKAGE INFORMATION
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MX28F640C3BT/B
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