HUF76429P3, HUF76429S3S
Data Sheet
October 1999
File Number
4672.1
44A, 60V, 0.025 Ohm, N-Channel, Logic
Level UltraFET Power MOSFET
Packaging
Features
JEDEC TO-220AB
JEDEC TO-263AB
DRAIN
(FLANGE)
SOURCE
DRAIN
GATE
GATE
SOURCE
DRAIN
(FLANGE)
HUF76429P3
HUF76429S3S
• Ultra Low On-Resistance
- rDS(ON) = 0.022Ω, VGS = 10V
- rDS(ON) = 0.025Ω, VGS = 5V
• Simulation Models
- Temperature Compensated PSPICE® and SABER©
Electrical Models
- Spice and SABER Thermal Impedance Models
- www.semi.Intersil.com
• Peak Current vs Pulse Width Curve
• UIS Rating Curve
Symbol
• Switching Time vs RGS Curves
D
Ordering Information
PART NUMBER
G
S
Absolute Maximum Ratings
PACKAGE
BRAND
HUF76429P3
TO-220AB
76429P
HUF76429S3S
TO-263AB
76429S
NOTE: When ordering, use the entire part number. Add the suffix T
to obtain the variant in tape and reel, e.g., HUF76429S3ST.
TC = 25oC, Unless Otherwise Specified
Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDSS
Drain to Gate Voltage (RGS = 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS
Drain Current
Continuous (TC= 25oC, VGS = 5V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID
Continuous (TC= 25oC, VGS = 10V) (Figure 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID
Continuous (TC= 100oC, VGS = 5V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID
Continuous (TC= 100oC, VGS = 4.5V) (Figure 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID
Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .IDM
Pulsed Avalanche Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .UIS
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD
Derate Above 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG
Maximum Temperature for Soldering
Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .TL
Package Body for 10s, See Techbrief TB334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tpkg
NOTES:
HUF76429P3, HUF76429S3S
60
60
±16
UNITS
V
V
V
44
47
31
30
Figure 4
Figures 6, 17, 18
A
A
A
A
110
0.74
-55 to 175
W
W/oC
oC
300
260
oC
oC
1. TJ = 25oC to 150oC.
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures.
UltraFET™ is a trademark of Intersil Corporation. PSPICE™ is a trademark of MicroSim Corporation.
SABER is a Copyright of Analogy, Inc. 1-888-INTERSIL or 407-727-9207 | Copyright © Intersil Corporation 1999.
HUF76429P3, HUF76429S3S
TC = 25oC, Unless Otherwise Specified
Electrical Specifications
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
ID = 250µA, VGS = 0V (Figure 12)
60
-
-
V
ID = 250µA, VGS = 0V , TC = -40oC (Figure 12)
55
-
-
V
VDS = 55V, VGS = 0V
-
-
1
µA
VDS = 50V, VGS = 0V, TC = 150oC
-
-
250
µA
VGS = ±16V
-
-
±100
nA
OFF STATE SPECIFICATIONS
Drain to Source Breakdown Voltage
Zero Gate Voltage Drain Current
BVDSS
IDSS
Gate to Source Leakage Current
IGSS
ON STATE SPECIFICATIONS
Gate to Source Threshold Voltage
VGS(TH)
VGS = VDS, ID = 250µA (Figure 11)
1
-
3
V
Drain to Source On Resistance
rDS(ON)
ID = 47A, VGS = 10V (Figures 9, 10)
-
0.018
0.022
Ω
ID = 31A, VGS = 5V (Figure 9)
-
0.021
0.025
Ω
ID = 30A, VGS = 4.5V (Figure 9)
-
0.022
0.027
Ω
TO-220 and TO-263
-
-
1.36
oC/W
-
-
62
oC/W
-
-
325
ns
THERMAL SPECIFICATIONS
Thermal Resistance Junction to Case
RθJC
Thermal Resistance Junction to
Ambient
RθJA
SWITCHING SPECIFICATIONS (VGS = 4.5V)
Turn-On Time
tON
Turn-On Delay Time
-
13
-
ns
tr
-
203
-
ns
td(OFF)
-
30
-
ns
tf
-
74
-
ns
tOFF
-
-
155
ns
-
-
160
ns
-
7.8
-
ns
td(ON)
Rise Time
Turn-Off Delay Time
Fall Time
Turn-Off Time
VDD = 30V, ID = 30A
VGS = 4.5V, RGS = 7.5Ω
(Figures 15, 21, 22)
SWITCHING SPECIFICATIONS (VGS = 10V)
Turn-On Time
tON
Turn-On Delay Time
td(ON)
Rise Time
Turn-Off Delay Time
Fall Time
Turn-Off Time
VDD = 30V, ID = 47A
VGS = 10V,RGS = 8.2Ω
(Figures 16, 21, 22)
tr
-
100
-
ns
td(OFF)
-
51
-
ns
tf
-
104
-
ns
tOFF
-
-
235
ns
-
38
46
nC
GATE CHARGE SPECIFICATIONS
Total Gate Charge
Gate Charge at 5V
Threshold Gate Charge
Qg(TOT)
VGS = 0V to 10V
Qg(5)
VGS = 0V to 5V
Qg(TH)
VGS = 0V to 1V
VDD = 30V,
ID = 31A,
Ig(REF) = 1.0mA
(Figures 14, 19, 20)
-
21
25
nC
-
1.3
1.6
nC
Gate to Source Gate Charge
Qgs
-
3.8
-
nC
Gate to Drain "Miller" Charge
Qgd
-
9.7
-
nC
-
1480
-
pF
-
440
-
pF
-
90
-
pF
MIN
TYP
MAX
UNITS
ISD = 44A
-
-
1.25
V
ISD = 22A
-
-
1.00
V
trr
ISD = 31A, dISD/dt = 100A/µs
-
-
98
ns
QRR
ISD = 31A, dISD/dt = 100A/µs
-
-
230
nC
CAPACITANCE SPECIFICATIONS
Input Capacitance
CISS
Output Capacitance
COSS
Reverse Transfer Capacitance
CRSS
VDS = 25V, VGS = 0V,
f = 1MHz
(Figure 13)
Source to Drain Diode Specifications
PARAMETER
SYMBOL
Source to Drain Diode Voltage
VSD
Reverse Recovery Time
Reverse Recovered Charge
2
TEST CONDITIONS
HUF76429P3, HUF76429S3S
Typical Performance Curves
50
1.0
ID, DRAIN CURRENT (A)
POWER DISSIPATION MULTIPLIER
1.2
0.8
0.6
0.4
40
VGS = 10V
30
VGS = 4.5V
20
10
0.2
0
0
0
25
50
75
100
150
125
25
175
50
75
100
125
150
175
TC, CASE TEMPERATURE (oC)
TC , CASE TEMPERATURE (oC)
FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE
TEMPERATURE
FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs
CASE TEMPERATURE
2
ZθJC, NORMALIZED
THERMAL IMPEDANCE
1
DUTY CYCLE - DESCENDING ORDER
0.5
0.2
0.1
0.05
0.02
0.01
PDM
0.1
t1
t2
NOTES:
DUTY FACTOR: D = t1/t2
PEAK TJ = PDM x ZθJC x RθJC + TC
SINGLE PULSE
0.01
10-5
10-4
10-3
10-2
10-1
100
101
t, RECTANGULAR PULSE DURATION (s)
FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
IDM, PEAK CURRENT (A)
600
TC = 25oC
FOR TEMPERATURES
ABOVE 25oC DERATE PEAK
CURRENT AS FOLLOWS:
175 - TC
I = I25
150
VGS = 10V
100
VGS = 5V
TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION
30
10-5
10-4
10-3
10-2
t, PULSE WIDTH (s)
FIGURE 4. PEAK CURRENT CAPABILITY
3
10-1
100
101
HUF76429P3, HUF76429S3S
Typical Performance Curves
(Continued)
100
IAS, AVALANCHE CURRENT (A)
ID, DRAIN CURRENT (A)
300
100
100µs
OPERATION IN THIS
AREA MAY BE
LIMITED BY rDS(ON)
10
1ms
SINGLE PULSE
TJ = MAX RATED
TC = 25oC
1
STARTING TJ = 150oC
If R = 0
tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD)
If R ≠ 0
tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1]
10ms
10
0.001
1
10
0.01
100
VDS, DRAIN TO SOURCE VOLTAGE (V)
0.1
FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING
CAPABILITY
50
50
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
VDD = 15V
VGS = 10V
ID, DRAIN CURRENT (A)
40
30
20
TJ= 175oC
TJ= -55oC
10
VGS = 5V
VGS = 4V
40
VGS = 3.5V
30
20
VGS = 3V
10
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
TC = 25oC
TJ= 25oC
0
0
1.5
2
2.5
3
3.5
VGS, GATE TO SOURCE VOLTAGE (V)
0
4
FIGURE 7. TRANSFER CHARACTERISTICS
1
2
3
VDS, DRAIN TO SOURCE VOLTAGE (V)
2.5
30
ID = 22A
20
10
NORMALIZED DRAIN TO SOURCE
ON RESISTANCE
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
TC = 25oC
ID = 44A
4
FIGURE 8. SATURATION CHARACTERISTICS
40
rDS(ON), DRAIN TO SOURCE
ON RESISTANCE (mΩ)
1
tAV, TIME IN AVALANCHE (ms)
NOTE: Refer to Intersil Application Notes AN9321 and AN9322.
FIGURE 5. FORWARD BIAS SAFE OPERATING AREA
ID, DRAIN CURRENT (A)
STARTING TJ = 25oC
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
VGS = 10V, ID = 47A
2.0
1.5
1.0
0.5
2
4
6
8
VGS, GATE TO SOURCE VOLTAGE (V)
10
FIGURE 9. DRAIN TO SOURCE ON RESISTANCE vs GATE
VOLTAGE AND DRAIN CURRENT
4
-80
-40
0
40
80
120
160
TJ, JUNCTION TEMPERATURE (oC)
FIGURE 10. NORMALIZED DRAIN TO SOURCE ON
RESISTANCE vs JUNCTION TEMPERATURE
200
HUF76429P3, HUF76429S3S
Typical Performance Curves
(Continued)
1.2
1.2
1.0
0.8
0.6
0.4
-80
ID = 250µA
NORMALIZED DRAIN TO SOURCE
BREAKDOWN VOLTAGE
NORMALIZED GATE
THRESHOLD VOLTAGE
VGS = VDS, ID = 250µA
1.1
1.0
0.9
-40
0
40
80
120
160
200
-80
-40
TJ, JUNCTION TEMPERATURE (oC)
0
40
80
120
160
200
TJ , JUNCTION TEMPERATURE (oC)
FIGURE 11. NORMALIZED GATE THRESHOLD VOLTAGE vs
JUNCTION TEMPERATURE
FIGURE 12. NORMALIZED DRAIN TO SOURCE BREAKDOWN
VOLTAGE vs JUNCTION TEMPERATURE
10
VGS , GATE TO SOURCE VOLTAGE (V)
3000
C, CAPACITANCE (pF)
VGS = 0V, f = 1MHz
CISS = CGS + CGD
1000
COSS ≅ CDS + CGD
100
CRSS = CGD
VDD = 30V
8
6
4
WAVEFORMS IN
DESCENDING ORDER:
ID = 44A
ID = 22A
2
0
30
0
0.1
1.0
10
60
VDS , DRAIN TO SOURCE VOLTAGE (V)
10
20
30
15
25
Qg, GATE CHARGE (nC)
35
40
NOTE: Refer to Intersil Application Notes AN7254 and AN7260.
FIGURE 13. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
FIGURE 14. GATE CHARGE WAVEFORMS FOR CONSTANT
GATE CURRENT
600
250
VGS = 10V, VDD = 30V, ID = 47A
SWITCHING TIME (ns)
VGS = 4.5V, VDD = 30V, ID = 30A
SWITCHING TIME (ns)
5
450
tr
300
tf
150
td(OFF)
200
tf
150
tr
100
td(OFF)
50
td(ON)
td(ON)
0
0
0
10
20
30
40
RGS, GATE TO SOURCE RESISTANCE (Ω)
FIGURE 15. SWITCHING TIME vs GATE RESISTANCE
5
50
0
10
20
30
40
RGS, GATE TO SOURCE RESISTANCE (Ω)
FIGURE 16. SWITCHING TIME vs GATE RESISTANCE
50
HUF76429P3, HUF76429S3S
Test Circuits and Waveforms
VDS
BVDSS
L
tP
VARY tP TO OBTAIN
REQUIRED PEAK IAS
+
RG
VDS
IAS
VDD
VDD
-
VGS
DUT
tP
0V
IAS
0
0.01Ω
tAV
FIGURE 17. UNCLAMPED ENERGY TEST CIRCUIT
FIGURE 18. UNCLAMPED ENERGY WAVEFORMS
VDS
VDD
RL
Qg(TOT)
VDS
VGS = 10V
VGS
Qg(5)
+
VDD
VGS = 5V
VGS
DUT
VGS = 1V
Ig(REF)
0
Qg(TH)
Qgs
Qgd
Ig(REF)
0
FIGURE 19. GATE CHARGE TEST CIRCUIT
FIGURE 20. GATE CHARGE WAVEFORMS
VDS
tON
tOFF
td(ON)
td(OFF)
tf
tr
RL
VDS
90%
90%
+
VGS
VDD
-
10%
10%
0
DUT
90%
RGS
VGS
VGS
0
FIGURE 21. SWITCHING TIME TEST CIRCUIT
6
10%
50%
50%
PULSE WIDTH
FIGURE 22. SWITCHING TIME WAVEFORM
HUF76429P3, HUF76429S3S
PSPICE Electrical Model
.SUBCKT HUF76429 2 1 3 ;
rev 25 June 1999
CA 12 8 1.95e-9
CB 15 14 1.95e-9
CIN 6 8 1.39e-9
LDRAIN
DPLCAP
DBODY 7 5 DBODYMOD
DBREAK 5 11 DBREAKMOD
DPLCAP 10 5 DPLCAPMOD
10
RLDRAIN
RSLC1
51
DBREAK
+
RSLC2
EBREAK 11 7 17 18 68.05
EDS 14 8 5 8 1
EGS 13 8 6 8 1
ESG 6 10 6 8 1
EVTHRES 6 21 19 8 1
EVTEMP 20 6 18 22 1
5
51
ESLC
11
-
RDRAIN
6
8
ESG
IT 8 17 1
LGATE
GATE
1
LDRAIN 2 5 1e-9
LGATE 1 9 5.80e-9
LSOURCE 3 7 4.57e-9
+
17
EBREAK 18
50
EVTHRES
+ 19 8
+
EVTEMP
RGATE +
18 22
9
20
21
DBODY
-
16
MWEAK
6
MMED
MSTRO
RLGATE
LSOURCE
CIN
MMED 16 6 8 8 MMEDMOD
MSTRO 16 6 8 8 MSTROMOD
MWEAK 16 21 8 8 MWEAKMOD
8
SOURCE
3
7
RSOURCE
RLSOURCE
S2A
S1A
RBREAK 17 18 RBREAKMOD 1
RDRAIN 50 16 RDRAINMOD 7.8e-3
RGATE 9 20 2.80
RLDRAIN 2 5 10
RLGATE 1 9 54.2
RLSOURCE 3 7 41.6
RSLC1 5 51 RSLCMOD 1e-6
RSLC2 5 50 1e3
RSOURCE 8 7 RSOURCEMOD 6.5e-3
RVTHRES 22 8 RVTHRESMOD 1
RVTEMP 18 19 RVTEMPMOD 1
S1A
S1B
S2A
S2B
DRAIN
2
5
12
14
13
13
8
S1B
17
18
RVTEMP
S2B
13
CA
RBREAK
15
CB
6
8
-
-
IT
14
+
+
EGS
19
VBAT
5
8
EDS
-
+
8
22
RVTHRES
6 12 13 8 S1AMOD
13 12 13 8 S1BMOD
6 15 14 13 S2AMOD
13 15 14 13 S2BMOD
VBAT 22 19 DC 1
ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*117),3))}
.MODEL DBODYMOD D (IS = 1.28e-12 IKF = 11.5 RS = 5.25e-3 TRS1 = 1.78e-3 TRS2 = 1.85e-6 CJO = 1.68e-9 TT = 6.14e-8 M = 0.48 XTI = 4.35)
.MODEL DBREAKMOD D (RS = 2.27e-1 TRS1 = 9.10e-4 TRS2 = -1e-6)
.MODEL DPLCAPMOD D (CJO = 1.23e-9 IS = 1e-30 N = 10 M = 0.8)
.MODEL MMEDMOD NMOS (VTO = 1.98 KP = 3.2 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 2.80)
.MODEL MSTROMOD NMOS (VTO = 2.30 KP = 67 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u)
.MODEL MWEAKMOD NMOS (VTO = 1.72 KP = 0.08 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 28.0 RS = 0.1)
.MODEL RBREAKMOD RES (TC1 = 1.08e-3 TC2 = 1.35e-7)
.MODEL RDRAINMOD RES (TC1 = 8.25e-3 TC2 = 1.85e-5)
.MODEL RSLCMOD RES (TC1 = 4.97e-3 TC2 = 5.05e-6)
.MODEL RSOURCEMOD RES (TC1 = 1.5e-3 TC2 = 1e-6)
.MODEL RVTHRESMOD RES (TC1 = -1.85e-3 TC2 = -9.48e-6)
.MODEL RVTEMPMOD RES (TC1 = -1.72e-3 TC2 = 9.50e-7)
.MODEL S1AMOD VSWITCH (RON = 1e-5
.MODEL S1BMOD VSWITCH (RON = 1e-5
.MODEL S2AMOD VSWITCH (RON = 1e-5
.MODEL S2BMOD VSWITCH (RON = 1e-5
ROFF = 0.1
ROFF = 0.1
ROFF = 0.1
ROFF = 0.1
VON = -6.2 VOFF= -2.4)
VON = -2.4 VOFF= -6.2)
VON = -1.1 VOFF= 0.5)
VON = 0.5 VOFF= -1.1)
.ENDS
NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global
Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley.
7
HUF76429P3, HUF76429S3S
SABER Electrical Model
REV 25 June 1999
template huf76429 n2,n1,n3
electrical n2,n1,n3
{
var i iscl
d..model dbodymod = (is = 1.28e-12, cjo = 1.68e-9, tt = 6.14e-8, xti = 4.35, m = 0.48)
d..model dbreakmod = ()
d..model dplcapmod = (cjo = 1.23e-9, is = 1e-30, n = 10, m = 0.8)
m..model mmedmod = (type=_n, vto = 1.98, kp = 3.2, is = 1e-30, tox = 1)
m..model mstrongmod = (type=_n, vto = 2.30, kp = 67, is = 1e-30, tox = 1)
m..model mweakmod = (type=_n, vto = 1.72, kp = 0.08, is = 1e-30, tox = 1)
sw_vcsp..model s1amod = (ron = 1e-5, roff = 0.1, von = -6.2, voff = -2.4)
DPLCAP
sw_vcsp..model s1bmod = (ron =1e-5, roff = 0.1, von = -2.4, voff = -6.2)
10
sw_vcsp..model s2amod = (ron = 1e-5, roff = 0.1, von = -1.1, voff = 0.5)
sw_vcsp..model s2bmod = (ron = 1e-5, roff = 0.1, von = 0.5, voff = -1.1)
c.ca n12 n8 = 1.95e-9
c.cb n15 n14 = 1.95e-9
c.cin n6 n8 = 1.39e-9
LDRAIN
DRAIN
2
5
RSLC1
51
RLDRAIN
RDBREAK
RSLC2
72
ISCL
EVTHRES
+ 19 8
+
i.it n8 n17 = 1
LGATE
GATE
1
l.ldrain n2 n5 = 1e-9
l.lgate n1 n9 = 5.80e-9
l.lsource n3 n7 = 4.57e-9
RDRAIN
6
8
ESG
EVTEMP
RGATE + 18 22
9
20
16
MWEAK
DBODY
EBREAK
+
17
18
MSTRO
CIN
71
11
MMED
m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u
m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u
m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u
-
8
LSOURCE
7
RSOURCE
RLSOURCE
S1A
12
S2A
13
8
S1B
CA
RBREAK
15
14
13
17
18
RVTEMP
S2B
13
CB
6
8
EGS
19
-
sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod
sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod
sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod
sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod
v.vbat n22 n19 = dc=1
equations {
i (n51->n50) +=iscl
iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/117))** 3))
}
}
-
IT
14
+
+
spe.ebreak n11 n7 n17 n18 = 68.05
spe.eds n14 n8 n5 n8 = 1
spe.egs n13 n8 n6 n8 = 1
spe.esg n6 n10 n6 n8 = 1
spe.evtemp n20 n6 n18 n22 = 1
spe.evthres n6 n21 n19 n8 = 1
8
21
6
RLGATE
res.rbreak n17 n18 = 1, tc1 = 1.08e-3, tc2 = 1.35e-7
res.rdbody n71 n5 = 5.25e-3, tc1 = 1.78e-3, tc2 = 1.85e-6
res.rdbreak n72 n5 = 2.27e-1, tc1 = 9.10e-4, tc2 = -1.00e-6
res.rdrain n50 n16 = 7.80e-3, tc1 = 8.25e-3, tc2 = 1.85e-5
res.rgate n9 n20 = 2.80
res.rldrain n2 n5 = 10
res.rlgate n1 n9 = 54.2
res.rlsource n3 n7 = 41.6
res.rslc1 n5 n51 = 1e-6, tc1 = 4.97e-3, tc2 = 5.05e-6
res.rslc2 n5 n50 = 1e3
res.rsource n8 n7 = 6.5e-3, tc1 = 1.5e-3, tc2 = 1e-6
res.rvtemp n18 n19 = 1, tc1 = -1.72e-3, tc2 = 9.50e-7
res.rvthres n22 n8 = 1, tc1 = -1.85e-3, tc2 = -9.48e-6
DBREAK
50
-
d.dbody n7 n71 = model=dbodymod
d.dbreak n72 n11 = model=dbreakmod
d.dplcap n10 n5 = model=dplcapmod
RDBODY
VBAT
5
8
EDS
-
+
8
22
RVTHRES
SOURCE
3
HUF76429P3, HUF76429S3S
SPICE Thermal Model
th
JUNCTION
REV 2 August 1999
HUF76429
RTHERM1
CTHERM1 th 6 2.45e-3
CTHERM2 6 5 8.15e-3
CTHERM3 5 4 7.40e-3
CTHERM4 4 3 7.45e-3
CTHERM5 3 2 1.01e-2
CTHERM6 2 tl 7.49e-2
CTHERM1
6
RTHERM2
RTHERM1 th 6 9.00e-3
RTHERM2 6 5 1.80e-2
RTHERM3 5 4 9.15e-2
RTHERM4 4 3 2.43e-1
RTHERM5 3 2 3.50e-1
RTHERM6 2 tl 3.62e-1
CTHERM2
5
RTHERM3
CTHERM3
SABER Thermal Model
4
SABER thermal model HUF76429
template thermal_model th tl
thermal_c th, tl
{
ctherm.ctherm1 th 6 = 2.45e-3
ctherm.ctherm2 6 5 = 8.15e-3
ctherm.ctherm3 5 4 = 7.40e-3
ctherm.ctherm4 4 3 = 7.45e-3
ctherm.ctherm5 3 2 = 1.01e-2
ctherm.ctherm6 2 tl = 7.49e-2
RTHERM4
CTHERM4
3
RTHERM5
rtherm.rtherm1 th 6 = 9.00e-3
rtherm.rtherm2 6 5 = 1.80e-2
rtherm.rtherm3 5 4 = 9.15e-2
rtherm.rtherm4 4 3 = 2.43e-1
rtherm.rtherm5 3 2 = 3.50e-1
rtherm.rtherm6 2 tl = 3.62e-1
}
CTHERM5
2
RTHERM6
CTHERM6
tl
CASE
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