Freescale MCF51JM32VQH Mcf51jm128 coldfire microcontroller Datasheet

Freescale Semiconductor
Data Sheet: Technical Data
Document Number: MCF51JM128
Rev. 2, 09/2008
MCF51JM128
MCF51JM128 ColdFire
Microcontroller
80 LQFP
14 mm × 14 mm
64 LQFP
10 mm × 10 mm
44 LQFP
10 mm × 10 mm
64 QFP
14 mm × 14 mm
The MCF51JM128 is a member of the ColdFire® family of
32-bit reduced instruction set computing (RISC)
microprocessors. This document provides an overview of the
MCF51JM128 series, focusing on its highly integrated and
diverse feature set.
The MCF51JM128 series is based on the V1 ColdFire core
and operates at processor core speeds up to 50.33 MHz. As
part of Freescale’s Controller Continuum®, it is an ideal
upgrade for designs based on the MC9S08JM60 series of 8-bit
microcontrollers.
The MCF51JM128 features the following functional units:
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V1 ColdFire core with background debug module
Up to 128 KBytes of flash memory
Up to 16 Kbytes of static RAM (SRAM)
Multipurpose clock generator (MCG)
Dual-role Universal Serial Bus On-The-Go device
(USBOTG)
Controller-area network (MSCAN)
Cryptographic acceleration unit (CAU)
Random number generator accelerator (RNGA)
Analog comparators (ACMP)
Analog-to-digital converter (ADC) with up to 12 channels
Two Inter-integrated circuit (IIC) modules
Two serial peripheral interfaces (SPI)
Two serial communications interfaces (SCI)
Carrier modulation timer (CMT)
Eight-channel timer/pulse-width modulators (TPM)
Real-time counter (RTC)
66 general-purpose input/output (GPIO) modules plus
Interrupt request input
Eight keyboard interrupts (KBI)
16-bit Rapid GPIO
This document contains information on a product under development. Freescale reserves the
right to change or discontinue this product without notice.
© Freescale Semiconductor, Inc., 2008. All rights reserved.
Table of Contents
1
2
3
4
MCF51JM128 Family Configurations . . . . . . . . . . . . . . . . . . . .3
1.1 Device Comparison. . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
1.2 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
1.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
1.3.1 Feature List . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
1.4 Part Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
1.5 Pinouts and Packaging . . . . . . . . . . . . . . . . . . . . . . . . .10
Preliminary Electrical Characteristics . . . . . . . . . . . . . . . . . . .15
2.1 Parameter Classification . . . . . . . . . . . . . . . . . . . . . . . .15
2.2 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . .15
2.3 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . .16
2.4 Electrostatic Discharge (ESD) Protection Characteristics
17
2.5 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
2.6 Supply Current Characteristics . . . . . . . . . . . . . . . . . . .22
2.7 Analog Comparator (ACMP) Electricals . . . . . . . . . . . .23
2.8 ADC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . .23
2.9 External Oscillator (XOSC) Characteristics . . . . . . . . .27
2.10 MCG Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . .28
2.11 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
2.11.1 Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . .29
2.11.2 Timer/PWM (TPM) Module Timing . . . . . . . . . .30
2.11.3 MSCAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
2.12 SPI Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
2.13 Flash Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . .35
2.14 USB Electricals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
2.15 EMC Performance. . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
2.15.1 Radiated Emissions . . . . . . . . . . . . . . . . . . . . . .36
Mechanical Outline Drawings . . . . . . . . . . . . . . . . . . . . . . . . .37
3.1 80-pin LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
3.2 64-pin LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
3.3 64-pin QFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
3.4 44-pin LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
List of Figures
Figure 1. MCF51JM128 Block Diagram . . . . . . . . . . . . . . . . . . . . 5
Figure 2. 80-pin LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 3. 64-pin QFP and LQFP . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 4. 44-pin LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 5. Typical Low-side Drive (sink)
characteristics – High Drive (PTxDSn = 1) . . . . . . . . . 21
Figure 6. Typical Low-side Drive (sink)
characteristics – Low Drive (PTxDSn = 0). . . . . . . . . .
Figure 7. Typical High-side Drive (source)
characteristics – High Drive (PTxDSn = 1) . . . . . . . . .
Figure 8. Typical High-side Drive (source)
characteristics – Low Drive (PTxDSn = 0). . . . . . . . . .
Figure 9. ADC Input Impedance Equivalency Diagram . . . . . . .
Figure 10.Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 11.IRQ/KBIPx Timing . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 12.Timer External Clock . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 13.Timer Input Capture Pulse . . . . . . . . . . . . . . . . . . . . .
Figure 14.SPI Master Timing (CPHA = 0) . . . . . . . . . . . . . . . . .
Figure 15.SPI Master Timing (CPHA = 1) . . . . . . . . . . . . . . . . .
Figure 16.SPI Slave Timing (CPHA = 0) . . . . . . . . . . . . . . . . . .
Figure 17.SPI Slave Timing (CPHA = 1) . . . . . . . . . . . . . . . . . .
21
21
22
24
30
30
31
31
33
33
34
34
List of Tables
Table 1. MCF51JM128 Series Device Comparison . . . . . . . . . . 3
Table 2. MCF51JM128 Series Functional Units . . . . . . . . . . . . . 6
Table 3. Orderable Part Number Summary. . . . . . . . . . . . . . . . . 9
Table 4. Pin Assignments by Package and Pin Sharing Priority 12
Table 5. Parameter Classifications . . . . . . . . . . . . . . . . . . . . . . 15
Table 6. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . 16
Table 7. Thermal Characteristics. . . . . . . . . . . . . . . . . . . . . . . . 16
Table 8. ESD and Latch-up Test Conditions . . . . . . . . . . . . . . . 17
Table 9. ESD and Latch-Up Protection Characteristics. . . . . . . 18
Table 10.DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 11. Supply Current Characteristics. . . . . . . . . . . . . . . . . . 22
Table 12.Analog Comparator Electrical Specifications. . . . . . . . 23
Table 13.5 Volt 12-bit ADC Operating Conditions . . . . . . . . . . . 23
Table 14.5 Volt 12-bit ADC Characteristics
(VREFH = VDDAD, VREFL = VSSAD) . . . . . . . . . . . . 25
Table 15.Oscillator Electrical Specifications
(Temperature Range = –40 to 105×C Ambient) . . . . . 27
Table 16.MCG Frequency Specifications
(Temperature Range = –40 to 125×C Ambient) . . . . . 28
Table 17.Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 18.TPM Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 19.MSCAN Wake-up Pulse Characteristics . . . . . . . . . . . 31
Table 20.SPI Electrical Characteristic . . . . . . . . . . . . . . . . . . . . 32
Table 21.Flash Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 22.Internal USB 3.3V Voltage Regulator Characteristics . 36
MCF51JM128 ColdFire Microcontroller, Rev. 2
2
Freescale Semiconductor
MCF51JM128 Family Configurations
1
MCF51JM128 Family Configurations
1.1
Device Comparison
The MCF51JM128 series consists of the devices compared in Table 1.
Table 1. MCF51JM128 Series Device Comparison
MCF51JM128
MCF51JM32
MCF51JM64
Feature
80-pin
64-pin
44-pin
80-pin
64-pin
44-pin
80-pin
64-pin
Flash memory size (Kbytes)
128
64
32
RAM size (Kbytes)
16
16
16
V1 ColdFire core with BDM (background
debug module)
Yes
ACMP (analog comparator)
Yes
44-pin
ADC (analog-to-digital converter)
channels (12-bit)
12
8
12
8
12
8
CAN (controller area network)
Yes
No
Yes
No
Yes
No
CAU (cryptographic acceleration unit)
Yes
No
No
Yes
No
CMT (carrier modulator timer)
Yes
COP (computer operating properly)
Yes
IIC1 (inter-integrated circuit)
Yes
IIC2
Yes
No
Yes
IRQ (interrupt request input)
KBI (keyboard interrupts)
No
Yes
No
Yes
No
No
Yes
8
8
6
8
8
LVD (low-voltage detector)
Yes
MCG (multipurpose clock generator)
Yes
1
No
6
8
8
6
Port I/O
66
51
33
66
51
33
66
51
33
RGPIO (rapid general-purpose I/O)
16
6
0
16
6
0
16
6
0
RNGA (random number generator
accelerator)
Yes
RTC (real-time counter)
Yes
SCI1 (serial communications interface)
Yes
SCI2
Yes
SPI1 (serial peripheral interface)
Yes
SPI2
Yes
MCF51JM128 ColdFire Microcontroller, Rev. 2
Freescale Semiconductor
3
MCF51JM128 Family Configurations
Table 1. MCF51JM128 Series Device Comparison (continued)
MCF51JM128
MCF51JM32
MCF51JM64
Feature
TPM1 (timer/pulse-width modulator)
channels
TPM2 channels
80-pin
64-pin
44-pin
80-pin
64-pin
44-pin
80-pin
64-pin
44-pin
6
6
4
6
6
4
6
6
4
2
USBOTG (USB On-The-Go dual-role
controller)
Yes
XOSC (crystal oscillator)
Yes
1
Up to 16 pins on Ports A, H, and J are shared with the ColdFire Rapid GPIO module.
1.2
Block Diagram
Figure 1 shows the connections between the MCF51JM128 series pins and modules.
MCF51JM128 ColdFire Microcontroller, Rev. 2
4
Freescale Semiconductor
TPMCLK
TPM1
Port F:
TPM1CH5
TPM1CH4
TPM1CH3
TPM1CH2
Port E:
TPM1CH1
TPM1CH0
TPM2
Port F:
TPM2CH1
TPM2CH0
SYSCTL
COP
LVD
IRQ
TPMCLK
IIC1
Port C:
SDA1
SCL1
IIC2
Port H:
SCL2
SDA2
KBI
Port B:
KBIP5
KBIP4
Port D:
KBIP3
KBIP2
Port G:
KBIP7
KBIP6
KBIP1
KBIP0
FLASH
128 or 64 Kbytes
Port G:
MCG
RAM
VDD
VDD
VSS
VSS
INTC
USB
Port C:
RXCAN
Port F:
TXCAN
SCI1
Port E:
RXD1
TXD1
SCI2
Port C:
RXD2
TXD2
SPI1
Port E:
SS1
SPSCK1
MOSI1
MISO1
SPI2
Port B:
SS2
SPSCK2
MOSI2
MISO2
RNGA
USBDN
USBDP
VUSB33
PTC7
PTC6/RXCAN
PTC5/RXD2
PTC4
PTC3/TXD2
PTC2/IRO
PTC1/SDA1
PTC0/SCL1
PTD7
PTD6
PTD5
PTD4/ADP11
PTD3/KBIP3/ADP10
PTD2/KBIP2/ACMPO
PTD1/ACMP–/ADP9
PTD0/ACMP+/ADP8
PTE7/SS1
PTE6/SPSCK1
PTE5/MOSI1
PTE4/MISO1
PTE3/TPM1CH1
PTE2/TPM1CH0
PTE1/RXD1
PTE0/TXD1
PTF7/TXCAN
PTF6
PTF5/TPM2CH1
PTF4/TPM2CH0
PTF3/TPM1CH5
PTF2/TPM1CH4
PTF1/TPM1CH3
PTF0/TPM1CH2
PTG7
PTG6
PTG5/EXTAL
PTG4/XTAL
PTG3/KBIP7
PTG2/KBIP6
PTG1/KBIP1
PTG0/KBIP0
PTH4/RGPIO10
PTH3/RGPIO9
PTH2/RGPIO8
PTH1/SCL2
PTH0/SDA2
PTJ4/RGPIO15
PTJ3/RGPIO14
PTJ2/RGPIO13
PTJ1/RGPIO12
PTJ0/RGPIO11
XTAL
CAN
VREG
PTB7/ADP7
PTB6/ADP6
PTB5/KBIP5/ADP5
PTB4/KBIP4/ADP4
PTB3/SS2/ADP3
PTB2/SPSCK2/ADP2
PTB1/MOSI2/ADP1
PTB0/MISO2/ADP0
XOSC EXTAL
16 or 8 Kbytes
Port J:
RGPIO15
RGPIO14
RGPIO13
RGPIO12
RGPIO11
Port H:
RGPIO10
RGPIO9
RGPIO RGPIO8
Port A:
RGPIO7
RGPIO6
RGPIO5
RGPIO4
RGPIO3
RGPIO2
RGPIO1
RGPIO0
Port A
IRQ/TPMCLK
Port C:
IRO
Port B
V1 ColdFire core
RESET
CMT
Port C
ADC
Port D
DBG
PTA7/RGPIO7
PTA6/RGPIO6
PTA5/RGPIO5
PTA4/RGPIO4
PTA3/RGPIO3
PTA2/RGPIO2
PTA1/RGPIO1
PTA0/RGPIO0
Port E
CAU
Port D:
ACMPO
ACMP ACMP–
ACMP+
Port F
BDM
Port B:
ADP7
ADP6
ADP5
ADP4
ADP3
ADP2
ADP1
ADP0
Port D:
ADP11
ADP10
ADP9
ADP8
Port G
BKGD/MS
VREFH
VREFL
VDDAD
VSSAD
Port H
VREFH
VREFL
VDDAD
VSSAD
Port J
MCF51JM128 Family Configurations
RTC
Figure 1. MCF51JM128 Block Diagram
MCF51JM128 ColdFire Microcontroller, Rev. 2
Freescale Semiconductor
5
MCF51JM128 Family Configurations
1.3
Features
Table 2 describes the functional units of the MCF51JM128 series.
Table 2. MCF51JM128 Series Functional Units
Unit
Function
CF1CORE (V1 ColdFire core)
Executes programs and interrupt handlers
BDM (background debug module)
Provides a single-pin debugging interface (part of the V1 ColdFire core)
DBG (debug)
Provides debugging and emulation capabilities (part of the V1 ColdFire core)
SYSCTL (system control)
Provides LVD, COP, external interrupt request, and so on
FLASH (flash memory)
Provides storage for program code and constants
RAM (random-access memory)
Provides storage for program code, constants, and variables
RGPIO (rapid general-purpose input/output)
Allows I/O port access at CPU clock speeds
VREG (voltage regulator)
Controls power management throughout the device
USBOTG (USB On-The-Go)
Supports the USB On-The-Go dual-role controller
ADC (analog-to-digital converter)
Measures analog voltages at up to 12 bits of resolution
TPM1, TPM2 (timer/pulse-width modulators)
Provide a variety of timing-based features
CF1_INTC (interrupt controller)
Controls and prioritizes all device interrupts
CAU (cryptographic acceleration unit)
Co-processor support for DES, 3DES, AES, MD5, and SHA-1
RNGA (random number generator accelerator)
32-bit random number generator that complies with FIPS-140
RTC (real-time counter)
Provides a constant-time base with optional interrupt
ACMP (analog comparator)
Compares two analog inputs
CMT (carrier modulator timer)
Infrared output used for the Remote Controller
IIC1, IIC2 (inter-integrated circuits)
Supports the standard IIC communications protocol
KBI (keyboard interrupt)
Provides pin interrupt capabilities
MCG (multipurpose clock generator)
Provides clocking options for the device, including a phase-locked loop (PLL)
and frequency-locked loop (FLL) for multiplying slower reference clock
sources
XOSC (crystal oscillator)
Supports low/high range crystals
CAN (controller area network)
Supports standard CAN communications protocol
SCI1, SCI2 (serial communications interfaces)
Serial communications UARTs that can support RS-232 and LIN protocols
SPI1, SPI2 (serial peripheral interfaces)
Provide a 4-pin synchronous serial interface
MCF51JM128 ColdFire Microcontroller, Rev. 2
6
Freescale Semiconductor
MCF51JM128 Family Configurations
1.3.1
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•
•
•
•
Feature List
32-Bit Version 1 ColdFire® Central Processor Unit (CPU)
— Up to 50.33 MHz at 2.7 V – 5.5 V
— Performance (Dhrystone 2.1):
– 0.94 Dhrystone 2.1 MIPS per MHz when running from internal RAM
– 0.76 Dhrystone 2.1 MIPS per MHz when running from flash
— Implements Instruction Set Revision C (ISA_C)
— Supports up to 30 peripheral interrupt requests and seven software interrupts
On-chip memory
— Up to 128 KBytes Flash memory with read/program/erase over full operating voltage and temperature range
— Up to 16 KBytes static random access memory (RAM)
— Security circuitry to prevent unauthorized access to RAM and flash contents
Power-saving modes
— Two low-power stop plus wait modes
— Peripheral clock enable register can disable clocks to unused modules, thereby reducing currents; this behavior
allows clocks to remain enabled to specific perhipherals in Stop3 mode
— Very lower power real-time counter for use in run, wait, and stop modes with internal and external clock sources
Four Clock Source Options
— Oscillator (XOSC) — Loop-control Pierce oscillator; crystal or ceramic resonator range of 31.25 kHz to 38.4 kHz
or 1 MHz to 16 MHz
— FLL/PLL controlled by internal or external reference
— Trimmable internal reference allows 0.2% resolution and 2% deviation
System protection features
— Watchdog computer operating properly (COP) reset with option to run from dedicated 1 kHz internal clock source
or bus clock
— Low-voltage detection with reset or interrupt; selectable trip points
— Illegal opcode and illegal address detection with programmable reset or exception response
— Flash block protection
Debug support
— Single-wire Background debug interface
— 4 Program Counters plus two address (optional data) breakpoint registers with programmable 1- or 2-level trigger
response
— 64-entry processor status and debug data trace buffer with programmable start/stop conditions
Universal Serial Bus (USB) On-The-Go dual-role controller
— Full-speed USB device controller
– Fully compliant with USB specification 1.1 and 2.0
– 16 bidirectional endpoints, with double buffering to provide the maximum throughput
– Supports control, bulk, interrupt, and isochronous endpoints
– Supports bus-powered capability with low-power consumption
— Full-speed / low-speed host controller
– Host mode allows control, bulk, interrupt, and isochronous transfers
— OTG protocol logic
— On-chip USB transceiver
— On-chip 3.3 V USB regulator and pull-up resistors save system cost
MCF51JM128 ColdFire Microcontroller, Rev. 2
Freescale Semiconductor
7
MCF51JM128 Family Configurations
•
•
•
•
•
•
•
•
•
Controller area network (MSCAN)
— Implementation of the CAN protocol — Version 2.0A/B
— Five receive buffers with FIFO storage scheme
— Three transmit buffers with internal prioritization using a “local priority” concept
— Flexible maskable identifier filter programmable as 2x32-bit, 4x16-bit, or 8x8-bit
— Programmable wakeup functionality with integrated low-pass filter
— Programmable loopback mode supports self-test operation
— Programmable bus-off recovery functionality
— Internal timer for time-stamping of received and transmitted messages
Cryptographic acceleration unit (CAU)
— Co-processor support of DES, 3DES, AES, MD5, and SHA-1
Random number generator accelerator (RNGA)
— 32-bit random number generator that complies with FIPS-140
Analog-to-digital converter (ADC)
— 12-channel, 12-bit resolution
— Output formatted in 12-, 10-, or 8-bit right-justified format
— Single or continuous conversion, and selectable asynchronous hardware conversion trigger
— Operation in Stop3 mode
— Automatic compare function
— Internal temperature sensor
Analog comparators (ACMP)
— Selectable interrupt on rising edge, falling edge, or either rising or falling edges of comparator output
— Option to compare to fixed internal bandgap reference voltage
— Option to route output to TPM module
— Operation in Stop3 mode
Inter-integrated circuit (IIC)
— Up to 100 kbps with maximum bus loading
— Multi-master operation
— Programmable slave address
— Supports broadcast mode and 10-bit address extension
Serial communications interfaces (SCI)
— Two SCIs with full-duplex, non-return-to-zero (NRZ) format
— LIN master extended break generation
— LIN slave extended break detection
— Programmable 8-bit or 9-bit character length
— Wake up on active edge
Serial peripheral interfaces (SPI)
— Two serial peripheral interfaces with full-duplex or single-wire bidirectional
— Double-buffered transmit and receive
— Programmable transmit bit rate, phase, polarity, and Slave Select output
— MSB-first or LSB-first shifting
Timer/pulse width modulator (TPM)
— 16-bit free-running or modulo up/down count operation
— Up to eight channels, where each channel can be an input capture, output compare, or edge-aligned PWM
— One interrupt per channel plus terminal count interrupt
MCF51JM128 ColdFire Microcontroller, Rev. 2
8
Freescale Semiconductor
MCF51JM128 Family Configurations
•
•
•
1.4
RTC
— 8-bit modulus counter with binary- or decimal-based prescaler
— External clock source for precise time base, time-of-day, calendar or task scheduling functions
— Free running on-chip low power oscillator (1 kHz) for cyclic wake-up without external components
Carrier modulator timer (CMT)
— carrier generator, modulator, and transmitter drive the infrared out (IRO) pin
— operation in independent high/low time control, baseband, FSK, and direct IRO control modes
Input/Output
— 66 GPIOs
— Eight keyboard interrupt pins with selectable polarity
— Hysteresis and configurable pull-up device on all input pins; configurable slew rate and drive strength on all output
pins
— 16 bits of Rapid GPIO connected to the processor’s local 32-bit platform bus with set, clear, and faster toggle
functionality
Part Numbers
Table 3. Orderable Part Number Summary
Freescale Part
Number
Description
Flash / SRAM
(Kbytes)
Package
Temperature
MCF51JM128EVLK
MCF51JM128 ColdFire Microcontroller
with CAU Enabled
128 / 16
80 LQFP
–40 to +105 °C
MCF51JM128VLK
MCF51JM128 ColdFire Microcontroller
128 / 16
80 LQFP
–40 to +105 °C
MCF51JM128VLH
MCF51JM128 ColdFire Microcontroller
128 / 16
64 LQFP
–40 to +105 °C
MCF51JM128VQH
MCF51JM128 ColdFire Microcontroller
128 / 16
64 QFP
–40 to +105 °C
MCF51JM128VLD
MCF51JM128 ColdFire Microcontroller
128 / 16
44 LQFP
–40 to +105 °C
MCF51JM64EVLK
MCF51JM64 ColdFire Microcontroller
with CAU enabled
64 / 16
80 LQFP
–40 to +105 °C
MCF51JM64VLK
MCF51JM64 ColdFire Microcontroller
64 / 16
80 LQFP
–40 to +105 °C
MCF51JM64VLH
MCF51JM64 ColdFire Microcontroller
64 / 16
64 LQFP
–40 to +105 °C
MCF51JM64VQH
MCF51JM64 ColdFire Microcontroller
64 / 16
64 QFP
–40 to +105 °C
MCF51JM64VLD
MCF51JM64 ColdFire Microcontroller
64 / 16
44 LQFP
–40 to +105 °C
MCF51JM32EVLK
MCF51JM32 ColdFire Microcontroller
with CAU enabled
32 / 16
80 LQFP
–40 to +105 °C
MCF51JM32VLK
MCF51JM32 ColdFire Microcontroller
32 / 16
80 LQFP
–40 to +105 °C
MCF51JM32VLH
MCF51JM32 ColdFire Microcontroller
32 / 16
64 LQFP
–40 to +105 °C
MCF51JM32VQH
MCF51JM32 ColdFire Microcontroller
32 / 16
64 QFP
–40 to +105 °C
MCF51JM32VLD
MCF51JM32 ColdFire Microcontroller
32 / 16
44 LQFP
–40 to +105 °C
MCF51JM128 ColdFire Microcontroller, Rev. 2
Freescale Semiconductor
9
MCF51JM128 Family Configurations
1.5
Pinouts and Packaging
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
PTJ3 / RGPIO14
PTJ2 / RGPIO13
PTJ1 / RGPIO12
PTJ0 / RGPIO11
PTD2 / KBIP2 / ACMPO
VSSAD
VREFL
VREFH
VDDAD
PTD1 / ADP9 / ACMP–
PTD0 / ADP8 / ACMP+
PTB7 / ADP7
PTB6 / ADP6
PTB5 / KBIP5 / ADP5
PTB4 / KBIP4 / ADP4
PTB3 / SS2 / ADP3
PTB2 / SPSCK2 / ADP2
PTB1 / MOSI2 / ADP1
PTB0 / MISO2 / ADP0
PTA7 / RGPIO7
PTH3 / RGPIO9
PTH4 / RGPIO10
PTE4 / MISO1
PTE5 / MOSI1
PTE6 / SPSCK1
PTE7 / SS1
VDD
VSS
USBDN
USBDP
VUSB33
PTG0 / KBIP0
PTG1 / KBIP1
PTA0 / RGPIO0
PTA1 / RGPIO1
PTA2 / RGPIO2
PTA3 / RGPIO3
PTA4 / RGPIO4
PTA5 / RGPIO5
PTA6 / RGPIO6
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
PTC4
IRQ / TPMCLK
RESET
PTF0 / TPM1CH2
PTF1 / TPM1CH3
PTF2 / TPM1CH4
PTF3 / TPM1CH5
PTF4 / TPM2CH0
PTC6 / RXCAN
PTF7 / TXCAN
PTF5 / TPM2CH1
PTF6
PTE0 / TXD1
PTE1 / RXD1
PTE2 / TPM1CH0
PTE3 / TPM1CH1
PTC7
PTH0 / SDA2
PTH1 / SCL2
PTH2 / RGPIO8
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
PTC5 / RXD2
PTC3 / TXD2
PTC2 / IRO
PTC1 / SDA1
PTC0 / SCL1
PTG7
PTG6
VDD
VSS
PTG5 / EXTAL
PTG4 / XTAL
BKGD/MS
PTG3 / KBIP7
PTG2 / KBIP6
PTD7
PTD6
PTD5
PTD4 / ADP11
PTD3 / KBIP3 / ADP10
PTJ4 / RGPIO15
Figure 2 shows the pinout of the 80-pin LQFP.
Figure 2. 80-pin LQFP
MCF51JM128 ColdFire Microcontroller, Rev. 2
10
Freescale Semiconductor
MCF51JM128 Family Configurations
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
PTD2 / KBIP2 / ACMPO
VSSAD
VREFL
VREFH
VDDAD
PTD1 / ADP9 / ACMP–
PTD0 / ADP8 / ACMP+
PTB7 / ADP7
PTB6 / ADP6
PTB5 / KBIP5 / ADP5
PTB4 / KBIP4 / ADP4
PTB3 / SS2 / ADP3
PTB2 / SPSCK2 / ADP2
PTB1 / MOSI2 / ADP1
PTB0 / MISO2 / ADP0
PTA5 / RGPIO5
PTE4 / MISO1
PTE5 / MOSI1
PTE6 / SPSCK1
PTE7 / SS1
VDD
VSS
USBDN
USBDP
VUSB33
PTG0 / KBIP0
PTG1 / KBIP1
PTA0 / RGPIO0
PTA1 / RGPIO1
PTA2 / RGPIO2
PTA3 / RGPIO3
PTA4 / RGPIO4
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
PTC4
IRQ / TPMCLK
RESET
PTF0 / TPM1CH2
PTF1 / TPM1CH3
PTF2 / TPM1CH4
PTF3 / TPM1CH5
PTF4 / TPM2CH0
PTC6 / RXCAN
PTF7 / TXCAN
PTF5 / TPM2CH1
PTF6
PTE0 / TXD1
PTE1 / RXD1
PTE2 / TPM1CH0
PTE3 / TPM1CH1
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
PTC5 / RXD2
PTC3 / TXD2
PTC2 / IRO
PTC1 / SDA1
PTC0 / SCL1
VSS
PTG5 / EXTAL
PTG4 / XTAL
BKGD/MS
PTG3 / KBIP7
PTG2 / KBIP6
PTD7
PTD6
PTD5
PTD4 / ADP11
PTD3 / KBIP3 / ADP10
Figure 3 shows the pinout of the 64-pin LQFP and QFP.
Figure 3. 64-pin QFP and LQFP
MCF51JM128 ColdFire Microcontroller, Rev. 2
Freescale Semiconductor
11
MCF51JM128 Family Configurations
33
32
31
30
29
28
27
26
25
24
23
12
13
14
15
16
17
18
19
20
21
22
1
2
3
4
5
6
7
8
9
10
11
PTD2 / KBIP2 / ACMPO
VSSAD / VREFL
VDDAD / VREFH
PTD1 / ADP9 / ACMP–
PTD0 / ADP8 / ACMP+
PTB5 / KBIP5 / ADP5
PTB4 / KBIP4 / ADP4
PTB3 / SS2 / ADP3
PTB2 / SPSCK2 / ADP2
PTB1 / MOSI2 / ADP1
PTB0 / MISO2 / ADP0
PTE4 / MISO1
PTE5 / MOSI1
PTE6 / SPSCK1
PTE7 / SS1
VDD
VSS
USBDN
USBDP
VUSB33
PTG0 / KBIP0
PTG1 / KBIP1
PTC4
IRQ / TPMCLK
RESET
PTF0 / TPM1CH2
PTF1 / TPM1CH3
PTF4 / TPM2CH0
PTF5 / TPM2CH1
PTE0 / TXD1
PTE1 / RXD1
PTE2 / TPM1CH0
PTE3 / TPM1CH1
44
43
42
41
40
39
38
37
36
35
34
PTC5 / RXD2
PTC3 / TXD2
PTC2 / IRO
PTC1 / SDA1
PTC0 / SCL1
VSS
PTG5 / EXTAL
PTG4 / XTAL
BKGD / MS
PTG3 / KBIP7
PTG2 / KBIP6
Figure 4 shows the pinout of the 44-pin LQFP.
Figure 4. 44-pin LQFP
Table 4 shows the package pin assignments.
Table 4. Pin Assignments by Package and Pin Sharing Priority
Pin Number
<-- Lowest
Priority --> Highest
80
64
44
Port Pin
Alt 1
Alt 2
1
1
1
PTC4
2
2
2
—
IRQ
TPMCLK
3
3
3
—
RESET
—
4
4
4
PTF0
TPM1CH2
—
5
5
5
PTF1
TPM1CH3
—
6
6
—
PTF2
TPM1CH4
—
7
7
—
PTF3
TPM1CH5
—
8
8
6
PTF4
TPM2CH0
BUSCLK_OUT
9
9
—
PTC6
RXCAN
—
10
10
—
PTF7
TXCAN
—
11
11
7
PTF5
TPM2CH1
—
12
12
—
PTF6
—
—
13
13
8
PTE0
TXD1
—
14
14
9
PTE1
RXD1
—
15
15
10
PTE2
TPM1CH0
—
—
MCF51JM128 ColdFire Microcontroller, Rev. 2
12
Freescale Semiconductor
MCF51JM128 Family Configurations
Table 4. Pin Assignments by Package and Pin Sharing Priority (continued)
Pin Number
<-- Lowest
Priority --> Highest
80
64
44
Port Pin
Alt 1
Alt 2
16
16
11
PTE3
TPM1CH1
—
17
—
—
PTC7
—
—
18
—
—
PTH0
SDA2
—
19
—
—
PTH1
SCL2
—
20
—
—
PTH2
RGPIO8
—
21
—
—
PTH3
RGPIO9
—
22
—
—
PTH4
RGPIO10
—
23
17
12
PTE4
MISO1
—
24
18
13
PTE5
MOSI1
—
25
19
14
PTE6
SPSCK1
—
26
20
15
PTE7
SS1
—
27
21
16
—
—
VDD
28
22
17
—
—
VSS
29
23
18
—
—
USBDN
30
24
19
—
—
USBDP
31
25
20
—
—
VUSB33
32
26
21
PTG0
KBIP0
USB_ALT_CLK
33
27
22
PTG1
KBIP1
—
34
28
—
PTA0
RGPIO0
USB_SESSVLD
35
29
—
PTA1
RGPIO1
USB_SESSEND
36
30
—
PTA2
RGPIO2
USB_VBUSVLD
37
31
—
PTA3
RGPIO3
USB_PULLUP(D+)
38
32
—
PTA4
RGPIO4
USB_DM_DOWN
39
33
—
PTA5
RGPIO5
USB_DP_DOWN
40
—
—
PTA6
RGPIO6
USB_ID
41
—
—
PTA7
RGPIO7
—
42
34
23
PTB0
MISO2
ADP0
43
35
24
PTB1
MOSI2
ADP1
44
36
25
PTB2
SPSCK2
ADP2
45
37
26
PTB3
SS2
ADP3
46
38
27
PTB4
KBIP4
ADP4
47
39
28
PTB5
KBIP5
ADP5
48
40
—
PTB6
ADP6
—
MCF51JM128 ColdFire Microcontroller, Rev. 2
Freescale Semiconductor
13
MCF51JM128 Family Configurations
Table 4. Pin Assignments by Package and Pin Sharing Priority (continued)
Pin Number
<-- Lowest
Priority --> Highest
80
64
44
Port Pin
Alt 1
Alt 2
49
41
—
PTB7
ADP7
—
50
42
29
PTD0
ADP8
ACMP+
51
43
30
PTD1
ADP9
ACMP–
52
44
31
—
—
VDDAD
53
45
—
—
VREFH
54
46
—
—
VREFL
55
47
—
—
VSSAD
56
48
33
PTD2
KBIP2
ACMPO
57
—
—
PTJ0
RGPIO11
—
58
—
—
PTJ1
RGPIO12
—
59
—
—
PTJ2
RGPIO13
—
60
—
—
PTJ3
RGPIO14
—
61
—
—
PTJ4
RGPIO15
—
62
49
—
PTD3
KBIP3
ADP10
63
50
—
PTD4
ADP11
—
64
51
—
PTD5
—
—
65
52
—
PTD6
—
—
66
53
—
PTD7
—
—
67
54
34
PTG2
KBIP6
—
68
55
35
PTG3
KBIP7
—
69
56
36
—
BKGD
MS
70
57
37
PTG4
XTAL
71
58
38
PTG5
EXTAL
72
59
39
—
—
VSS
73
—
—
—
—
VDD
74
—
—
PTG6
—
—
75
—
—
PTG7
—
—
76
60
40
PTC0
SCL1
—
77
61
41
PTC1
SDA1
—
78
62
42
PTC2
IRO
—
79
63
43
PTC3
TXD2
—
80
64
44
PTC5
RXD2
—
32
MCF51JM128 ColdFire Microcontroller, Rev. 2
14
Freescale Semiconductor
Preliminary Electrical Characteristics
2
Preliminary Electrical Characteristics
This section contains electrical specification tables and reference timing diagrams for the MCF51JM128 microcontroller,
including detailed information on power considerations, DC/AC electrical characteristics, and AC timing specifications.
The electrical specifications are preliminary and are from previous designs or design simulations. These specifications may not
be fully tested or guaranteed at this early stage of the product life cycle. These specifications will, however, be met for
production silicon. Finalized specifications will be published after complete characterization and device qualifications have
been completed.
NOTE
The parameters specified in this data sheet supersede any values found in the module
specifications.
2.1
Parameter Classification
The electrical parameters shown in this supplement are guaranteed by various methods. To give the customer a better
understanding the following classification is used and the parameters are tagged accordingly in the tables where appropriate:
Table 5. Parameter Classifications
P
Those parameters are guaranteed during production testing on each individual device.
C
Those parameters are achieved by the design characterization by measuring a
statistically relevant sample size across process variations.
T
Those parameters are achieved by design characterization on a small sample size from
typical devices under typical conditions unless otherwise noted. All values shown in the
typical column are within this category.
D
Those parameters are derived mainly from simulations.
NOTE
The classification is shown in the column labeled C in the parameter tables where
appropriate.
2.2
Absolute Maximum Ratings
Absolute maximum ratings are stress ratings only, and functional operation at the maxima is not guaranteed. Stress beyond the
limits specified in Table 6 may affect device reliability or cause permanent damage to the device. For functional operating
conditions, refer to the remaining tables in this section.
This device contains circuitry protecting against damage due to high static voltage or electrical fields; however, it is advised
that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages to this
high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (for
instance, VSS or VDD).
MCF51JM128 ColdFire Microcontroller, Rev. 2
Freescale Semiconductor
15
Preliminary Electrical Characteristics
Table 6. Absolute Maximum Ratings
Rating
Symbol
Value
Unit
Supply voltage
VDD
–0.3 to + 5.8
V
Input voltage
VIn
– 0.3 to VDD + 0.3
V
ID
± 25
mA
IDD
120
mA
Tstg
–55 to +150
°C
TJ
150
°C
Instantaneous maximum current
(applies to all port pins)1, 2, 3
Single pin limit
Maximum current into VDD
Storage temperature
Maximum junction temperature
1
Input must be current limited to the value specified. To determine the value of the required
current-limiting resistor, calculate resistance values for positive (VDD) and negative (VSS) clamp
voltages, then use the larger of the two resistance values.
2 All functional non-supply pins are internally clamped to V
SS and VDD.
3
Power supply must maintain regulation within operating VDD range during instantaneous and
operating maximum current conditions. If positive injection current (VIn > VDD) is greater than
IDD, the injection current may flow out of VDD and could result in external power supply going
out of regulation. Ensure external VDD load shunt current is greater than maximum injection
current. This is the greatest risk when the MCU is not consuming power. Examples: if no system
clock is present or if the clock rate is low, which would reduce overall power consumption.
2.3
Thermal Characteristics
This section provides information about operating temperature range, power dissipation, and package thermal resistance. Power
dissipation on I/O pins is usually small compared to the power dissipation in on-chip logic and it is user-determined rather than
being controlled by the MCU design. To take PI/O into account in power calculations, determine the difference between actual
pin voltage and VSS or VDD and multiply by the pin current for each I/O pin. Except in cases of unusually high pin current
(heavy loads), the difference between pin voltage and VSS or VDD is small.
Table 7. Thermal Characteristics
Rating
Symbol
Value
Unit
Operating temperature range (packaged)
TA
–40 to +105
°C
Thermal resistance
80-pin LQFP
1,2,3,4
52
40
1s
2s2p
64-pin LQFP
1s
2s2p
θJA
65
47
°C/W
64-pin QFP
1s
2s2p
54
40
1s
2s2p
69
48
44-pin LQFP
1
Junction temperature is a function of die size, on-chip power dissipation, package thermal
resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation
of other components on the board, and board thermal resistance.
2 Junction to Ambient Natural Convection
MCF51JM128 ColdFire Microcontroller, Rev. 2
16
Freescale Semiconductor
Preliminary Electrical Characteristics
3
4
1s - Single Layer Board, one signal layer
2s2p - Four Layer Board, 2 signal and 2 power layers
The average chip-junction temperature (TJ) in °C can be obtained from:
TJ = TA + (PD × θJA)
Eqn. 1
where:
TA = Ambient temperature, °CθJA = Package thermal resistance, junction-to-ambient, °C/WPD = Pint + PI/OPint =
IDD × VDD, Watts — chip internal powerPI/O = Power dissipation on input and output pins — user determined
For most applications, PI/O << Pint and can be neglected. An approximate relationship between PD and TJ (if PI/O is neglected)
is:
PD = K ÷ (TJ + 273°C)
Eqn. 2
K = PD × (TA + 273°C) + θJA × (PD)2
Eqn. 3
Solving equations 1 and 2 for K gives:
where K is a constant pertaining to the particular part. K can be determined from equation 3 by measuring PD (at equilibrium)
for a known TA. Using this value of K, the values of PD and TJ can be obtained by solving equations 1 and 2 iteratively for any
value of TA.
2.4
Electrostatic Discharge (ESD) Protection Characteristics
Although damage from static discharge is much less common on these devices than on early CMOS circuits, normal handling
precautions should be used to avoid exposure to static discharge. Qualification tests are performed to ensure that these devices
can withstand exposure to reasonable levels of static without suffering any permanent damage.
All ESD testing is in conformity with CDF-AEC-Q00 Stress Test Qualification for Automotive Grade Integrated Circuits.
(http://www.aecouncil.com/) This device was qualified to AEC-Q100 Rev E.
A device is considered to have failed if, after exposure to ESD pulses, the device no longer meets the device specification
requirements. Complete DC parametric and functional testing is performed per the applicable device specification at room
temperature followed by hot temperature, unless specified otherwise in the device specification.
Table 8. ESD and Latch-up Test Conditions
Model
Human Body
Description
Symbol
Value
Unit
Series Resistance
R1
1500
Ω
Storage Capacitance
C
100
pF
Number of Pulse per pin
–
3
Minimum input voltage limit
–2.5
V
Maximum input voltage limit
7.5
V
Latch-up
MCF51JM128 ColdFire Microcontroller, Rev. 2
Freescale Semiconductor
17
Preliminary Electrical Characteristics
Table 9. ESD and Latch-Up Protection Characteristics
Num
2.5
Rating
Symbol
Min
Max
Unit
1
Human Body Model (HBM)
VHBM
+/– 2000
—
V
2
Charge Device Model (CDM)
VCDM
+/– 500
—
V
3
Latch-up Current at TA = 105°C
ILAT
+/– 100
—
mA
DC Characteristics
This section includes information about power supply requirements, I/O pin characteristics, and power supply current in various
operating modes.
Table 10. DC Characteristics
Num C
Parameter
Symbol
Operating voltage2
1
Output high voltage — Low Drive (PTxDSn = 0)
5 V, ILoad = –4 mA
3 V, ILoad = –2 mA
5 V, ILoad = –2 mA
3 V, ILoad = –1 mA
2
P
Output high voltage — High Drive (PTxDSn = 1)
5 V, ILoad = –15 mA
3 V, ILoad = –8 mA
5 V, ILoad = –8 mA
3 V, ILoad = –4 mA
Min
Typ1
Max
Unit
2.7
—
5.5
V
VDD – 1.5
VDD – 1.5
VDD – 0.8
VDD – 0.8
—
—
—
—
—
—
—
—
VOH
V
VDD – 1.5
VDD – 1.5
VDD – 0.8
VDD – 0.8
Output low voltage — Low Drive (PTxDSn = 0)
5 V, ILoad = 4mA
3 V, ILoad = 2 mA
5 V, ILoad = 2 mA
3 V, ILoad = 1 mA
3
P
5
—
—
—
—
—
—
—
—
1.5
1.5
0.8
0.8
VOL
V
Output low voltage — High Drive (PTxDSn = 1)
5 V, ILoad = 15 mA
3 V, ILoad = 8 mA
5 V, ILoad = 8 mA
3 V, ILoad = 4 mA
4
—
—
—
—
P Output high current — Max total IOH for all ports
5V
3V
—
—
—
—
1.5
1.5
0.8
0.8
IOHT
—
—
—
—
100
60
mA
IOLT
—
—
—
—
100
60
mA
P Output low current — Max total IOL for all ports
5V
3V
MCF51JM128 ColdFire Microcontroller, Rev. 2
18
Freescale Semiconductor
Preliminary Electrical Characteristics
Table 10. DC Characteristics (continued)
Num C
6
Parameter
Symbol
Typ1
3.25
—
VIH
2.10
VDD = 3V
V
1.75
—
—
P Input hysteresis; all digital inputs
P Input leakage current; input only
V
1.05
VDD = 3V
10
—
P Input low voltage; all digital inputs
VIL
9
Unit
—
VDD = 5V
8
Max
P Input high voltage; all digital inputs
VDD = 5V
7
Min
pins3
P High Impedance (off-state) leakage current
3
4
Vhys
0.06 x VDD
|IIn|
—
0.1
1
μA
|IOZ|
—
0.1
1
μA
mV
11
P Internal pullup resistors
RPU
20
45
65
kΩ
12
P Internal pulldown resistors5
RPD
20
45
65
kΩ
900
1425
1300
2400
1575
3090
CIn
—
—
8
pF
13
Internal pullup resistor to USBDP (to VUSB33)
Idle RPUPD
Transmit
kΩ
14
C Input Capacitance; all non-supply pins
15
P POR rearm voltage
VPOR
0.9
1.4
2.0
V
16
D POR rearm time
tPOR
10
—
—
μs
MCF51JM128 ColdFire Microcontroller, Rev. 2
Freescale Semiconductor
19
Preliminary Electrical Characteristics
Table 10. DC Characteristics (continued)
Num C
17
18
19
20
21
P
P
C
P
P
22
C
23
T
Parameter
Symbol
Min
Typ1
Max
VLVD1
Low-voltage detection threshold —
high range
VDD falling
VDD rising
Low-voltage detection threshold —
low range
V
3.9
4.0
4.0
4.1
4.1
4.2
VLVD0
VDD falling
VDD rising
Low-voltage warning threshold —
high range 1
V
2.48
2.54
2.56
2.62
2.64
2.70
VLVW3
VDD falling
VDD rising
Low-voltage warning threshold —
high range 0
V
4.5
4.6
4.6
4.7
4.7
4.8
VLVW2
VDD falling
VDD rising
Low-voltage warning threshold
low range 1
V
4.2
4.3
4.3
4.4
4.4
4.5
VLVW1
VDD falling
VDD rising
Low-voltage warning threshold —
low range 0
V
2.84
2.90
2.92
2.98
3.00
3.06
V
VLVW0
VDD falling
VDD rising
Low-voltage inhibit reset/recover hysteresis
2.66
2.72
2.74
2.80
2.82
2.88
—
—
100
60
—
—
Vhys
5V
3V
Unit
mV
1
Typical values are based on characterization data at 25°C unless otherwise stated.
Operating voltage with USB enabled can be found in Section 2.14, “USB Electricals.”
3 Measured with V = V
In
DD or VSS.
4 Measured with V = V .
In
SS
5
Measured with VIn = VDD.
2
MCF51JM128 ColdFire Microcontroller, Rev. 2
20
Freescale Semiconductor
Preliminary Electrical Characteristics
Typical VOL vs. IOL AT VDD = 5V
1.40
Hot (105°C)
0.70
Room (25°C)
0.60
Cold (-40°C)
0.50
VOL (v)
VOL (v)
0.80
Typical V OL vs. IOL AT V DD = 3V
0.40
0.30
Hot (105°C)
1.20
Room (25°C)
1.00
Cold (-40°C)
0.80
0.60
0.40
0.20
0.20
0.10
0.00
0.00
0
1
2
3
4
5
6
7
8
9
0
10 11 12 13 14 15
1
2
3
4
5
6
7
8
9
10
11
12
13
IOL (mA)
IOL (mA)
Figure 5. Typical Low-side Drive (sink) characteristics – High Drive (PTxDSn = 1)
Typical VOL vs. IOL AT VDD = 5V
0.90
Typical VOL vs. IOL AT VDD = 3V
0.90
Hot (105°C)
0.80
0.70
Room (25°C)
0.70
Cold (-40°C)
Cold (-40°C)
0.60
VOL (v)
0.60
VOL (v)
Hot (105°C)
0.80
Room (25°C)
0.50
0.40
0.50
0.40
0.30
0.30
0.20
0.20
0.10
0.10
0.00
0.00
0
1
2
3
4
0
5
1
2
3
IOL (mA)
IOL (mA)
Figure 6. Typical Low-side Drive (sink) characteristics – Low Drive (PTxDSn = 0)
Typical VDD - VOH vs. IOH AT VDD = 5V
0.6
1.2
Hot (105°C)
Hot (105°C)
1.0
Room (25°C)
VDD - VOH (v)
V DD - VOH (v)
0.8
Typical VDD - VOH vs. IOH AT VDD=3V
Cold (-40°C)
0.4
0.2
Room (25°C)
Cold (-40°C)
0.8
0.6
0.4
0.2
0.0
0 -1 -2 -3 -4 -5 -6 -7 -8 -9 -10 -11 -12 -13 -14 -15
IOH (mA)
0.0
0
-1
-2
-3
-4
-5
-6
-7
IOH (mA)
-8
-9 -10 -11 -12 -13
Figure 7. Typical High-side Drive (source) characteristics – High Drive (PTxDSn = 1)
MCF51JM128 ColdFire Microcontroller, Rev. 2
Freescale Semiconductor
21
Preliminary Electrical Characteristics
Typical VDD - VOH vs. IOH AT VDD=3V
Typical VDD - VOH vs. IOH AT VDD = 5V
1.2
1.2
VDD - VOH (v)
Cold (-40°C)
0.8
Room (25°C)
1.0
Room (25°C)
1.0
V DD - VOH (v)
Hot (105°C)
Hot (105°C)
0.6
0.4
Cold (-40°C)
0.8
0.6
0.4
0.2
0.2
0.0
0.0
0
-1
-2
-3
-4
-5
0
-1
IOH (mA)
IOH (mA)
-2
-3
Figure 8. Typical High-side Drive (source) characteristics – Low Drive (PTxDSn = 0)
2.6
Supply Current Characteristics
Table 11. Supply Current Characteristics
Num
C
1
C
2
3
3
P
C
P
Parameter
Run supply current3 measured at
2 MHz, fBus = 1 MHz)
Symbol
(CPU clock =
RIDD
Run supply current3 measured at
16 MHz, fBus = 8 MHz)
(CPU clock =
Run supply current3 measured at
48 MHz, fBus = 24 MHz)
(CPU clock =
RIDD
RIDD
VDD (V)
Typical1
Max2
5
3.6
7
3
3.6
7
5
22
30
3
21.7
30
5
60
70
3
59
70
5
0.80
3
3
20
μA
3
3
20
μA
Unit
mA
mA
mA
Stop2 mode supply current
–40 °C
25 °C
105 °C
S2IDD
5
P
–40 °C
25 °C
105 °C
3
0.80
–40 °C
25 °C
105 °C
5
0.90
3
3
20
μA
3
0.90
3
3
20
μA
5
300
nA
3
300
nA
Stop3 mode supply current
–40 °C
25 °C
105 °C
6
P
RTC adder to stop2 or stop34, 25°C
S3IDD
MCF51JM128 ColdFire Microcontroller, Rev. 2
22
Freescale Semiconductor
Preliminary Electrical Characteristics
Table 11. Supply Current Characteristics
Num
C
7
P
8
Parameter
Symbol
VDD (V)
Typical1
5
110
μA
3
90
μA
5
5
μA
3
5
μA
LVD adder to stop3 (LVDE = LVDSE = 1)
5
P
Adder to stop3 for oscillator enabled
(ERCLKEN =1 and EREFSTEN = 1)
Max2
Unit
1
Typicals are measured at 25°C.
Values given here are preliminary estimates prior to completing characterization.
3
All modules’ clocks are switched on, code runs from flash, in FEI mode, and there are no DC loads on port pins.
4
Most customers are expected to find that auto-wakeup from stop2 or stop3 can be used instead of the higher current wait mode.
5
Values given under the following conditions: low range operation (RANGE = 0), low power mode (HGO = 0)
2
2.7
Analog Comparator (ACMP) Electricals
Table 12. Analog Comparator Electrical Specifications
Num
C
Rating
Symbol
Min
Typical
Max
Unit
VDD
2.7
—
5.5
V
1
Supply voltage
2
Supply current (active)
IDDAC
—
20
35
μA
3
Analog input voltage
VAIN
VSS – 0.3
—
VDD
V
4
Analog input offset voltage
VAIO
20
40
mV
5
Analog Comparator hysteresis
6
VH
3.0
6.0
20.0
mV
Analog input leakage current
IALKG
--
--
1.0
μA
7
Analog Comparator initialization delay
tAINIT
—
—
1.0
μs
8
Bandgap Voltage Reference
Factory trimmed at VDD = 3.0 V, Temp = 25°C
VBG
1.19
1.20
1.21
V
2.8
ADC Characteristics
Table 13. 5 Volt 12-bit ADC Operating Conditions
Characteristic
Conditions
Symb
Min
Typ1
Max
Unit
VDDAD
2.7
—
5.5
V
2
Delta to VDD (VDD-VDDAD)
ΔVDDAD
–100
0
+100
mV
2
ΔVSSAD
–100
0
+100
mV
Ref Voltage High
VREFH
2.7
VDDAD
VDDAD
V
Ref Voltage Low
VREFL
VSSAD
VSSAD
VSSAD
V
Input Voltage
VADIN
VREFL
—
VREFH
V
Input
Capacitance
CADIN
—
4.5
5.5
pF
Supply voltage
Ground voltage
Absolute
Delta to VSS (VSS-VSSAD)
Comment
MCF51JM128 ColdFire Microcontroller, Rev. 2
Freescale Semiconductor
23
Preliminary Electrical Characteristics
Table 13. 5 Volt 12-bit ADC Operating Conditions (continued)
Symb
Min
Typ1
Max
Unit
RADIN
—
3
5
kΩ
—
—
—
—
2
5
10 bit mode
fADCK > 4MHz
fADCK < 4MHz
—
—
—
—
5
10
8 bit mode (all valid fADCK)
—
—
10
0.4
—
8.0
0.4
—
4.0
Characteristic
Conditions
Input Resistance
Analog Source
Resistance
RAS
12 bit mode
fADCK > 4MHz
fADCK < 4MHz
ADC Conversion High Speed (ADLPC=0)
Clock Freq.
Low Power (ADLPC=1)
fADCK
Comment
kΩ
External to MCU
MHz
1
Typical values assume VDDAD = 5.0V, Temp = 25°C, fADCK=1.0MHz unless otherwise stated. Typical values are for reference
only and are not tested in production.
2 DC potential difference.
SIMPLIFIED
INPUT PIN EQUIVALENT
CIRCUIT
Pad
leakage
due to
input
protection
ZAS
RAS
ZADIN
SIMPLIFIED
CHANNEL SELECT
CIRCUIT
RADIN
ADC SAR
ENGINE
+
VADIN
VAS
+
–
CAS
–
RADIN
INPUT PIN
INPUT PIN
RADIN
RADIN
INPUT PIN
CADIN
Figure 9. ADC Input Impedance Equivalency Diagram
MCF51JM128 ColdFire Microcontroller, Rev. 2
24
Freescale Semiconductor
Preliminary Electrical Characteristics
Table 14. 5 Volt 12-bit ADC Characteristics (VREFH = VDDAD, VREFL = VSSAD)
C
Symb
Min
Typ1
Max
Unit
Supply
CurrentADLPC=
1ADLSMP=1AD
CO=1
T
IDDAD
—
133
—
μA
Supply
CurrentADLPC=
1ADLSMP=0AD
CO=1
T
IDDAD
—
218
—
μA
Supply
CurrentADLPC=
0ADLSMP=1AD
CO=1
T
IDDAD
—
327
—
μA
Supply
CurrentADLPC=
0ADLSMP=0AD
CO=1
P
IDDAD
—
0.582
1
mA
IDDAD
—
0.011
1
μA
fADACK
2
3.3
5
MHz
1.25
2
3.3
tADACK =
1/fADACK
—
20
—
—
40
—
ADCK
cycles
See Table 9 for
conversion time
variances
—
3.5
—
—
23.5
—
—
±3.0
—
P
—
±1
±2.5
8 bit mode
T
—
±0.5
±1.0
12 bit mode
T
—
±1.75
—
10 bit mode3
Characteristic
Conditions
Supply Current
Stop, Reset, Module Off
ADC
Asynchronous
Clock Source
High Speed (ADLPC=0)
T
Low Power (ADLPC=1)
Conversion Time Short Sample (ADLSMP=0)
(Including
Long Sample (ADLSMP=1)
sample time)
T
Sample Time
T
Short Sample (ADLSMP=0)
tADC
tADS
Long Sample (ADLSMP=1)
Total Unadjusted 12 bit mode
Error
10 bit mode
Differential
Non-Linearity
ETUE
DNL
P
—
±0.5
±1.0
mode3
T
—
±0.3
±0.5
12 bit mode
T
—
±1.5
—
10 bit mode
T
—
±0.5
±1.0
8 bit mode
T
—
±0.3
±0.5
—
±1.5
—
8 bit
Integral
Non-Linearity
T
INL
Zero-Scale Error 12 bit mode
T
10 bit mode
P
—
±0.5
±1.5
8 bit mode
T
—
±0.5
±0.5
12 bit mode
T
—
±1
—
10 bit mode
T
—
±0.5
±1
8 bit mode
T
—
±0.5
±0.5
Full-Scale Error
EZS
EFS
Comment
ADCK
cycles
LSB2
Includes
quantization
LSB2
LSB2
LSB2
VADIN = VSSAD
LSB2
VADIN = VDDAD
MCF51JM128 ColdFire Microcontroller, Rev. 2
Freescale Semiconductor
25
Preliminary Electrical Characteristics
Table 14. 5 Volt 12-bit ADC Characteristics (VREFH = VDDAD, VREFL = VSSAD) (continued)
Characteristic
Quantization
Error
Input Leakage
Error
C
Symb
Min
Typ1
Max
Unit
D
EQ
—
-1 to 0
—
LSB2
10 bit mode
—
—
±0.5
8 bit mode
—
—
±0.5
—
±1
—
10 bit mode
—
±0.2
±2.5
8 bit mode
—
±0.1
±1
Conditions
12 bit mode
12 bit mode
D
EIL
LSB2
Comment
Pad leakage4 *
RAS
1
Typical values assume VDDAD = 5.0V, Temp = 25°C, fADCK=1.0MHz unless otherwise stated. Typical values are for reference
only and are not tested in production.
2
1 LSB = (VREFH - VREFL)/2N
3
Monotonicity and No-Missing-Codes guaranteed in 10 bit and 8 bit modes
4 Based on input pad leakage current. Refer to pad electricals.
MCF51JM128 ColdFire Microcontroller, Rev. 2
26
Freescale Semiconductor
Preliminary Electrical Characteristics
2.9
External Oscillator (XOSC) Characteristics
Table 15. Oscillator Electrical Specifications (Temperature Range = –40 to 105°C Ambient)
Num
C
Rating
Symbol
Min
Typ1
Max
Unit
flo
32
1
1
1
1
—
—
—
—
—
38.4
5
16
16
8
kHz
MHz
MHz
MHz
MHz
1
Oscillator crystal or resonator (EREFS = 1, ERCLKEN = 1)
• Low range (RANGE = 0)
• High range (RANGE = 1) FEE or FBE mode 2
• High range (RANGE = 1) PEE or PBE mode 3
• High range (RANGE = 1, HGO = 1) BLPE mode
• High range (RANGE = 1, HGO = 0) BLPE mode
2
Load capacitors
C1
C2
3
Feedback resistor
• Low range (32 kHz to 38.4 kHz)
• High range (1 MHz to 16 MHz)
RF
fhi-fll
fhi-pll
fhi-hgo
fhi-lp
See crystal or resonator
manufacturer’s recommendation.
10
1
MΩ
MΩ
Series resistor
• Low range, low gain (RANGE = 0, HGO = 0)
• Low range, high gain (RANGE = 0, HGO = 1)
4
—
≥ 8 MHz
4 MHz
1 MHz
RS
• High range, low gain (RANGE = 1, HGO = 0)
• High range, high gain (RANGE = 1, HGO = 1)
≥ 8 MHz
4 MHz
1 MHz
5
6
Crystal start-up time 4
• Low range, low gain (RANGE = 0, HGO = 0)
T • Low range, high gain (RANGE = 0, HGO = 1)
• High range, low gain (RANGE = 1, HG0 = 0)5
• High range, high gain (RANGE = 1, HG0 = 1)5
Square wave input clock frequency (EREFS = 0, ERCLKEN = 1)
• FEE or FBE mode 2
T
• PEE or PBE mode 3
• BLPE mode
t
CSTL-LP
t
CSTL-HGO
t
CSTH-LP
t
CSTH-HGO
fextal
—
—
—
0
100
0
—
—
—
—
—
—
0
0
0
0
10
20
—
—
—
—
200
400
5
15
—
—
—
—
ms
0.03125
1
0
—
—
—
5
16
40
MHz
MHz
MHz
kΩ
1
Data in Typical column was characterized at 3.0 V, 25°C or is typical recommended value.
When MCG is configured for FEE or FBE mode, input clock source must be divisible using RDIV to within the range of 31.25 kHz
to 39.0625 kHz.
3
When MCG is configured for PEE or PBE mode, input clock source must be divisible using RDIV to within the range of 1 MHz
to 2 MHz.
4
This parameter is characterized and not tested on each device. Proper PC board-layout procedures must be followed to achieve
specifications.
5
4 MHz crystal
2
MCF51JM128 ColdFire Microcontroller, Rev. 2
Freescale Semiconductor
27
Preliminary Electrical Characteristics
2.10
MCG Specifications
Table 16. MCG Frequency Specifications (Temperature Range = –40 to 125°C Ambient)
Num C
Rating
Symbol
Min
Typical
Max
Unit
1
Internal reference frequency - factory
P trimmed at VDD = 5 V and temperature
= 25 °C
fint_ft
—
31.25
—
kHz
2
P
Average internal reference frequency untrimmed 1
fint_ut
25
32.7
41.66
kHz
3
P
Average internal reference frequency user trimmed
fint_t
31.25
—
39.0625
kHz
4
D Internal reference startup time
tirefst
—
60
100
us
5
DCO output frequency range untrimmed 1
—
value provided for reference: fdco_ut =
1024 X fint_ut
fdco_ut
25.6
33.48
42.66
MHz
6
P DCO output frequency range - trimmed
fdco_t
32
—
40
MHz
7
Resolution of trimmed DCO output
C frequency at fixed voltage and
temperature (using FTRIM)
Δfdco_res_t
—
± 0.1
± 0.2
%fdco
8
Resolution of trimmed DCO output
C frequency at fixed voltage and
temperature (not using FTRIM)
Δfdco_res_t
—
± 0.2
± 0.4
%fdco
9
Total deviation of trimmed DCO output
P frequency over voltage and
temperature
Δfdco_t
—
+ 0.5
-1.0
±2
%fdco
10
Total deviation of trimmed DCO output
C frequency over fixed voltage and
temperature range of 0 - 70 °C
Δfdco_t
—
± 0.5
±1
%fdco
11
C FLL acquisition time 2
tfll_acquire
—
—
1
ms
12
D PLL acquisition time 3
tpll_acquire
—
—
1
ms
13
C
CJitter
—
0.02
0.2
%fdco
14
D VCO operating frequency
fvco
7.0
—
55.0
MHz
17
T
fpll_jitter_625ns
—
0.5665
—
%fpll
18
D Lock entry frequency tolerance 6
Dlock
± 1.49
—
± 2.98
%
Long term Jitter of DCO output clock
(averaged over 2ms interval) 4
Jitter of PLL output clock measured
over 625 ns5
MCF51JM128 ColdFire Microcontroller, Rev. 2
28
Freescale Semiconductor
Preliminary Electrical Characteristics
Table 16. MCG Frequency Specifications (continued)(Temperature Range = –40 to 125°C Ambient)
Num C
Rating
Symbol
Min
Typical
Max
Unit
Dunl
± 4.47
—
± 5.97
%
1075(1/fint_t
)
19
D Lock exit frequency tolerance 7
20
D Lock time - FLL
tfll_lock
—
—
21
D Lock time - PLL
tpll_lock
—
—
tfll_acquire+
tpll_acquire+
1075(1/fpll_r
s
s
ef)
Loss of external clock minimum
D frequency - RANGE = 0
22
1
2
3
4
5
6
7
(3/5) x fint
floc_low
—
—
kHz
TRIM register at default value (0x80) and FTRIM control bit at default value (0x0).
This specification applies to any time the FLL reference source or reference divider is changed, trim value changed or changing
from FLL disabled (BLPE, BLPI) to FLL enabled (FEI, FEE, FBE, FBI). If a crystal/resonator is being used as the reference,
this specification assumes it is already running.
This specification applies to any time the PLL VCO divider or reference divider is changed, or changing from PLL disabled
(BLPE, BLPI) to PLL enabled (PBE, PEE). If a crystal/resonator is being used as the reference, this specification assumes it is
already running.
Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum fBUS.
Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise
injected into the FLL circuitry via VDD and VSS and variation in crystal oscillator frequency increase the CJitter percentage for a
given interval.
625 ns represents 5 time quanta for CAN applications, under worst case conditions of 8 MHz CAN bus clock, 1 Mbps CAN bus
speed, and 8 time quanta per bit for bit time settings. 5 time quanta is the minimum time between a synchronization edge and
the sample point of a bit using 8 time quanta per bit.
Below Dlock minimum, the MCG is guaranteed to enter lock. Above Dlock maximum, the MCG does not enter lock. But if the
MCG is already in lock, then the MCG may stay in lock.
Below Dunl minimum, the MCG does not exit lock if already in lock. Above Dunl maximum, the MCG is guaranteed to exit lock.
2.11
AC Characteristics
This section describes ac timing characteristics for each peripheral system.
2.11.1
Control Timing
Table 17. Control Timing
Num
C
Parameter
Symbol
Min
Typ1
Max
Unit
—
24
MHz
1
Bus frequency (tcyc = 1/fBus)
fBus
dc
2
Internal low-power oscillator period
tLPO
700
1300
μs
3
External reset pulse width2
(tcyc = 1/fSelf_reset)
textrst
100
—
ns
4
Reset low drive
trstdrv
66 x tcyc
—
ns
5
Active background debug mode latch setup time
tMSSU
500
—
ns
MCF51JM128 ColdFire Microcontroller, Rev. 2
Freescale Semiconductor
29
Preliminary Electrical Characteristics
Table 17. Control Timing
Num
C
Parameter
Symbol
Min
tMSH
100
Typ1
Max
Unit
—
ns
6
Active background debug mode latch hold time
7
IRQ pulse width
Asynchronous path2
Synchronous path3
tILIH, tIHIL
100
1.5 x tcyc
—
—
ns
KBIPx pulse width
Asynchronous path2
Synchronous path3
tILIH, tIHIL
100
1.5 x tcyc
—
—
ns
Port rise and fall time (load = 50 pF)4
Slew rate control disabled (PTxSE = 0)
Slew rate control enabled (PTxSE = 1)
tRise, tFall
—
—
3
30
8
9
ns
1
Typical values are based on characterization data at VDD = 5.0V, 25°C unless otherwise stated.
This is the shortest pulse guaranteed to be recognized as a reset pin request. Shorter pulses are not guaranteed to override
reset requests from internal sources.
3 This is the minimum pulse width guaranteed to pass through the pin synchronization circuitry. Shorter pulses may or may not
be recognized. In stop mode, the synchronizer is bypassed so shorter pulses can be recognized in that case.
4 Timing is shown with respect to 20% V
DD and 80% VDD levels. Temperature range –40°C to 105°C.
2
textrst
RESET PIN
Figure 10. Reset Timing
tIHIL
IRQ/KBIPx
IRQ/KBIPx
tILIH
Figure 11. IRQ/KBIPx Timing
2.11.2
Timer/PWM (TPM) Module Timing
Synchronizer circuits determine the shortest input pulses that can be recognized or the fastest clock that can be used as the
optional external source to the timer counter. These synchronizers operate from the current bus rate clock.
MCF51JM128 ColdFire Microcontroller, Rev. 2
30
Freescale Semiconductor
Preliminary Electrical Characteristics
Table 18. TPM Input Timing
NUM
C
Function
Symbol
Min
Max
Unit
1
—
External clock frequency
fTPMext
dc
fBus/4
MHz
2
—
External clock period
tTPMext
4
—
tcyc
3
D
External clock high time
tclkh
1.5
—
tcyc
4
D
External clock low time
tclkl
1.5
—
tcyc
5
D
Input capture pulse width
tICPW
1.5
—
tcyc
tTPMext
tclkh
TPMxCLK
tclkl
Figure 12. Timer External Clock
tICPW
TPMxCHn
TPMxCHn
tICPW
Figure 13. Timer Input Capture Pulse
2.11.3
MSCAN
Table 19. MSCAN Wake-up Pulse Characteristics
1
Num
C
Parameter
Symbol
1
D
MSCAN Wake-up dominant pulse filtered
tWUP
2
D
MSCAN Wake-up dominant pulse pass
tWUP
Min
Typ1
5
Max
Unit
2
μs
5
μs
Typical values are based on characterization data at VDD = 5.0V, 25°C unless otherwise stated.
MCF51JM128 ColdFire Microcontroller, Rev. 2
Freescale Semiconductor
31
Preliminary Electrical Characteristics
2.12
SPI Characteristics
Table 20 and Figure 14 through Figure 17 describe the timing requirements for the SPI system.
Table 20. SPI Electrical Characteristic
Num1
C
1
D
2
3
4
5
6
7
8
D
D
D
D
D
D
D
Characteristic2
Symbol
Min
Max
Unit
Master
Slave
fop
fop
fBus/2048dc
fBus/2
fBus/4
Hz
Master
Slave
tSCK
tSCK
2
4
2048
tcyc
tcyc
Master
Slave
tLead
tLead
—
1/2
1/2
—
tSCKtS
Master
Slave
tLag
tLag
—
1/2
1/2
—
tSCKtS
Clock (SPSCK) high time Master and
Slave
tSCKH
1/2 tSCK – 25
—
ns
Clock (SPSCK) low time Master and
Slave
tSCKL
1/2 tSCK – 25
—
ns
Master
Slave
tSI(M)
tSI(S)
30
30
—
—
ns
ns
Master
Slave
tHI(M)
tHI(S)
30
30
—
—
ns
ns
Operating frequency
Cycle time
Enable lead time
Enable lag time
—
CK
CK
Data setup time (inputs)
Data hold time (inputs)
9
D
Access time, slave3
tA
0
40
ns
10
D
Disable time, slave4
tdis
—
40
ns
11
D
Data setup time (outputs)
Master
Slave
tSO
tSO
25
25
—
—
ns
ns
Master
Slave
tHO
tHO
–10
–10
—
—
ns
ns
12
D
Data hold time (outputs)
1
Refer to Figure 14 through Figure 17.
All timing is shown with respect to 20% VDD and 70% VDD, unless noted; 100 pF load on all SPI pins. All
timing assumes slew rate control disabled and high drive strength enabled for SPI output pins.
3 Time to data active from high-impedance state.
4
Hold time to high-impedance state.
2
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Freescale Semiconductor
Preliminary Electrical Characteristics
SS1
(OUTPUT)
3
1
2
SCK
(CPOL = 0)
(OUTPUT)
5
4
SCK
(CPOL = 1)
(OUTPUT)
5
4
6
MISO
(INPUT)
7
MSB IN2
BIT 6 . . . 1
10
MOSI
(OUTPUT)
LSB IN
11
10
MSB OUT2
BIT 6 . . . 1
LSB OUT
NOTES:
1. SS output mode (MODFEN = 1, SSOE = 1).
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
Figure 14. SPI Master Timing (CPHA = 0)
SS(1)
(OUTPUT)
1
3
2
SCK
(CPOL = 0)
(OUTPUT)
5
4
SCK
(CPOL = 1)
(OUTPUT)
5
4
6
MISO
(INPUT)
7
MSB IN(2)
LSB IN
11
10
MOSI
(OUTPUT)
BIT 6 . . . 1
MSB OUT(2)
BIT 6 . . . 1
LSB OUT
NOTES:
1. SS output mode (MODFEN = 1, SSOE = 1).
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
Figure 15. SPI Master Timing (CPHA = 1)
MCF51JM128 ColdFire Microcontroller, Rev. 2
Freescale Semiconductor
33
Preliminary Electrical Characteristics
SS
(INPUT)
3
2
SCK
(CPOL = 0)
(INPUT)
5
4
2
SCK
(CPOL = 1)
(INPUT)
5
4
8
MISO
(OUTPUT)
12
11
BIT 6 . . . 1
MSB OUT
SLAVE
SEE
NOTE
SLAVE LSB OUT
7
6
MOSI
(INPUT)
9
BIT 6 . . . 1
MSB IN
LSB IN
NOTE:
1. Not defined but normally MSB of character received
Figure 16. SPI Slave Timing (CPHA = 0)
SS
(INPUT)
3
2
2
SCK
(CPOL = 0)
(INPUT)
5
4
SCK
(CPOL = 1)
(INPUT)
5
4
11
MISO
(OUTPUT)
SEE
NOTE
8
MOSI
(INPUT)
SLAVE
12
MSB OUT
6
BIT 6 . . . 1
9
SLAVE LSB OUT
7
MSB IN
BIT 6 . . . 1
LSB IN
NOTE:
1. Not defined but normally LSB of character received
Figure 17. SPI Slave Timing (CPHA = 1)
MCF51JM128 ColdFire Microcontroller, Rev. 2
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Freescale Semiconductor
Preliminary Electrical Characteristics
2.13
Flash Specifications
This section provides details about program/erase times and program-erase endurance for the Flash memory.
Program and erase operations do not require any special power sources other than the normal VDD supply.
Table 21. Flash Characteristics
Num
C
Characteristic
Symbol
Min
Typ1
Max
Unit
1
Supply voltage for program/erase
Vprog/erase
2.7
5.5
V
2
Supply voltage for read operation
VRead
2.7
5.5
V
3
Internal FCLK frequency2
fFCLK
150
200
kHz
4
Internal FCLK period (1/FCLK)
tFcyc
5
6.67
μs
5
Byte program time (random location)(2)
tprog
9
tFcyc
6
Byte program time (burst mode)(2)
tBurst
4
tFcyc
7
Page erase time3
tPage
4000
tFcyc
8
Mass erase time(2)
tMass
20,000
tFcyc
9
10
C
Program/erase endurance4
TL to TH = –40°C to + 105°C
T = 25°C
Data retention5
tD_ret
10,000
—
—
100,000
—
—
cycles
15
100
—
years
1
Typical values are based on characterization data at VDD = 5.0 V, 25°C unless otherwise stated.
The frequency of this clock is controlled by a software setting.
3
These values are hardware state machine controlled. User code does not need to count cycles. This information
supplied for calculating approximate time to program and erase.
4 Typical endurance for Flash was evaluated for this product family on the 9S12Dx64. For additional information on
how Freescale Semiconductor defines typical endurance, please refer to Engineering Bulletin EB619/D, Typical
Endurance for Nonvolatile Memory.
5 Typical data retention values are based on intrinsic capability of the technology measured at high temperature and
de-rated to 25°C using the Arrhenius equation. For additional information on how Freescale Semiconductor defines
typical data retention, please refer to Engineering Bulletin EB618/D, Typical Data Retention for Nonvolatile Memory.
2
2.14
USB Electricals
The USB electricals for the USBOTG module conform to the standards documented by the Universal Serial Bus Implementers
Forum. For the most up-to-date standards, visit http://www.usb.org.
If the Freescale USBOTG implementation requires additional or deviant electrical characteristics, this space would be used to
communicate that information.
MCF51JM128 ColdFire Microcontroller, Rev. 2
Freescale Semiconductor
35
Preliminary Electrical Characteristics
Table 22. Internal USB 3.3V Voltage Regulator Characteristics
Symbol
Unit
Min
Typ
Max
Regulator operating voltage
Vregin
V
3.9
—
5.5
Vreg output
Vregout
V
3
3.3
3.6
Vusb33 input with internal Vreg
disabled
Vusb33in
V
3
3.3
3.6
IVRQ
mA
—
0.5
—
VREG Quiescent Current
2.15
EMC Performance
Electromagnetic compatibility (EMC) performance is highly dependant on the environment in which the MCU resides. Board
design and layout, circuit topology choices, location and characteristics of external components as well as MCU software
operation all play a significant role in EMC performance. The system designer should consult Freescale applications notes such
as AN2321, AN1050, AN1263, AN2764, and AN1259 for advice and guidance specifically targeted at optimizing EMC
performance.
2.15.1
Radiated Emissions
Microcontroller radiated RF emissions are measured from 150 kHz to 1 GHz using the TEM/GTEM Cell method in accordance
with the IEC 61967-2 and SAE J1752/3 standards. The measurement is performed with the microcontroller installed on a
custom EMC evaluation board while running specialized EMC test software. The radiated emissions from the microcontroller
are measured in a TEM cell in two package orientations (North and East). For more detailed information concerning the
evaluation results, conditions and setup, please refer to the EMC Evaluation Report for this device.
MCF51JM128 ColdFire Microcontroller, Rev. 2
36
Freescale Semiconductor
Mechanical Outline Drawings
3
Mechanical Outline Drawings
3.1
80-pin LQFP
MCF51JM128 ColdFire Microcontroller, Rev. 2
Freescale Semiconductor
37
Mechanical Outline Drawings
MCF51JM128 ColdFire Microcontroller, Rev. 2
38
Freescale Semiconductor
Mechanical Outline Drawings
MCF51JM128 ColdFire Microcontroller, Rev. 2
Freescale Semiconductor
39
Mechanical Outline Drawings
3.2
64-pin LQFP
MCF51JM128 ColdFire Microcontroller, Rev. 2
40
Freescale Semiconductor
Mechanical Outline Drawings
MCF51JM128 ColdFire Microcontroller, Rev. 2
Freescale Semiconductor
41
Mechanical Outline Drawings
MCF51JM128 ColdFire Microcontroller, Rev. 2
42
Freescale Semiconductor
Mechanical Outline Drawings
3.3
64-pin QFP
MCF51JM128 ColdFire Microcontroller, Rev. 2
Freescale Semiconductor
43
Mechanical Outline Drawings
MCF51JM128 ColdFire Microcontroller, Rev. 2
44
Freescale Semiconductor
Mechanical Outline Drawings
MCF51JM128 ColdFire Microcontroller, Rev. 2
Freescale Semiconductor
45
Mechanical Outline Drawings
3.4
44-pin LQFP
MCF51JM128 ColdFire Microcontroller, Rev. 2
46
Freescale Semiconductor
Mechanical Outline Drawings
MCF51JM128 ColdFire Microcontroller, Rev. 2
Freescale Semiconductor
47
Mechanical Outline Drawings
MCF51JM128 ColdFire Microcontroller, Rev. 2
48
Freescale Semiconductor
Revision History
4
Revision History
This section lists major changes between versions of the MCF51JM128 Data Sheet document.
Table 23. Changes Between Revisions
Revision
Description
1
Updated features list
Updated the figures Typical Low-side Drive (sink) characteristics – High Drive (PTxDSn = 1), Typical
Low-side Drive (sink) characteristics – Low Drive (PTxDSn = 0), and Typical High-side Drive
(source) characteristics – High Drive (PTxDSn = 1)
Added the figure Typical High-side Drive (source) characteristics – Low Drive (PTxDSn = 0)
Updated the Supply Current Characteristics table
Updated the Oscillator Electrical Specifications (Temperature Range = –40 to 105×C Ambient) table
Updated the SPI Electrical Characteristic table
Updated the DC Characteristics table
2
Updated the table Orderable Part Number Summary, DC Characteristics, and Supply Current
Characteristics
MCF51JM128 ColdFire Microcontroller, Rev. 2
Freescale Semiconductor
49
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Document Number: MCF51JM128
Rev. 2
09/2008
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