Cypress CY14C512I 512-kbit (64 k x 8) serial (i2c) nvsram with real time clock Datasheet

CY14C512I
CY14B512I, CY14E512I
2
512-Kbit (64 K × 8) Serial (I C) nvSRAM
with Real Time Clock
512-Kbit (64 K × 8) Serial (I2C) nvSRAM with Real Time Clock
Features
■
I2C access to special functions
❐ Nonvolatile STORE/RECALL
❐ 8-byte serial number
❐ Manufacturer ID and Product ID
❐ Sleep mode
■
Low power consumption
❐ Average active current of 1 mA at 3.4 MHz operation
❐ Average standby mode current of 250 µA
❐ Sleep mode current of 8 µA
■
Industry standard configurations
❐ Operating voltages:
• CY14C512I : VCC = 2.4 V to 2.6 V
• CY14B512I : VCC = 2.7 V to 3.6 V
• CY14E512I : VCC = 4.5 V to 5.5 V
❐ Industrial temperature
❐ 16-pin small outline integrated circuit (SOIC) package
❐ Restriction of hazardous substances (RoHS) compliant
■
512-Kbit nonvolatile static random access memory (nvSRAM)
❐ Internally organized as 64 K × 8
❐ STORE to QuantumTrap nonvolatile elements initiated
automatically on power-down (AutoStore) or by using I2C
command (Software STORE) or HSB pin (Hardware STORE)
❐ RECALL to SRAM initiated on power-up (Power-Up
RECALL) or by I2C command (Software RECALL)
❐ Automatic STORE on power-down with a small capacitor
■ High reliability
❐ Infinite read, write, and RECALL cycles
❐ 1 million STORE cycles to QuantumTrap
❐ Data retention: 20 years at 85 C
■ Real Time Clock (RTC)
❐ Full-featured RTC
❐ Watchdog timer
❐ Clock alarm with programmable interrupts
❐ Backup power fail indication
❐ Square wave output with programmable frequency (1 Hz,
512 Hz, 4096 Hz, 32.768 kHz)
❐ Capacitor or battery backup for RTC
❐ Backup current of 0.45 µA (typical)
2
■ High-speed I C interface
❐ Industry standard 100 kHz and 400 kHz speed
❐ Fast mode Plus 1 MHz speed
❐ High speed 3.4 MHz
❐ Zero cycle delay reads and writes
■ Write protection
❐ Hardware protection using Write Protect (WP) pin
❐ Software block protection for one-quarter, one-half, or entire
array
Logic Block Diagram
Overview
The Cypress CY14C512I/CY14B512I/CY14E512I combines a
512-Kbit nvSRAM[1] with a full-featured RTC in a monolithic
integrated circuit with serial I2C interface. The memory is
organized as 64 K words of 8 bits each. The embedded
nonvolatile elements incorporate the QuantumTrap technology,
creating the world’s most reliable nonvolatile memory. The
SRAM provides infinite read and write cycles, while the
QuantumTrap cells provide highly reliable nonvolatile storage of
data. Data transfers from SRAM to the nonvolatile elements
(STORE operation) takes place automatically at power-down.
On power-up, data is restored to the SRAM from the nonvolatile
memory (RECALL operation). The STORE and RECALL
operations can also be initiated by the user through I2C
commands.
Serial Number
8x8
VCC VCAP VRTCcap VRTCbat
Manufacture ID/
Product ID
Power Control
Block
Memory Control Register
Quantrum Trap
64 K x 8
Command Register
Sleep
SDA
SCL
A2, A1, A0
WP
Control Registers Slave
2
I C Control Logic
Slave Address
Decoder
Memory Slave
RTC Slave
X in
INT/SQW
Xout
Memory
Address and Data
Control
SRAM
64 K x 8
STORE
RECALL
RTC Control Logic
Registers
Counters
Note
1. Serial (I2C) nvSRAM will be referred to as nvSRAM throughout the datasheet.
Cypress Semiconductor Corporation
Document #: 001-64879 Rev. *B
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised May 4, 2011
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CY14C512I
CY14B512I, CY14E512I
Contents
Pinout ................................................................................ 3
Pin Definitions .................................................................. 3
I2C Interface ...................................................................... 4
Protocol Overview ............................................................ 4
I2C Protocol – Data Transfer ....................................... 4
Data Validity ...................................................................... 5
START Condition (S) ........................................................ 5
STOP Condition (P) .......................................................... 5
Repeated START (Sr) ....................................................... 5
Byte Format ....................................................................... 5
Acknowledge / No-acknowledge ..................................... 5
High-Speed Mode (Hs-mode) .......................................... 6
Serial Data Format in Hs-mode ................................... 6
Slave Device Address ...................................................... 7
Memory Slave Device ................................................. 7
RTC Registers Slave Device ....................................... 7
Control Registers Slave Device ................................... 7
Memory Control Register ............................................ 8
Command Register ..................................................... 8
Write Protection (WP) ....................................................... 9
AutoStore Operation ........................................................ 9
Hardware STORE and HSB pin Operation ..................... 9
Hardware RECALL (Power Up) ................................... 9
Write Operation ............................................................... 10
Read Operation ............................................................... 10
Memory Slave Access .................................................... 10
Write nvSRAM ........................................................... 10
Current nvSRAM Read .............................................. 12
Random Address Read ............................................. 13
RTC Registers Slave Access ......................................... 14
Write RTC Registers ................................................. 14
Current Address RTC Registers Read ...................... 15
Random Address RTC Registers Read .................... 15
Control Registers Slave ................................................. 16
Write Control Registers ............................................. 16
Current Control Registers Read ................................ 17
Random Control Registers Read .............................. 17
Serial Number ................................................................. 18
Serial Number Write .................................................. 18
Serial Number Lock ................................................... 18
Serial Number Read .................................................. 18
Device ID ......................................................................... 19
Device ID Read ......................................................... 19
Document #: 001-64879 Rev. *B
Executing Commands Using Command Register ....... 19
Real Time Clock Operation ............................................ 20
nvTIME Operation ..................................................... 20
Clock Operations ....................................................... 20
Reading the Clock ..................................................... 20
Setting the Clock ....................................................... 20
Backup Power ........................................................... 20
Stopping and Starting the Oscillator .......................... 20
Calibrating the Clock ................................................. 21
Alarm ......................................................................... 21
Watchdog Timer ........................................................ 21
Programmable Square Wave Generator ................... 22
Power Monitor ........................................................... 22
Backup Power Monitor .............................................. 22
Interrupts ................................................................... 22
Interrupt Register ....................................................... 22
Flags Register ........................................................... 23
Best Practices ................................................................. 29
Maximum Ratings ........................................................... 30
Operating Range ............................................................. 30
DC Electrical Characteristics ........................................ 30
Data Retention and Endurance ..................................... 31
Thermal Resistance ........................................................ 31
AC Test Conditions ........................................................ 32
RTC Characteristics ....................................................... 32
AC Switching Characteristics ....................................... 33
nvSRAM Specifications ................................................. 34
Software Controlled STORE/RECALL Cycles .............. 35
Hardware STORE Cycle ................................................. 36
Ordering Information ...................................................... 37
Ordering Code Definitions ......................................... 37
Package Diagram ............................................................ 38
Acronyms ........................................................................ 39
Document Conventions ................................................. 39
Units of Measure ....................................................... 39
Document History Page ................................................. 40
Sales, Solutions, and Legal Information ...................... 41
Worldwide Sales and Design Support ....................... 41
Products .................................................................... 41
PSoC Solutions ......................................................... 41
Page 2 of 41
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CY14C512I
CY14B512I, CY14E512I
Pinout
Figure 1. Pin Diagram - 16-pin SOIC
NC
1
16
VCC
VRTCbat
2
15
INT/SQW
Xout
3
14
VCAP
13
A2
Xin
4
Top View
not to scale
WP
5
12
SDA
A0
6
11
SCL
VRTCcap
7
10
A1
8
9
HSB
VSS
Pin Definitions
Pin Name
I/O Type
SCL
Input
Description
SDA
Input/Output
WP
Input
Write Protect: Protects the memory from all writes. This pin is internally pulled LOW and hence can
be left open if not connected.
A2-A0
Input
Slave Address: Defines the slave address for I2C. These pins are internally pulled LOW and hence
can be left open if not connected.
HSB
Input/Output
Hardware STORE Busy:
Output: Indicates busy status of nvSRAM when LOW. After each Hardware and Software STORE
operation HSB is driven HIGH for a short time (tHHHD) with standard output high current and then a
weak internal pull-up resistor keeps this pin HIGH (External pull-up resistor connection optional).
Input: Hardware STORE implemented by pulling this pin LOW externally.
VCAP
Power supply
AutoStore capacitor: Supplies power to the nvSRAM during power loss to STORE data from the
SRAM to nonvolatile elements. If not required, AutoStore must be disabled and this pin left as No
Connect. It must never be connected to ground.
VRTCcap
Power supply
Capacitor backup for RTC: Left unconnected if VRTCbat is used.
VRTCbat
Power supply
Battery backup for RTC: Left unconnected if VRTCcap is used.
Xout
Output
Xin
Input
INT/SQW
Output
NC
No connect
VSS
Power supply
Ground
VCC
Power supply
Power supply
Clock: Runs at speeds up to a maximum of fSCL
I/O: Input/output of data through I2C interface.
Crystal output connection
Crystal input connection
Interrupt output/calibration/square wave. Programmable to respond to the clock alarm, the watchdog
timer, and the power monitor. Also programmable to either active HIGH (push or pull) or LOW (open
drain). In Calibration mode, a 512 Hz square wave is driven out. In Square Wave mode, the user
may select a frequency of 1 Hz, 512 Hz, 4096 Hz, or 32768 Hz to be used as a continuous output.
No connect. This pin is not connected to the die.
Document #: 001-64879 Rev. *B
Page 3 of 41
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CY14C512I
CY14B512I, CY14E512I
I2C Interface
I2C bus consists of two lines – serial clock line (SCL) and serial
data line (SDA) – that carry information between multiple devices
on the bus. I2C supports multi-master and multi-slave
configurations. The data is transmitted from the transmitter to the
receiver on the SDA line and is synchronized with the clock SCL
generated by the master.
The SCL and SDA lines are open-drain lines and are pulled up
to VCC using resistors. The choice of a pull-up resistor on the
system depends on the bus capacitance and the intended speed
of operation. The master generates the clock, and all the data
I/Os are transmitted in synchronization with this clock. The
CY14X512I supports up to 3.4 MHz clock speed on SCL line.
Protocol Overview
This device supports only a 7-bit addressable scheme. The
master generates a START condition to initiate the
communication followed by broadcasting a slave select byte.
The slave select byte consists of a 7-bit slave address that the
master intends to communicate with and R/W bit indicating a
read or a write operation. The selected slave responds to this
with an acknowledgement (ACK). After a slave is selected, the
remaining part of the communication takes place between the
master and the selected slave device. The other devices on the
bus ignore the signals on the SDA line until a STOP or Repeated
START condition is detected. The data transfer is done between
the master and the selected slave device through the SDA pin
synchronized with the SCL clock generated by the master.
I2C Protocol – Data Transfer
Each transaction in I2C protocol starts with the master
generating a START condition on the bus, followed by a 7-bit
slave address and eighth bit (R/W) indicating a read (1) or a write
(0) operation. All signals are transmitted on the open-drain SDA
line and are synchronized with the clock on SCL line. Each byte
of data transmitted on the I2C bus is acknowledged by the
receiver by holding the SDA line LOW on the ninth clock pulse.
The request for write by the master is followed by the memory
address and data bytes on the SDA line. The writes can be
performed in burst-mode by sending multiple bytes of data. The
memory address increments automatically after the
receive/transmit of each byte on the falling edge of the ninth
clock cycle. The new address is latched just prior to
sending/receiving the acknowledgment bit. This allows the next
sequential byte to be accessed with no additional addressing. On
reaching the last memory location, the address rolls back to
0x0000 and writes continue. The slave responds to each byte
sent by the master during a write operation with an ACK. A write
sequence can be terminated by the master generating a STOP
or Repeated START condition.
A read request is performed at the current address location
(address next to the last location accessed for read or write). The
memory slave device responds to a read request by transmitting
the data on the current address location to the master. A random
address read may also be performed by first sending a write
request with the intended address of read. The master must
abort the write immediately after the last address byte and issue
a Repeated START or STOP signal to prevent any write
operation. The following read operation starts from this address.
The master acknowledges the receipt of one byte of data by
holding the SDA pin LOW for the ninth clock pulse. The reads
can be terminated by the master sending a no-acknowledge
(NACK) signal on the SDA line after the last data byte. The NACK
signal causes the CY14X512I to release the SDA line and the
master can then generate a STOP or a Repeated START
condition to initiate a new operation.
Figure 2. System Configuration using Serial (I2C) nvSRAM
Vcc
RPmin = (VCC - VOLmax) / IOL
RPmax = tr / Cb
SDA
Microcontroller
SCL
Vcc
Vcc
A0
SCL
A0
SCL
A0
SCL
A1
SDA
A1
SDA
A1
SDA
WP
A2
WP
A2
CY14X512I
#0
Document #: 001-64879 Rev. *B
A2
WP
CY14X512I
CY14X512I
#1
#7
Page 4 of 41
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CY14C512I
CY14B512I, CY14E512I
Data Validity
STOP Condition (P)
The data on the SDA line must be stable during the HIGH period
of the clock. The state of the data line can only change when the
clock on the SCL line is LOW for the data to be valid. There are
only two conditions under which the SDA line may change state
with SCL line held HIGH: START and STOP condition. The
START and STOP conditions are generated by the master to
signal the beginning and end of a communication sequence on
the I2C bus.
A LOW to HIGH transition on the SDA line while SCL is HIGH
indicates a STOP condition. This condition indicates the end of
the ongoing transaction.
START and STOP conditions are always generated by the
master. The bus is considered to be busy after the START
condition. The bus is considered to be free again after the STOP
condition.
Repeated START (Sr)
START Condition (S)
If a Repeated START condition is generated instead of a STOP
condition, the bus continues to be busy. The ongoing transaction
on the I2C lines is stopped and the bus waits for the master to
send a slave ID for communication to restart.
A HIGH to LOW transition on the SDA line while SCL is HIGH
indicates a START condition. Every transaction in I2C begins
with the master generating a START condition.
Figure 3. START and STOP Conditions
full pagewidth
SDA
SDA
SCL
SCL
S
P
STOP Condition
START Condition
2C
Figure 4. Data Transfer on the I
Bus
handbook, full pagewidth
P
SDA
Acknowledgement
signal from slave
MSB
SCL
S
or
Sr
1
2
START or
Repeated START
condition
7
1
9
8
Acknowledgement
signal from receiver
ACK
2
3-8
9
ACK
Byte complete,
interrupt within slave
Clock line held LOW while
interrupts are serviced
Sr
Sr
or
P
STOP or
Repeated START
condition
Byte Format
does not acknowledge the receipt of data and the operation is
aborted.
Each operation in I2C is done using 8-bit words. The bits are sent
in MSB first format on SDA line and each byte is followed by an
ACK signal by the receiver.
NACK can be generated by master during a READ operation in
following cases:
An operation continues till a NACK is sent by the receiver or
STOP or Repeated START condition is generated by the master
The SDA line must remain stable when the clock (SCL) is HIGH
except for a START or STOP condition.
Acknowledge / No-acknowledge
After transmitting one byte of data or address, the transmitter
releases the SDA line. The receiver pulls the SDA line LOW to
acknowledge the receipt of the byte. Every byte of data
transferred on the I2C bus needs a response with an ACK signal
by the receiver to continue the operation. Failing to do so is
considered as a NACK state. NACK is the state where receiver
Document #: 001-64879 Rev. *B
■
The master did not receive valid data due to noise.
■
The master generates a NACK to abort the READ sequence.
After a NACK is issued by the master, nvSRAM slave releases
control of the SDA pin and the master is free to generate a
Repeated START or STOP condition.
NACK can be generated by nvSRAM slave during a WRITE
operation in these cases:
■
nvSRAM did not receive valid data due to noise.
■
The master tries to access write protected locations on the
nvSRAM. Master must restart the communication by
generating a STOP or Repeated START condition.
Page 5 of 41
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CY14C512I
CY14B512I, CY14E512I
Figure 5. Acknowledge on the I2C Bus
handbook, full pagewidth
DATA OUTPUT
BY MASTER
Not acknowledge (A)
DATA OUTPUT
BY SLAVE
Acknowledge (A)
SCL FROM
MASTER
1
2
8
9
S
Clock pulse for
acknowledgement
START
Condition
High-Speed Mode (Hs-mode)
1. START condition (S)
2. 8-bit master code (0000 1XXXb)
3. No-acknowledge bit (A)
In Hs-mode, nvSRAM can transfer data at bit rates of up to
3.4 Mbit/s. A master code (0000 1XXXb) must be issued to place
the device in high-speed mode. This enables master/slave
communication for speeds up to 3.4 MHz. A stop condition will
exit Hs-mode.
Single and multiple-byte reads and writes are supported. After
the device enters into Hs-mode, data transfer continues in
Hs-mode until stop condition is sent by master device. The slave
switches back to F/S-mode after a STOP condition (P). To
continue data transfer in Hs-mode, the master sends Repeated
START (Sr).
Serial Data Format in Hs-mode
Serial data transfer format in Hs-mode meets the standard-mode
I2C-bus specification. Hs-mode can only commence after the
following conditions (all of which are in F/S-modes):
See Figure 13 on page 11 and Figure 16 on page 12 for Hs-mode
timings for read and write operation.
Figure 6. Data Transfer Format in Hs-mode
handbook, full pagewidth
F/S-mode
S
MASTER CODE
Hs-mode
A Sr SLAVE ADD. R/W A
F/S-mode
DATA
n (bytes+ ack.)
A/A P
Hs-mode continues
Sr SLAVE ADD.
Document #: 001-64879 Rev. *B
Page 6 of 41
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CY14C512I
CY14B512I, CY14E512I
Slave Device Address
Control Registers. The accessing mechanism is described in the
following section.
Every slave device on an I2C bus has a device select address.
The first byte after START condition contains the slave device
address with which the master intends to communicate. The
seven MSBs are the device address and the LSB (R/W bit) is
used for indicating Read or Write operation. The CY14X512I
reserves three sets of upper 4 MSBs [7:4] in the slave device
address field for accessing the Memory, RTC Registers, and
The nvSRAM product provides three different functionalities:
Memory, RTC Registers and Control Registers functions (such
as serial number and product ID). The three functions of the
device are accessed through different slave device addresses.
The first four most significant bits [7:4] in the device address
register are used to select between the nvSRAM functions.
Table 1. Slave Device Addressing
Bit 3
Bit 2
Bit 1
nvSRAM
Bit 0 Function
Select
Bit 7
Bit 6
Bit 5
Bit 4
1
0
1
0
Device select ID
R/W Selects Memory
1
1
0
1
Device select ID
R/W
CY14X512I Slave Devices
Memory, 64 K × 8
Selects RTC
Registers
RTC Registers, 16 × 8
Control Registers
- Memory Control Register, 1 × 8
0
0
1
1
Device select ID
R/W
- Serial Number, 8 × 8
Selects Control
Registers
- Device ID, 4 × 8
- Command Register, 1 × 8
Memory Slave Device
The nvSRAM device is selected for read/write if the master
issues the slave address as 1010b followed by three bits of
device select. If the slave address sent by the master matches
with the Memory Slave device address, then depending on the
R/W bit of the slave address, the data will be either read from
(R/W = ‘1’) or written to (R/W = ‘0’) the nvSRAM.
The address length for CY14X512I is 16 bits, and thus it requires
two address bytes to map the entire memory address location.
The dedicated two address bytes represent bit A0 to A15.
select. Then, depending on the R/W bit of the slave address,
data is either read from (R/W = ‘1’) or written to (R/W = ‘0’) the
RTC Registers. The RTC Registers slave address is followed by
one byte address of RTC Register for read/write operation. The
RTC Registers map is explained in the Table 10.
Figure 8. RTC Registers Slave Device Address
MSB
handbook, halfpage
1
LSB
1
0
Figure 7. Memory Slave Device Address
Slave ID
MSB
handbook, halfpage
1
LSB
0
1
0
Slave ID
A2
A1
A0 R/W
Device Select
RTC Registers Slave Device
The RTC Registers is selected for read/write if the master issues
the slave address as 1101b followed by three bits of device
Document #: 001-64879 Rev. *B
1
A2
A1
A0 R/W
Device Select
Control Registers Slave Device
The Control Registers Slave device includes the serial number,
product ID, Memory Control, and Command Register.
The nvSRAM Control Register Slave device is selected for
read/write if the master issues the slave address as 0011b
followed by three bits of device select. Then, depending on the
R/W bit of the slave address, data is either read from (R/W = ‘1’)
or written to (R/W = ‘0’) the device.
Page 7 of 41
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CY14C512I
CY14B512I, CY14E512I
■
Figure 9. Control Registers Slave Device Address
MSB
handbook, halfpage
0
LSB
0
1
A2
1
A1
A0 R/W
Device Select
Slave ID
Table 2. Control Registers Map
Address
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0xAA
Description
Memory
Control
Register
Serial Number
8 bytes
Device ID
Read/Write
Details
Read/Write Contains Block
Protect bits and Serial
Number lock bit
Read/Write Programmable Serial
(Read only Number. Locked by
when SNL setting the Serial
is set)
Number lock bit in the
Memory Control
Register to ‘1’.
Command Register
The Command Register resides at address ‘AA’ of the Control
Registers Slave device. This is a write only register. The byte
written to this register initiates a STORE, RECALL, AutoStore
Enable, AutoStore Disable, and Sleep mode operation as listed
in Table 5. The section Executing Commands Using Command
Register on page 19 explains how you can execute Command
Register bytes.
Table 5. Command Register Bytes
Read only Device ID is factory
programmed
Command
Register
Write only Allows commands for
STORE, RECALL,
AutoStore
Enable/Disable,
SLEEP Mode
■
Bit 6
SNL
(0)
Bit 5
0
Bit 4
0
Bit 3
BP1
(0)
Bit 2
BP0
(0)
Bit 1
0
Table 4. Block Protection
Level
0
1/4
1/2
1
BP1:BP0
00
01
10
11
Block Protection
None
0xC000-0xFFFF
0x8000-0xFFFF
0x0000-0xFFFF
Document #: 001-64879 Rev. *B
Description
STORE
0110 0000
RECALL
0101 1001
0001 1001
1011 1001
ASENB
ASDISB
SLEEP
STORE SRAM data to nonvolatile
memory
RECALL data from nonvolatile
memory to SRAM
Enable AutoStore
Disable AutoStore
Enter Sleep Mode for low power
consumption
■
RECALL: Initiates nvSRAM Software RECALL. The nvSRAM
cannot be accessed for tRECALL time after this instruction has
been executed. The RECALL operation does not alter the data
in the nonvolatile elements. A RECALL may be initiated in two
ways: Hardware RECALL, initiated on power-up; and Software
RECALL, initiated by a I2C RECALL instruction.
■
ASENB: Enables nvSRAM AutoStore. The nvSRAM cannot be
accessed for tSS time after this instruction has been executed.
This setting is not nonvolatile and needs to be followed by a
manual STORE sequence if this is desired to survive the power
cycle. The part comes from the factory with AutoStore Enabled.
■
ASDISB: Disables nvSRAM AutoStore. The nvSRAM cannot
be accessed for tSS time after this instruction has been
executed. This setting is not nonvolatile and needs to be
followed by a manual STORE sequence if this is desired to
survive power cycle.
Bit 0
0
BP1:BP0: Block protect bits are used to protect 1/4, 1/2 or full
memory array. These bits can be written through a write
instruction to the 0x00 location of the Control Register Slave
device. However, any STORE cycle transfers SRAM data into
a nonvolatile cell regardless of whether or not the block is
protected. The default value shipped from the factory for BP0
and BP1 is ‘0’.
Command
STORE: Initiates nvSRAM Software STORE. The nvSRAM
cannot be accessed for tSTORE time after this instruction has
been executed. When initiated, the device performs a STORE
operation regardless of whether or not a write has been
performed since the last NV operation. After the tSTORE cycle
time is completed, the SRAM is activated again for read/write
operations.
The Memory Control Register contains the following bits:
Bit 7
0
Data Byte
[7:0]
0011 1100
■
Memory Control Register
Table 3. Memory Control Register Bits
S/N Lock (SNL) Bit: Serial Number Lock bit (SNL) is used to
lock the serial number. After the bit is set to ‘1’, the serial number
registers are locked and no modification is allowed. This bit
cannot be cleared to ‘0’. The serial number is secured on the
next STORE operation (Software STORE or AutoStore). If
AutoStore is not enabled, user must perform the Software
STORE operation to secure the lock bit status. If a STORE was
not performed, the serial number lock bit will not survive the
power cycle. The default value shipped from the factory for SNL
is ‘0’.
Note If AutoStore is disabled and VCAP is not required, it is
required that the VCAP pin is left open. VCAP pin must never be
connected to ground. Power Up RECALL operation cannot be
disabled in any case.
Page 8 of 41
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CY14C512I
CY14B512I, CY14E512I
■
SLEEP: SLEEP instruction puts the nvSRAM in a sleep mode.
When the SLEEP instruction is registered, the nvSRAM
performs a STORE operation to secure the data to nonvolatile
memory and then enters into sleep mode. Whenever nvSRAM
enters into sleep mode, it initiates non volatile STORE cycle
which results in losing an endurance cycle per sleep command
execution. A STORE cycle starts only if a write to the SRAM
has been performed since the last STORE or RECALL cycle.
The nvSRAM enters into sleep mode in this manner:
1. The master sends a START command.
2. The master sends Control Registers Slave device ID with I2C
write bit set (R/W = ’0’).
3. The slave (nvSRAM) sends an ACK back to the master.
4. The master sends Command Register address (0xAA).
5. The slave (nvSRAM) sends an ACK back to the master.
6. The master sends Command Register byte for entering into
sleep mode.
7. The slave (nvSRAM) sends an ACK back to the master.
8. The master generates a STOP condition.
Once in sleep mode, the device starts consuming IZZ current
tSLEEP time after SLEEP instruction is registered. The device is
not accessible for normal operations until it is out of sleep mode.
The nvSRAM wakes up after tWAKE duration after the device
slave address is transmitted by the master.
Transmitting any of the three slave addresses wakes the
nvSRAM from sleep mode. The nvSRAM device is not
accessible during tSLEEP and tWAKE interval and any attempt to
access the nvSRAM device by the master is ignored and
nvSRAM sends NACK to the master. An alternate method of
determining when the device is ready is for the master to send
read or write commands and look for an ACK.
Write Protection (WP)
The Write Protect (WP) pin is an active HIGH pin and protects
the entire memory and all registers from write operations. To
inhibit all the write operations, this pin must be held HIGH. When
this pin is HIGH, all memory and register writes are prohibited
and the address counter is not incremented. This pin is internally
pulled LOW and, therefore, can be left open if not used.
AutoStore Operation
The AutoStore operation is a unique feature of nvSRAM that
automatically stores the SRAM data to QuantumTrap cells
during power-down. This STORE makes use of an external
capacitor (VCAP) and enables the device to safely STORE the
data in the nonvolatile memory when power goes down.
During normal operation, the device draws current from VCC to
charge the capacitor connected to the VCAP pin. When the
voltage on the VCC pin drops below VSWITCH during power-down,
the device inhibits all memory accesses to nvSRAM and
automatically performs a conditional STORE operation using the
charge from the VCAP capacitor. The AutoStore operation is not
initiated if no write cycle has been performed since the last
STORE or RECALL.
Note If a capacitor is not connected to VCAP pin, AutoStore must
be disabled by issuing the AutoStore Disable instruction
Document #: 001-64879 Rev. *B
specified in Command Register on page 8. If AutoStore is
enabled without a capacitor on VCAP pin, the device attempts an
AutoStore operation without sufficient charge to complete the
Store. This will corrupt the data stored in nvSRAM as well as the
serial number and it will unlock the SNL bit.
Figure 10 shows the proper connection of the storage capacitor
(VCAP) for AutoStore operation. See the DC Electrical
Characteristics on page 30 for the size of the VCAP.
Figure 10. AutoStore Mode
VCC
0.1 uF
VCC
VCAP
VSS
VCAP
Hardware STORE and HSB pin Operation
The HSB pin in CY14X512I is used to control and acknowledge
STORE operations. If no STORE or RECALL is in progress, this
pin can be used to request a Hardware STORE cycle. When the
HSB pin is driven LOW, the device conditionally initiates a
STORE operation after tDELAY duration. An actual STORE cycle
starts only if a write to the SRAM has been performed since the
last STORE or RECALL cycle. Reads and Writes to the memory
are inhibited for tSTORE duration or as long as HSB pin is LOW.
The HSB pin also acts as an open drain driver (internal 100 k
weak pull-up resistor) that is internally driven LOW to indicate a
busy condition when the STORE (initiated by any means) is in
progress.
Note After each Hardware and Software STORE operation HSB
is driven HIGH for a short time (tHHHD) with standard output high
current and then remains HIGH by internal 100 k pull-up
resistor.
Note For successful last data byte STORE, a hardware STORE
should be initiated at least one clock cycle after the last data bit
D0 is received.
Upon completion of the STORE operation, the nvSRAM memory
access is inhibited for tLZHSB time after HSB pin returns HIGH.
Leave the HSB pin unconnected if not used.
Hardware RECALL (Power Up)
During power-up, when VCC crosses VSWITCH, an automatic
RECALL sequence is initiated that transfers the content of
nonvolatile memory to the SRAM. The data may have been
previously stored on the nonvolatile memory through a STORE
sequence.
Page 9 of 41
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CY14C512I
CY14B512I, CY14E512I
A Power Up RECALL cycle takes tFA time to complete and the
memory access is disabled during this time. HSB pin can be
used to detect the ready status of the device.
Write Operation
The last bit of the slave device address indicates a read or a write
operation. In case of a write operation, the slave device address
is followed by the memory or register address and data. A write
operation continues as long as a STOP or Repeated START
condition is generated by the master or if a NACK is issued by
the nvSRAM.
A NACK is issued from the nvSRAM under the following conditions:
1. A valid Device ID is not received.
2. A write (burst write) access to a protected memory block
address returns a NACK from nvSRAM after the data byte is
received. However, the address counter is set to this address
and the following current read operation starts from this
address.
3. A write/random read access to an invalid or out-of-bound
memory address returns a NACK from the nvSRAM after the
address is received. The address counter remains unchanged
in such a case.
4. A write to the Command Register with an invalid command.
This operation returns a NACK from the nvSRAM.
After a NACK is sent out from the nvSRAM, the write operation
is terminated and any data on the SDA line is ignored till a STOP
or a Repeated START condition is generated by the master.
For example, consider a case where the burst write access is
performed on Control Register Slave address 0x01 for writing the
serial number and continued to the address 0x09, which is a
read-only register. The device returns a NACK and address
counter is not incremented. A following read operation is started
from the address 0x09. Further, any write operation which starts
from a write protected address (say, 0x09) is responded by the
nvSRAM with a NACK after the data byte is sent and set the
address counter to this address. A following read operation starts
from the address 0x09 in this case also.
Note In case you try to read/write access an address that does
not exist (for example 0x0D in Control Register Slave or 0x3F in
RTC registers), nvSRAM responds with a NACK immediately
after the out-of-bound address is transmitted. The address
counter remains unchanged and holds the previous successful
read or write operation address.
A write operation is performed internally with no delay after the
eighth bit of data is transmitted. If a write operation is not
intended, the master must terminate the write operation before
the eighth clock cycle by generating a STOP or Repeated
START condition.
More details on write instructions are provided in the section
Memory Slave Access.
Document #: 001-64879 Rev. *B
Read Operation
If the last bit of the slave device address is ‘1’, a read operation
is assumed and the nvSRAM takes control of the SDA line
immediately after the slave device address byte is sent out by
the master. The read operation starts from the current address
location (the location following the previous successful write or
read operation). When the last address is reached, the address
counter loops back to the first address.
In case of the Control Register Slave, whenever a burst read is
performed such that it flows to a non-existent address, the reads
operation loops back to 0x00. This is applicable, in particular, for
the Command Register.
Read operation can be ended using the following methods:
1. The master issues a NACK on the ninth clock cycle followed
by a STOP or a Repeated START condition on the tenth clock
cycle.
2. The master generates a STOP or Repeated START condition
on the ninth clock cycle.
More details on write instruction are provided in the section
Memory Slave Access.
Memory Slave Access
The following sections describe the data transfer sequence
required to perform read or write operations from nvSRAM.
Write nvSRAM
Each write operation consists of a slave address being
transmitted after the start condition. The last bit of slave address
must be set as ‘0’ to indicate a Write operation. The master may
write one byte of data or continue writing multiple consecutive
address locations while the internal address counter keeps
incrementing automatically. The address register is reset to
0x0000 after the last address in memory is accessed. The write
operation continues till a STOP or Repeated START condition is
generated by the master or a NACK is issued by the nvSRAM.
A write operation is executed only after nvSRAM receives all the
eight data bits. The nvSRAM sends an ACK signal after a
successful write operation. A write operation may be terminated
by the master by generating a STOP condition or a Repeated
START operation. If the master desires to abort the current write
operation without altering the memory contents, this should be
done using a START/STOP condition prior to the eighth data bit.
If the master tries to access a write protected memory address
on the nvSRAM, a NACK is returned after the data byte intended
to write the protected address is transmitted and address counter
will not be incremented. Similarly, in a burst mode write
operation, a NACK is returned when the data byte that attempts
to write a protected memory location and the address counter is
not incremented.
Page 10 of 41
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CY14C512I
CY14B512I, CY14E512I
Figure 11. Single-Byte Write into nvSRAM (except Hs-mode)
S
T
A
R
T
By Master
SDA Line
Address MSB
Memory Slave Address
S
1
0
1
0 A2 A1 A0
Address LSB
S
T
0
P
Data Byte
P
0
By nvSRAM
A
A
A
A
Figure 12. Multi-Byte Write into nvSRAM (except Hs-mode)
SDA Line
S
1
0
1
Address MSB
Address LSB
S
T
0
P
Data Byte N
Data Byte 1
~
~
By Master
S
T
A
R Memory Slave Address
T
0 A2 A1 A0 0
P
By nvSRAM
A
A
A
A
A
Figure 13. Single-Byte Write into nvSRAM (Hs-mode)
By Master
SDA Line
S
T
A
R
T
Hs-mode command
S 0 0 0
0 1
Memory Slave Address
X X X
Sr 1 0
Address MSB
S
T
0
P
Data Byte
Address LSB
P
1 0 A2 A1 A0 0
By nvSRAM
A
A
A
A
A
Figure 14. Multi-Byte Write into nvSRAM (Hs-mode)
SDA Line
Hs-mode command
S 0 0 0
0 1
Memory Slave Address
X X X
Sr 1 0
Address MSB
Data Byte 1
Address LSB
~
~
By Master
S
T
A
R
T
1 0 A2 A1 A0 0
By nvSRAM
A
By Master
A
By nvSRAM
Document #: 001-64879 Rev. *B
~
~
SDA Line
A
A
A
S
T
0
P
Data Byte N
Data Byte 3
Data Byte 2
A
A
P
A
Page 11 of 41
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CY14C512I
CY14B512I, CY14E512I
Current nvSRAM Read
terminate a read operation after reading 1 byte or continue
reading addresses sequentially till the last address in the
memory after which the address counter rolls back to the
address 0x0000. The valid methods of terminating read access
are described in Section Read Operation on page 10.
Each read operation starts with the master transmitting the
nvSRAM slave address with the LSB set to ‘1’ to indicate ‘Read’.
The reads start from the address on the address counter. The
address counter is set to the address location next to the last
accessed with a ‘Write’ or ‘Read’ operation. The master may
Figure 15. Current Location Single-Byte nvSRAM Read (except Hs–mode)
S
T
A
R
T
By Master
SDA Line
Memory Slave Address
S
1
1
0
0
S
T
0
P
A
P
A2 A1 A0 1
By nvSRAM
Data Byte
A
Figure 16. Current Location Multi-Byte nvSRAM Read (except Hs–mode)
SDA Line
S
A
A
Memory Slave Address
1
0
1
0 A2 A1 A0 1
By nvSRAM
S
T
0
P
P
~
~
By Master
S
T
A
R
T
Data Byte N
Data Byte
A
Figure 17. Current Location Single-Byte nvSRAM Read (Hs–mode)
By Master
SDA Line
S
T
A
R
T
Hs-mode command
S 0 0 0
0 1
S
A T
0
P
Memory Slave Address
X X X
Sr 1 0
P
1 0 A2 A1 A0 1
By nvSRAM
A
A
Data Byte
Figure 18. Current Location Multi-Byte nvSRAM Read (Hs–mode)
SDA Line
A
Hs-mode command
S 0 0 0
0 1
X X X
Sr 1 0
1 0 A2 A1 A0 1
Data Byte
By nvSRAM
A
Document #: 001-64879 Rev. *B
A
Memory Slave Address
~
~
By Master
S
T
A
R
T
S
T
0
P
P
Data Byte N
A
Page 12 of 41
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CY14C512I
CY14B512I, CY14E512I
Random Address Read
A random address read is performed by first initiating a write
operation and generating a Repeated START immediately after
the last address byte is acknowledged. The address counter is
set to this address and the next read access to this slave initiates
read operation from here. The master may terminate a read
operation after reading 1 byte or continue reading addresses
sequentially till the last address in the memory after which the
address counter rolls back to the start address 0x0000.
Figure 19. Random Address Single-Byte Read (except Hs–mode)
By Master
SDA Line
S
T
A
R
T
S
S
T
0
P
A
Memory Slave Address
1
0
1
Address MSB
Address LSB
Memory slave Address
0 A2 A1 A0 0
Sr 1
0
1
P
0 A2 A1 A0 1
By nvSRAM
Data Byte
A
A
A
A
Figure 20. Random Address Multi-Byte Read (except Hs–mode)
By Master
SDA Line
S
A
Memory Slave Address
1
0
1
Address MSB
Address LSB
Memory slave Address
0 A2 A1 A0 0
Sr 1
0
1
0 A2 A1 A0 1
By nvSRAM
Data Byte 1
A
A
S
T
0
P
A
~
~
S
T
A
R
T
A
A
P
Data Byte N
Figure 21. Random Address Single-Byte Read (Hs–mode)
SDA Line
Hs-mode command
S 0 0 0
0 1
Address MSB
Memory Slave Address
X X X
Sr 1 0
Address LSB
Memory Slave Address
1 0 A2 A1 A0 0
Sr 1 0
1 0 A2 A1 A0 1
~
~
By Master
S
T
A
R
T
By nvSRAM
A
A
A
A
A
S
T
A 0
P
P
Data Byte
Document #: 001-64879 Rev. *B
Page 13 of 41
[+] Feedback
CY14C512I
CY14B512I, CY14E512I
Figure 22. Random Address Multi-Byte Read (Hs–mode)
SDA Line
Hs-mode command
S 0 0 0
0 1
Address MSB
Memory Slave Address
X X X
Sr 1 0
Address LSB
Memory Slave Address
Sr 1 0
1 0 A2 A1 A0 0
1 0 A2 A1 A0 1
~
~
By Master
S
T
A
R
T
By nvSRAM
A
A
A
A
A
A
P
~
~
Data Byte
A
S
T
0
P
Data Byte N
RTC Registers Slave Access
The following sections describe the data transfer sequence
required to perform read or write operations from RTC registers.
Write RTC Registers
A write to RTC registers is initiated with the RTC Registers Slave
address followed by one byte of address and data. The master
may write one byte of data or continue writing multiple
consecutive address locations while the internal address counter
keeps incrementing automatically. The address register is reset
to 0x00 after the last RTC register is accessed. The write
operation continues till a STOP or Repeated START condition is
generated by the master or a NACK is issued by the nvSRAM
RTC Registers Slave.
A write operation is executed only after all the eight data bits
have been received by the nvSRAM. The nvSRAM sends an
ACK signal after the successful operation of the write instruction
A write operation may be terminated by the master by generating
a STOP condition or a Repeated START operation before the
last data bit is sent.
If the master tries to access an out of bound memory address on
the RTC Registers Slave, a NACK is returned after the address
byte is transmitted. The address counter remains unaffected and
the following current read operation starts from the address
value held in the address counter.
Figure 23. Single-Byte Write into RTC Registers
S
T
A
R
T
By Master
SDA Line
S
RTC Registers Slave Address
1
1
0
RTC Register Address
S
T
0
P
Data Byte
P
1 A2 A1 A0 0
By nvSRAM
A
A
A
Figure 24. Multi-Byte Write into RTC Registers
SDA Line
S
RTC Register Address
RTC Registers Slave Address
1
1
0
By nvSRAM
A
Document #: 001-64879 Rev. *B
Data Byte N
Data Byte
1 A2 A1 A0 0
S
T
0
P
P
~
~
By Master
S
T
A
R
T
A
A
A
Page 14 of 41
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CY14C512I
CY14B512I, CY14E512I
Current Address RTC Registers Read
first location (0x00) and read operation continues. The master
may terminate a read operation after reading one byte or
continue reading addresses sequentially till the last address in
the memory after which the address counter rolls back to the
address 0x00. A read operation may be terminated by the master
by generating a STOP condition or a Repeated START operation
or a NACK.
A current read of RTC registers starts with the master sending
the RTC Registers Slave address after the START condition. All
read operations begin from the current address (the address
next to previously accessed address location). After the last
address is read sequentially, the address latch loops back to the
Figure 25. Current Address RTC Registers Single-Byte Read
S
T
A
R
T
By Master
SDA Line
S
A
RTC Registers Slave Address
1
1
0
S
T
0
P
P
1 A2 A1 A0 1
By nvSRAM
Data Byte
A
Figure 26. Current Address RTC Registers Multi-Byte Read
By Master
SDA Line
S
A
RTC Registers Slave Address
1
0
1
1 A2 A1 A0 1
A
By nvSRAM
Data Byte 1
Random Address RTC Registers Read
A
S
T
0
P
P
~
~
S
T
A
R
T
Data Byte N
address counter rolls back to the start address location of RTC
(0x00).
A random address read is performed by first initiating a write
operation and generating a Repeated START immediately after
the last address byte is acknowledged. The address counter is
set to this address and the next read access to this slave initiates
the read operation from here. The master may terminate a read
operation after reading one byte or continue reading addresses
sequentially till the last address in the memory after which the
A random address read attempt on an out of bound memory
address on the RTC Registers Slave is responded back with a
NACK from the nvSRAM after the address byte is transmitted.
The address counter remains unaffected and the following
current read operation starts from the address value held in the
address counter.
Figure 27. Random Address RTC Registers Single-Byte Read
S
T
A
R
T
By Master
SDA Line
RTC Register Address
RTC Registers Slave Address
S
1
1
0
1
RTC Registers Slave Address
A2 A1 A0 0
Sr
1
1
0
1
A2 A1 A0
S
T
0
P
A
P
1
By nvSRAM
Data Byte
A
A
A
Figure 28. Random Address RTC Registers Multi-Byte Read
RTC Registers Slave Address
SDA Line
S
1
1
0
A
RTC Register Address
1 A2 A1 A0 0
Sr 1
1
0
1 A2 A1 A0 1
BynvSRAM
Data Byte 1
A
Document #: 001-64879 Rev. *B
A
RTC Registers Slave Address
A
~
~
By Master
S
T
A
R
T
S
T
0
P
P
Data Byte N
A
Page 15 of 41
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CY14C512I
CY14B512I, CY14E512I
Control Registers Slave
The following sections describe the data transfer sequence
required to perform read or write operations from Control
Registers Slave.
Write Control Registers
To write the Control Registers Slave, the master transmits the
Control Registers Slave address after generating the START
condition. The write sequence continues from the address
location specified by the master till the master generates a STOP
condition or the last writable address location.
If a non-writable address location is accessed for write operation
during a normal write or a burst, the slave generates a NACK
after the data byte is sent and the write sequence terminates.
Any following data bytes are ignored and the address counter is
not incremented.
If a write operation is performed on the Command Register
(0xAA), the following current read operation also begins from the
first address (0x00) as in this case, the current address is an
out-of-bound address. The address is not incremented and the
next current read operation begins from this address location. If
a write operation is attempted on an out-of-bound address
location, the nvSRAM sends a NACK immediately after the
address byte is sent.
Further, if the serial number is locked, only two addresses (0xAA
or Command Register, and 0x00 or Memory Control Register)
are writable in the Control Registers Slave. On a write operation
to any other address location, the device will acknowledge
command byte and address bytes but it returns a NACK from the
control Registers Slave for data bytes. In this case, the address
will not be incremented and a current read will happen from the
last acknowledged address.
The nvSRAM Control Registers Slave sends a NACK when an
out of bound memory address is accessed for write operation, by
the master. In such a case, a following current read operation
begins from the last acknowledged address.
Figure 29. Single-Byte Write into Control Registers
S
T
A
R
T
By Master
SDA Line
S
Control Registers
Slave Address
0
0
1
Control Register Address
S
T
0
P
Data Byte
P
1 A2 A1 A0 0
By nvSRAM
A
A
A
Figure 30. Multi-Byte Write into Control Registers
SDA Line
S
Control Registers
Slave Address
0
0
1
Control Register Address
Data Byte
1 A2 A1 A0 0
By nvSRAM
A
Document #: 001-64879 Rev. *B
S
T
0
P
Data Byte N
P
~
~
By Master
S
T
A
R
T
A
A
A
Page 16 of 41
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CY14C512I
CY14B512I, CY14E512I
Current Control Registers Read
address location and loops back to the first location (0x00). Note
that the Command Register is a write only register and is not
accessible through the sequential read operations. If a burst read
operation begins from the Command Register (0xAA), the
address counter wraps around to the first address in the register
map (0x00).
A read of Control Registers Slave is started with master sending
the Control Registers Slave address after the START condition
with the LSB set to ‘1’. The reads begin from the current address
which is the next address to the last accessed location. The
reads to Control Registers Slave continues until the last readable
Figure 31. Control Registers Single-Byte Read
S
T
A
R
T
By Master
SDA Line
Control Registers
Slave Address
S
0
0
1
A
S
T
0
P
P
1 A2 A1 A0 1
By nvSRAM
Data Byte
A
Figure 32. Current Control Registers Multi-Byte Read
SDA Line
S
Control Registers
Slave Address
0
0
1
A
A
1 A2 A1 A0 1
~
~
By Master
S
T
A
R
T
By nvSRAM
Data Byte
S
T
0
P
P
Data Byte N
A
Random Control Registers Read
A read of random address may be performed by initiating a write
operation to the intended location of read and immediately
following with a Repeated START operation. The reads to
Control Registers Slave continues till the last readable address
location and loops back to the first location (0x00). Note that the
Command Register is a write only register and is not accessible
through the sequential read operations. A random read starting
at the Command Register (0xAA) loops back to the first address
in the Control Register register map (0x00). If a random read
operation is initiated from an out-of-bound memory address, the
nvSRAM sends a NACK after the address byte is sent.
Figure 33. Random Control Registers Single-Byte Read
By Master
SDA Line
S
T
A
R
T
S
Control Registers
Slave Address
0
0
1
Control Register Address
A
Control Registers Slave Address
Sr 0
1 A2 A1 A0 0
0
1
1
A2 A1 A0 1
S
T
0
P
P
By nvSRAM
Data Byte
A
Document #: 001-64879 Rev. *B
A
A
Page 17 of 41
[+] Feedback
CY14C512I
CY14B512I, CY14E512I
Figure 34. Random Control Registers Multi-Byte Read
SDA Line
S
Control Registers
Slave Address
0
0
1
Control Register Address
A
Control Registers Slave Address
Sr 0
1 A2 A1 A0 0
0
1
1
A2 A1 A0 1
~
~
By Master
S
T
A
R
T
By nvSRAM
Data Byte
A
A
A
A
S
T
0
P
P
Data Byte N
Serial Number
Serial number is an 8 byte memory space provided to the user
to uniquely identify this device. It typically consists of a two byte
customer ID, followed by five bytes of unique serial number and
one byte of CRC check. However, nvSRAM does not calculate
the CRC and it is up to the user to utilize the eight byte memory
space in the desired format. The default values for the eight byte
locations are set to ‘0x00’.
Serial Number Write
The serial number can be accessed through the Control
Registers Slave Device. To write the serial number, master
transmits the Control Registers Slave address after the START
condition and writes to the address location from 0x01 to 0x08.
The content of Serial Number registers is secured to nonvolatile
memory on the next STORE operation. If AutoStore is enabled,
nvSRAM automatically stores the serial number in the
nonvolatile memory on power-down. However, if AutoStore is
disabled, user must perform a STORE operation to secure the
contents of Serial Number registers.
Note If the serial number lock (SNL) bit is not set, the serial
number registers can be re-written regardless of whether or not
a STORE has happened. After the serial number lock bit is set,
no writes to the serial number registers are allowed. If the master
tries to perform a write operation to the serial number registers
Document #: 001-64879 Rev. *B
when the lock bit is set, a NACK is returned and write is not
performed.
Serial Number Lock
After writes to serial number registers is complete, the master is
responsible for locking the serial number by setting the serial
number lock bit to ‘1’ in the Memory Control Register (0x00). The
content of Memory Control Register and serial number are
secured on the next STORE operation (STORE or AutoStore). If
AutoStore is not enabled, user must perform the STORE
operation to secure the lock bit status.
If a STORE was not performed, the serial number lock bit will not
survive the power cycle. The serial number lock bit and 8-byte
serial number is defaults to ‘0’ at power-up.
Serial Number Read
Serial number can be read back by a read operation of the
intended address of the Control Registers Slave. The Control
Registers Device loops back from the last address (excluding the
Command Register) to 0x00 address location while performing
burst read operation. The serial number resides in the locations
from 0x01 to 0x08. Even if the serial number is not locked, a
serial number read operation returns the current values written
to the serial number registers. The master may perform a serial
number read operation to confirm if the correct serial number is
written to the registers before setting the lock bit.
Page 18 of 41
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CY14C512I
CY14B512I, CY14E512I
Device ID
Device ID Read
Device ID is a 4-byte code consisting of JEDEC assigned manufacturer ID, product ID, density ID, and die revision. These registers
are set in the factory and are read only registers for the user.
Table 6. Device ID
Bits
#of Bits
31 - 21
(11 bits)
20 - 7
(14 bits)
6-3
(4 bits)
2-0
(3 bits)
Device
Manufacturer ID
Product ID
Density ID
Die Rev
CY14C512I
00000110100
00001111000001
0011
000
CY14B512I
00000110100
00001111010001
0011
000
CY14E512I
00000110100
00001111100101
0011
000
The device ID is divided into four parts as shown in Table 6:
4. Die Rev (3 bits)
1. Manufacturer ID (11 bits)
This is used to represent any major change in the design of the
product. The initial setting of this is always 0x0.
This is the JEDEC assigned manufacturer ID for Cypress.
JEDEC assigns the manufacturer ID in different banks. The first
three bits of the manufacturer ID represent the bank in which ID
is assigned. The next eight bits represent the manufacturer ID.
Executing Commands Using Command
Register
Cypress manufacturer ID is 0x34 in bank 0. Therefore the
manufacturer ID for all Cypress nvSRAM products is as given
below:
The Control Registers Slave allows different commands to be
executed by writing the specific command byte in the Command
Register (0xAA). The command byte codes for each command
are specified in Table 5. During the execution of these
commands the device is not accessible and returns a NACK if
any of the three slave devices is selected. If an invalid command
is sent by the master, nvSRAM responds with a NACK indicating
that the command was not successful. The address latch of this
slave continues to point to the Command Register address.
Cypress ID - 000_0011_0100
2. Product ID (14 bits)
The product ID for device is shown in the Table 6.
3. Density ID (4 bits)
The 4-bit density ID is used as shown in Table 6 for indicating the
512 Kb density of the product.
Figure 35. Command Execution using Command Register
By Master
SDA Line
S
T
A
R
T
S
Control Register
Slave Address
0
0
1
Command Register Address
1 A2 A1 A0 0
1
0
1
0
1
0
1
S
T
O
P
Command Byte
P
0
By nvSRAM
A
Document #: 001-64879 Rev. *B
A
A
Page 19 of 41
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CY14C512I
CY14B512I, CY14E512I
Real Time Clock Operation
nvTIME Operation
The CY14X512I offers internal registers that contain clock,
alarm, watchdog, interrupt, and control functions. The RTC
registers occupy a separate address space from nvSRAM and
are accessible through the Read RTC register and Write RTC
register sequence on register addresses 0x00 to 0x0F. Internal
double buffering of the clock and the timer information registers
prevents accessing transitional internal clock data during a read
or write operation. Double buffering also circumvents disrupting
normal timing counts or the clock accuracy of the internal clock
when accessing clock data. Clock and alarm registers store data
in BCD format.
Clock Operations
The clock registers maintain time up to 9,999 years in
one-second increments. The time can be set to any calendar
time and the clock automatically keeps track of days of the week
and month, leap years, and century transitions. There are eight
registers dedicated to the clock functions, which are used to set
time with a write cycle and to read time during a read cycle.
These registers contain the time of day in BCD format. Bits
defined as ‘0’ are currently not used and are reserved for future
use by Cypress.
Reading the Clock
The double buffered RTC register structure reduces the chance
of reading incorrect data from the clock. Stop internal updates to
the CY14X512I time keeping registers before reading clock data
to prevent reading of data in transition. Stopping the register
updates does not affect clock accuracy.
When an read sequence of RTC device is initiated, the update
of the user timekeeping registers stops and does not restart until
a STOP or a Repeated START condition is generated. The RTC
registers are read while the internal clock continues to run. After
the end of read sequence, all the RTC registers are
simultaneously updated within 20 ms.
Setting the Clock
A write access to the RTC device stops updates to the time
keeping registers and enables the time to be set. The correct
day, date, and time is then written into the registers and must be
in 24 hour BCD format. The time written is referred to as the
“Base Time”. This value is stored in nonvolatile registers and
used in the calculation of the current time. When a STOP or a
Repeated START condition is encountered, the values of
timekeeping registers are transferred to the actual clock
counters after which the clock resumes normal operation. If a
valid STOP or Repeated START condition is not generated by
the master, the time written to the RTC registers is never transferred to the actual clock counters.
If the time written to the timekeeping registers is not in the correct
BCD format, each invalid nibble of the RTC registers continue
counting to 0xF before rolling over to 0x0 after which RTC
resumes normal operation.
Note After ‘W’ bit is set to ‘0’, values written into the timekeeping,
alarm, calibration, and interrupt registers are transferred to the
RTC time keeping counters in tRTCp time. These counter values
must be saved to nonvolatile memory either by initiating a
Document #: 001-64879 Rev. *B
Software/Hardware STORE or AutoStore operation. While
working in AutoStore disabled mode, perform a STORE
operation after tRTCp time while writing into the RTC registers for
the modifications to be correctly recorded.
Backup Power
The RTC in the CY14X512I is intended for permanently powered
operation. The VRTCcap or VRTCbat pin is connected depending
on whether a capacitor or battery is chosen for the application.
When the primary power, VCC, fails and drops below VSWITCH
the device switches to the backup power supply.
The clock oscillator uses very little current, which maximizes the
backup time available from the backup source. Regardless of the
clock operation with the primary source removed, the data stored
in the nvSRAM is secure, having been stored in the nonvolatile
elements when power was lost.
During backup operation, the CY14X512I consumes a 0.45 µA
(Typ) at room temperature. The user must choose capacitor or
battery values according to the application.
Backup time values based on maximum current specifications
are shown in the following table. Nominal backup times are
approximately two times longer.
Table 7. RTC Backup Time
Capacitor Value
0.1F
0.47F
1.0F
Backup Time
(CY14B512I)
60 hours
12 days
25 days
Using a capacitor has the obvious advantage of recharging the
backup source each time the system is powered up. If a battery
backup is used, a 3-V lithium battery is recommended and the
CY14X512I sources current only from the battery when the
primary power is removed. However, the battery is not recharged
at any time by the CY14X512I. The battery capacity must be
chosen for total anticipated cumulative down time required over
the life of the system.
Stopping and Starting the Oscillator
The OSCEN bit in the calibration register at 0x08 controls the
enable and disable of the oscillator. This bit is nonvolatile and is
shipped to customers in the “enabled” (set to ‘0’) state. To
preserve the battery life when the system is in storage, OSCEN
must be set to ‘1’. This turns off the oscillator circuit, extending
the battery life. If the OSCEN bit goes from disabled to enabled,
it takes approximately one second (two seconds maximum) for
the oscillator to start.
While system power is off, if the voltage on the backup supply
(VRTCcap or VRTCbat) falls below their respective minimum level,
the oscillator may fail.The CY14X512I has the ability to detect
oscillator failure when system power is restored. This is recorded
in the Oscillator Fail Flag (OSCF) of the flags register at the
address 0x00. When the device is powered on (VCC goes above
VSWITCH) the OSCEN bit is checked for the ‘enabled’ status. If
the OSCEN bit is enabled and the oscillator is not active within
the first 5 ms, the OSCF bit is set to ‘1’. The system must check
for this condition and then write ‘0’ to clear the flag.
Page 20 of 41
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CY14C512I
CY14B512I, CY14E512I
Note that in addition to setting the OSCF flag bit, the time
registers are reset to the ‘Base Time’ (when a read sequence of
the RTC device is initiated, the update of the user timekeeping
registers stops and does not restart until a STOP or a Repeated
START condition is generated. The RTC registers are read while
the internal clock continues to run. After the end of read
sequence, all the RTC registers are simultaneously updated
within 20 ms.), which is the value last written to the timekeeping
registers. The control or calibration registers and the OSCEN bit
are not affected by the ‘oscillator failed’ condition.
The value of OSCF must be reset to ‘0’ when the time registers
are written for the first time. This initializes the state of this bit
which may have become set when the system was first powered
on.
To reset OSCF, set the write bit ‘W’ (in the flags register at 0x00)
to a ‘1’ to enable writes to the flags register. Write a ‘0’ to the
OSCF bit and then reset the write bit to ‘0’ to disable writes.
Calibrating the Clock
The RTC is driven by a quartz-controlled crystal with a nominal
frequency of 32.768 kHz. Clock accuracy depends on the quality
of the crystal and calibration. The crystals available in the market
typically have an error of +20 ppm to +35 ppm. However,
CY14X512I employs a calibration circuit that improves the
accuracy to +1/–2 ppm at 25 °C. This implies an error of
+2.5 seconds to -5 seconds per month.
The calibration circuit adds or subtracts counts from the oscillator
divider circuit to achieve this accuracy. The number of pulses that
are suppressed (subtracted, negative calibration) or split (added,
positive calibration) depends upon the value loaded into the five
calibration bits found in the calibration register at 0x08. The
calibration bits occupy the five lower order bits in the calibration
register. These bits are set to represent any value between ‘0’
and 31 in binary form. Bit D5 is a sign bit, where a ‘1’ indicates
positive calibration and a ‘0’ indicates negative calibration.
Adding counts speeds the clock up and subtracting counts slows
the clock down. If a binary ‘1’ is loaded into the register, it
corresponds to an adjustment of 4.068 or –2.034 ppm offset in
oscillator error, depending on the sign.
Calibration occurs within a 64-minute cycle. The first 62 minutes
in the cycle may, once per minute, have one second shortened
by 128 or lengthened by 256 oscillator cycles. If a binary ‘1’ is
loaded into the register, only the first two minutes of the
64-minute cycle are modified. If a binary 6 is loaded, the first 12
are affected, and so on. Therefore, each calibration step has the
effect of adding 512 or subtracting 256 oscillator cycles for every
125,829,120 actual oscillator cycles, that is, 4.068 or –2.034 ppm
of adjustment per calibration step in the calibration register.
To determine the required calibration, the CAL bit in the flags
register (0x00) must be set to ‘1’. This causes the INT pin to
toggle at a nominal frequency of 512 Hz. Any deviation
measured from the 512 Hz indicates the degree and direction of
the required correction. For example, a reading of 512.01024 Hz
indicates a +20 ppm error. Hence, a decimal value of –10
(001010b) must be loaded into the Calibration register to offset
this error.
Note Setting or changing the calibration register does not affect
the test output frequency.
Document #: 001-64879 Rev. *B
To set or clear CAL, set the write bit ‘W’ (in the flags register at
0x00) to ‘1’ to enable writes to the flags register. Write a value to
CAL, and then reset the write bit to ‘0’ to disable writes.
Alarm
The alarm function compares user programmed values of alarm
time and date (stored in the registers 0x01-5) with the
corresponding time of day and date values. When a match
occurs, the alarm internal flag (AF) is set and an interrupt is
generated on INT pin if alarm interrupt enable (AIE) bit is set.
There are four alarm match fields - date, hours, minutes, and
seconds. Each of these fields has a match bit that is used to
determine if the field is used in the alarm match logic. Setting the
match bit to ‘0’ indicates that the corresponding field is used in
the match process. Depending on the match bits, the alarm
occurs as specifically as once a month or as frequently as once
every minute. Selecting none of the match bits (all 1s) indicates
that no match is required and therefore, alarm is disabled.
Selecting all match bits (all 0s) causes an exact time and date
match.
There are two ways to detect an alarm event: by reading the AF
flag or monitoring the INT pin. The AF flag in the flags register at
0x00 indicates that a date or time match has occurred. The AF
bit is set to ‘1’ when a match occurs. Reading the flags register
clears the alarm flag bit (and all others). A hardware interrupt pin
may also be used to detect an alarm event.
To set, clear or enable an alarm, set the ‘W’ bit (in flags register
- 0x00) to ‘1’ to enable writes to alarm registers. After writing the
alarm value, clear the ‘W’ bit back to ‘0’ for the changes to take
effect.
Note CY14X512I requires the alarm match bit for seconds (0x02
- D7) to be set to ‘0’ for proper operation of Alarm Flag and
Interrupt.
Watchdog Timer
The watchdog timer is a free running down counter that uses the
32 Hz clock (31.25 ms) derived from the crystal oscillator. The
oscillator must be running for the watchdog to function. It begins
counting down from the value loaded in the watchdog timer
register.
The timer consists of a loadable register and a free running
counter. On power-up, the watchdog time out value in register
0x07 is loaded into the Counter Load register. Counting begins
on power-up and restarts from the loadable value any time the
Watchdog Strobe (WDS) bit is set to ‘1’. The counter is compared
to the terminal value of ‘0’. If the counter reaches this value, it
causes an internal flag and an optional interrupt output. You can
prevent the time out interrupt by setting WDS bit to ‘1’ prior to the
counter reaching ‘0’. This causes the counter to reload with the
watchdog time out value and to be restarted. As long as the user
sets the WDS bit prior to the counter reaching the terminal value,
the interrupt and WDT flag never occur.
New time out values are written by setting the watchdog write bit
to ‘0’. When the WDW is ‘0’, new writes to the watchdog time out
value bits D5-D0 are enabled to modify the time out value. When
WDW is ‘1’, writes to bits D5-D0 are ignored. The WDW function
enables a user to set the WDS bit without concern that the
watchdog timer value is modified. A logical diagram of the
watchdog timer is shown in Figure 36 on page 22. Note that
Page 21 of 41
[+] Feedback
CY14C512I
CY14B512I, CY14E512I
setting the watchdog time out value to ‘0’ disables the watchdog
function.
The output of the watchdog timer is the flag bit WDF that is set if
the watchdog is allowed to time out. If the watchdog interrupt
enable (WIE) bit in the Interrupt register is set, a hardware
interrupt on INT pin is also generated on watchdog timeout. The
flag and the hardware interrupt are both cleared when user reads
the flag registers.
Figure 36. Watchdog Timer Block Diagram
.
Clock
Divider
Oscillator
32.768 KHz
Zero
Compare
WDF
Load
Register
WDS
D
Q
WDW
Q
write to
Watchdog
Register
Watchdog
Register
Programmable Square Wave Generator
The square wave generator block uses the crystal output to
generate a desired frequency on the INT pin of the device. The
output frequency can be programmed to be one of the following:
1. 1 Hz
2. 512 Hz
3. 4096 Hz
4. 32768 Hz
The square wave output is not generated while the device is
running on backup power.
Power Monitor
The CY14X512I provides a power management scheme with
power fail interrupt capability. It also controls the internal switch
to back up power for the clock and protects the memory from low
VCC access. The power monitor is based on an internal band gap
reference circuit that compares the VCC voltage to VSWITCH
threshold.
When VSWITCH is reached, as VCC decays from power loss, a
data store operation is initiated from SRAM to the nonvolatile
elements, securing the last SRAM data state. Power is also
switched from VCC to the backup supply (battery or capacitor) to
operate the RTC oscillator.
When operating from the backup source, read and write
operations to nvSRAM are inhibited and the RTC functions are
not available to the user. The RTC clock continues to operate in
the background. The updated RTC time keeping registers are
available to the user after VCC is restored to the device (see
nvSRAM Specifications on page 34).
Document #: 001-64879 Rev. *B
The CY14X512I provides a backup power monitoring system
that detects the backup power (either battery or capacitor
backup) failure. The backup power fail flag (BPF) is issued on
the next power-up in case of backup power failure. The BPF flag
is set in the event of backup voltage falling lower than VBAKFAIL.
The backup power is monitored even while the RTC is running
in backup mode. Low voltage detected during backup mode is
flagged through the BPF flag. BPF can hold the data only until a
defined low level of the back up voltage (VDR).
Interrupts
1 Hz
32 Hz
Counter
Backup Power Monitor
The CY14X512I has a flags register, interrupt register, and
interrupt logic that can signal interrupt to the microcontroller.
There are three potential sources for interrupt: watchdog timer,
power monitor, and alarm timer. Each of these can be individually
enabled to drive the INT pin by appropriate setting in the interrupt
register (0x06). In addition, each has an associated flag bit in the
flags register (0x00) that the host processor uses to determine
the cause of the interrupt. The INT pin driver has two bits that
specify its behavior when an interrupt occurs.
An interrupt is raised only if both a flag is raised by one of the
three sources and the respective interrupt enable bit in interrupts
register is enabled (set to ‘1’). After an interrupt source is active,
two programmable bits, H/L and P/L, determine the behavior of
the output pin driver on INT pin. These two bits are located in the
Interrupt register and can be used to drive level or pulse mode
output from the INT pin. In pulse mode, the pulse width is
internally fixed at approximately 200 ms. This mode is intended
to reset a host microcontroller. In the level mode, the pin goes to
its active polarity until the flags register is read by the user. This
mode is used as an interrupt to a host microcontroller. The
control bits are summarized in the following section.
Interrupts are only generated while working on normal power and
are not triggered when system is running in backup power mode.
Note CY14X512I generates valid interrupts only after the
Powerup RECALL sequence is completed. All events on INT pin
must be ignored for tFA duration after powerup.
Interrupt Register
Watchdog Interrupt Enable (WIE): When set to ‘1’, the
watchdog timer drives the INT pin and an internal flag when a
watchdog time out occurs. When WIE is set to ‘0’, the watchdog
timer only affects the WDF flag in flags register.
Alarm Interrupt Enable (AIE): When set to ‘1’, the alarm match
drives the INT pin and an internal flag. When AIE is set to ‘0’, the
alarm match only affects the AF flag in the flags register.
Power Fail Interrupt Enable (PFE): When set to ‘1’, the power
fail monitor drives the pin and an internal flag. When PFE is set
to ‘0’, the power fail monitor only affects the PF flag in the flags
register.
Square Wave Enable (SQWE): When set to ‘1’, a square wave
of programmable frequency is generated on the INT pin. The
frequency is decided by the SQ1 and SQ0 bits of the interrupts
register. This bit is nonvolatile and survives power cycle. The
SQWE bit overrides all other interrupts. However, CAL bit will
take precedence over the square wave generator. This bit
defaults to ‘0’ from the factory.
Page 22 of 41
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CY14C512I
CY14B512I, CY14E512I
High/Low (H/L): When set to a ‘1’, the INT pin is active HIGH
and the driver mode is push pull. The INT pin drives HIGH only
when VCC is greater than VSWITCH. When set to a ‘0’, the INT pin
is active LOW and the drive mode is open drain. The INT pin
must be pulled up to Vcc by a 10 k resistor while using the
interrupt in active LOW mode.
Pulse/Level (P/L): When set to a ‘1’ and an interrupt occurs, the
INT pin is driven for approximately 200 ms. When P/L is set to a
‘0’, the INT pin is driven HIGH or LOW (determined by H/L) until
the flags register is read.
SQ1 and SQ0. These bits are used together to fix the frequency
of square wave on INT pin output when SQWE bit is set to ‘1’.
These bits are nonvolatile and survive power cycle. The output
frequency is decided as illustrated in this table.
the flag and the pin. The pulse does not complete its specified
duration if the flags register is read. If the INT pin is used as a
host reset, the flags register is not read during a reset.
Following is a summary table that shows the state of the INT pin.
Table 9. State of the INT pin
CAL
SQWE
WIE/AIE/
PFE
INT Pin Output
1
X
X
512 Hz
0
1
X
Square wave
output
0
0
1
Alarm
0
0
0
HI-Z
Table 8. SQW Output Selection
SQ1
SQ0
Frequency
Comment
0
0
1 Hz
0
1
512 Hz
512 Hz clock output
1
0
4096 Hz
4 kHz clock output
1
1
32768 Hz
Oscillator output
frequency
1 Hz signal
When an enabled interrupt source activates the INT pin, an
external host reads the flag registers to determine the cause.
Remember that all flags are cleared when the register is read. If
the INT pin is programmed for Level mode, then the condition
clears and the INT pin returns to its inactive state. If the pin is
programmed for Pulse mode, then reading the flag also clears
Document #: 001-64879 Rev. *B
Flags Register
The flags register has three flag bits: WDF, AF, and PF, which
can be used to generate an interrupt. These flags are set by the
watchdog timeout, alarm match, or power fail monitor
respectively. The processor can either poll this register or enable
interrupts to be informed when a flag is set. These flags are
automatically reset after the register is read. The flags register is
automatically loaded with the value 0x00 on power-up (except
for the OSCF bit. See Stopping and Starting the Oscillator on
page 20).
Page 23 of 41
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CY14C512I
CY14B512I, CY14E512I
Figure 37. RTC Recommended Component Configuration
Recommended Values
Y1 = 32.768 KHz (12.5 pF)
C1 = 12 pF
C2 = 69 pF
Xout
C1
Y1
Note: The recommended values for C1 and C2 include
board trace capacitance.
Xin
C2
Figure 38. Interrupt Block Diagram
WIE
Watchdog
Timer
WDF
Power
Monitor
PFE
PF
AIE
P/L
512 Hz
Clock
AF
Pin
Driver
Mux
Clock
Alarm
Square
Wave
HI-Z
Control
SEL Line
VCC
INT
H/L
VSS
WDF - Watchdog timer flag
WIE - Watchdog interrupt
enable
PF - Power fail flag
PFE - Power Fail Enable
AF - Alarm fag
AIE - Alarm interrupt enable
P/L - Pulse level
H/L - High/Low
SQWE - Square wave enable
SQWE
Priority
CAL
Encoder
WIE/PIE/
AIE
Document #: 001-64879 Rev. *B
Page 24 of 41
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CY14C512I
CY14B512I, CY14E512I
Table 10. RTC Register Map[2, 3]
Register
BCD Format Data
D7
0x0F
0x0E
D6
D5
D4
D3
D2
D1
10s years
0
0
0x0D
0
0
0x0C
0
0
0x0B
0
0
0x0A
0
0
10s
months
10s day of month
0
0
D0
Years
Years: 00–99
Months
Months: 01–12
Day of month
Day of month: 01–31
0
Day of week
10s hours
10s minutes
Day of week: 01–07
Hours
Hours: 00–23
Minutes
Minutes: 00–59
0x09
0
0x08
OSCEN
(0)
0x07
WDS (0) WDW (0)
0x06
WIE (0)
AIE (0)
0x05
M (1)
0
10s alarm date
Alarm day
Alarm, day of month: 01–31
0x04
M (1)
0
10s alarm hours
Alarm hours
Alarm, hours: 00–23
0x03
M (1)
10s alarm minutes
Alarm minutes
Alarm, minutes: 00–59
0x02
M (1)
10s alarm seconds
Alarm seconds
Alarm, seconds: 00–59
0x01
0x00
10s seconds
Function/Range
0
Seconds
Cal Sign
(0)
AF
Watchdog [4]
WDT (000000)
PFE (0)
SQWE
(0)
H/L (1)
10s centuries
WDF
Seconds: 00–59
Calibration Values [4]
Calibration (00000)
PF
P/L (0)
SQ1
(0)
SQ0
(0)
Centuries
OSCF[5]
BPF[5]
CAL (0)
W (0)
Interrupts [4]
Centuries: 00–99
R (0)
Flags [4]
Notes
2. ( ) designates values shipped from the factory.
3. The unused bits of RTC registers are reserved for future use and should be set to ‘0’
4. This is a binary value, not a BCD value.
5. When user resets OSCF and BPF flag bits, the flags register will be updated after tRTCp time.
Document #: 001-64879 Rev. *B
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CY14C512I
CY14B512I, CY14E512I
Table 11. Register Map Detail
Register
Description
Time Keeping - Years
0x0F
D7
D6
D5
D4
D3
D2
10s years
D1
D0
Years
Contains the lower two BCD digits of the year. Lower nibble (four bits) contains the value for years; upper nibble (four
bits) contains the value for 10s of years. Each nibble operates from 0 to 9. The range for the register is 0–99.
Time Keeping - Months
0x0E
D7
D6
D5
D4
0
0
0
10s month
D3
D2
D1
D0
Months
Contains the BCD digits of the month. Lower nibble (four bits) contains the lower digit and operates from 0 to 9; upper
nibble (one bit) contains the upper digit and operates from 0 to 1. The range for the register is 1–12.
Time Keeping - Date
0x0D
D7
D6
0
0
D5
D4
D3
10s day of month
D2
D1
D0
Day of month
Contains the BCD digits for the date of the month. Lower nibble (four bits) contains the lower digit and operates from 0
to 9; upper nibble (two bits) contains the 10s digit and operates from 0 to 3. The range for the register is 1–31. Leap
years are automatically adjusted for.
Time Keeping - Day
0x0C
D7
D6
D5
D4
D3
0
0
0
0
0
D2
D1
D0
Day of week
Lower nibble (three bits) contains a value that correlates to day of the week. Day of the week is a ring counter that
counts from 1 to 7 then returns to 1. The user must assign meaning to the day value, because the day is not integrated
with the date.
Time Keeping - Hours
0x0B
D7
D6
0
0
D5
D4
D3
D2
10s hours
D1
D0
Hours
Contains the BCD value of hours in 24 hour format. Lower nibble (four bits) contains the lower digit and operates from
0 to 9; upper nibble (two bits) contains the upper digit and operates from 0 to 2. The range for the register is 0–23.
Time Keeping - Minutes
D7
0x0A
D6
0
D5
D4
D3
D2
10s minutes
D1
D0
Minutes
Contains the BCD value of minutes. Lower nibble (four bits) contains the lower digit and operates from 0 to 9; upper
nibble (three bits) contains the upper minutes digit and operates from 0 to 5. The range for the register is 0–59.
Time Keeping - Seconds
D7
0x09
D6
0
D5
D4
D3
D2
10s seconds
D1
D0
Seconds
Contains the BCD value of seconds. Lower nibble (four bits) contains the lower digit and operates from 0 to 9; upper
nibble (three bits) contains the upper digit and operates from 0 to 5. The range for the register is 0–59.
Calibration/Control
0X08
OSCEN
D7
D6
D5
OSCEN
0
Calibration
sign
D4
D3
D2
D1
D0
Calibration
Oscillator Enable. When set to ‘1’, the oscillator is stopped. When set to ‘0’, the oscillator runs. Disabling the oscillator
saves battery or capacitor power during storage.
Calibration Determines if the calibration adjustment is applied as an addition (1) to or as a subtraction (0) from the time-base.
Sign
Calibration These five bits control the calibration of the clock.
Document #: 001-64879 Rev. *B
Page 26 of 41
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CY14C512I
CY14B512I, CY14E512I
Table 11. Register Map Detail (continued)
Register
Description
Watchdog Timer
0x07
D7
D6
WDS
WDW
D5
D4
D3
D2
D1
D0
WDT
WDS
Watchdog Strobe. Setting this bit to ‘1’ reloads and restarts the watchdog timer. Setting the bit to ‘0’ has no effect. The
bit is cleared automatically after the watchdog timer is reset. The WDS bit is write only. Reading it always returns a 0.
WDW
Watchdog Write Enable. Setting this bit to ‘1’ disables any WRITE to the watchdog timeout value (D5–D0). This enables
the user to set the watchdog strobe bit without disturbing the timeout value. Setting this bit to ‘0’ allows bits D5–D0 to
be written to the watchdog register when the next write cycle is complete. This function is explained in more detail in
Watchdog Timer on page 21.
WDT
Watchdog timeout selection. The watchdog timer interval is selected by the 6-bit value in this register. It represents a
multiplier of the 32 Hz count (31.25 ms). The range of timeout value is 31.25 ms (a setting of 1) to 2 seconds (setting
of 3 Fh). Setting the watchdog timer register to ‘0’ disables the timer. These bits can be written only if the WDW bit was
set to 0 on a previous cycle.
Interrupt Status/Control
0x06
D7
D6
D5
D4
D3
D2
D1
D0
WIE
AIE
PFE
SQWE
H/L
P/L
SQ1
SQ0
WIE
Watchdog Interrupt Enable. When set to ‘1’ and a watchdog timeout occurs, the watchdog timer drives the INT pin and
the WDF flag. When set to ‘0’, the watchdog timeout affects only the WDF flag.
AIE
Alarm Interrupt Enable. When set to ‘1’, the alarm match drives the INT pin and the AF flag. When set to ‘0’, the alarm
match only affects the AF flag.
PFE
Power Fail Enable. When set to ‘1’, the alarm match drives the INT pin and the PF flag. When set to ‘0’, the power fail
monitor affects only the PF flag.
SQWE
Square Wave Enable. When set to ‘1’, a square wave is driven on the INT pin with frequency programmed using SQ1
and SQ0 bits. The square wave output takes precedence over interrupt logic. If the SQWE bit is set to ‘1’. when an
enabled interrupt source becomes active, only the corresponding flag is raised and the INT pin continues to drive the
square wave.
H/L
High/Low. When set to ‘1’, the INT pin is driven active HIGH. When set to ‘0’, the INT pin is open drain, active LOW.
P/L
Pulse/Level. When set to ‘1’, the INT pin is driven active (determined by H/L) by an interrupt source for approximately
200 ms. When set to ‘0’, the INT pin is driven to an active level (as set by H/L) until the flags register is read.
SQ1, SQ0 SQ1, SQ0. These bits are used to decide the frequency of the Square wave on the INT pin output when SQWE bit is
set to ‘1’. The following is the frequency output for each combination of (SQ1, SQ0):
(0, 0) - 1 Hz
(0, 1) - 512 Hz
(1, 0) - 4096 Hz
(1, 1) - 32768 Hz
Alarm - Day
0x05
D7
D6
M
0
D5
D4
D3
D2
10s alarm date
D1
D0
Alarm date
Contains the alarm value for the date of the month and the mask bit to select or deselect the date value.
M
Match. When this bit is set to ‘0’, the date value is used in the alarm match. Setting this bit to ‘1’ causes the match circuit
to ignore the date value.
Alarm - Hours
0x04
D7
D6
M
0
D5
D4
10s alarm hours
D3
D2
D1
D0
Alarm hours
Contains the alarm value for the hours and the mask bit to select or deselect the hours value.
M
Match. When this bit is set to ‘0’, the hours value is used in the alarm match. Setting this bit to ‘1’ causes the match
circuit to ignore the hours value.
Document #: 001-64879 Rev. *B
Page 27 of 41
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CY14B512I, CY14E512I
Table 11. Register Map Detail (continued)
Register
Description
Alarm - Minutes
0x03
D7
D6
M
D5
D4
D3
10s alarm minutes
D2
D1
D0
Alarm minutes
Contains the alarm value for the minutes and the mask bit to select or deselect the minutes value.
M
Match. When this bit is set to ‘0’, the minutes value is used in the alarm match. Setting this bit to ‘1’ causes the match
circuit to ignore the minutes value.
Alarm - Seconds
0x02
D7
D6
M
D5
D4
D3
10s alarm seconds
D2
D1
D0
Alarm seconds
Contains the alarm value for the seconds and the mask bit to select or deselect the seconds’ value.
M
Match. When this bit is set to ‘0’, the seconds value is used in the alarm match. Setting this bit to ‘1’ causes the match
circuit to ignore the seconds value.
Time Keeping - Centuries
0x01
D7
D6
D5
D4
D3
D2
10s centuries
D1
D0
Centuries
Contains the BCD value of centuries. Lower nibble contains the lower digit and operates from 0 to 9; upper nibble
contains the upper digit and operates from 0 to 9. The range for the register is 0-99 centuries.
Flags
0x00
D7
D6
D5
D4
D3
D2
D1
D0
WDF
AF
PF
OSCF
BPF
CAL
W
R
WDF
Watchdog Timer Flag. This read only bit is set to ‘1’ when the watchdog timer is allowed to reach ‘0’ without being reset
by the user. It is cleared to ‘0’ when the flags register is read or on power-up
AF
Alarm Flag. This read only bit is set to ‘1’ when the time and date match the values stored in the alarm registers with
the match bits = ‘0’. It is cleared when the flags register is read or on power-up.
PF
Power Fail Flag. This read only bit is set to ‘1’ when power falls below the power fail threshold VSWITCH. It is cleared
when the flags register is read.
OSCF
Oscillator Fail Flag. Set to ‘1’ on power-up if the oscillator is enabled and not running in the first 5 ms of operation. This
indicates that RTC backup power failed and clock value is no longer valid. This bit survives power cycle and is never
cleared internally by the chip. The user must check for this condition and write '0' to clear this flag. When user resets
OSCF flag bit, the bit will be updated after tRTCp time.
BPF
Backup Power Fail Flag. Set to ‘1’ on power-up if the backup power (battery or capacitor) failed. The backup power fail
condition is determined by the voltage falling below their respective minimum specified voltage. BPF can hold the data
only till a defined low level of the back up voltage (VDR). User must reset this bit to clear this flag. When user resets
BPF flag bit, the bit will be updated after tRTCp time.
CAL
Calibration Mode. When set to ‘1’, a 512 Hz square wave is output on the INT pin. When set to ‘0’, the INT pin resumes
normal operation. This bit takes priority than SQ0/SQ1 and other functions. This bit defaults to ‘0’ (disabled) on power-up.
W
Write Enable: Setting the ‘W’ bit to ‘1’ freezes updates of the RTC registers. The user can then write to RTC registers,
alarm registers, calibration register, interrupt register and flags register. Setting the ‘W’ bit to ‘0’ causes the contents of
the RTC registers to be transferred to the time keeping counters if the time has changed. This transfer process takes
tRTCp time to complete. This bit defaults to 0 on power-up.
R
Read Enable: Setting ‘R’ bit to ‘1’, stops clock updates to user RTC registers so that clock updates are not seen during
the reading process. Set ‘R’ bit to ‘0’ to resume clock updates to the holding register. Setting this bit does not require
‘W’ bit to be set to ‘1’. This bit defaults to ‘0’ on power-up.
Document #: 001-64879 Rev. *B
Page 28 of 41
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CY14C512I
CY14B512I, CY14E512I
Best Practices
■
Power up boot firmware routines should rewrite the nvSRAM
into the desired state (for example, AutoStore enabled). While
the nvSRAM is shipped in a preset state, best practice is to
again rewrite the nvSRAM into the desired state as a safeguard
against events that might flip the bit inadvertently such as
program bugs and incoming inspection routines.
■
The VCAP value specified in this datasheet includes a minimum
and a maximum value size. Best practice is to meet this
requirement and not exceed the maximum VCAP value because
the nvSRAM internal algorithm calculates VCAP charge and
discharge time based on this max VCAP value. Customers that
want to use a larger VCAP value to make sure there is extra store
charge and store time should discuss their VCAP size selection.
■
When base time is updated, these updates are transferred to
the time keeping registers when ‘W’ bit is set to ‘0’. This transfer
takes tRTCp time to complete. It is recommended to initiate
software STORE or Hardware STORE after tRTCp time to save
the base time into nonvolatile memory.
nvSRAM products have been used effectively for over 26 years.
While ease-of-use is one of the product’s main system values,
experience gained working with hundreds of applications has
resulted in the following suggestions as best practices:
■
The nonvolatile cells in this nvSRAM product are delivered by
Cypress with 0x00 written in all cells. Incoming inspection
routines at customer or contract manufacturer’s sites
sometimes reprogram these values. Final NV patterns are
typically repeating patterns of AA, 55, 00, FF, A5, or 5A. End
product’s firmware should not assume an NV array is in a set
programmed state. Routines that check memory content
values to determine first time system configuration, cold or
warm boot status, and so on should always program a unique
NV pattern (that is, complex 4-byte pattern of 46 E6 49 53 hex
or more random bytes) as part of the final system
manufacturing test to ensure these system routines work
consistently.
Document #: 001-64879 Rev. *B
Page 29 of 41
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CY14C512I
CY14B512I, CY14E512I
Maximum Ratings
Transient voltage (<20 ns) on
any pin to ground potential .................. –2.0 V to VCC + 2.0 V
Exceeding maximum ratings may shorten the useful life of the
device. These user guidelines are not tested.
Package power dissipation
capability (TA = 25 °C) .................................................. 1.0 W
Storage temperature ................................ –65 C to +150 C
Maximum accumulated storage time
Surface mount lead soldering
temperature (3 seconds) .......................................... +260 C
At 150 C ambient temperature ....................... 1000 h
DC output current (1 output at a time, 1s duration). .... 15 mA
At 85 C ambient temperature ..................... 20 Years
Static discharge voltage.......................................... > 2001 V
(per MIL-STD-883, Method 3015)
Ambient temperature with
power applied ........................................... –55 C to +150 C
Latch up current..................................................... > 140 mA
Supply voltage on VCC relative to VSS
CY14C512I: VCC = 2.4 V to 2.6 V......–0.5 V to +3.1 V
CY14B512I: VCC = 2.7 V to 3.6 V ......–0.5 V to +4.1 V
CY14E512I: VCC = 4.5 V to 5.5 V ......–0.5 V to +7.0 V
DC voltage applied to outputs
in high Z State...................................... –0.5 V to VCC + 0.5 V
Operating Range
CY14B512I
2.7 V to 3.6 V
Input voltage ........................................ –0.5 V to VCC + 0.5 V
CY14E512I
4.5 V to 5.5 V
Product
CY14C512I
Range
Ambient
Temperature
VCC
Industrial –40 C to +85 C
2.4 V to 2.6 V
DC Electrical Characteristics
Over the Operating Range
Parameter
Description
VCC
Test Conditions
Power supply
Min
Typ[6]
Max
Unit
CY14C512I
2.4
2.5
2.6
V
CY14B512I
2.7
3.0
3.6
V
CY14E512I
4.5
5.0
5.5
V
ICC1
Average VCC current
fSCL = 3.4 MHz;
Values obtained without output loads (IOUT = 0 mA)
–
–
1
mA
ICC2
Average VCC current
during STORE
All inputs don’t care, VCC = max
Average current for duration tSTORE
–
–
2
mA
ICC3
Average VCC current
fSCL = 100 kHz;
VCC = VCC (Typ), 25 °C
All inputs cycling at CMOS levels.
Values obtained without output loads (IOUT = 0 mA)
–
–
1
mA
ICC4
Average VCAP current
during AutoStore cycle
All inputs don't care. Average current for duration tSTORE
–
–
3
mA
ISB
VCC standby current
SCL > (VCC – 0.2 V). VIN < 0.2 V or > (VCC – 0.2 V).
‘W’ bit set to ‘0’. Standby current level after nonvolatile
cycle is complete. Inputs are static. fSCL = 0 MHz.
–
–
250
A
IZZ
Sleep mode current
tSLEEP time after SLEEP Instruction is registered. All
inputs are static and configured at CMOS logic level.
–
–
8
A
IIX[7]
Input current in each I/O pin 0.1 VCC < Vi < 0.9 VCCmax
(except HSB)
–1
–
+1
A
–100
–
+1
A
–1
–
+1
A
–
–
7
pF
Input current in each I/O pin
(for HSB)
IOZ
Output leakage current
Ci
Capacitance for each I/O
pin
Capacitance measured across all input and output
signal pin and VSS.
Notes
6. Typical values are at 25 °C, VCC = VCC (Typ). Not 100% tested.
7. Not applicable to WP, A2, A1 and A0 pins.
Document #: 001-64879 Rev. *B
Page 30 of 41
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CY14B512I, CY14E512I
DC Electrical Characteristics (continued)
Over the Operating Range
Parameter
Description
Test Conditions
Min
Typ[6]
Max
Unit
VIH
Input HIGH voltage
0.7 Vcc
–
VCC + 0.5
V
VIL
Input LOW voltage
– 0.5
–
0.3 VCC
V
VOL
Output LOW voltage
IOL = 3 mA
0
–
0.4
V
Rin[8]
Input resistance (WP, A2,
A1, A0)
For VIN = VIL (Max)
50
–
–
K
For VIN = VIH (Max)
1
–
–
M
0.05 VCC
–
–
V
CY14C512I
170
220
270
F
CY14B512I
CY14E512I
42
47
180
F
Vhys
Hysteresis of Schmitt
trigger inputs
VCAP
Storage capacitor
Between VCAP pin and VSS
Data Retention and Endurance
Parameter
Description
DATAR
Data retention
NVC
Nonvolatile STORE operations
Min
Unit
20
Years
1,000
K
16-pin SOIC
Unit
56.68
C/W
32.11
C/W
Thermal Resistance
Parameter[9]
JA
JC
Description
Thermal resistance
(Junction to ambient)
Thermal resistance
(Junction to case)
Test Conditions
Test conditions follow standard test methods
and procedures for measuring thermal
impedance, according to EIA / JESD51.
Notes
8. The input pull-down circuit is stronger (50 k) when the input voltage is below VIL and weak (1 M) when the input voltage is above VIH.
9. These parameters are guaranteed by design and are not tested.
Document #: 001-64879 Rev. *B
Page 31 of 41
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CY14C512I
CY14B512I, CY14E512I
Figure 39. AC Test Loads and Waveforms
For 3.0 V (CY14B512I)
For 2.5 V (CY14C512I)
For 5.0 V (CY14E512I)
3.0 V
2.5 V
5.0 V
867 
700 
1.6 K
OUTPUT
OUTPUT
OUTPUT
100 pF
100 pF
50 pF
AC Test Conditions
Description
CY14C512I
CY14B512I
CY14E512I
0 V to 2.5 V
0 V to 3 V
0 V to 5 V
Input rise and fall times (10% - 90%)
10 ns
10 ns
10 ns
Input and output timing reference levels
1.25 V
1.5 V
2.5 V
Input pulse levels
RTC Characteristics
Parameters
Description
Min
Typ
Max
Units
1.8
–
3.6
V
–
0.45
0.6
µA
1.6
–
3.6
V
VRTCbat
RTC battery pin voltage
IBAK[10]
RTC backup current
VRTCcap[11]
RTC capacitor pin voltage
VBAKFAIL
Backup failure threshold
1.8
–
2
V
VDR
BPF flag retention voltage
1.6
–
–
V
tOCS
RTC oscillator time to start
–
1
2
sec
tRTCp
RTC processing time from end of ‘W’ bit set to ‘0’
–
–
1
ms
RBKCHG
RTC backup capacitor charge current-limiting resistor
350
–
850

Notes
10. Current drawn from either VRTCcap or VRTCbat when VCC < VSWITCH.
11. If VRTCcap > 0.5 V or if no capacitor is connected to VRTCcap pin, the oscillator will start in tOCS time. If a backup capacitor is connected and VRTCcap < 0.5 V, the
capacitor must be allowed to charge to 0.5 V for oscillator to start.
Document #: 001-64879 Rev. *B
Page 32 of 41
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CY14B512I, CY14E512I
AC Switching Characteristics
Parameter
3.4 MHz[12]
Description
1 MHz[12]
400 kHz[12]
Unit
Min
Max
Min
Max
Min
Max
–
3400
–
1000
–
400
kHz
fSCL
Clock frequency, SCL
tSU; STA
Setup time for Repeated START condition
160
–
250
–
600
–
ns
tHD;STA
Hold time for START condition
160
–
250
–
600
–
ns
tLOW
LOW period of the SCL
160
–
500
–
1300
–
ns
tHIGH
HIGH period of the SCL
60
–
260
–
600
–
ns
tSU;DATA
Data in setup time
10
–
100
–
100
–
ns
tHD;DATA
Data hold time (In/Out)
0
–
0
–
0
–
ns
tDH
Data out hold time
0
–
0
–
0
–
ns
Rise time of SDA and SCL
–
80
–
120
–
300
ns
tr
[13]
tf[13]
Fall time of SDA and SCL
tSU;STO
Setup time for STOP condition
tVD;DATA
tVD;ACK
[13]
–
80
–
120
–
300
ns
160
–
250
–
600
–
ns
Data output valid time
–
130
–
400
–
900
ns
ACK output valid time
–
130
–
400
–
900
ns
–
80
–
120
–
300
ns
tBUF
Bus free time between STOP and next START condition
0.3
–
0.5
–
1.3
–
us
tSP
Pulse width of spikes that must be suppressed by input
filter
–
5
–
50
–
50
ns
tOF
Output fall time from VIH min to VILmax
~
~
~
~
Figure 40. Timing Diagram
tr
~
~
~
~
SDA
t HD;STA
t SU;DATA
t LOW
tf
t SP
t BUF
t HD;DATA
t HIGH
~
~
t HD;STA
S
~
~
SCL
t SU;STA
Sr
tr
tf
t SU;STO
P
S
Note
12. (Bus Load Capacitance (Cb) Considerations; Cb < 500 pF for I2C clock frequency (SCL) 100/400/1000 KHz; Cb <100 pF for SCL at 3.4 MHz).
13. These parameters are guaranteed by design and are not tested.
Document #: 001-64879 Rev. *B
Page 33 of 41
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CY14B512I, CY14E512I
nvSRAM Specifications
Parameter
tFA [14]
Power-up RECALL duration
tSTORE [15]
tDELAY[16]
tVCCRISE[17]
VSWITCH
STORE cycle duration
Time allowed to complete SRAM write cycle
VCC rise time
Low voltage trigger level
tLZHSB[17]
HSB high to nvSRAM active time
HSB output disable voltage
VHDIS[17]
tHHHD[17]
tWAKE
tSLEEP
tSB
Description
CY14C512I
CY14B512I
CY14E512I
CY14C512I
CY14B512I
CY14E512I
HSB HIGH active time
Time for nvSRAM to wake up from SLEEP mode
CY14C512I
CY14B512I
CY14E512I
Time to enter low power mode after issuing SLEEP instruction
Time to enter into standby mode after issuing STOP condition
Min
–
–
–
–
–
150
–
–
–
–
–
Max
40
20
20
8
25
–
2.35
2.65
4.40
5
1.9
Unit
ms
ms
ms
ms
ns
µs
V
V
V
µs
V
–
–
–
–
–
–
500
40
20
20
8
100
ns
ms
ms
ms
ms
µs
Figure 41. AutoStore or Power-Up RECALL[18]
VCC
VSWITCH
VHDIS
t VCCRISE
tHHHD
Note15
15
tSTORE
Note
tHHHD
19
Note
tSTORE
19
Note
HSB OUT
tDELAY
tLZHSB
AutoStore
tLZHSB
tDELAY
POWERUP
RECALL
tFA
tFA
Read & Write
Inhibited
(RWI)
POWER-UP
RECALL
Read & Write
BROWN
OUT
AutoStore
POWER-UP
RECALL
Read & Write
POWER
DOWN
AutoStore
Notes
14. tFA starts from the time VCC rises above VSWITCH.
15. If an SRAM write has not taken place since the last nonvolatile cycle, no AutoStore or Hardware STORE takes place.
16. On a Hardware STORE and AutoStore initiation, SRAM write operation continues to be enabled for time tDELAY.
17. These parameters are guaranteed by design and are not tested.
18. Read and Write cycles are ignored during STORE, RECALL, and while VCC is below VSWITCH.
19. During power-up and power-down, HSB glitches when HSB pin is pulled up through an external resistor.
Document #: 001-64879 Rev. *B
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CY14B512I, CY14E512I
Software Controlled STORE/RECALL Cycles
CY14X512I
Parameter
Description
Unit
Min
Max
tRECALL
RECALL duration
–
600
µs
tSS[20, 21]
Software sequence processing time
–
500
µs
Figure 42. Software STORE/RECALL Cycle[21]
DATA OUTPUT
BY MASTER
Command Reg Address
nvSRAM Control Slave Address
acknowledge (A) by Slave
acknowledge (A) by Slave
SCL FROM
MASTER
1
2
8
9
1
Command Byte (STORE/RECALL)
2
8
9
1
acknowledge (A) by Slave
2
8
9
S
P
START
condition
STOP
condition
RWI
t STORE / t
RECALL
Figure 43. AutoStore Enable/Disable Cycle
DATA OUTPUT
BY MASTER
Command Reg Address
nvSRAM Control Slave Address
acknowledge (A) by Slave
acknowledge (A) by Slave
SCL FROM
MASTER
1
2
S
START
condition
8
9
1
Command Byte (ASENB/ASDISB)
2
8
9
1
acknowledge (A) by Slave
2
8
9
P
STOP
condition
RWI
t SS
Notes
20. This is the amount of time it takes to take action on a soft sequence command. Vcc power must remain HIGH to effectively register command.
21. Commands such as STORE and RECALL lock out I/O until operation is complete which further increases this time. See the specific command.
Document #: 001-64879 Rev. *B
Page 35 of 41
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CY14C512I
CY14B512I, CY14E512I
Hardware STORE Cycle
CY14X512I
Parameter
tPHSB
Description
Unit
Min
Max
15
–
Hardware STORE pulse width
ns
Figure 44. Hardware STORE Cycle[22]
Write Latch set
~
~
tPHSB
HSB (IN)
tSTORE
tHHHD
~
~
tDELAY
HSB (OUT)
tLZHSB
RWI
tPHSB
HSB (IN)
HSB pin is driven HIGH to VCC only by Internal
100 K: resistor, HSB driver is disabled
SRAM is disabled as long as HSB (IN) is driven LOW.
tDELAY
RWI
~
~
HSB (OUT)
~
~
Write Latch not set
Note
22. If an SRAM write has not taken place since the last nonvolatile cycle, no AutoStore or Hardware STORE takes place.
Document #: 001-64879 Rev. *B
Page 36 of 41
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CY14C512I
CY14B512I, CY14E512I
Ordering Information
Ordering Code
Package Diagram
Package Type
Operating Range
51-85022
16-pin SOIC
Industrial
CY14B512I-SFXI
CY14B512I-SFXIT
The above part is Pb-free. This table contains Final information. Contact your local Cypress sales representative for availability of these parts.
Ordering Code Definitions
CY 14 B 512 I - SF X I T
Option:
T - Tape and Reel
Blank - Std.
Temperature:
I - Industrial (-40 to 85 °C)
Pb-free
Package:
SF - 16-pin SOIC
I - Serial (I2C) nvSRAM with RTC
Density:
Voltage:
C - 2.5 V
B - 3.0 V
E - 5.0 V
512 - 512 Kb
14 - nvSRAM
Cypress
Document #: 001-64879 Rev. *B
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CY14C512I
CY14B512I, CY14E512I
Package Diagram
Figure 45. 16-pin (300 mil) SOIC, 51-85022
51-85022 *C
Document #: 001-64879 Rev. *B
Page 38 of 41
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CY14C512I
CY14B512I, CY14E512I
Acronyms
Document Conventions
Acronym
Description
Units of Measure
BCD
Binary coded decimal
CMOS
Complementary metal oxide semiconductor
°C
degrees Celsius
CRC
Cyclic redundancy check
Hz
Hertz
EIA
Electronic industries alliance
kbit
1024 bits
I2C
Inter-integrated circuit bus
kHz
kilo Hertz
I/O
Input/output
K
kilo ohms
JEDEC
Joint Electron Devices Engineering Council
A
micro Amperes
nvSRAM
nonvolatile static random access memory
mA
milli Ampere
OSCF
Oscillator Fail Flag
F
micro Farad
RoHS
Restriction of hazardous substances
Mbit/s
Mega bit per second
R/W
read/write
MHz
Mega Hertz
RWI
Read and write inhibited
s
micro seconds
SCL
Serial clock line
ms
milli seconds
SDA
Serial data line
ns
nano seconds
SNL
serial number lock
pF
pico Farad
SOIC
Small outline integrated circuit
V
Volts

ohms
W
Watts
Document #: 001-64879 Rev. *B
Symbol
Unit of Measure
Page 39 of 41
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CY14C512I
CY14B512I, CY14E512I
Document History Page
Document Title: CY14C512I, CY14B512I, CY14E512I, 512-Kbit (64 K × 8) Serial (I2C) nvSRAM with Real Time Clock
Document Number: 001-64879
Rev.
ECN No.
Submission
Date
Orig. of
Change
**
3089747
11/18/2010
GVCH
New datasheet
*A
3201531
03/21/2011
GVCH
Updated AutoStore Operation (description).
Updated Hardware STORE and HSB pin Operation (Added more clarity on
HSB pin operation).
Updated Table 6 (Product ID column).
Updated Setting the Clock (description).
Updated Figure 37 (changed C1, C2 values to 12 pF, 69 pF from 10 pF,
67 pF respectively).
Updated Register Map Detail table (‘W’ bit description).
Updated Best Practices.
Updated RTC Characteristics (Added tRTCp parameter to the table).
Updated nvSRAM Specifications (tLZHSB parameter description).
Fixed typo error in Figure 41.
Updated in new template.
*B
3248510
05/04/2011
GVCH
Datasheet status changed from “Preliminary” to “Final”
Document #: 001-64879 Rev. *B
Description of Change
Page 40 of 41
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CY14C512I
CY14B512I, CY14E512I
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
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cypress.com/go/USB
cypress.com/go/wireless
© Cypress Semiconductor Corporation, 2010-2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document #: 001-64879 Rev. *B
Revised May 4, 2011
Page 41 of 41
All products and company names mentioned in this document may be the trademarks of their respective holders.
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