Micro Linear ML4950ES Adjustable output, low current single cell boost regulator with detect Datasheet

G
FEATURINperature Range
July 2000
Tem
ommercial
Extended C
70˚C
to
C
0˚
-2
ment
dheld Equip
an
H
e
bl
ta
or
for P
ML4950*
Adjustable Output, Low Current
Single Cell Boost Regulator with Detect
GENERAL DESCRIPTION
FEATURES
The ML4950 is a low power boost regulator designed for
low voltage DC to DC conversion in single cell battery
powered systems. The maximum switching frequency can
exceed 100kHz, allowing the use of small, low cost
inductors.
■
Guaranteed full load start-up and operation at 1V input
■
Pulse Frequency Modulation (PFM) and internal
synchronous rectification for high efficiency
■
Minimum external components
■
Low ON resistance internal switching FETs
■
Micropower operation
■
Adjustable output voltage (2V to 3V)
■
Low battery detect
The combination of integrated synchronous rectification,
variable frequency operation, and low supply current
make the ML4950 ideal for single cell applications. The
ML4950 is capable of start-up with input voltages as low
as 1V, and the output voltage can be set anywhere
between 2V and 3V.
An integrated synchronous rectifier eliminates the need for
an external Schottky diode and provides a lower forward
voltage drop, resulting in higher conversion efficiency. In
addition, low quiescent battery current and variable
frequency operation result in high efficiency even at light
loads. The ML4950 requires a minimum number of
external components and is capable of achieving
conversion efficiencies in excess of 90%.
The circuit also contains a RESET output which goes low
when the IC can no longer function due to low input
voltage, or when the DETECT input drops below 200mV.
*Some Packages Are Obsolete
BLOCK DIAGRAM
7
RESET
DETECT
4
6
VL
+
COMP
VREF
1
–
VIN
START-UP
+
VOUT
5
–
S
Q
R
Q
5µs
ONE SHOT
PWR
GND
8
SENSE
3
–
+
REFERENCE
VREF
VREF
GND
2
1
ML4950
PIN CONFIGURATION
ML4950
8-Pin SOIC (S08)
VIN
1
8
PWR GND
GND
2
7
RESET
SENSE
3
6
VL
DETECT
4
5
VOUT
TOP VIEW
PIN DESCRIPTION
PIN
NAME
FUNCTION
PIN
NAME
FUNCTION
1
VIN
Battery input voltage
5
VOUT
Boost regulator output
2
GND
Analog signal ground
6
VL
Boost inductor connection
3
SENSE
Programming pin for setting the output
voltage
7
RESET
Output goes low when regulation
cannot be achieved, or when DETECT
goes below 200mV
4
DETECT
Pulling this pin below 200mV causes
the RESET pin to go low
8
PWR GND Return for the NMOS output transistor
2
ML4950
ABSOLUTE MAXIMUM RATINGS
OPERATING CONDITIONS
Absolute maximum ratings are those values beyond which
the device could be permanently damaged. Absolute
maximum ratings are stress ratings only and functional
device operation is not implied.
Temperature Range
ML4950CS-X .............................................. 0ºC to 70ºC
ML4950ES-X ........................................... -20ºC to 70ºC
VIN Operating Range
ML4950CS-X ................................. 1.0V to VOUT - 0.2V
ML4950ES-X ................................. 1.1V to VOUT - 0.2V
VOUT Operating Range ....................................... 2V to 3V
VOUT ............................................................................................... 7V
Voltage on Any Other Pin ..... GND - 0.3V to VOUT + 0.3V
Peak Switch Current (IPEAK) .......................................... 1A
Average Switch Current (IAVG) .............................. 250mA
Junction Temperature .............................................. 150ºC
Storage Temperature Range...................... –65ºC to 150ºC
Lead Temperature (Soldering, 10 sec) ...................... 150ºC
Thermal Resistance (qJA) .................................... 160ºC/W
ELECTRICAL CHARACTERISTICS
Unless otherwise specified, VIN = Operating Voltage Range, TA = Operating Temperature Range (Note 1)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
50
60
µA
8
10
µA
1
µA
SUPPLY
IIN
VIN Current
IOUT(Q)
IL(Q)
VIN = VOUT - 0.2V
VOUT Quiescent Current
VL Quiescent Current
PFM REGULATOR
tON
VSENSE
Pulse Width
4.5
5
5.5
µs
SENSE Compator Threshold Voltage
196
201
208
mV
2.425
2.5
2.575
V
0.85
0.95
V
200
206
mV
100
nA
Load Regulation
See Figure 1
VIN = 1.2V, IOUT £ 25mA
Undervoltage Lockout Threshold
RESET COMPARATOR
Note 1:
DETECT Threshold Voltage
194
DETECT Bias Current
-100
RESET Output High Voltage
IOH = -100µA
RESET Output Low Voltage
IOL = 100µA
VOUT-0.2
V
0.2
V
Limits are guaranteed by 100% testing, sampling, or correlation with worst-case test conditions.
3
ML4950
27µH
(Sumida CD75)
ML4950
VIN
VIN
PWR GND
RESET
GND
100µF
SENSE
VL
DETECT
IOUT
VOUT
VOUT
464kΩ
0.1%
100µF
40.2kΩ
0.1%
Figure 1. Application Test Circuit.
L1
VIN
6
VL
START-UP
Q2
VOUT
+
A2
–
+
5
C1
Q1
S
Q
R
Q
5µs
ONE SHOT
–
R1
SENSE
3
–
A1
+
VREF
R2
Figure 2. PFM Regulator Block Diagram.
INDUCTOR
CURRENT
Q(ONE SHOT)
Q1 ON
Q2
ON
Q1 ON
Q2
ON
Q1 & Q2 OFF
Figure 3. PFM Inductor Current Waveforms and Timing.
4
VOUT
ML4950
FUNCTIONAL DESCRIPTION
DESIGN CONSIDERATIONS
The ML4950 combines Pulse Frequency Modulation (PFM)
and synchronous rectification to create a boost converter
that is both highly efficient and simple to use. A PFM
regulator charges a single inductor for a fixed period of
time and then completely discharges before another cycle
begins, simplifying the design by eliminating the need for
conventional current limiting circuitry. Synchronous
rectification is accomplished by replacing an external
Schottky diode with an on-chip PMOS device, reducing
switching losses and external component count.
INDUCTOR
REGULATOR OPERATION
A block diagram of the boost converter is shown in Figure
2. The circuit remains idle when VOUT is at or above the
desired output voltage, drawing 50µA from VIN, and 8µA
from VOUT through the feedback resistors R1 and R2.
When VOUT drops below the desired output level, the
output of amplifier A1 goes high, signaling the regulator to
deliver charge to the output. Since the output of amplifier
A2 is normally high, the flip-flop captures the A1 set signal
and creates a pulse at the gate of the NMOS transistor Q1.
The NMOS transistor will charge the inductor L1 for 5µs,
resulting in a peak current given by:
IL(PEAK)
t ™ VIN 5ms ™ VIN
= ON
=
L1
L1
(1)
For reliable operation, L1 should be chosen so that IL(PEAK)
does not exceed 1A.
When the one-shot times out, the NMOS transistor
releases the VL pin, allowing the inductor to fly-back and
momentarily charge the output through the body diode of
PMOS transistor Q2. But as the voltage across the PMOS
transistor changes polarity, its gate will be driven low by
the current sense amplifier A2, causing Q2 to short out its
body diode. The inductor then discharges into the load
through Q2. The output of A2 also serves to reset the flipflop and one-shot in preparation for the next charging
cycle. A2 releases the gate of Q2 when its current falls to
zero. If VOUT is still low, the flip-flop will immediately
initiate another pulse. The output capacitor (C1) filters the
inductor current, limiting output voltage ripple. Inductor
current and one-shot waveforms are shown in Figure 3.
RESET COMPARATOR
An additional comparator is provided to detect low VIN or
any other error condition that is important to the user. The
inverting input of the comparator is internally connected
to VREF, while the non-inverting input is provided
externally at the DETECT pin. The output of the
comparator is the RESET pin, which swings from VOUT to
GND when an error is detected.
Selecting the proper inductor for a specific application
usually involves a trade-off between efficiency and
maximum output current. Choosing too high a value will
keep the regulator from delivering the required output
current under worst case conditions. Choosing too low a
value causes efficiency to suffer. It is necessary to know
the maximum required output current and the input
voltage range to select the proper inductor value. The
maximum inductor value can be estimated using the
following formula:
LMAX =
VIN( MIN) 2 ™ t ON( MIN) ™ h
2 ™ VOUT ™ IOUT( MAX)
(2)
where h is the efficiency, typically between 0.8 and 0.9.
Note that this is the value of inductance that just barely
delivers the required output current under worst case
conditions. A lower value may be required to cover
inductor tolerance, the effect of lower peak inductor
currents caused by resistive losses, and minimum dead
time between pulses.
Another method of determining the appropriate inductor
value is to make an estimate based on the typical
performance curves given in Figures 4 and 5. Figure 4
shows maximum output current as a function of input
voltage for several inductor values. These are typical
performance curves and leave no margin for inductance
and ON-time variations. To accommodate worst case
conditions, it is necessary to derate these curves by at least
10% in addition to inductor tolerance.
For example, a single cell to 2.5 V application requires
20mA of output current while using an inductor with 15%
tolerance. The output current should be derated by 25% to
25mA to cover the combined inductor and ON-time
tolerances. Assuming that 1V is the end of life voltage of a
single cell input, Figure 4 shows that with the ML4950
delivers 25mA at 2.5V with a 27µH inductor.
Figure 5 shows efficiency under the conditions used to
create Figure 4. It can be seen that efficiency is mostly
independent of input voltage and is closely related to
inductor value. This illustrates the need to keep the
inductor value as high as possible to attain peak system
efficiency. As the inductor value goes down to 18µH, the
efficiency drops to between 75% and 80%. With 68µH,
the efficiency exceeds 90% and there is little room for
improvement. At values greater than 100µH, the operation
of the synchronous rectifier becomes unreliable because
the inductor current is so small that it is difficult for the
control circuitry to detect. The data used to generate
Figures 4 and 5 is provided in Table 1.
5
ML4950
DESIGN CONSIDERATIONS (Continued)
After the appropriate inductor value is chosen, it is
necessary to find the minimum inductor current rating
required. Peak inductor current is determined from the
following formula:
IL(PEAK) =
t ON( MAX) ™ VIN( MAX)
(3)
LMIN
In the single cell application previously described, a
maximum input voltage of 1.6V would give a peak current
of 383mA. When comparing various inductors, it is
important to keep in mind that suppliers use different
criteria to determine their ratings. Many use a conservative
current level, where inductance has dropped to 90% of its
normal level. In any case, it is a good idea to try inductors
of various current ratings with the ML4950 to determine
which inductor is the best choice. Check efficiency and
maximum output current, and if a current probe is
available, look at the inductor current to see if it looks like
the waveform shown in Figure 3. For additional
information, see Application Note 29.
Suitable inductors can be purchased from the following
suppliers:
Coilcraft
(847) 639-6400
Coiltronics
(561) 241-7876
Dale
(605) 665-9301
Sumida
(847) 956-0666
Capacitor Equivalent Series Resistance (ESR) and
Equivalent Series Inductance (ESL), also contribute to the
output ripple due to the inductor discharge current
waveform. Just after the NMOS transistor turns off, the
output current ramps quickly to match the peak inductor
current. This fast change in current through the output
capacitor’s ESL causes a high frequency (5ns) spike that
can be over 1V in magnitude. After the ESL spike settles,
the output voltage still has a ripple component equal to
the inductor discharge current times the ESR. This
component will have a sawtooth shape and a peak value
equal to the peak inductor current times the ESR. ESR also
has a negative effect on efficiency by contributing I2R
losses during the discharge cycle.
An output capacitor with a capacitance of 100µF, an ESR
of less than 0.1W, and an ESL of less than 5nH is a good
general purpose choice. Tantalum capacitors which meet
these requirements can be obtained from the following
suppliers:
AVX
(207) 282-5111
Sprague
(207) 324-4140
If ESL spikes are causing output noise problems, an EMI
filter can be added in series with the output.
INPUT CAPACITOR
XFMRS, Inc. (317) 834-1066
OUTPUT CAPACITOR
The choice of output capacitor is also important, as it
controls the output ripple and optimizes the efficiency of
the circuit. Output ripple is influenced by three
parameters: capacitance, ESR, and ESL. The contribution
due to capacitance can be determined by looking at the
change in capacitor voltage required to store the energy
delivered by the inductor in a single charge-discharge
cycle, as determined by the following formula:
DVOUT =
t ON2 ™ VIN2
2 ™ L ™ C ™ VOUT - VIN
1
6
(4)
For a 1.2V input, a 2.5V output, a 27µH inductor, and a
47µF capacitor, the expected output ripple due to
capacitor value is 11mV.
Unless the input source is a very low impedance battery, it
will be necessary to decouple the input with a capacitor
with a value of between 47µF and 100µF. This prevents
input ripple from affecting the ML4950 control circuitry,
and it also improves efficiency by reducing I2R losses
during the charge and discharge cycles of the inductor.
Again, a low ESR capacitor (such as tantalum) is
recommended.
SETTING THE OUTPUT VOLTAGE
The adjustable output can be set to any voltage between
2V and 3V by connecting a resistor divider to the SENSE
pin as shown in the block diagram. The resistor values R1
and R2 can be calculated using the following equation:
VOUT = 0.2 ™
1
2
R2
(5)
The value of R2 should be 40kW or less to minimize bias
current errors. R1 is then found by rearranging the
equation:
R1 = R 2 ™
6
1R + R 6
V - 1
0.2 OUT
(6)
ML4950
140
95
L = 18µH
VOUT = 2V
VOUT = 2V
120
L = 68µH
90
IOUT (mA)
L = 33µH
80
L = 47µH
60
EFFICIENCY (%)
100
L = 47µH
L = 33µH
85
L = 68µH
40
80
L = 18µH
20
0
1.0
1.2
1.4
75
1.0
1.8
1.6
1.2
VIN (V)
1.4
1.6
1.8
VIN (V)
140
95
L = 18µH
VOUT = 2.5V
VOUT = 2.5V
120
L = 68µH
90
100
IOUT (mA)
80
L = 47µH
60
EFFICIENCY (%)
L = 47µH
L = 33µH
L = 33µH
85
L = 18µH
40
80
L = 68µH
20
0
1.0
1.2
1.4
75
1.0
1.8
1.6
1.2
VIN (V)
1.8
95
VOUT = 3V
L = 18µH
VOUT = 3V
70
L = 68µH
L = 33µH
50
40
L = 47µH
EFFICIENCY (%)
90
60
IOUT (mA)
1.6
VIN (V)
90
80
1.4
L = 47µH
L = 33µH
85
L = 18µH
30
L = 68µH
20
80
10
0
1.0
1.2
1.4
1.6
VIN (V)
Figure 4. Output Current vs Input Voltage
1.8
75
1.0
1.2
1.4
1.6
1.8
VIN (V)
Figure 5. Typical Efficiency as a Function of VIN
7
ML4950
DESIGN CONSIDERATIONS (Continued)
It is important to note that the accuracy of these resistors
directly affects the accuracy of the output voltage. The
SENSE pin threshold variation is ±3%, and the tolerance of
R1 and R2 will add to this to determine the total output
variation.
LAYOUT
Under some circumstances, input ripple cannot be
reduced effectively. This occurs primarily in applications
where inductor currents are high, causing excess output
ripple due to “pulse grouping”, where the chargedischarge pulses are not evenly spaced in time. In such
cases it may be necessary to add a small 20pF to 100pF
ceramic feedforward capacitor (CFF) from the VIN pin to
the SENSE pin. This is particularly true if the ripple voltage
at VIN is greater than 100mV.
■
Use adequate ground and power traces or planes
■
Keep components as close as possible to the ML4950
■
Use short trace lengths from the inductor to the VL pin
and from the output capacitor to the VOUT pin
■
Use a single point ground for the ML4950 PWR GND
pin and the input and output capacitors, and connect
GND to PWR GND with a separate trace
SETTING THE RESET THRESHOLD
To use the RESET comparator as an input voltage monitor,
it is necessary to use an external resistor divider tied to the
DETECT pin as shown in Figure 7. The resistor values RA
and RB can be calculated using the following equation:
VIN( MIN) = 0.2 ™
1R
A
+ RB
6
V
0.2
RB
IN( MIN)
A typical PC board layout is shown in Figure 8.
7
VIN
RESET
1
(7)
The value of RB should be 100kW or less to minimize bias
current errors. RA is then found by rearranging the
equation:
R A = RB ™
Good PC board layout practices will ensure the proper
operation of the ML4950. Important layout considerations
include:
-1
RA
DETECT
4
+
COMP
RB
VREF
–
(8)
FROM
START-UP
CIRCUITRY
Figure 7. Battery Monitoring Circuit
80
60
IIN (µA)
2V OUTPUT
3V OUTPUT
40
20
0
1.0
1.5
2.0
2.5
3.0
VIN (V)
Figure 6. No Load Input Current vs. VIN
For 2V, R1 = 365kW, R2 = 40.2kW
For 3V, R1 = 562kW, R2 = 40.2kW
L = Sumida CD43, 22µH
8
Figure 8. Typical PC Board Layout
ML4950
VOUT = 2V
VIN
L = 18µH
1.0
1.2
1.4
1.6
1.8
L = 33µH
1.0
1.2
1.4
1.6
1.8
L = 47µH
1.0
1.2
1.4
1.6
1.8
L = 68µH
1.0
1.2
1.4
1.6
1.8
VOUT = 2.5V
IOUT (mA)
EFFICIENCY (%)
45.8
65.8
89.4
111.7
132.9
77.5
78.0
78.3
78.9
79.8
27.9
41.9
57.8
73.7
89.8
83.6
84.5
85.0
85.6
86.4
20.1
31.6
43.7
57.5
70.1
85.1
86.6
87.4
87.5
88.9
14.9
23.3
32.6
43.5
54.6
86.5
88.5
89.1
89.6
90.9
VIN
IOUT (mA)
EFFICIENCY (%)
38.3
54.5
74.6
98.5
124
80.0
80.2
80.5
80.8
81.0
22.7
33.0
47.0
61.8
79.3
84.2
85.2
86.0
86.6
87.0
16.4
24.1
33.4
46.1
58.6
86.2
87.1
88.1
89.0
89.5
12.6
17.4
25.2
33.9
43.8
86.4
87.9
89.2
90.1
90.9
L = 18µH
1.0
1.2
1.4
1.6
1.8
L = 33µH
1.0
1.2
1.4
1.6
1.8
L = 47µH
1.0
1.2
1.4
1.6
1.8
L = 68µH
1.0
1.2
1.4
1.6
1.8
VOUT = 3V
VIN
L = 18µH
1.0
1.2
1.4
1.6
1.8
L = 33µH
1.0
1.2
1.4
1.6
1.8
L = 47µH
1.0
1.2
1.4
1.6
1.8
L = 68µH
1.0
1.2
1.4
1.6
1.8
IOUT (mA)
EFFICIENCY (%)
30.9
43.8
55.4
65.6
84.4
81.6
81.9
82.1
82.2
82.3
18.7
27.9
38.1
50.6
65.4
85.1
85.6
86.4
86.9
87.5
13.3
19.9
27.9
36.7
47.4
84.7
86.5
87.7
88.5
89.1
9.2
14.0
20.5
27.6
35.7
84.7
86.3
88.2
89.1
90.2
Table 1. Typical IOUT and Efficiency vs. VIN
9
ML4950
PHYSICAL DIMENSIONS inches (millimeters)
Package: S08
8-Pin SOIC
0.189 - 0.199
(4.80 - 5.06)
8
PIN 1 ID
0.148 - 0.158 0.228 - 0.244
(3.76 - 4.01) (5.79 - 6.20)
1
0.017 - 0.027
(0.43 - 0.69)
(4 PLACES)
0.050 BSC
(1.27 BSC)
0.059 - 0.069
(1.49 - 1.75)
0º - 8º
0.055 - 0.061
(1.40 - 1.55)
0.012 - 0.020
(0.30 - 0.51)
0.004 - 0.010
(0.10 - 0.26)
0.015 - 0.035
(0.38 - 0.89)
0.006 - 0.010
(0.15 - 0.26)
SEATING PLANE
ORDERING INFORMATION
© Micro Linear 1998.
PART NUMBER
TEMPERATURE RANGE
PACKAGE
ML4950CS
ML4950ES (Obsolete)
0°C to 70°C
–20°C to 70°C
8-Pin SOIC (S08)
8-Pin SOIC (S08)
is a registered trademark of Micro Linear Corporation. All other trademarks are the property of their respective owners.
Products described herein may be covered by one or more of the following U.S. patents: 4,897,611; 4,964,026; 5,027,116; 5,281,862; 5,283,483;
5,418,502; 5,508,570; 5,510,727; 5,523,940; 5,546,017; 5,559,470; 5,565,761; 5,592,128; 5,594,376; 5,652,479; 5,661,427; 5,663,874; 5,672,959;
5,689,167; 5,714,897; 5,717,798; 5,742,151; 5,754,012; 5,757,174. Japan: 2,598,946; 2,619,299; 2,704,176. Other patents are pending.
Micro Linear reserves the right to make changes to any product herein to improve reliability, function or design. Micro Linear does not assume any
liability arising out of the application or use of any product described herein, neither does it convey any license under its patent right nor the rights of
others. The circuits contained in this data sheet are offered as possible applications only. Micro Linear makes no warranties or representations as to
whether the illustrated circuits infringe any intellectual property rights of others, and will accept no responsibility or liability for use of any application
herein. The customer is urged to consult with appropriate legal counsel before deciding on a particular application.
10
DS4950-01
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San Jose, CA 95131
Tel: 408/433-5200
Fax: 408/432-0295
www.microlinear.com
7/18/98 Printed in U.S.A.
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