MOTOROLA MCM63Z819TQ15R 128k x 36 and 256k x 18 bit flow-through zbt ram synchronous fast static ram Datasheet

MOTOROLA
Order this document
by MCM63Z737/D
SEMICONDUCTOR TECHNICAL DATA
Advance Information
128K x 36 and 256K x 18 Bit
Flow–Through ZBT RAM
Synchronous Fast Static RAM
MCM63Z737
MCM63Z819
The ZBT RAM is a 4M–bit synchronous fast static RAM designed to provide
zero bus turnaround. The ZBT RAM allows 100% use of bus cycles during
back–to–back read/write and write/read cycles. The MCM63Z737 is organized
as 128K words of 36 bits each and the MCM63Z819 is organized as 256K words
of 18 bits each, fabricated with high performance silicon gate CMOS technology.
This device integrates input registers, a 2–bit address counter, and high speed
SRAM onto a single monolithic circuit for reduced parts count in communication
applications. Synchronous design allows precise cycle control with the use of an
external clock (CK). CMOS circuitry reduces the overall power consumption of
the integrated functions for greater reliability.
Addresses (SA), data inputs (DQ), and all control signals except output enable
(G) and linear burst order (LBO) are clock (CK) controlled through positive–
edge–triggered noninverting registers.
Write cycles are internally self–timed and are initiated by the rising edge of the
clock (CK) input. This feature eliminates complex off–chip write pulse generation
and provides increased timing flexibility for incoming signals.
For read cycles, a flow–through SRAM allows output data to simply flow freely
from the memory array.
TQ PACKAGE
TQFP
CASE 983A–01
• 3.3 V LVTTL and LVCMOS Compatible
• MCM63Z737/MCM63Z819–11 = 11 ns Access/15 ns Cycle (66 MHz)
MCM63Z737/MCM63Z819–15 = 15 ns Access/20 ns Cycle (50 MHz)
• Selectable Burst Sequencing Order (Linear/Interleaved)
• Internally Self–Timed Write Cycle
• Single–Cycle Deselect
• Byte Write Control
• ADV Controlled Burst
• 100–Pin TQFP Package
ZBT and Zero Bus Turnaround are trademarks of Integrated Device Technology, Inc., and the architecture is supported by
Micron Technology, Inc. and Motorola, Inc.
This document contains information on a new product. Specifications and information herein are subject to change without notice.
2/6/98

Motorola, Inc. 1998
MOTOROLA
FAST SRAM
MCM63Z737DMCM63Z819
1
SA
SA
SE1
SE2
SBd
SBc
SBb
SBa
SE3
VDD
VSS
CK
SW
CKE
G
ADV
NC
NC
SA
SA
PIN ASSIGNMENT
100 99 98 97 9695 94 93 92 91 90 89 88 87 86 85 84 83 82 81
1
80
2
79
3
78
4
77
5
76
6
75
7
74
8
73
9
72
10
71
11
70
12
69
13
68
14
67
15
66
16
65
17
64
18
63
19
62
20
61
21
60
22
59
23
58
24
57
25
56
26
55
27
54
28
53
29
52
30
51
31 32 33 34 35 36 3738 39 40 41 42 43 44 4546 47 48 49 50
DQb
DQb
DQb
VDDQ
VSS
DQb
DQb
DQb
DQb
VSS
VDDQ
DQb
DQb
VSS
VSS
VDD
VSS
DQa
DQa
VDDQ
VSS
DQa
DQa
DQa
DQa
VSS
VDDQ
DQa
DQa
DQa
LBO
SA
SA
SA
SA
SA1
SA0
NC
NC
VSS
VDD
NC
NC
SA
SA
SA
SA
SA
SA
SA
DQc
DQc
DQc
VDDQ
VSS
DQc
DQc
DQc
DQc
VSS
VDDQ
DQc
DQc
VSS
VDD
VDD
VSS
DQd
DQd
VDDQ
VSS
DQd
DQd
DQd
DQd
VSS
VDDQ
DQd
DQd
DQd
TOP VIEW
MCM63Z737
MCM63Z737DMCM63Z819
2
MOTOROLA FAST SRAM
SA
SA
SE1
SE2
NC
NC
SBb
SBa
SE3
VDD
VSS
CK
SW
CKE
G
ADV
NC
NC
SA
SA
PIN ASSIGNMENT
100 99 98 97 9695 94 93 92 91 90 89 88 87 86 85 84 83 82 81
1
80
2
79
3
78
4
77
5
76
6
75
7
74
8
73
9
72
10
71
11
70
12
69
13
68
14
67
15
66
16
65
17
64
18
63
19
62
20
61
21
60
22
59
23
58
24
57
25
56
26
55
27
54
28
53
29
52
30
51
31 32 33 34 35 36 3738 39 40 41 42 43 44 4546 47 48 49 50
SA
NC
NC
VDDQ
VSS
NC
DQa
DQa
DQa
VSS
VDDQ
DQa
DQa
VSS
VSS
VDD
VSS
DQa
DQa
VDDQ
VSS
DQa
DQa
NC
NC
VSS
VDDQ
NC
NC
NC
LBO
SA
SA
SA
SA
SA1
SA0
NC
NC
VSS
VDD
NC
NC
SA
SA
SA
SA
SA
SA
SA
NC
NC
NC
VDDQ
VSS
NC
NC
DQb
DQb
VSS
VDDQ
DQb
DQb
VSS
VDD
VDD
VSS
DQb
DQb
VDDQ
VSS
DQb
DQb
DQb
NC
VSS
VDDQ
NC
NC
NC
TOP VIEW
MCM63Z819
MOTOROLA FAST SRAM
MCM63Z737DMCM63Z819
3
MCM63Z737 PIN DESCRIPTIONS
Pin Locations
Symbol
Type
85
ADV
Input
Synchronous Load/Advance: Loads a new address into counter when
low. RAM uses internally generated burst addresses when high.
89
CK
Input
Clock: This signal registers the address, data in, and all control signals
except G and LBO.
87
CKE
Input
Clock Enable: Disables the CK input when CKE is high.
DQx
I/O
86
G
Input
Asynchronous Output Enable.
31
LBO
Input
Linear Burst Order Input: This pin must remain in steady state (this
signal not registered or latched). It must be tied high or low.
Low – linear burst counter.
High – interleaved burst counter.
32, 33, 34, 35, 44, 45, 46,
47, 48, 49, 50, 81, 82, 99, 100
SA
Input
Synchronous Address Inputs: These inputs are registered and must
meet setup and hold times.
36, 37
SA0, SA1
Input
Synchronous Burst Address Inputs: The two LSB’s of the address field.
These pins must preset the burst address counter values. These inputs
are registered and must meet setup and hold times.
93, 94, 95, 96
(a) (b) (c) (d)
SBx
Input
Synchronous Byte Write Inputs: Enables write to byte “x”
(byte a, b, c, d) in conjunction with SW. Has no effect on read cycles.
98
SE1
Input
Synchronous Chip Enable: Active low to enable chip.
97
SE2
Input
Synchronous Chip Enable: Active high for depth expansion.
92
SE3
Input
Synchronous Chip Enable: Active low for depth expansion.
88
SW
Input
Synchronous Write: This signal writes only those bytes that have been
selected using the byte write SBx pins.
15, 16, 41, 65, 91
VDD
Supply
Core Power Supply.
4, 11, 20, 27, 54, 61, 70, 77
VDDQ
Supply
I/O Power Supply.
5, 10, 14, 17, 21, 26, 40,
55, 60, 64, 66, 67, 71, 76, 90
VSS
Supply
Ground.
38, 39, 42, 43, 83, 84
NC
—
(a) 51, 52, 53, 56, 57, 58, 59, 62, 63
(b) 68, 69, 72, 73, 74, 75, 78, 79, 80
(c) 1, 2, 3, 6, 7, 8, 9, 12, 13
(d) 18, 19, 22, 23, 24, 25, 28, 29, 30
MCM63Z737DMCM63Z819
4
Description
Synchronous Data I/O: “x” refers to the byte being read or written
(byte a, b, c, d).
No Connection: There is no connection to the chip.
MOTOROLA FAST SRAM
MCM63Z819 PIN DESCRIPTIONS
Pin Locations
Symbol
Type
85
ADV
Input
Synchronous Load/Advance: Loads a new address into counter when
low. RAM uses internally generated burst addresses when high.
89
CK
Input
Clock: This signal registers the address, data in, and all control signals
except G and LBO.
87
CKE
Input
Clock Enable: Disables the CK input when CKE is high.
DQx
I/O
86
G
Input
Asynchronous Output Enable.
31
LBO
Input
Linear Burst Order Input: This pin must remain in steady state (this
signal not registered or latched). It must be tied high or low.
Low – linear burst counter.
High – interleaved burst counter.
32, 33, 34, 35, 44, 45, 46,
47, 48, 49, 50, 80, 81, 82, 99, 100
SA
Input
Synchronous Address Inputs: These inputs are registered and must
meet setup and hold times.
36, 37
SA0, SA1
Input
Synchronous Burst Address Inputs: The two LSB’s of the address field.
These pins must preset the burst address counter values. These inputs
are registered and must meet setup and hold times.
93, 94
(a) (b)
SBx
Input
Synchronous Byte Write Inputs: Enables write to byte “x”
(byte a, b) in conjunction with SW. Has no effect on read cycles.
98
SE1
Input
Synchronous Chip Enable: Active low to enable chip.
97
SE2
Input
Synchronous Chip Enable: Active high for depth expansion.
92
SE3
Input
Synchronous Chip Enable: Active low for depth expansion.
88
SW
Input
Synchronous Write: This signal writes only those bytes that have been
selected using the byte write SBx pins.
(a) 58, 59, 62, 63, 68, 69, 72, 73, 74
(b) 8, 9, 12, 13, 18, 19, 22, 23, 24
Description
Synchronous Data I/O: “x” refers to the byte being read or written
(byte a, b).
15, 16, 41, 65, 91
VDD
Supply
Core Power Supply.
4, 11, 20, 27, 54, 61, 70, 77
VDDQ
Supply
I/O Power Supply.
5, 10, 14, 17, 21, 26, 40,
55, 60, 64, 66, 67, 71, 76, 90
VSS
Supply
Ground.
1, 2, 3, 6, 7, 25, 28, 29, 30, 38,
39, 42, 43, 51, 52, 53, 56, 57,
75, 78, 79, 83, 84, 95, 96
NC
—
MOTOROLA FAST SRAM
No Connection: There is no connection to the chip.
MCM63Z737DMCM63Z819
5
TRUTH TABLE
CK
CKE
E
SW
SBx
ADV
SA0 –
SAx
Input Command
Code
Notes
L–H
1
X
X
X
X
X
Hold
H
1, 2
L–H
0
False
X
X
0
X
Deselect
D
1, 2
L–H
0
True
0
V
0
V
Load Address, New Write
W
1, 2, 3, 4, 5
L–H
0
True
1
L–H
0
X
X
X
0
V
Load Address, New Read
R
1, 2
V (W)
1
X
Burst
B
1, 2, 4,
6 7
6,
X (R, D)
Next Operation
Continue
NOTES:
1. X = don‘t care, 1 = logic high, 0 = logic low, V = valid signal, according to AC Operating Conditions and Characteristics.
2. E = true if SE1 and SE3 = 0, and SE2 = 1.
3. Byte write enables, SBx, are evaluated only as new write addresses are loaded.
4. No control inputs except CKE, SBx, and ADV are recognized in a clock cycle where ADV is sampled high.
5. A write with SBx not valid does load addresses.
6. A burst write with SBx not valid does increment address.
7. ADV controls whether the RAM enters burst mode. If the previous cycle was a write, then ADV = 1 results in a burst write. If the previous
cycle is a read, then ADV = 1 results in a burst read. ADV = 1 will also continue a deselect cycle.
WRITE TRUTH TABLE
SW
SBa
SBb
SBc
(See Note 1)
SBd
(See Note 1)
Read
H
X
X
X
X
Write Byte a
L
L
H
H
H
Write Byte b
L
H
L
H
H
Write Byte c (See Note 1)
L
H
H
L
H
Write Byte d (See Note 1)
L
H
H
H
L
Write All Bytes
L
L
L
L
L
Cycle Type
NOTE:
1. Valid only for MCM63Z737.
LINEAR BURST ADDRESS TABLE (LBO = VSS)
1st Address (External)
2nd Address (Internal)
3rd Address (Internal)
4th Address (Internal)
X . . . X00
X . . . X01
X . . . X10
X . . . X11
X . . . X01
X . . . X10
X . . . X11
X . . . X00
X . . . X10
X . . . X11
X . . . X00
X . . . X01
X . . . X11
X . . . X00
X . . . X01
X . . . X10
INTERLEAVED BURST ADDRESS TABLE (LBO = VDD)
1st Address (External)
2nd Address (Internal)
3rd Address (Internal)
4th Address (Internal)
X . . . X00
X . . . X01
X . . . X10
X . . . X11
X . . . X01
X . . . X00
X . . . X11
X . . . X10
X . . . X10
X . . . X11
X . . . X00
X . . . X01
X . . . X11
X . . . X10
X . . . X01
X . . . X00
MCM63Z737DMCM63Z819
6
MOTOROLA FAST SRAM
INPUT COMMAND CODE AND STATE NAME DEFINITION DIAGRAM
INPUT
COMMAND
CODE
D
B
DESELECT
CONTINUE
DESELECT
W
B
NEW WRITE
BURST
WRITE
R
B
NEW READ
BURST
READ
H
HOLD
CK
CKE
E
FALSE
SA0 – SAx
TRUE
TRUE
VALID
VALID
ADV
SW
SBX
VALID
VALID
NOTE: Cycles are named for their control inputs, not for data I/O state.
MOTOROLA FAST SRAM
MCM63Z737DMCM63Z819
7
B
B
BURST
READ
D
BURST
WRITE
W
R
R
B
B
D
D
W
NEW
READ
R
R
D
NEW
WRITE
W
W
B
W
R
DESELECT
KEY:
D
CURRENT
STATE (n)
ƒ
NEXT
STATE (n + 1)
TRANSITION
NOTES:
1. Input command codes (D, W, R, and B) represent control pin inputs
as indicated in the Truth Table.
2. Hold (i.e., CKE sampled high) is not shown simply because
CKE = 1 blocks clock input and therefore, blocks any state change.
INPUT
COMMAND
CODE
Figure 1. ZBT RAM State Diagram
STATE
n
n+1
n+2
n+3
CK
COMMAND
CODE
ƒ
DQ
CURRENT
STATE
NEXT
STATE
Figure 2. State Definitions for ZBT RAM State Diagram
MCM63Z737DMCM63Z819
8
MOTOROLA FAST SRAM
D
B
HIGH–Z
R
W
D
R
D
B
DATA OUT
(Q VALID)
W
B
W
HIGH–Z
(DATA IN)
R
KEY:
CURRENT
STATE (n)
NEXT STATE
n+1
NOTES:
1. Input command codes (D, W, R, and B) represent control
pin inputs as indicated in the Truth Table.
2. Hold (i.e., CKE sampled high) is not shown simply because CKE = 1 blocks clock input and therefore, blocks
any state change.
ƒ
INPUT
COMMAND
CODE
Figure 3. Data I/O State Diagram
STATE
n
n+1
n+2
n+3
CK
COMMAND
CODE
ƒ
DQ
CURRENT
STATE
NEXT
STATE
Figure 4. State Definitions for ZBT RAM State Diagram
MOTOROLA FAST SRAM
MCM63Z737DMCM63Z819
9
ABSOLUTE MAXIMUM RATINGS (See Note 1)
Rating
Symbol
Value
Unit
VDD
– 0.5 to + 4.6
V
VDDQ
VSS – 0.5 to VDD
V
2
Vin, Vout
– 0.5 to VDD + 0.5
V
2
Input Voltage (Three State I/O)
VIT
VSS – 0.5 to
VDDQ + 0.5
V
2
Output Current (per I/O)
Iout
± 20
mA
Package Power Dissipation
PD
1.3
W
Tbias
– 10 to 85
°C
Tstg
– 55 to 125
°C
Power Supply Voltage
I/O Supply Voltage
Input Voltage Relative to VSS for
Any Pin Except VDD
Temperature Under Bias
Storage Temperature
Notes
This device contains circuitry to protect the
inputs against damage due to high static voltages or electric fields; however, it is advised
that normal precautions be taken to avoid
application of any voltage higher than maximum rated voltages to this high–impedance
circuit.
3
NOTES:
1. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are
exceeded. Functional operation should be restricted to RECOMMENDED
OPERATING CONDITIONS. Exposure to higher than recommended voltages for
extended periods of time could affect device reliability.
2. This is a steady–state DC parameter that is in effect after the power supply has
achieved its nominal operating level. Power sequencing is not necessary.
3. Power dissipation capability is dependent upon package characteristics and use
environment. See Package Thermal Characteristics.
PACKAGE THERMAL CHARACTERISTICS
Thermal Resistance
Symbol
Max
Unit
Notes
RθJA
40
25
°C/W
1, 2
Junction to Board (Bottom)
RθJB
17
°C/W
3
Junction to Case (Top)
RθJC
9
°C/W
4
Junction to Ambient (@ 200 lfm)
Single–Layer Board
Four–Layer Board
NOTES:
1. Junction temperature is a function of on–chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient
temperature, air flow, board population, and board thermal resistance.
2. Per SEMI G38–87.
3. Indicates the average thermal resistance between the die and the printed circuit board.
4. Indicates the average thermal resistance between the die and the case top surface via the cold plate method (MIL SPEC–883
Method 1012.1).
MCM63Z737DMCM63Z819
10
MOTOROLA FAST SRAM
DC OPERATING CONDITIONS AND CHARACTERISTICS
(VDD = 3.3 V ± 5%, TA = 0 to 70°C Unless Otherwise Noted)
RECOMMENDED OPERATING CONDITIONS (Voltages Referenced to VSS = 0 V)
Parameter
Supply Voltage
I/O Supply Voltage
Symbol
Min
Typ
Max
Unit
VDD
3.135
3.3
3.465
V
VDDQ*
3.135
3.3
VDD
V
Ambient Temperature
TA
0
—
70
°C
Input Low Voltage
VIL
– 0.3
—
0.8
V
Input High Voltage
VIH
2
—
VDD + 0.3
V
Input High Voltage I/O Pins
VIH2
2
—
VDDQ + 0.3
V
* VDD and VDDQ are shorted together on the device and must be supplied with identical voltage levels.
VIH
VSS
VSS – 1.0 V
20% tKHKH (MIN)
Figure 5. Undershoot Voltage
DC CHARACTERISTICS AND SUPPLY CURRENTS
Parameter
Symbol
Min
Typ
Max
Unit
Notes
Input Leakage Current (0 V ≤ Vin ≤ VDD)
Ilkg(I)
—
—
±1
µA
1
Output Leakage Current (0 V ≤ Vin ≤ VDDQ)
Ilkg(O)
—
—
±1
µA
AC Supply Current (Device Selected, All Outputs Open,
Freq = Max) Includes Supply Current for Both VDD and VDDQ
IDDA
—
—
300
mA
2, 3, 4
Hold Supply Current (Device Selected, Freq = Max,
VDD = Max, VDDQ = Max, CKE ≥ VDD – 0.2 V,
All Inputs Static at CMOS Levels)
IDD1
—
—
15
mA
6
CMOS Standby Supply Current (Device Deselected, Freq = 0,
VDD = Max, VDDQ = Max, All Inputs Static at CMOS Levels)
ISB2
—
—
5
mA
5, 6
TTL Standby Supply Current (Device Deselected, Freq = 0,
VDD = Max, VDDQ = Max, All Inputs Static at TTL Levels)
ISB3
—
—
25
mA
5, 7
Output Low Voltage (IOL = 8 mA)
VOL
—
—
0.4
V
Output High Voltage (IOH = – 8 mA)
VOH
2.4
—
—
V
NOTES:
1. LBO has an internal pullup and will exhibit leakage currents of ± 5 µA.
2. Reference AC Operating Conditions and Characteristics for Input and Timing.
3. All addresses transition simultaneously low (LSB) then high (MSB).
4. Data states are all zero.
5. Device in deselected mode as defined by the Truth Table.
6. CMOS levels for I/O’s are VIT ≤ VSS + 0.2 V or ≥ VDDQ – 0.2 V. CMOS levels for other inputs are Vin ≤ VSS + 0.2 V or ≥ VDD – 0.2 V.
7. TTL levels for I/O’s are VIT ≤ VIL or ≥ VIH2. TTL levels for other inputs are Vin ≤ VIL or ≥ VIH.
CAPACITANCE (f = 1.0 MHz, dV = 3.0 V, TA = 0 to 70°C, Periodically Sampled Rather Than 100% Tested)
Symbol
Min
Typ
Max
Unit
Input Capacitance
Cin
—
4
5
pF
Input/Output Capacitance
CI/O
—
7
8
pF
Parameter
MOTOROLA FAST SRAM
MCM63Z737DMCM63Z819
11
AC OPERATING CONDITIONS AND CHARACTERISTICS
(VDD = 3.3 V ± 5%, TA = 0 to 70°C Unless Otherwise Noted)
Input Timing Measurement Reference Level . . . . . . . . . . . . . . . 1.5 V
Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 3.0 V
Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . 1 V/ns (20% to 80%)
Output Timing Reference Level . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 V
Output Load . . . . . . . . . . . . . . See Figure 6 Unless Otherwise Noted
RθJA Under Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TBD
READ/WRITE CYCLE TIMING (See Notes 1 and 2)
MCM63Z737–11
MCM63Z819–11
66 MHz
P
Parameter
MCM63Z737–15
MCM63Z819–15
50 MHz
S b l
Symbol
Min
Max
Min
Max
U i
Unit
Cycle Time
tKHKH
15
—
20
—
ns
Clock High Pulse Width
tKHKL
6
—
8
—
ns
3
Clock Low Pulse Width
tKLKH
6
—
8
—
ns
3
Clock Access Time
tKHQV
—
11
—
15
ns
Output Enable to Output Valid
N
Notes
tGLQV
—
6
—
7
ns
Clock High to Output Active
tKHQX1
1.5
—
1.5
—
ns
4, 5
Output Hold Time
tKHQX
1.5
—
1.5
—
ns
4
Output Enable to Output Active
tGLQX
0
—
0
—
ns
4, 5
Output Disable to Q High–Z
tGHQZ
—
4.5
—
5
ns
4, 5
Clock High to Q High–Z
tKHQZ
1.5
4.5
1.5
5
ns
4, 5
Setup Times:
Address
ADV
Data In
Write
Chip Enable
Clock Enable
tADKH
tLVKH
tDVKH
tWVKH
tEVKH
tCVKH
2.5
2.5
2
2.5
2.5
2.5
—
2.5
2.5
2
2.5
2.5
2.5
—
ns
Hold Times:
Address
ADV
Data In
Write
Chip Enable
Clock Enable
tKHAX
tKHLX
tKHDX
tKHWX
tKHEX
tKHCX
0.5
0.5
0.5
0.5
0.5
0.5
—
0.5
0.5
0.5
0.5
0.5
0.5
—
ns
NOTES:
1. Write is defined as any SBx and SW low. Chip enable is defined as SE1 low, SE2 high, and SE3 low whenever ADV is low.
2. All read and write cycle timings are referenced from CK or G.
3. In order to reduce test correlation issues and to reduce the effects of application specific input edge rate variations on correlation between
data sheet parameters and actual system performance, FSRAM AC parametric specifications are always specified at VDDQ/2. In some
design exercises, it is desirable to evaluate timing using other reference levels. Since the maximum test input edge rate is known and is
given in the AC Test Conditions section of the data sheet as 1 V/ns, one can easily interpolate timing values to other reference levels.
4. This parameter is sampled and not 100% tested.
5. Measured at ± 200 mV from steady state.
OUTPUT
Z0 = 50 Ω
RL = 50 Ω
1.5 V
Figure 6. AC Test Load
MCM63Z737DMCM63Z819
12
MOTOROLA FAST SRAM
tKHKH
tKHKL
tKLKH
CK
tAVKH
tKHAX
SA0 – SAx
tWVKH
tKHWX
SW
tWVKH
tKHWX
SBx
tEVKH
tKHEX
E
tLVKH
tKHLX
ADV
tCVKH
tKHCX
CKE
G
tGLQX
tGLQV
tGHQZ
DQ
Q
tDVKH
tKHDX
DQ
D
tKHQV
tKHQX1
DQ
tKHQX
tKHQZ
Q
Q
Figure 7. AC Timing Parameter Definitions
MOTOROLA FAST SRAM
MCM63Z737DMCM63Z819
13
MCM63Z737DMCM63Z819
14
MOTOROLA FAST SRAM
R
COMMAND
CODE
Q(A0)
W
B
H
D(B0)
R
C
Q(C0)
W
D
NOTE: Command code definitions are shown in Truth Table.
DQ
A
ADDRESS
CK
D(D0)
D
R
E
Q(E0)
H
W
F
D(F0)
R
G
Q(G0)
D
READ/WRITE CYCLES WITH HOLD AND DESELECT CYCLES
W
H
D(H0)
R
I
Q(I0)
D
J
MOTOROLA FAST SRAM
MCM63Z737DMCM63Z819
15
R
COMMAND
CODE
Q(A0)
R
B
Q(B0)
B
Q(B1)
B
B
Q(B2)
NOTE: Command code definitions are shown in Truth Table.
DQ
A
ADDRESS
CK
Q(B3)
R
C
Q(C0)
B
Q(C1)
B
Q(C2)
B
READ CYCLES (SINGLE, BURST, AND BURST WRAP–AROUND)
Q(C3)
B
Q(C0)
MCM63Z737DMCM63Z819
16
MOTOROLA FAST SRAM
W
COMMAND
CODE
B
D(B0)
W
D(A0)
B
D(B1)
B
B
D(B2)
NOTE: Command code definitions are shown in Truth Table.
DQ
A
ADDRESS
CK
D(B3)
W
C
D(C0)
B
D(C1)
B
D(C2)
B
WRITE CYCLES (SINGLE, BURST, AND BURST WRAP–AROUND)
D(C3)
B
D(C0)
MOTOROLA FAST SRAM
MCM63Z737DMCM63Z819
17
R
COMMAND
CODE
Q(A0)
W
B
D(B0)
R
B
Q(B0)
W
C
B
D(C0)
NOTE: Command code definitions are shown in Truth Table.
DQ
A
ADDRESS
CK
D(C1)
R
C
Q(C0)
B
Q(C1)
D
W
D
H
D(D0)
R
D
READ, WRITE, READ COHERENCY WITH HOLD, AND DESELECT CYCLES
Q(D0)
R
E
Q(E0)
ORDERING INFORMATION
(Order by Full Part Number)
MCM
63Z737
63Z819
XX
X
X
Motorola Memory Prefix
Blank = Trays, R = Tape and Reel
Part Number
Speed (11 = 11 ns, 15 = 15 ns)
Package (TQ = TQFP)
MCM63Z737DMCM63Z819
18
Full Part Numbers — MCM63Z737TQ11
MCM63Z737TQ11R
MCM63Z737TQ15
MCM63Z737TQ15R
MCM63Z819TQ11
MCM63Z819TQ11R
MCM63Z819TQ15
MCM63Z819TQ15R
MOTOROLA FAST SRAM
PACKAGE DIMENSIONS
TQ PACKAGE
100–PIN TQFP
CASE 983A–01
4X
e
0.20 (0.008) H A–B D
2X 30 TIPS
e/2
0.20 (0.008) C A–B D
–D–
80
51
B
50
81
E/2
–A–
–X–
B
X=A, B, OR D
–B–
VIEW Y
E1 E
BASE
METAL
PLATING
31
100
1
c
30
D1/2
ÉÉÉÉ
ÇÇÇÇ
ÇÇÇÇ
ÉÉÉÉ
b1
E1/2
c1
b
D/2
D1
D
0.13 (0.005)
M
C A–B
S
D
S
SECTION B–B
2X 20 TIPS
0.20 (0.008) C A–B D
A
q
2
0.10 (0.004) C
–H–
–C–
SEATING
PLANE
q
3
VIEW AB
0.05 (0.002)
S
S
q
1
0.25 (0.010)
R2
A2
A1
R1
L2
L
L1
VIEW AB
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DATUM PLANE –H– IS LOCATED AT BOTTOM OF
LEAD AND IS COINCIDENT WITH THE LEAD
WHERE THE LEAD EXITS THE PLASTIC BODY AT
THE BOTTOM OF THE PARTING LINE.
4. DATUMS –A–, –B– AND –D– TO BE DETERMINED AT
DATUM PLANE –H–.
5. DIMENSIONS D AND E TO BE DETERMINED AT
SEATING PLANE –C–.
6. DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD
PROTRUSION. ALLOWABLE PROTRUSION IS 0.25
(0.010) PER SIDE. DIMENSIONS D1 AND B1 DO
INCLUDE MOLD MISMATCH AND ARE
DETERMINED AT DATUM PLANE –H–.
7. DIMENSION b DOES NOT INCLUDE DAMBAR
PROTRUSION. DAMBAR PROTRUSION SHALL NOT
CAUSE THE b DIMENSION TO EXCEED 0.45 (0.018).
GAGE PLANE
q
DIM
A
A1
A2
b
b1
c
c1
D
D1
E
E1
e
L
L1
L2
S
R1
R2
q
1
2
q3
q
q
MOTOROLA FAST SRAM
MILLIMETERS
MIN
MAX
–––
1.60
0.05
0.15
1.35
1.45
0.22
0.38
0.22
0.33
0.09
0.20
0.09
0.16
22.00 BSC
20.00 BSC
16.00 BSC
14.00 BSC
0.65 BSC
0.45
0.75
1.00 REF
0.50 REF
0.20
–––
0.08
–––
0.08
0.20
0
7
0
–––
11
13
11
13
_
_
_
_
_
_
_
INCHES
MIN
MAX
–––
0.063
0.002
0.006
0.053
0.057
0.009
0.015
0.009
0.013
0.004
0.008
0.004
0.006
0.866 BSC
0.787 BSC
0.630 BSC
0.551 BSC
0.026 BSC
0.018
0.030
0.039 REF
0.020 REF
0.008
–––
0.003
–––
0.003
0.008
0
7
0
–––
11
13
11
13
_
_
_
_
_
_
_
MCM63Z737DMCM63Z819
19
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola
data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals”
must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of
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applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury
or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola
and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees
arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that
Motorola was negligent regarding the design or manufacture of the part. Motorola and
are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal
Opportunity/Affirmative Action Employer.
Mfax is a trademark of Motorola, Inc.
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MCM63Z737DMCM63Z819
20
◊
MCM63Z737/D
MOTOROLA FAST
SRAM