GTL2007 13-bit GTL to LVTTL translator with power good control Rev. 01 — 2 June 2005 Product data sheet 1. General description The GTL2007 is a customized translator between dual Xeon processors, Platform Health Management, South Bridge and Power Supply LVTTL and GTL signals. The GTL2007 is derived from the GTL2006 with an enable function added that disables the error output to the monitoring agent for platforms that monitor the individual error conditions from each processor. This enable function can be used so that false error conditions are not passed to the monitoring agent when the system is unexpectedly powered down. This unexpected power-down could be from a power supply overload, a CPU thermal trip, or some other event of which the monitoring agent is unaware. A typical implementation would be to connect each enable line to the system power good signal or the individual enables to the VRD power good for each processor. The Nocona and Dempsey/Blackford Xeon processors specify a VTT of 1.2 V and 1.1 V, as well as a nominal Vref of 0.76 V and 0.73 V respectively. To allow for future voltage level changes that may extend Vref to 0.63 of VTT (minimum of 0.693 V with VTT of 1.1 V) the GTL2009 allows a minimum Vref of 0.66 V. Characterization results show that there is little DC or AC performance variation between these levels. The GTL2007 is the companion chip to the GTL2009 3-bit GTL Front-Side Bus frequency comparator that is used in dual-processor Xeon applications. 2. Features ■ ■ ■ ■ ■ Operates as a GTL to LVTTL sampling receiver or LVTTL to GTL driver 3.0 V to 3.6 V operation LVTTL I/O not 5 V tolerant Series termination on the LVTTL outputs of 30 Ω ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per JESD22-A115, and 1000 V CDM per JESD22-C101 ■ Latch-up testing is done to JEDEC Standard JESD78 which exceeds 500 mA ■ Package offered: TSSOP28 GTL2007 Philips Semiconductors 13-bit GTL to LVTTL translator with power good control 3. Quick reference data Table 1: Quick reference data Tamb = 25 °C Symbol Parameter Conditions Min Typ Max Unit tPLH propagation delay; An-to-Bn or Bn-to-An CL = 50 pF; VCC = 3.3 V - 5.5 - ns - 5.5 - ns input/output capacitance; A-to-B outputs disabled; VI and VO = 0 V or 3.0 V - 2.0 3.0 pF - 1.5 2.5 pF tPHL Cio input/output capacitance; B-to-A 4. Ordering information Table 2: Ordering information Tamb = −40 °C to +85 °C Type number GTL2007PW Topside mark Package Name Description Version GTL2007 TSSOP28 plastic thin shrink small outline package; 28 leads; body width 4.4 mm SOT361-1 Standard packing quantities and other packaging data are available at www.semiconductors.philips.com/standardics/packaging. 9397 750 13264 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 01 — 2 June 2005 2 of 19 GTL2007 Philips Semiconductors 13-bit GTL to LVTTL translator with power good control 5. Functional diagram GTL2007 GTL VREF 1AO 1 27 2 1BI GTL inputs LVTTL outputs 2AO 5A LVTTL inputs/outputs (open-drain) 26 3 4 25 5 24 6 23 2BI 7BO1 GTL outputs 6A LVTTL input EN1 GTL input 11BI LVTTL input/output (open-drain) 11A GTL input 9BI 7 22 EN2 LVTTL input 11BO GTL output DELAY(1) 8 21 9 7BO2 5BI DELAY(1) 20 6BI GTL inputs 3AO 19 10 3BI LVTTL outputs 4AO 10AI1 18 11 17 12 4BI 10BO1 GTL outputs LVTTL inputs 10AI2 16 13 15 10BO2 9AO LVTTL output 002aab210 (1) The enable on 7BO1/7BO2 include a delay that prevents the transient condition where 5BI/6BI go from LOW to HIGH, and the LOW to HIGH on 5A/6A lags up to 100 ns from causing a LOW glitch on the 7BO1/7BO2 outputs. Fig 1. Logic diagram of GTL2007 9397 750 13264 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 01 — 2 June 2005 3 of 19 GTL2007 Philips Semiconductors 13-bit GTL to LVTTL translator with power good control 6. Pinning information 6.1 Pinning VREF 1 28 VCC 1AO 2 27 1BI 2AO 3 26 2BI 5A 4 25 7BO1 6A 5 24 7BO2 EN1 6 23 EN2 11BI 7 11A 8 9BI 9 20 6BI 3AO 10 19 3BI 4AO 11 18 4BI GTL2007PW 22 11BO 21 5BI 10AI1 12 17 10BO1 10AI2 13 16 10BO2 GND 14 15 9AO 002aab209 Fig 2. Pin configuration for TSSOP28 6.2 Pin description Table 3: Pin description Symbol Pin Description VREF 1 GTL reference voltage 1AO 2 data output (LVTTL) 2AO 3 data output (LVTTL) 5A 4 data input/output (LVTTL), open-drain 6A 5 data input/output (LVTTL), open-drain EN1 6 enable input (LVTTL) 11BI 7 data input (GTL) 11A 8 data input/output (LVTTL), open-drain 9BI 9 data input (GTL) 3AO 10 data output (LVTTL) 4AO 11 data output (LVTTL) 10AI1 12 data input (LVTTL) 10AI2 13 data input (LVTTL) GND 14 ground (0 V) 9AO 15 data output (LVTTL) 10BO2 16 data output (GTL) 10BO1 17 data output (GTL) 4BI 18 data input (GTL) 3BI 19 data input (GTL) 9397 750 13264 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 01 — 2 June 2005 4 of 19 GTL2007 Philips Semiconductors 13-bit GTL to LVTTL translator with power good control Table 3: Pin description …continued Symbol Pin Description 6BI 20 data input (GTL) 5BI 21 data input (GTL) 11BO 22 data output (GTL) EN2 23 enable input (LVTTL) 7BO2 24 data output (GTL) 7BO1 25 data output (GTL) 2BI 26 data input (GTL) 1BI 27 data input (GTL) VCC 28 positive supply voltage 7. Functional description Refer to Figure 1 “Logic diagram of GTL2007” on page 3. 7.1 Function tables Table 4: GTL input signals H = HIGH voltage level; L = LOW voltage level. Input Output [1] 1BI/2BI/3BI/4BI/9BI 1AO/2AO/3AO/4AO/9AO L L H H [1] 1AO, 2AO, 3AO, 4AO and 5A/6A condition changed by ENn power good signal as described in Table 5 and Table 6. Table 5: EN1 power good signal H = HIGH voltage level; L = LOW voltage level. EN1 1AO and 2AO 5A L H 5BI disconnected H follows BI 5BI connected Table 6: EN2 power good signal H = HIGH voltage level; L = LOW voltage level. EN2 3AO and 4AO 6A L H 6BI disconnected H follows BI 6BI connected 9397 750 13264 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 01 — 2 June 2005 5 of 19 GTL2007 Philips Semiconductors 13-bit GTL to LVTTL translator with power good control Table 7: SMI signals H = HIGH voltage level; L = LOW voltage level. Input Input Output 10AI1/10AI2 9BI 10BO1/10BO2 L L L L H L H L L H H H Table 8: PROCHOT signals H = HIGH voltage level; L = LOW voltage level. Input Input/output Output 5BI/6BI 5A/6A (open-drain) 7BO1/7BO2 L L H [1] H L [2] L H H H [1] The enable on 7BO1/7BO2 includes a delay that prevents the transient condition where 5BI/6BI go from LOW to HIGH, and the LOW to HIGH on 5A/6A lags up to 100 ns from causing a low glitch on the 7BO1/7BO2 outputs. [2] Open-drain input/output terminal is driven to logic LOW state by other driver. Table 9: NMI signals H = HIGH voltage level; L = LOW voltage level. Input Input/output Output 11BI 11A (open-drain) 11BO L H L L L [1] H H L H [1] Open-drain input/output terminal is driven to logic LOW state by other driver. 9397 750 13264 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 01 — 2 June 2005 6 of 19 GTL2007 Philips Semiconductors 13-bit GTL to LVTTL translator with power good control 8. Application design-in information VTT VTT 56 Ω 56 Ω R VCC 1.5 kΩ to 1.2 kΩ 2R 1.5 kΩ PLATFORM HEALTH MANAGEMENT VCC VREF VCC CPU1 CPU1 1ERR_L 1AO 1BI IERR_L CPU1 THRMTRIP L 2AO 2BI THRMTRIP L CPU1 PROCHOT L 5A 7BO1 FORCEPR_L CPU2 PROCHOT L 6A 7BO2 PROCHOT L EN1 EN2 NMI CPU1 SMI L 11B1 11B0 GTL2007 11A 5BI 9BI 6BI PROCHOT L CPU2 IERR_L 3AO 3BI IERR_L CPU2 THRMTRIP L 4AO 4BI THRMTRIP L NMI_L FORCEPR_L CPU1 SMI L 10AI1 10BO1 NMI CPU2 SMI L 10AI2 10BO2 CPU2 SMI L SMI_BUFF_L GND 9AO CPU2 SOUTHBRIDGE NMI SOUTHBRIDGE SMI_L power supply POWER GOOD 002aab211 Fig 3. Typical application 9397 750 13264 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 01 — 2 June 2005 7 of 19 GTL2007 Philips Semiconductors 13-bit GTL to LVTTL translator with power good control 9. Limiting values Table 10: Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). [1] Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Max Unit VCC DC supply voltage −0.5 +4.6 V IIK input clamping diode current VI < 0 V - −50 mA VI DC input voltage A port (LVTTL) −0.5 [3] +4.6 V B port (GTL) −0.5 [3] +4.6 V IOK output diode clamping current VO < 0 V - −50 mA VO DC output voltage output in OFF or HIGH state; A port −0.5 [3] +4.6 V output in OFF or HIGH state; B port −0.5 [3] +4.6 V A port - 32 mA B port - 30 mA IOH current into any output in the HIGH state A port - −32 mA Tstg storage temperature −60 +150 °C Tj(max) maximum junction temperature − +125 °C current into any output in the LOW state IOL [2] [1] Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under Section 10 “Recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. [2] The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150 °C. [3] The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed. 10. Recommended operating conditions Table 11: Operating conditions Symbol Parameter Conditions Min Typ Max Unit VCC supply voltage 3.0 3.3 3.6 V VTT termination voltage GTL - 1.2 - V Vref reference voltage GTL 0.64 0.8 1.1 V VI input voltage A port 0 3.3 3.6 V B port 0 VTT 3.6 V VIH HIGH-level input voltage A port and ENn 2 - - V B port Vref + 0.050 - - V A port and ENn - - 0.8 V VIL LOW-level input voltage B port - - Vref − 0.050 V IOH HIGH-level output current A port - - −16 mA IOL LOW-level output current A port - - 16 mA B port - - 15 mA operating in free-air −40 - +85 °C Tamb ambient temperature 9397 750 13264 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 01 — 2 June 2005 8 of 19 GTL2007 Philips Semiconductors 13-bit GTL to LVTTL translator with power good control 11. Static characteristics Table 12: Static characteristics Recommended operating conditions; voltages are referenced to GND (ground = 0 V). Tamb = −40 °C to +85 °C Symbol VOH Parameter HIGH-level output voltage LOW-level output voltage VOL input current II Min Typ [1] Max Unit A port; VCC = 3.0 V to 3.6 V; IOH = −100 µA [2] VCC − 0.2 3.0 - V A port; VCC = 3.0 V; IOH = −16 mA [2] 2.1 2.3 - V A port; VCC = 3.0 V; IOL = 4 mA [2] - 0.15 0.4 V A port; VCC = 3.0 V; IOL = 8 mA [2] - 0.3 0.55 V A port; VCC = 3.0 V; IOL = 16 mA [2] - 0.6 0.8 V B port; VCC = 3.0 V; IOL = 15 mA [2] - 0.13 0.4 V A port; VCC = 3.6 V; VI = VCC - - ±1 µA A port; VCC = 3.6 V; VI = 0 V - - ±1 µA Conditions B port; VCC = 3.6 V; VI = VTT or GND - - ±1 µA ICC supply current A or B port; VCC = 3.6 V; VI = VCC or GND; IO = 0 mA - 8 12 mA ∆ICC [3] additional quiescent current (per input) A port or control inputs; VCC = 3.6 V; VI = VCC − 0.6 V - - 500 µA Cio input/output capacitance A port; VO = 3.0 V or 0 V - 2.5 3.5 pF B port; VO = VTT or 0 V - 1.5 2.5 pF [1] All typical values are measured at VCC = 3.3 V and Tamb = 25 °C. [2] The input and output voltage ratings may be exceeded if the input and output current ratings are observed. [3] This is the increase in supply current for each input that is at the specified LVTTL voltage level rather than VCC or GND. 9397 750 13264 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 01 — 2 June 2005 9 of 19 GTL2007 Philips Semiconductors 13-bit GTL to LVTTL translator with power good control 12. Dynamic characteristics Table 13: Dynamic characteristics VCC = 3.3 V ± 0.3 V Symbol Parameter Conditions Min Typ [1] Max Unit see Figure 4 1 4 8 ns 2 5.5 10 ns 2 5.5 10 ns 2 5.5 10 ns Vref = 0.73 V; VTT = 1.1 V propagation delay, An to Bn tPLH tPHL propagation delay, nBI to nAO tPLH see Figure 5 tPHL propagation delay, 9BI to 10BOn tPLH tPHL propagation delay, 11BI to 11BO tPLH tPHL [2] tPLZ disable time from LOW level, nBI to nA (I/O) tPZL enable time to LOW level, nBI to nA (I/O) tPLH propagation delay, 5BI to 7BO1 or 6BI to 7BO2 see Figure 7 propagation delay, EN1 to nAO or EN2 to nAO see Figure 8 tPLZ disable time from LOW level, EN1 to 5A (I/O) or EN2 to 6A (I/O) see Figure 9 tPZL enable time to LOW level, EN1 to 5A (I/O) or EN2 to 6A (I/O) tPHL tPLH tPHL see Figure 6 2 6 11 ns 2 6 11 ns 2 8 13 ns 2 14 21 ns 2 13 18 ns 2 12 16 ns 4 7 12 ns 100 205 350 ns 2 6.5 10 ns 2 6.5 10 ns 1 3 7 ns 2 7 10 ns 1 4 8 ns 2 5.5 10 ns 2 5.5 10 ns 2 5.5 10 ns 2 6 11 ns 2 6 11 ns 2 8 13 ns Vref = 0.76 V; VTT = 1.2 V propagation delay, An to Bn tPLH see Figure 4 tPHL propagation delay, nBI to nAO tPLH see Figure 5 tPHL propagation delay, 9BI to 10BOn tPLH tPHL propagation delay, 11BI to 11BO tPLH tPHL [2] tPLZ disable time from LOW level, nBI to nA (I/O) tPZL enable time to LOW level, nBI to nA (I/O) tPLH propagation delay, 5BI to 7BO1 or 6BI to 7BO2 tPHL see Figure 6 see Figure 7 9397 750 13264 Product data sheet 2 14 21 ns 2 13 18 ns 2 12 16 ns 4 7 12 ns 100 205 350 ns © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 01 — 2 June 2005 10 of 19 GTL2007 Philips Semiconductors 13-bit GTL to LVTTL translator with power good control Table 13: Dynamic characteristics …continued VCC = 3.3 V ± 0.3 V Symbol Parameter Conditions Min Typ [1] Max Unit tPLH propagation delay, EN1 to nAO or EN2 to nAO see Figure 8 2 6.5 10 ns 2 6.5 10 ns tPLZ disable time from LOW level, EN1 to 5A (I/O) or EN2 to 6A (I/O) see Figure 9 1 3 7 ns tPZL enable time to LOW level, EN1 to 5A (I/O) or EN2 to 6A (I/O) 2 7 10 ns tPHL [1] All typical values are at VCC = 3.3 V and Tamb = 25 °C. [2] Includes ~7.6 ns RC rise time of test load pull-up on 11A, 1.5 kΩ pull-up and 21 pF load on 11A has about 23 ns RC rise time. 12.1 Waveforms VM = 1.5 V at VCC ≥ 3.0 V for A ports; VM = Vref for B ports. 3.0 V input 1.5 V 1.5 V 0V tPLH tpulse tPHL VOH VH VM output VM Vref Vref VOL 0V 002aab000 002aaa999 VM = 3.0 V for A port and VTT for B port a. Pulse duration A port to B port b. Propagation delay times Fig 4. Voltage waveforms 9397 750 13264 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 01 — 2 June 2005 11 of 19 GTL2007 Philips Semiconductors 13-bit GTL to LVTTL translator with power good control VTT Vref input VTT Vref input 1/ V 3 TT tPLH tPHL Vref Vref tPZL tPLZ 1/ V 3 TT VOH 1.5 V output VCC 1.5 V output 1.5 V VOL + 0.3 V VOL 002aab001 002aab002 PRR ≤ 10 MHz; ZO = 50 Ω; tr ≤ 2.5 ns; tf ≤ 2.5 ns Fig 5. Propagation delay, nBI to nAO Fig 6. nBI to nA (I/O) VTT input Vref Vref tPLH tPHL 3.0 V input 1/ V 3 TT 1.5 V 1.5 V tPLH tPHL 0V VOH/VTT output Vref VOH 1.5 V output Vref 1.5 V VOL VOL 002aab003 002aab004 Fig 7. 5BI to 7BO or 6BI to 7BO2 Fig 8. EN1 to nAO or EN2 to nAO 3.0 V input 1.5 V 1.5 V tPLZ tPZL 0V VOH output VOL + 0.3 V 1.5 V VOL 002aab005 Fig 9. EN1 to 5A (I/O) or EN2 to 6A (I/O) 9397 750 13264 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 01 — 2 June 2005 12 of 19 GTL2007 Philips Semiconductors 13-bit GTL to LVTTL translator with power good control 13. Test information VCC PULSE GENERATOR VI VO D.U.T. RL 500 Ω CL 50 pF RT 002aab006 Fig 10. Load circuit for A outputs VTT VCC PULSE GENERATOR VI 50 Ω VO D.U.T. CL 30 pF RT 002aab264 Fig 11. Load circuit for B outputs VCC VCC PULSE GENERATOR VI RL 1.5 kΩ VO D.U.T. RT CL 21 pF 002aab265 Fig 12. Load circuit for open-drain LVTTL I/O RL — Load resistor CL — Load capacitance; includes jig and probe capacitance RT — Termination resistance; should be equal to ZOUT of pulse generators. 9397 750 13264 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 01 — 2 June 2005 13 of 19 GTL2007 Philips Semiconductors 13-bit GTL to LVTTL translator with power good control 14. Package outline TSSOP28: plastic thin shrink small outline package; 28 leads; body width 4.4 mm D SOT361-1 E A X c HE y v M A Z 15 28 Q A2 (A 3) A1 pin 1 index A θ Lp 1 L 14 detail X w M bp e 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) θ mm 1.1 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.2 0.1 9.8 9.6 4.5 4.3 0.65 6.6 6.2 1 0.75 0.50 0.4 0.3 0.2 0.13 0.1 0.8 0.5 8 o 0 o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT361-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 MO-153 Fig 13. Package outline SOT361-1 (TSSOP28) 9397 750 13264 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 01 — 2 June 2005 14 of 19 GTL2007 Philips Semiconductors 13-bit GTL to LVTTL translator with power good control 15. Soldering 15.1 Introduction to soldering surface mount packages This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our Data Handbook IC26; Integrated Circuit Packages (document order number 9398 652 90011). There is no soldering method that is ideal for all surface mount IC packages. Wave soldering can still be used for certain surface mount ICs, but it is not suitable for fine pitch SMDs. In these situations reflow soldering is recommended. 15.2 Reflow soldering Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Driven by legislation and environmental forces the worldwide use of lead-free solder pastes is increasing. Several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 seconds and 200 seconds depending on heating method. Typical reflow peak temperatures range from 215 °C to 270 °C depending on solder paste material. The top-surface temperature of the packages should preferably be kept: • below 225 °C (SnPb process) or below 245 °C (Pb-free process) – for all BGA, HTSSON..T and SSOP..T packages – for packages with a thickness ≥ 2.5 mm – for packages with a thickness < 2.5 mm and a volume ≥ 350 mm3 so called thick/large packages. • below 240 °C (SnPb process) or below 260 °C (Pb-free process) for packages with a thickness < 2.5 mm and a volume < 350 mm3 so called small/thin packages. Moisture sensitivity precautions, as indicated on packing, must be respected at all times. 15.3 Wave soldering Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. To overcome these problems the double-wave soldering method was specifically developed. If wave soldering is used the following conditions must be observed for optimal results: • Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. • For packages with leads on two sides and a pitch (e): – larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; 9397 750 13264 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 01 — 2 June 2005 15 of 19 GTL2007 Philips Semiconductors 13-bit GTL to LVTTL translator with power good control – smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end. • For packages with leads on four sides, the footprint must be placed at a 45° angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time of the leads in the wave ranges from 3 seconds to 4 seconds at 250 °C or 265 °C, depending on solder material applied, SnPb or Pb-free respectively. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 15.4 Manual soldering Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C. When using a dedicated tool, all other leads can be soldered in one operation within 2 seconds to 5 seconds between 270 °C and 320 °C. 15.5 Package related soldering information Table 14: Suitability of surface mount IC packages for wave and reflow soldering methods Package [1] Soldering method Wave Reflow [2] BGA, HTSSON..T [3], LBGA, LFBGA, SQFP, SSOP..T [3], TFBGA, VFBGA, XSON not suitable suitable DHVQFN, HBCC, HBGA, HLQFP, HSO, HSOP, HSQFP, HSSON, HTQFP, HTSSOP, HVQFN, HVSON, SMS not suitable [4] suitable PLCC [5], SO, SOJ suitable suitable not recommended [5] [6] suitable SSOP, TSSOP, VSO, VSSOP not recommended [7] suitable CWQCCN..L [8], PMFP [9], WQCCN..L [8] not suitable LQFP, QFP, TQFP [1] For more detailed information on the BGA packages refer to the (LF)BGA Application Note (AN01026); order a copy from your Philips Semiconductors sales office. [2] All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods. [3] These transparent plastic packages are extremely sensitive to reflow soldering conditions and must on no account be processed through more than one soldering cycle or subjected to infrared reflow soldering with peak temperature exceeding 217 °C ± 10 °C measured in the atmosphere of the reflow oven. The package body peak temperature must be kept as low as possible. 9397 750 13264 Product data sheet not suitable © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 01 — 2 June 2005 16 of 19 GTL2007 Philips Semiconductors 13-bit GTL to LVTTL translator with power good control [4] These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side, the solder might be deposited on the heatsink surface. [5] If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. [6] Wave soldering is suitable for LQFP, QFP and TQFP packages with a pitch (e) larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. [7] Wave soldering is suitable for SSOP, TSSOP, VSO and VSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. [8] Image sensor packages in principle should not be soldered. They are mounted in sockets or delivered pre-mounted on flex foil. However, the image sensor package can be mounted by the client on a flex foil by using a hot bar soldering process. The appropriate soldering profile can be provided on request. [9] Hot bar soldering or manual soldering is suitable for PMFP packages. 16. Abbreviations Table 15: Abbreviations Acronym Description CDM Charged Device Model CMOS Complementary Metal Oxide Silicon CPU Central Processing Unit ESD Electrostatic Discharge GTL Gunning Transceiver Logic HBM Human Body Model LVTTL Low Voltage Transistor-Transistor Logic MM Machine Model PRR Pulse Rate Repetition TTL Transistor-Transistor Logic VRD Voltage Regulator Down 17. Revision history Table 16: Revision history Document ID Release date Data sheet status Change notice Doc. number Supersedes GTL2007_1 20050602 Product data sheet - 9397 750 13264 - 9397 750 13264 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 01 — 2 June 2005 17 of 19 GTL2007 Philips Semiconductors 13-bit GTL to LVTTL translator with power good control 18. Data sheet status Level Data sheet status [1] Product status [2] [3] Definition I Objective data Development This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. II Preliminary data Qualification This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. III Product data Production This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). [1] Please consult the most recently issued data sheet before initiating or completing a design. [2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. [3] For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. 19. Definitions customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Right to make changes — Philips Semiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. When the product is in full production (status ‘Production’), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 21. Trademarks 20. Disclaimers Notice — All referenced brands, product names, service names and trademarks are the property of their respective owners. Life support — These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors 22. Contact information For additional information, please visit: http://www.semiconductors.philips.com For sales office addresses, send an email to: [email protected] 9397 750 13264 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 01 — 2 June 2005 18 of 19 GTL2007 Philips Semiconductors 13-bit GTL to LVTTL translator with power good control 23. Contents 1 2 3 4 5 6 6.1 6.2 7 7.1 8 9 10 11 12 12.1 13 14 15 15.1 15.2 15.3 15.4 15.5 16 17 18 19 20 21 22 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Quick reference data . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 3 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 Functional description . . . . . . . . . . . . . . . . . . . 5 Function tables . . . . . . . . . . . . . . . . . . . . . . . . . 5 Application design-in information . . . . . . . . . . 7 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 8 Recommended operating conditions. . . . . . . . 8 Static characteristics. . . . . . . . . . . . . . . . . . . . . 9 Dynamic characteristics . . . . . . . . . . . . . . . . . 10 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Test information . . . . . . . . . . . . . . . . . . . . . . . . 13 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 14 Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Introduction to soldering surface mount packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 15 Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 15 Manual soldering . . . . . . . . . . . . . . . . . . . . . . 16 Package related soldering information . . . . . . 16 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 17 Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 18 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Contact information . . . . . . . . . . . . . . . . . . . . 18 © Koninklijke Philips Electronics N.V. 2005 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Date of release: 2 June 2005 Document number: 9397 750 13264 Published in The Netherlands