MOTOROLA MPC992 Low voltage pll clock driver Datasheet

SEMICONDUCTOR TECHNICAL DATA
The MPC992 is a 3.3V compatible, PLL based PECL clock generator
and distributor. The fully differential design ensures optimum skew and
PLL jitter performance. The performance of the device makes the
MPC992 ideal for workstations, main frame computer, telecommunication
and instrumentation applications. The device offers a crystal oscillator or
a differential PECL reference clock input to provide flexibility in the
reference clock interface. All of the control signals to the MPC992 are
LVTTL compatible inputs.
•
•
•
•
•
•
•
LOW VOLTAGE
PLL CLOCK DRIVER
Fully Integrated PLL
Output Frequency of up to 400MHz
PECL Clock Inputs and Outputs
Operates from a 3.3V VCC Supply
Output Frequency Configurable
32 TQFP Packaging
FA SUFFIX
PLASTIC TQFP PACKAGE
CASE 873A-02
±25ps Cycle–Cycle Jitter
The MPC992 offers two banks of outputs which can be configured into
four different relationships. The output banks can be configured into 2:1,
3:1, 3:2 and 5:2 ratios to provide a wide variety of potential frequency
outputs. In addition to these two banks of outputs a synchronization output is also offered. The SYNC output will provide
information as to the time when the two output banks will transition positively in phase. This information can be important when
the odd ratios are used as it provides for a baseline point in the system timing. The SYNC output will pulse high for one Qa clock
period, centered on the rising Qa clock edge four edges prior to the Qb synchronous edge. The relationship is illustrated in the
timing diagrams in the data sheet.
The MPC992 offers several features to aid in system debug and test. The PECL reference input pins can be interfaced to a test
signal and the PLL can be bypassed to allow the designer to drive the MPC992 outputs directly. This allows for single stepping in
a system functional debug mode. In addition an overriding reset is provided which will force all of the Q outputs LOW upon
assertion.
The MPC992 is packaged in a 32–lead TQFP package to optimize both performance and board density.
MPC992 LOGIC DIAGRAM
PLL_EN
VCO_SEL
XTAL_SEL
XTAL1
XTAL2
PECL_CLK
PECL_CLK
XTAL
OSC
x2
1
0
FSEL0
FSEL1
Integrated
PLL
0
1
0
1
(x4)
Qbn
Qbn
(x3)
SYNC
SYNC
(x1)
Frequency
Generator
POR
Reset
7/96
 Motorola, Inc. 1996
Qan
Qan
1
REV 1
21
20
19
VCCO2
Qa3
22
SYNC
Qa2
23
SYNC
Qa2
24
Qa3
VCCO1
MPC992
18
17
Qa1
25
16
Qb0
Qa1
26
15
Qb0
Qa0
27
14
Qb1
Qa0
28
13
Qb1
MPC992
GNDA
29
12
Qb2
VCCA
30
11
Qb2
Reset
31
10
PLL_EN
VCCI
32
5
FSEL0
FSEL1
XTAL_SEL
PECL_CLK
FUNCTION TABLE 1
6
7
8
XTAL2
4
XTAL1
3
PECL_CLK
2
VCO_SEL
9
1
GNDI
FUNCTION TABLE 2
FSEL0
FSEL1
Qa
Qb
Feedback
Ratio
Control Signal
Logic ‘0’
Logic ‘1’
0
0
1
1
0
1
0
1
VCO/4
VCO/2
VCO/4
VCO/2
VCO/6
VCO/4
VCO/10
VCO/6
VCO/24
VCO/16
VCO/40
VCO/24
3:2
2:1
5:2
3:1
Reset
Outputs Enabled
Outputs Disabled
XTAL_SEL
PECL REF
XTAL REF
PLL_EN
Disabled
Enabled
VCO_SEL
High Frequency
Low Frequency
INPUT vs OUTPUT FREQUENCY
PIN DESCRIPTION
FSEL0
FSEL1
Qa
Qb
Int Feedback
0
0
1
1
0
1
0
1
6 (fref)
8 (fref)
10 (fref)
12 (fref)
4 (fref)
4 (fref)
4 (fref)
4 (fref)
fref
fref
fref
fref
MOTOROLA
Pin Name
2
Function
VCO_SEL
VCO range select pin (Int Pullup)
PLL_EN
PLL bypass select pin (Int Pullup)
XTAL_SEL
Input reference source select pin (Int Pullup)
XTAL1:2
Crystal interface pins for the internal oscillator
PECL_CLK
True PECL reference clock input (Int Pulldown)
PECL_CLK
Compliment PECL reference clock input
(Int Pullup)
FSELn
Internal divider select pins (Int Pullup)
RESET
Internal flip–flop reset, true outputs go LOW
(Int Pulldown)
TIMING SOLUTIONS
BR1333 — REV 5
MPC992
2:1 Mode
Qa
Qb
SYNC
3:1 Mode
Qa
Qb
SYNC
3:2 Mode
Qa
Qb
SYNC
5:2 Mode
Qa
Qb
SYNC
Figure 1. Output Waveforms
ABSOLUTE MAXIMUM RATINGS*
Symbol
Parameter
Min
Max
Unit
VCC
Supply Voltage
–0.3
4.6
V
VI
Input Voltage
–0.3
VDD + 0.3
V
IOUT
Output Current
50
100
mA
TStor
Storage Temperature Range
125
°C
Continuous
Surge
–40
* Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or
conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute-maximum-rated conditions is not
implied.
TIMING SOLUTIONS
BR1333 — REV 5
3
MOTOROLA
MPC992
DC CHARACTERISTICS (TA = 0° to 70°C, VCC = 3.3V ±5%)
Symbol
Characteristic
Min
VIH
Input HIGH Voltage
PECL_CLK1
Other
VIL
Input LOW Voltage
PECL_CLK1
Other
VOH
Output HIGH Voltage1
VOL
Output LOW Voltage1
IIN
Input Current
ICCI
Maximum Quiescent Supply Current
Typ
Max
Unit
2.15
2.0
2.4
VCC
V
VCC = 3.3V
1.5
0
1.8
0.8
V
VCC = 3.3V
1.8
2.4
V
VCC = 3.3V
VCC = 3.3V
1.2
1.7
V
–120
120
µA
130
150
mA
15
20
mA
ICCA
Maximum PLL Supply Current
1. DC levels will vary 1:1 with VCC.
Condition
AC CHARACTERISTICS (TA = 0° to 70°C, VCC = 3.3V ±5%)
Symbol
Characteristic
Min
Typ
Max
Unit
Condition
tr, tf
Output Rise/Fall Time
200
850
ps
tpw1
Output Duty Cycle
49
51
%
tpw2
SYNC Output Duty Cycle
0.95
1.05
%
fref
Input Reference Frequency
10
Note 2
20
Note 2
MHz
tos
Output-to-Output Skew
100
300
ps
fVCO
PLL VCO Lock Range
440
750
MHz
VCO_SEL = 1
VCO_SEL = 0
fmax
Maximum Output Frequency
375
187.5
125
75
MHz
Note 1
tjitter
Cycle–to–Cycle Jitter (Peak–to–Peak)
±50
ps
Note 3
Xtal
FREF
Qa, Qb
Qa (–) to SYNC (+)
200
400
Qa (÷2)
Qa,Qb (÷4)
Qb (÷6)
Qb (÷10)
±25
tlock
Maximum PLL Lock Time
10
1. At 400MHz the output swing will be less than the nominal value.
2. ECLK and XTAL input reference limited by the feedback divide and the guaranteed VCO lock range.
3. Guaranteed by characterization.
20% to 80%
PCLK Period
ms
APPLICATIONS INFORMATION
eliminates the need for large on–board capacitors. Because
the design is a series resonant design, for optimum
frequency accuracy a series resonant crystal should be used
(see specification table below). Unfortunately most off the
shelf crystals are characterized in a parallel resonant mode.
However a parallel resonant crystal is physically no different
than a series resonant crystal, a parallel resonant crystal is
simply a crystal which has been characterized in its parallel
resonant mode. Therefore in the majority of cases a parallel
specified crystal can be used with the MPC992 with just a
minor frequency error due to the actual series resonant
frequency of the parallel resonant specified crystal. Typically
Using the On–Board Crystal Oscillator
The MPC992 features an on–board crystal oscillator to
allow for seed clock generation as well as final distribution.
The on–board oscillator is completely self contained so that
the only external component required is the crystal. As the
oscillator is somewhat sensitive to loading on its inputs the
user is advised to mount the crystal as close to the MPC992
as possible to avoid any board level parasitics. To facilitate
co–location surface mount crystals are recommended, but
not required.
The oscillator circuit is a series resonant circuit as
opposed to the more common parallel resonant circuit, this
MOTOROLA
4
TIMING SOLUTIONS
BR1333 — REV 5
MPC992
Figure 3 illustrates a typical power supply filter scheme.
The MPC992 is most susceptible to noise with spectral
content in the 10kHz to 1MHz range. Therefore the filter
should be designed to target this range. The key parameter
that needs to be met in the final filter design is the DC voltage
drop that will be seen between the VCC supply and the VCCA
pin of the MPC992. From the data sheet the IVCCA current
(the current sourced through the VCCA pin) is typically 15mA
(20mA maximum), assuming that a minimum of 3.0V must be
maintained on the VCCA pin very little DC voltage drop can
be tolerated when a 3.3V VCC supply is used. The resistor
shown in Figure 3 must have a resistance of 10–15Ω to meet
the voltage drop criteria. The RC filter pictured will provide a
broadband filter with approximately 100:1 attenuation for
noise whose spectral content is above 20KHz. As the noise
frequency crosses the series resonant point of an individual
capacitor it’s overall impedance begins to look inductive and
thus increases with increasing frequency. The parallel
capacitor combination shown ensures that a low impedance
path to ground exists for frequencies well above the
bandwidth of the PLL.
a parallel specified crystal used in a series resonant mode
will exhibit an oscillatory frequency a few hundred ppm lower
than the specified value. For most processor implementa–
tions a few hundred ppm translates into kHz inaccuracies, a
level which does not represent a major issue.
Figure 2 shows an optional series capacitor in the crystal
oscillator interface. The on–board oscillator introduces a
small phase shift in the overall loop which causes the
oscillator to operate at a frequency slightly slower than the
specified crystal. The series capacitor is used to compensate
the loop and allow the oscillator to function at the specified
crystal frequency. If a 100ppm type error is not important, the
capacitor can be left off the PCB. For more detailed
information, order Motorola Application Note AN1579/D.
MPC992
XTAL1
XTAL2
CTUNE
(Optional)
3.3V
Figure 2. Recommended Crystal Interface
RS=10–15Ω
VCCA
22µF
Table 1. Crystal Specifications
Parameter
Value
Crystal Cut
Fundamental AT Cut
Resonance
Series Resonance*
Frequency Tolerance
±75ppm at 25°C
Frequency/Temperature Stability
±150ppm 0 to 70°C
Operating Range
0 to 70°C
Shunt Capacitance
5–7pF
Equivalent Series Resistance (ESR)
50 to 80Ω max
Correlation Drive Level
100µW
Aging
5ppm/Yr (First 3 Years)
VCC
0.01µF
Figure 3. Power Supply Filter
A higher level of attenuation can be achieved by replacing
the resistor with an appropriate valued inductor. A 1000µH
choke will show a significant impedance at 10KHz
frequencies and above. Because of the current draw and the
voltage that must be maintained on the VCCA pin a low DC
resistance inductor is required (less than 15Ω). Generally the
resistor/capacitor filter will be cheaper, easier to implement
and provide an adequate level of supply filtering.
Power Supply Filtering
The MPC992 is a mixed analog/digital product and as
such it exhibits some sensitivities that would not necessarily
be seen on a fully digital product. Analog circuitry is naturally
susceptible to random noise, especially if this noise is seen
on the power supply pins. The MPC992 provides separate
power supplies for the digital circuitry (VCCI) and the internal
PLL (VCCA) of the device. The purpose of this design
technique is to try and isolate the high switching noise digital
outputs from the relatively sensitive internal analog
phase–locked loop. In a controlled environment such as an
evaluation board this level of isolation is sufficient. However,
in a digital system environment where it is more difficult to
minimize noise on the power supplies a second level of
isolation may be required. The simplest form of isolation is a
power supply filter on the VCCA pin for the MPC992.
TIMING SOLUTIONS
BR1333 — REV 5
0.01µF
MPC992
The MPC992 provides sub–nanosecond output edge
rates and thus a good power supply bypassing scheme is a
must. The important aspect of the layout for the MPC992 is
low impedance connections between VCC and GND for the
bypass capacitors. Combining good quality general purpose
chip capacitors with good PCB layout techniques will
produce effective capacitor resonances at frequencies
adequate to supply the instantaneous switching current for
the MPC992 outputs. It is imperative that low inductance chip
capacitors are used; it is equally important that the board
layout does not introduce back all of the inductance saved by
using the leadless capacitors. Thin interconnect traces
between the capacitor and the power plane should be
avoided and multiple large vias should be used to tie the
5
MOTOROLA
MPC992
circuitry will be adversely affected by activity on the
PECL_CLK inputs. Therefore, it is recommended that the
PECL input signals be static when the crystal oscillator
circuitry is being used.
Although the MPC992 has several design features to
minimize the susceptibility to power supply noise (isolated
power and grounds and fully differential PLL) there still may
be applications in which overall performance is being
degraded due to system power supply noise. The power
supply filter and bypass schemes discussed in this section
should be adequate to eliminate power supply noise related
problems in most designs.
capacitors to the buried power planes. Fat interconnect and
large vias will help to minimize layout induced inductance and
thus maximize the series resonant point of the bypass
capacitors.
No active signal lines should pass below the crystal
interface to the MPC992. The oscillator is a series resonant
circuit and the voltage amplitude across the crystal is
relatively small. It is imperative that no actively switching
signals cross under the crystal as crosstalk energy coupled
to these lines could significantly impact the jitter of the device.
Special attention should be paid to the layout of the crystal to
ensure a stable, jitter free interface between the crystal and
the on–board oscillator. In addition, the crystal interface
MOTOROLA
6
TIMING SOLUTIONS
BR1333 — REV 5
MPC992
OUTLINE DIMENSIONS
A
–T–, –U–, –Z–
FA SUFFIX
PLASTIC TQFP PACKAGE
CASE 873A-02
ISSUE A
4X
A1
32
0.20 (0.008) AB T–U Z
25
1
–U–
–T–
B
V
AE
P
B1
DETAIL Y
17
8
V1
AE
DETAIL Y
9
4X
–Z–
9
0.20 (0.008) AC T–U Z
S1
S
DETAIL AD
G
–AB–
0.10 (0.004) AC
AC T–U Z
–AC–
BASE
METAL
ÉÉ
ÉÉ
ÉÉ
ÉÉ
F
8X
M_
R
J
M
N
D
0.20 (0.008)
SEATING
PLANE
SECTION AE–AE
W
K
X
DETAIL AD
TIMING SOLUTIONS
BR1333 — REV 5
Q_
GAUGE PLANE
H
0.250 (0.010)
C E
7
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DATUM PLANE –AB– IS LOCATED AT BOTTOM OF
LEAD AND IS COINCIDENT WITH THE LEAD
WHERE THE LEAD EXITS THE PLASTIC BODY AT
THE BOTTOM OF THE PARTING LINE.
4. DATUMS –T–, –U–, AND –Z– TO BE DETERMINED
AT DATUM PLANE –AB–.
5. DIMENSIONS S AND V TO BE DETERMINED AT
SEATING PLANE –AC–.
6. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION. ALLOWABLE PROTRUSION IS
0.250 (0.010) PER SIDE. DIMENSIONS A AND B
DO INCLUDE MOLD MISMATCH AND ARE
DETERMINED AT DATUM PLANE –AB–.
7. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. DAMBAR PROTRUSION SHALL
NOT CAUSE THE D DIMENSION TO EXCEED
0.520 (0.020).
8. MINIMUM SOLDER PLATE THICKNESS SHALL BE
0.0076 (0.0003).
9. EXACT SHAPE OF EACH CORNER MAY VARY
FROM DEPICTION.
DIM
A
A1
B
B1
C
D
E
F
G
H
J
K
M
N
P
Q
R
S
S1
V
V1
W
X
MILLIMETERS
MIN
MAX
7.000 BSC
3.500 BSC
7.000 BSC
3.500 BSC
1.400
1.600
0.300
0.450
1.350
1.450
0.300
0.400
0.800 BSC
0.050
0.150
0.090
0.200
0.500
0.700
12_ REF
0.090
0.160
0.400 BSC
1_
5_
0.150
0.250
9.000 BSC
4.500 BSC
9.000 BSC
4.500 BSC
0.200 REF
1.000 REF
INCHES
MIN
MAX
0.276 BSC
0.138 BSC
0.276 BSC
0.138 BSC
0.055
0.063
0.012
0.018
0.053
0.057
0.012
0.016
0.031 BSC
0.002
0.006
0.004
0.008
0.020
0.028
12_ REF
0.004
0.006
0.016 BSC
1_
5_
0.006
0.010
0.354 BSC
0.177 BSC
0.354 BSC
0.177 BSC
0.008 REF
0.039 REF
MOTOROLA
MPC992
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MOTOROLA
◊
8
*MPC992/D*
MPC992/D
TIMING SOLUTIONS
BR1333 — REV 5
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